Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	38287	1			T2	4		T4	77		T5	19
auto[SpiFlashAddrCfg]	8162	1			T2	6		T4	22		T5	5
auto[SpiFlashAddr3b]	9931	1			T2	4		T4	23		T5	7
auto[SpiFlashAddr4b]	8231	1			T2	4		T4	27		T5	9

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37275

1

T2

18

T4

88

T5

21

auto[1]

27336

1

T4

61

T5

19

T8

119

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33872

1

T2

16

T4

74

T5

21

auto[1]

30739

1

T2

2

T4

75

T5

19

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	43392	1			T2	4		T4	86		T5	21
values[1]	1190	1			T4	3		T5	1		T8	10
values[2]	1558	1			T2	2		T4	3		T5	2
values[3]	1548	1			T4	7		T5	1		T8	15
values[4]	1549	1			T8	7		T10	2		T13	7
values[5]	1534	1			T2	8		T4	5		T5	2
values[6]	1568	1			T4	6		T5	1		T8	14
values[7]	1572	1			T4	5		T8	13		T10	8
values[8]	10700	1			T2	4		T4	34		T5	12

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35184

1

T2

18

T5

40

T7

28

auto[1]

29427

1

T4

149

T10

485

T13

84

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

61012

1

T2

18

T4

145

T5

38

write

3599

1

T4

4

T5

2

T8

23

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20813

1

T2

8

T4

66

T5

23

valids[0x1]

43798

1

T2

10

T4

83

T5

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1724	1			T4	5		T5	3		T8	9
internal_process_ops[0x5a]	1627	1			T4	5		T8	10		T10	7
internal_process_ops[0x05]	23327	1			T2	4		T4	17		T5	2
internal_process_ops[0x35]	1640	1			T4	6		T5	3		T8	5
internal_process_ops[0x15]	1648	1			T4	8		T5	1		T8	8
internal_process_ops[0x03]	1186	1			T2	4		T4	2		T5	1
internal_process_ops[0x0b]	1151	1			T4	1		T5	2		T8	7
internal_process_ops[0x3b]	1121	1			T4	1		T8	12		T40	2
internal_process_ops[0x6b]	1123	1			T8	13		T10	3		T13	3
internal_process_ops[0xbb]	1158	1			T2	4		T4	3		T5	2
internal_process_ops[0xeb]	1141	1			T4	1		T5	3		T8	14

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62802

1

T2

18

T4

147

T5

40

auto[1]

1809

1

T4

2

T8

12

T10

12

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62009

1

T2

18

T4

145

T5

40

auto[1]

2602

1

T4

4

T8

18

T10

15

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12861

1

T2

4

T5

11

T7

28

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6689

1

T5

8

T8

22

T40

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2272

1

T2

6

T5

1

T8

25

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2052

1

T5

2

T8

29

T41

19

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2760

1

T2

4

T5

5

T8

26

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2383

1

T5

2

T8

38

T41

32

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2222

1

T2

4

T5

4

T8

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2027

1

T5

5

T8

18

T40

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

154

1

T8

2

T46

1

T156

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

90

1

T8

3

T41

2

T42

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

85

1

T40

2

T42

1

T47

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

116

1

T8

1

T41

2

T48

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

124

1

T41

2

T42

4

T47

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

104

1

T8

1

T41

1

T46

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

120

1

T5

2

T8

2

T42

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

145

1

T8

5

T42

2

T47

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

143

1

T8

4

T41

3

T96

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

108

1

T40

3

T41

3

T42

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

115

1

T8

3

T41

2

T42

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

121

1

T8

1

T41

7

T42

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

143

1

T41

4

T42

2

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

129

1

T8

1

T41

2

T47

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

102

1

T41

4

T42

2

T47

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

119

1

T41

2

T42

1

T46

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10266

1

T4

53

T10

291

T13

22

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7640

1

T4

23

T10

93

T13

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1465

1

T4

11

T10

16

T13

6

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1458

1

T4

10

T10

11

T13

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2062

1

T4

15

T10

20

T13

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1836

1

T4

7

T10

15

T13

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1487

1

T4

7

T10

11

T13

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1532

1

T4

19

T10

8

T13

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

115

1

T13

2

T52

2

T61

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

107

1

T36

7

T61

1

T83

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

74

1

T10

1

T36

4

T61

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T4

1

T13

1

T36

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

106

1

T10

1

T36

2

T52

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

117

1

T4

1

T10

2

T36

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T36

2

T19

2

T83

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

104

1

T10

3

T36

4

T19

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

92

1

T4

1

T10

3

T36

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

128

1

T10

3

T157

3

T83

6

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

89

1

T36

4

T52

2

T61

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

94

1

T10

2

T52

4

T83

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

106

1

T10

3

T61

1

T157

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

114

1

T10

1

T13

2

T36

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

127

1

T4

1

T52

1

T61

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

123

1

T10

1

T36

2

T52

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4454	1			T5	10		T7	28		T8	39
auto[0]	values[0]	valids[0x1]	18338	1			T2	4		T5	11		T8	76
auto[0]	values[1]	valids[0x1]	627	1			T5	1		T8	10		T40	2
auto[0]	values[2]	valids[0x0]	540	1			T2	2		T5	2		T8	5
auto[0]	values[2]	valids[0x1]	356	1			T8	3		T42	7		T46	1
auto[0]	values[3]	valids[0x0]	585	1			T5	1		T8	14		T41	5
auto[0]	values[3]	valids[0x1]	320	1			T8	1		T41	2		T42	4
auto[0]	values[4]	valids[0x0]	587	1			T8	5		T40	1		T41	1
auto[0]	values[4]	valids[0x1]	368	1			T8	2		T41	3		T42	5
auto[0]	values[5]	valids[0x0]	582	1			T2	4		T8	4		T41	4
auto[0]	values[5]	valids[0x1]	323	1			T2	4		T5	2		T41	4
auto[0]	values[6]	valids[0x0]	583	1			T5	1		T8	11		T41	6
auto[0]	values[6]	valids[0x1]	356	1			T8	3		T40	1		T45	6
auto[0]	values[7]	valids[0x0]	597	1			T8	6		T41	8		T42	3
auto[0]	values[7]	valids[0x1]	300	1			T8	7		T45	4		T41	2
auto[0]	values[8]	valids[0x0]	4044	1			T2	2		T5	9		T8	47
auto[0]	values[8]	valids[0x1]	2224	1			T2	2		T5	3		T8	27
auto[1]	values[0]	valids[0x0]	4038	1			T4	36		T10	37		T13	13
auto[1]	values[0]	valids[0x1]	16562	1			T4	50		T10	373		T13	29
auto[1]	values[1]	valids[0x1]	563	1			T4	3		T10	3		T13	9
auto[1]	values[2]	valids[0x0]	386	1			T4	2		T36	6		T52	3
auto[1]	values[2]	valids[0x1]	276	1			T4	1		T10	2		T13	2
auto[1]	values[3]	valids[0x0]	391	1			T4	1		T10	4		T36	8
auto[1]	values[3]	valids[0x1]	252	1			T4	6		T10	2		T13	3
auto[1]	values[4]	valids[0x0]	312	1			T10	2		T13	2		T36	7
auto[1]	values[4]	valids[0x1]	282	1			T13	5		T36	4		T83	4
auto[1]	values[5]	valids[0x0]	372	1			T4	3		T10	3		T13	1
auto[1]	values[5]	valids[0x1]	257	1			T4	2		T10	3		T36	2
auto[1]	values[6]	valids[0x0]	366	1			T4	3		T10	8		T13	2
auto[1]	values[6]	valids[0x1]	263	1			T4	3		T10	2		T36	6
auto[1]	values[7]	valids[0x0]	397	1			T4	5		T10	2		T13	1
auto[1]	values[7]	valids[0x1]	278	1			T10	6		T36	3		T52	7
auto[1]	values[8]	valids[0x0]	2579	1			T4	16		T10	28		T13	7
auto[1]	values[8]	valids[0x1]	1853	1			T4	18		T10	10		T13	10