Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3661800

1

T2

5865

T4

13170

T5

666

auto[1]

28905

1

T4

9

T8

302

T10

305

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

932760

1

T2

1

T4

42

T5

7

auto[1]

2757945

1

T2

5864

T4

13137

T5

659

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	686076	1			T2	5865		T4	1951		T5	13
auto[524288:1048575]	428264	1			T4	1		T5	132		T8	635
auto[1048576:1572863]	447773	1			T4	3836		T8	21		T10	8818
auto[1572864:2097151]	438367	1			T7	13		T8	26		T13	2
auto[2097152:2621439]	452523	1			T4	3010		T5	265		T8	27
auto[2621440:3145727]	434502	1			T8	1679		T10	677		T13	1
auto[3145728:3670015]	390759	1			T4	3862		T5	256		T7	13
auto[3670016:4194303]	412441	1			T4	519		T8	9268		T10	11

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2793024

1

T2

5865

T4

13179

T5

666

auto[1]

897681

1

T7

2

T8

17

T10

6

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3186933

1

T2

5865

T4

11996

T5

409

auto[1]

503772

1

T4

1183

T5

257

T7

6

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	191112	1			T2	1		T4	3		T7	61
auto[0]	auto[0]	auto[0:524287]	auto[1]	404835	1			T2	5864		T4	1948		T5	13
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	106306	1			T4	1		T5	3		T8	77
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	259973	1			T5	128		T8	256		T10	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	104637	1			T4	9		T8	21		T10	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	288776	1			T4	3812		T10	8813		T13	1694
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	95771	1			T7	7		T8	26		T13	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	256621	1			T40	4		T36	4		T41	1390
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	122355	1			T5	3		T8	15		T10	11
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	272971	1			T4	2366		T5	262		T10	2218
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	98613	1			T8	59		T10	5		T13	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	282427	1			T8	1603		T10	662		T36	1541
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	85052	1			T4	5		T7	13		T8	107
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	248921	1			T4	3333		T8	5544		T10	110
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	113718	1			T4	3		T8	77		T10	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	231299	1			T4	513		T8	9142		T10	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	1322	1			T8	9		T10	2		T52	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	84168	1			T10	1		T52	547		T46	2404
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	794	1			T5	1		T8	24		T10	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	57944	1			T8	256		T10	256		T36	512
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	545	1			T4	7		T13	2		T36	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	49765	1			T4	3		T13	3		T36	2761
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	3086	1			T7	6		T13	1		T40	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	79402	1			T40	1095		T36	770		T41	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1120	1			T4	4		T8	12		T40	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	53091	1			T4	640		T10	1419		T40	128
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	907	1			T8	2		T10	1		T36	9
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	49416	1			T36	642		T46	512		T48	3711
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2103	1			T4	6		T8	14		T10	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	50761	1			T4	517		T5	256		T8	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1277	1			T8	7		T36	3		T41	10
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	62712	1			T36	1		T41	3011		T42	3380
auto[1]	auto[0]	auto[0:524287]	auto[0]	493	1			T10	1		T13	2		T40	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3520	1			T10	2		T13	2		T40	19
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	389	1			T8	15		T10	1		T36	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2417	1			T10	54		T36	13		T41	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	428	1			T36	4		T41	2		T42	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2286	1			T36	14		T41	60		T42	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	379	1			T36	3		T41	2		T52	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2473	1			T36	9		T41	39		T47	21
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	358	1			T10	4		T36	3		T41	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2140	1			T10	93		T36	31		T41	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	406	1			T8	15		T10	3		T36	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2189	1			T10	6		T36	67		T41	69
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	407	1			T8	35		T10	2		T36	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2775	1			T8	188		T10	4		T36	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	408	1			T4	1		T8	32		T10	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2478	1			T4	2		T10	7		T36	11
auto[1]	auto[1]	auto[0:524287]	auto[0]	121	1			T10	1		T48	1		T64	7
auto[1]	auto[1]	auto[0:524287]	auto[1]	505	1			T10	67		T48	5		T157	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	74	1			T8	7		T83	2		T215	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	367	1			T83	46		T215	9		T173	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	125	1			T4	2		T36	2		T52	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1211	1			T4	3		T36	16		T52	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	107	1			T40	3		T36	2		T41	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	528	1			T40	10		T36	13		T18	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	77	1			T36	1		T18	1		T19	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	411	1			T18	7		T19	1		T176	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	63	1			T36	2		T48	1		T44	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	481	1			T36	22		T48	28		T44	8
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	117	1			T4	1		T10	2		T83	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	623	1			T10	57		T83	22		T176	18
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	90	1			T8	10		T36	1		T41	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	459	1			T41	26		T42	4		T48	10

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2272399	1			T2	5865		T4	11993		T5	409
auto[0]	auto[0]	auto[1]	890988	1			T7	1		T10	5		T15	1897
auto[0]	auto[1]	auto[0]	492435	1			T4	1177		T5	257		T7	5
auto[0]	auto[1]	auto[1]	5978	1			T7	1		T10	1		T40	3
auto[1]	auto[0]	auto[0]	22967	1			T4	3		T8	271		T10	178
auto[1]	auto[0]	auto[1]	579	1			T8	14		T36	4		T41	2
auto[1]	auto[1]	auto[0]	5223	1			T4	6		T8	14		T10	127
auto[1]	auto[1]	auto[1]	136	1			T8	3		T36	2		T41	1