Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2787417	1			T2	203		T3	2		T4	28546
all_pins[1]	2787417	1			T2	203		T3	2		T4	28546
all_pins[2]	2787417	1			T2	203		T3	2		T4	28546
all_pins[3]	2787417	1			T2	203		T3	2		T4	28546
all_pins[4]	2787417	1			T2	203		T3	2		T4	28546
all_pins[5]	2787417	1			T2	203		T3	2		T4	28546
all_pins[6]	2787417	1			T2	203		T3	2		T4	28546
all_pins[7]	2787417	1			T2	203		T3	2		T4	28546

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22279427	1			T2	1624		T3	16		T4	228368
values[0x1]	19909	1			T10	19		T17	32		T19	26
transitions[0x0=>0x1]	19278	1			T10	15		T17	24		T19	17
transitions[0x1=>0x0]	19290	1			T10	15		T17	24		T19	17

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2787137	1			T2	203		T3	2		T4	28546
all_pins[0]	values[0x1]	280	1			T17	5		T19	2		T21	8
all_pins[0]	transitions[0x0=>0x1]	243	1			T17	4		T19	1		T21	4
all_pins[0]	transitions[0x1=>0x0]	248	1			T10	14		T19	3		T44	1
all_pins[1]	values[0x0]	2787132	1			T2	203		T3	2		T4	28546
all_pins[1]	values[0x1]	285	1			T10	14		T17	1		T19	4
all_pins[1]	transitions[0x0=>0x1]	238	1			T10	10		T17	1		T19	3
all_pins[1]	transitions[0x1=>0x0]	174	1			T10	1		T17	2		T19	1
all_pins[2]	values[0x0]	2787196	1			T2	203		T3	2		T4	28546
all_pins[2]	values[0x1]	221	1			T10	5		T17	2		T19	2
all_pins[2]	transitions[0x0=>0x1]	186	1			T10	5		T17	2		T44	2
all_pins[2]	transitions[0x1=>0x0]	127	1			T19	4		T44	2		T21	3
all_pins[3]	values[0x0]	2787255	1			T2	203		T3	2		T4	28546
all_pins[3]	values[0x1]	162	1			T19	6		T44	2		T21	5
all_pins[3]	transitions[0x0=>0x1]	123	1			T19	5		T44	2		T21	3
all_pins[3]	transitions[0x1=>0x0]	122	1			T17	6		T19	1		T44	3
all_pins[4]	values[0x0]	2787256	1			T2	203		T3	2		T4	28546
all_pins[4]	values[0x1]	161	1			T17	6		T19	2		T44	3
all_pins[4]	transitions[0x0=>0x1]	124	1			T17	4		T19	2		T44	2
all_pins[4]	transitions[0x1=>0x0]	943	1			T17	4		T19	2		T44	1
all_pins[5]	values[0x0]	2786437	1			T2	203		T3	2		T4	28546
all_pins[5]	values[0x1]	980	1			T17	6		T19	2		T44	2
all_pins[5]	transitions[0x0=>0x1]	622	1			T17	5		T19	2		T44	1
all_pins[5]	transitions[0x1=>0x0]	17316	1			T17	2		T19	4		T44	3
all_pins[6]	values[0x0]	2769743	1			T2	203		T3	2		T4	28546
all_pins[6]	values[0x1]	17674	1			T17	3		T19	4		T44	4
all_pins[6]	transitions[0x0=>0x1]	17633	1			T17	2		T44	1		T21	1
all_pins[6]	transitions[0x1=>0x0]	105	1			T17	8		T21	2		T30	1
all_pins[7]	values[0x0]	2787271	1			T2	203		T3	2		T4	28546
all_pins[7]	values[0x1]	146	1			T17	9		T19	4		T44	3
all_pins[7]	transitions[0x0=>0x1]	109	1			T17	6		T19	4		T44	3
all_pins[7]	transitions[0x1=>0x0]	255	1			T17	2		T19	2		T21	8