Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21110

1

T2

18

T5

21

T7

28

auto[1]

14074

1

T5

19

T8

119

T40

5

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4765	1			T9	4		T41	105		T42	54
values[1]	4695	1			T8	20		T15	4		T174	10
values[2]	4505	1			T8	60		T41	33		T42	28
values[3]	4176	1			T5	20		T8	20		T42	20
values[4]	4911	1			T2	18		T5	20		T8	20
values[5]	3735	1			T7	28		T41	24		T46	20
values[6]	4115	1			T8	40		T45	22		T41	94
values[7]	4282	1			T8	100		T40	53		T41	147

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4183	1			T8	20		T45	22		T42	78
values[1]	4052	1			T2	18		T7	28		T8	60
values[2]	4374	1			T8	40		T40	53		T41	187
values[3]	4750	1			T8	60		T9	4		T46	20
values[4]	4147	1			T5	20		T41	139		T42	74
values[5]	4696	1			T5	20		T8	40		T15	4
values[6]	3787	1			T8	40		T174	10		T41	20
values[7]	5195	1			T41	33		T42	83		T216	8

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	229	1			T48	14		T179	9		T217	10
auto[0]	values[0]	values[1]	232	1			T22	15		T33	13		T218	11
auto[0]	values[0]	values[2]	248	1			T41	12		T44	15		T202	14
auto[0]	values[0]	values[3]	500	1			T9	4		T47	9		T18	25
auto[0]	values[0]	values[4]	303	1			T42	11		T48	40		T51	13
auto[0]	values[0]	values[5]	561	1			T22	28		T23	16		T214	12
auto[0]	values[0]	values[6]	316	1			T41	10		T18	16		T44	8
auto[0]	values[0]	values[7]	294	1			T42	16		T46	24		T48	8
auto[0]	values[1]	values[0]	416	1			T8	12		T42	8		T18	25
auto[0]	values[1]	values[1]	318	1			T41	6		T156	10		T75	93
auto[0]	values[1]	values[2]	299	1			T47	6		T179	12		T188	14
auto[0]	values[1]	values[3]	275	1			T47	9		T18	9		T23	35
auto[0]	values[1]	values[4]	325	1			T42	10		T46	12		T18	15
auto[0]	values[1]	values[5]	412	1			T15	4		T41	13		T42	10
auto[0]	values[1]	values[6]	249	1			T174	10		T51	15		T188	33
auto[0]	values[1]	values[7]	396	1			T219	14		T54	14		T33	12
auto[0]	values[2]	values[0]	218	1			T220	6		T48	9		T43	14
auto[0]	values[2]	values[1]	287	1			T8	9		T201	12		T23	14
auto[0]	values[2]	values[2]	319	1			T44	14		T23	11		T53	16
auto[0]	values[2]	values[3]	299	1			T8	10		T213	23		T176	14
auto[0]	values[2]	values[4]	423	1			T47	18		T23	14		T30	21
auto[0]	values[2]	values[5]	476	1			T8	10		T42	8		T18	12
auto[0]	values[2]	values[6]	268	1			T213	5		T54	20		T221	13
auto[0]	values[2]	values[7]	479	1			T41	26		T216	8		T131	6
auto[0]	values[3]	values[0]	219	1			T23	17		T181	13		T222	24
auto[0]	values[3]	values[1]	333	1			T51	13		T223	9		T200	7
auto[0]	values[3]	values[2]	219	1			T190	8		T151	10		T182	21
auto[0]	values[3]	values[3]	253	1			T18	10		T179	11		T210	12
auto[0]	values[3]	values[4]	386	1			T47	9		T30	114		T33	11
auto[0]	values[3]	values[5]	181	1			T5	9		T200	9		T198	23
auto[0]	values[3]	values[6]	296	1			T8	9		T214	13		T33	55
auto[0]	values[3]	values[7]	370	1			T42	14		T47	11		T43	10
auto[0]	values[4]	values[0]	416	1			T42	52		T224	4		T22	16
auto[0]	values[4]	values[1]	395	1			T2	18		T8	7		T41	9
auto[0]	values[4]	values[2]	303	1			T42	28		T46	14		T51	15
auto[0]	values[4]	values[3]	841	1			T46	9		T48	13		T18	25
auto[0]	values[4]	values[4]	334	1			T5	12		T18	14		T23	4
auto[0]	values[4]	values[5]	381	1			T90	16		T42	10		T18	13
auto[0]	values[4]	values[6]	271	1			T47	8		T44	13		T213	13
auto[0]	values[4]	values[7]	292	1			T42	36		T176	13		T22	17
auto[0]	values[5]	values[0]	197	1			T43	13		T23	15		T179	16
auto[0]	values[5]	values[1]	363	1			T7	28		T41	12		T225	2
auto[0]	values[5]	values[2]	447	1			T46	16		T48	10		T51	16
auto[0]	values[5]	values[3]	127	1			T18	9		T226	4		T227	12
auto[0]	values[5]	values[4]	172	1			T53	8		T188	22		T54	13
auto[0]	values[5]	values[5]	327	1			T97	14		T48	14		T18	23
auto[0]	values[5]	values[6]	280	1			T22	12		T23	11		T151	18
auto[0]	values[5]	values[7]	339	1			T228	10		T176	32		T172	22
auto[0]	values[6]	values[0]	651	1			T45	22		T43	16		T64	14
auto[0]	values[6]	values[1]	298	1			T44	16		T229	26		T22	6
auto[0]	values[6]	values[2]	200	1			T47	17		T48	12		T230	16
auto[0]	values[6]	values[3]	285	1			T8	24		T43	14		T64	16
auto[0]	values[6]	values[4]	218	1			T41	24		T42	15		T153	11
auto[0]	values[6]	values[5]	219	1			T18	12		T44	35		T231	20
auto[0]	values[6]	values[6]	192	1			T22	13		T186	15		T167	13
auto[0]	values[6]	values[7]	389	1			T96	12		T47	14		T18	101
auto[0]	values[7]	values[0]	273	1			T47	19		T232	10		T64	12
auto[0]	values[7]	values[1]	185	1			T8	13		T47	21		T48	11
auto[0]	values[7]	values[2]	397	1			T8	22		T40	48		T41	95
auto[0]	values[7]	values[3]	500	1			T233	10		T18	13		T22	19
auto[0]	values[7]	values[4]	392	1			T41	16		T46	28		T18	14
auto[0]	values[7]	values[5]	209	1			T8	14		T176	19		T167	11
auto[0]	values[7]	values[6]	341	1			T8	11		T46	18		T22	46
auto[0]	values[7]	values[7]	477	1			T18	60		T51	11		T22	14
auto[1]	values[0]	values[0]	274	1			T48	135		T179	11		T218	35
auto[1]	values[0]	values[1]	183	1			T22	5		T33	7		T218	9
auto[1]	values[0]	values[2]	428	1			T41	73		T44	11		T23	13
auto[1]	values[0]	values[3]	198	1			T47	11		T18	23		T20	4
auto[1]	values[0]	values[4]	283	1			T42	23		T48	7		T51	7
auto[1]	values[0]	values[5]	255	1			T22	7		T23	8		T214	8
auto[1]	values[0]	values[6]	288	1			T41	10		T18	24		T44	49
auto[1]	values[0]	values[7]	173	1			T42	4		T46	8		T48	18
auto[1]	values[1]	values[0]	271	1			T8	8		T42	12		T18	3
auto[1]	values[1]	values[1]	321	1			T41	37		T54	14		T33	7
auto[1]	values[1]	values[2]	246	1			T47	72		T179	9		T188	6
auto[1]	values[1]	values[3]	263	1			T47	11		T18	44		T23	32
auto[1]	values[1]	values[4]	153	1			T42	10		T46	8		T18	16
auto[1]	values[1]	values[5]	245	1			T41	7		T42	10		T64	10
auto[1]	values[1]	values[6]	180	1			T51	5		T188	36		T30	12
auto[1]	values[1]	values[7]	326	1			T219	6		T234	16		T54	6
auto[1]	values[2]	values[0]	170	1			T48	15		T43	6		T64	8
auto[1]	values[2]	values[1]	170	1			T8	11		T23	6		T185	6
auto[1]	values[2]	values[2]	195	1			T44	8		T23	9		T53	11
auto[1]	values[2]	values[3]	183	1			T8	10		T213	13		T176	6
auto[1]	values[2]	values[4]	241	1			T47	24		T23	8		T30	6
auto[1]	values[2]	values[5]	378	1			T8	10		T42	20		T18	8
auto[1]	values[2]	values[6]	157	1			T213	15		T54	4		T221	23
auto[1]	values[2]	values[7]	242	1			T41	7		T18	8		T22	25
auto[1]	values[3]	values[0]	152	1			T23	10		T181	14		T222	11
auto[1]	values[3]	values[1]	176	1			T51	7		T223	11		T200	16
auto[1]	values[3]	values[2]	142	1			T151	14		T182	5		T227	14
auto[1]	values[3]	values[3]	172	1			T18	25		T179	9		T188	16
auto[1]	values[3]	values[4]	142	1			T47	11		T30	8		T33	9
auto[1]	values[3]	values[5]	336	1			T5	11		T200	19		T198	4
auto[1]	values[3]	values[6]	214	1			T8	11		T214	8		T33	13
auto[1]	values[3]	values[7]	585	1			T42	6		T47	64		T43	75
auto[1]	values[4]	values[0]	137	1			T42	6		T22	8		T23	15
auto[1]	values[4]	values[1]	272	1			T8	13		T41	22		T42	11
auto[1]	values[4]	values[2]	172	1			T42	3		T46	52		T51	5
auto[1]	values[4]	values[3]	344	1			T46	11		T48	7		T18	21
auto[1]	values[4]	values[4]	183	1			T5	8		T18	6		T23	23
auto[1]	values[4]	values[5]	183	1			T42	10		T18	9		T176	10
auto[1]	values[4]	values[6]	187	1			T47	14		T44	7		T213	7
auto[1]	values[4]	values[7]	200	1			T42	7		T50	8		T176	9
auto[1]	values[5]	values[0]	206	1			T49	12		T43	7		T23	25
auto[1]	values[5]	values[1]	127	1			T41	12		T179	10		T153	14
auto[1]	values[5]	values[2]	182	1			T46	4		T48	15		T51	4
auto[1]	values[5]	values[3]	142	1			T18	26		T235	4		T236	14
auto[1]	values[5]	values[4]	143	1			T53	12		T188	21		T54	7
auto[1]	values[5]	values[5]	149	1			T48	6		T18	10		T22	7
auto[1]	values[5]	values[6]	305	1			T22	8		T23	9		T151	10
auto[1]	values[5]	values[7]	229	1			T63	10		T176	5		T151	7
auto[1]	values[6]	values[0]	144	1			T43	4		T64	6		T23	6
auto[1]	values[6]	values[1]	228	1			T44	15		T22	14		T167	21
auto[1]	values[6]	values[2]	286	1			T47	8		T48	19		T53	13
auto[1]	values[6]	values[3]	198	1			T8	16		T43	6		T64	4
auto[1]	values[6]	values[4]	232	1			T41	70		T42	5		T153	9
auto[1]	values[6]	values[5]	313	1			T18	8		T44	9		T231	10
auto[1]	values[6]	values[6]	123	1			T22	8		T186	5		T167	7
auto[1]	values[6]	values[7]	139	1			T47	11		T18	6		T33	6
auto[1]	values[7]	values[0]	210	1			T47	48		T64	8		T44	20
auto[1]	values[7]	values[1]	164	1			T8	7		T47	4		T48	9
auto[1]	values[7]	values[2]	291	1			T8	18		T40	5		T41	7
auto[1]	values[7]	values[3]	170	1			T18	10		T22	8		T167	11
auto[1]	values[7]	values[4]	217	1			T41	29		T46	10		T18	8
auto[1]	values[7]	values[5]	71	1			T8	6		T176	4		T167	9
auto[1]	values[7]	values[6]	120	1			T8	9		T46	2		T22	12
auto[1]	values[7]	values[7]	265	1			T18	5		T51	9		T22	9