Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	402	1			T5	1		T8	3		T41	3
auto[ReadAddrCrossIntoMailbox]	325	1			T5	1		T8	1		T41	4
auto[ReadAddrCrossOutOfMailbox]	349	1			T5	1		T8	1		T41	3
auto[ReadAddrCrossAllMailbox]	241	1			T5	2		T8	1		T41	5
auto[ReadAddrOutsideMailbox]	3963	1			T2	8		T5	3		T8	62

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2696

1

T2

4

T5

3

T8

30

auto[1]

2584

1

T2

4

T5

5

T8

38

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	903	1			T2	4		T5	1		T8	12
read_ops[0x0b]	873	1			T5	2		T8	7		T15	2
read_ops[0x3b]	866	1			T8	12		T40	2		T41	15
read_ops[0x6b]	871	1			T8	13		T40	1		T41	11
read_ops[0xbb]	885	1			T2	4		T5	2		T8	10
read_ops[0xeb]	882	1			T5	3		T8	14		T15	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T41	2		T42	2		T47	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T8	1		T42	1		T18	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T41	1		T46	1		T47	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T47	1		T48	2		T64	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T47	1		T224	1		T176	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T47	1		T44	1		T224	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T46	1		T47	3		T51	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T5	1		T46	2		T64	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	354	1			T2	2		T8	7		T41	5
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	326	1			T2	2		T8	4		T41	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T46	1		T18	1		T203	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T42	1		T51	1		T203	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T131	1		T18	1		T176	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T131	1		T48	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T48	1		T64	1		T53	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T5	1		T8	1		T23	3
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T179	1		T153	1		T200	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T8	1		T41	1		T42	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	309	1			T5	1		T8	3		T15	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	368	1			T8	2		T15	1		T45	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T41	1		T190	1		T47	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T8	1		T42	1		T190	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T42	1		T51	1		T44	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T51	2		T23	1		T53	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T41	1		T131	1		T48	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T41	1		T131	1		T46	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T48	1		T18	1		T44	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T41	1		T53	1		T30	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	327	1			T8	2		T40	2		T41	6
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T8	9		T41	5		T90	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T42	1		T44	1		T23	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T46	1		T18	2		T22	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T41	2		T48	1		T18	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T18	2		T44	1		T22	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T64	1		T44	1		T23	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T42	1		T18	1		T43	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T41	1		T47	2		T54	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T53	1		T30	1		T54	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	344	1			T8	3		T41	6		T42	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	324	1			T8	10		T40	1		T41	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T47	1		T18	2		T43	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T51	2		T44	1		T176	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T41	1		T43	1		T224	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T46	1		T47	1		T51	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T42	1		T51	1		T201	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T46	1		T18	1		T43	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T5	1		T42	1		T44	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T46	2		T22	1		T23	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	338	1			T2	2		T5	1		T8	6
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T2	2		T8	4		T45	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T8	1		T190	1		T51	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T5	1		T42	1		T190	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T8	1		T46	1		T51	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T5	1		T47	1		T23	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T44	2		T23	1		T179	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T41	1		T48	1		T23	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T41	2		T23	1		T179	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T51	1		T210	1		T188	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	364	1			T8	7		T15	1		T45	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T5	1		T8	5		T15	1