Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4955	1			T8	60		T42	54		T216	8
values[1]	4770	1			T8	20		T41	149		T42	20
values[2]	4202	1			T5	20		T8	20		T40	53
values[3]	4077	1			T2	18		T8	40		T41	122
values[4]	3897	1			T8	20		T41	31		T42	51
values[5]	5486	1			T8	60		T9	4		T15	4
values[6]	3629	1			T5	20		T7	28		T8	20
values[7]	4168	1			T8	20		T45	22		T41	53

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4404	1			T2	18		T8	20		T41	43
values[1]	4440	1			T8	60		T40	53		T41	40
values[2]	3928	1			T8	40		T9	4		T41	107
values[3]	4630	1			T7	28		T8	40		T41	122
values[4]	3949	1			T15	4		T41	85		T42	20
values[5]	4219	1			T5	20		T8	40		T174	10
values[6]	5039	1			T8	40		T41	25		T42	94
values[7]	4575	1			T5	20		T8	20		T45	22

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34252

1

T2

18

T5

40

T7

28

auto[1]

932

1

T8

12

T40

3

T41

19

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	529	1			T46	20		T47	118		T48	47
auto[0]	values[0]	values[1]	643	1			T8	39		T44	22		T188	22
auto[0]	values[0]	values[2]	503	1			T44	84		T176	24		T182	26
auto[0]	values[0]	values[3]	538	1			T213	17		T22	20		T23	20
auto[0]	values[0]	values[4]	755	1			T216	8		T47	47		T18	65
auto[0]	values[0]	values[5]	616	1			T8	19		T96	12		T230	16
auto[0]	values[0]	values[6]	577	1			T42	53		T49	10		T53	23
auto[0]	values[0]	values[7]	639	1			T46	19		T220	6		T18	19
auto[0]	values[1]	values[0]	580	1			T47	20		T232	10		T179	20
auto[0]	values[1]	values[1]	583	1			T41	36		T30	20		T167	40
auto[0]	values[1]	values[2]	468	1			T44	39		T153	20		T33	25
auto[0]	values[1]	values[3]	689	1			T8	18		T42	18		T47	19
auto[0]	values[1]	values[4]	521	1			T41	85		T51	20		T213	35
auto[0]	values[1]	values[5]	785	1			T18	35		T23	51		T179	42
auto[0]	values[1]	values[6]	730	1			T18	18		T23	46		T30	179
auto[0]	values[1]	values[7]	302	1			T41	24		T47	21		T151	22
auto[0]	values[2]	values[0]	700	1			T219	20		T18	25		T229	26
auto[0]	values[2]	values[1]	559	1			T40	50		T48	80		T23	23
auto[0]	values[2]	values[2]	383	1			T18	51		T197	16		T22	34
auto[0]	values[2]	values[3]	677	1			T42	25		T48	20		T43	19
auto[0]	values[2]	values[4]	524	1			T190	8		T18	18		T44	20
auto[0]	values[2]	values[5]	455	1			T5	20		T174	10		T46	20
auto[0]	values[2]	values[6]	410	1			T8	20		T42	18		T151	17
auto[0]	values[2]	values[7]	380	1			T47	20		T63	6		T44	25
auto[0]	values[3]	values[0]	404	1			T2	18		T18	19		T64	20
auto[0]	values[3]	values[1]	571	1			T42	20		T18	22		T201	12
auto[0]	values[3]	values[2]	589	1			T64	19		T22	24		T23	45
auto[0]	values[3]	values[3]	522	1			T8	20		T41	101		T22	27
auto[0]	values[3]	values[4]	287	1			T23	29		T188	23		T54	20
auto[0]	values[3]	values[5]	341	1			T41	20		T179	20		T188	23
auto[0]	values[3]	values[6]	768	1			T8	18		T42	20		T203	10
auto[0]	values[3]	values[7]	506	1			T42	39		T22	56		T23	20
auto[0]	values[4]	values[0]	434	1			T47	22		T48	23		T51	20
auto[0]	values[4]	values[1]	395	1			T18	20		T202	14		T22	25
auto[0]	values[4]	values[2]	303	1			T23	20		T188	20		T77	4
auto[0]	values[4]	values[3]	329	1			T42	31		T234	12		T33	20
auto[0]	values[4]	values[4]	652	1			T42	20		T18	20		T179	18
auto[0]	values[4]	values[5]	404	1			T8	18		T51	20		T43	17
auto[0]	values[4]	values[6]	647	1			T47	20		T48	20		T22	16
auto[0]	values[4]	values[7]	626	1			T41	29		T18	20		T22	45
auto[0]	values[5]	values[0]	735	1			T8	20		T46	30		T48	146
auto[0]	values[5]	values[1]	736	1			T8	20		T51	19		T64	19
auto[0]	values[5]	values[2]	606	1			T8	16		T9	4		T42	41
auto[0]	values[5]	values[3]	810	1			T46	63		T18	20		T23	19
auto[0]	values[5]	values[4]	540	1			T15	4		T18	21		T176	20
auto[0]	values[5]	values[5]	529	1			T156	10		T48	26		T18	93
auto[0]	values[5]	values[6]	524	1			T41	23		T43	84		T44	20
auto[0]	values[5]	values[7]	860	1			T43	18		T44	22		T92	20
auto[0]	values[6]	values[0]	465	1			T41	42		T90	16		T18	28
auto[0]	values[6]	values[1]	362	1			T18	107		T192	22		T30	23
auto[0]	values[6]	values[2]	440	1			T8	20		T41	68		T46	20
auto[0]	values[6]	values[3]	351	1			T7	28		T43	20		T22	27
auto[0]	values[6]	values[4]	258	1			T43	20		T44	31		T53	46
auto[0]	values[6]	values[5]	534	1			T47	73		T64	17		T185	25
auto[0]	values[6]	values[6]	564	1			T131	6		T46	37		T30	49
auto[0]	values[6]	values[7]	570	1			T5	20		T18	20		T22	55
auto[0]	values[7]	values[0]	432	1			T42	56		T48	20		T22	18
auto[0]	values[7]	values[1]	503	1			T47	25		T48	54		T51	19
auto[0]	values[7]	values[2]	533	1			T41	30		T64	19		T23	36
auto[0]	values[7]	values[3]	577	1			T41	20		T207	8		T237	10
auto[0]	values[7]	values[4]	310	1			T51	20		T195	18		T22	18
auto[0]	values[7]	values[5]	440	1			T97	14		T47	23		T18	30
auto[0]	values[7]	values[6]	678	1			T18	33		T23	20		T30	55
auto[0]	values[7]	values[7]	571	1			T8	20		T45	22		T18	21
auto[1]	values[0]	values[0]	18	1			T47	5		T50	2		T22	1
auto[1]	values[0]	values[1]	16	1			T8	1		T188	1		T54	2
auto[1]	values[0]	values[2]	13	1			T44	3		T183	2		T238	1
auto[1]	values[0]	values[3]	21	1			T213	3		T231	3		T54	2
auto[1]	values[0]	values[4]	22	1			T22	2		T23	1		T239	2
auto[1]	values[0]	values[5]	22	1			T8	1		T23	4		T53	2
auto[1]	values[0]	values[6]	17	1			T42	1		T49	2		T53	1
auto[1]	values[0]	values[7]	26	1			T46	1		T18	1		T54	4
auto[1]	values[1]	values[0]	9	1			T198	2		T240	2		T241	1
auto[1]	values[1]	values[1]	20	1			T41	4		T221	3		T168	1
auto[1]	values[1]	values[2]	17	1			T44	5		T33	3		T177	1
auto[1]	values[1]	values[3]	15	1			T8	2		T42	2		T47	1
auto[1]	values[1]	values[4]	9	1			T213	1		T242	2		T243	1
auto[1]	values[1]	values[5]	17	1			T23	1		T179	3		T54	1
auto[1]	values[1]	values[6]	15	1			T18	2		T23	1		T30	2
auto[1]	values[1]	values[7]	10	1			T47	1		T175	1		T244	1
auto[1]	values[2]	values[0]	18	1			T18	1		T176	2		T151	1
auto[1]	values[2]	values[1]	10	1			T40	3		T48	1		T177	1
auto[1]	values[2]	values[2]	10	1			T18	2		T22	1		T245	1
auto[1]	values[2]	values[3]	24	1			T42	3		T43	1		T153	3
auto[1]	values[2]	values[4]	10	1			T18	2		T44	1		T231	2
auto[1]	values[2]	values[5]	8	1			T239	2		T246	1		T136	4
auto[1]	values[2]	values[6]	23	1			T42	2		T151	3		T167	2
auto[1]	values[2]	values[7]	11	1			T63	4		T44	1		T185	2
auto[1]	values[3]	values[0]	8	1			T18	4		T188	1		T221	2
auto[1]	values[3]	values[1]	8	1			T177	1		T240	1		T247	1
auto[1]	values[3]	values[2]	9	1			T64	1		T23	2		T188	1
auto[1]	values[3]	values[3]	17	1			T41	1		T23	3		T54	1
auto[1]	values[3]	values[4]	6	1			T23	1		T227	4		T248	1
auto[1]	values[3]	values[5]	7	1			T179	1		T151	1		T196	2
auto[1]	values[3]	values[6]	17	1			T8	2		T22	1		T188	4
auto[1]	values[3]	values[7]	17	1			T42	1		T22	1		T30	1
auto[1]	values[4]	values[0]	15	1			T48	2		T249	2		T241	1
auto[1]	values[4]	values[1]	4	1			T250	2		T251	2		-	-
auto[1]	values[4]	values[2]	5	1			T252	1		T253	1		T254	1
auto[1]	values[4]	values[3]	12	1			T234	4		T242	1		T175	3
auto[1]	values[4]	values[4]	14	1			T179	3		T200	2		T240	2
auto[1]	values[4]	values[5]	18	1			T8	2		T43	3		T23	1
auto[1]	values[4]	values[6]	25	1			T22	5		T23	1		T53	1
auto[1]	values[4]	values[7]	14	1			T41	2		T22	3		T200	1
auto[1]	values[5]	values[0]	22	1			T46	2		T48	3		T18	1
auto[1]	values[5]	values[1]	12	1			T51	1		T64	1		T44	1
auto[1]	values[5]	values[2]	20	1			T8	4		T42	2		T255	3
auto[1]	values[5]	values[3]	24	1			T46	3		T23	1		T179	4
auto[1]	values[5]	values[4]	22	1			T18	1		T22	2		T256	2
auto[1]	values[5]	values[5]	9	1			T167	2		T198	1		T181	1
auto[1]	values[5]	values[6]	22	1			T41	2		T43	1		T54	4
auto[1]	values[5]	values[7]	15	1			T43	2		T193	1		T175	2
auto[1]	values[6]	values[0]	17	1			T41	1		T252	1		T135	2
auto[1]	values[6]	values[1]	3	1			T255	2		T254	1		-	-
auto[1]	values[6]	values[2]	11	1			T41	6		T257	3		T258	2
auto[1]	values[6]	values[3]	11	1			T33	2		T200	1		T259	1
auto[1]	values[6]	values[4]	5	1			T53	1		T54	1		T260	3
auto[1]	values[6]	values[5]	17	1			T47	2		T64	3		T185	1
auto[1]	values[6]	values[6]	12	1			T46	1		T261	1		T262	1
auto[1]	values[6]	values[7]	9	1			T22	3		T53	1		T244	2
auto[1]	values[7]	values[0]	18	1			T42	2		T22	3		T200	3
auto[1]	values[7]	values[1]	15	1			T48	1		T51	1		T238	1
auto[1]	values[7]	values[2]	18	1			T41	3		T64	1		T214	4
auto[1]	values[7]	values[3]	13	1			T151	2		T218	2		T263	3
auto[1]	values[7]	values[4]	14	1			T22	5		T264	1		T253	2
auto[1]	values[7]	values[5]	17	1			T47	2		T18	1		T51	3
auto[1]	values[7]	values[6]	10	1			T30	1		T54	2		T223	2
auto[1]	values[7]	values[7]	19	1			T18	1		T44	2		T30	2