Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	662	1			T10	4		T17	17		T19	14
all_values[1]	662	1			T10	4		T17	17		T19	14
all_values[2]	662	1			T10	4		T17	17		T19	14
all_values[3]	662	1			T10	4		T17	17		T19	14
all_values[4]	662	1			T10	4		T17	17		T19	14
all_values[5]	662	1			T10	4		T17	17		T19	14
all_values[6]	662	1			T10	4		T17	17		T19	14
all_values[7]	662	1			T10	4		T17	17		T19	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2803

1

T10

22

T17

73

T19

61

auto[1]

2493

1

T10

10

T17

63

T19

51

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2166

1

T10

15

T17

55

T19

47

auto[1]

3130

1

T10

17

T17

81

T19

65

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3067

1

T10

20

T17

76

T19

70

auto[1]

2229

1

T10

12

T17

60

T19

42

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	141	1			T10	2		T17	4		T19	6
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T10	1		T17	1		T19	1
all_values[0]	auto[0]	auto[1]	auto[0]	92	1			T17	2		T19	2		T44	1
all_values[0]	auto[0]	auto[1]	auto[1]	67	1			T17	3		T19	2		T21	3
all_values[0]	auto[1]	auto[0]	auto[1]	162	1			T17	5		T19	2		T44	3
all_values[0]	auto[1]	auto[1]	auto[1]	124	1			T10	1		T17	2		T19	1
all_values[1]	auto[0]	auto[0]	auto[0]	137	1			T17	1		T19	3		T44	3
all_values[1]	auto[0]	auto[0]	auto[1]	64	1			T10	1		T17	4		T19	2
all_values[1]	auto[0]	auto[1]	auto[0]	113	1			T10	1		T17	3		T19	2
all_values[1]	auto[0]	auto[1]	auto[1]	63	1			T10	1		T17	1		T19	1
all_values[1]	auto[1]	auto[0]	auto[1]	150	1			T10	1		T17	4		T19	2
all_values[1]	auto[1]	auto[1]	auto[1]	135	1			T17	4		T19	4		T44	2
all_values[2]	auto[0]	auto[0]	auto[0]	159	1			T17	6		T44	2		T21	3
all_values[2]	auto[0]	auto[0]	auto[1]	55	1			T17	2		T19	2		T21	1
all_values[2]	auto[0]	auto[1]	auto[0]	108	1			T10	1		T17	1		T19	4
all_values[2]	auto[0]	auto[1]	auto[1]	73	1			T19	1		T44	2		T21	5
all_values[2]	auto[1]	auto[0]	auto[1]	141	1			T10	1		T17	6		T19	3
all_values[2]	auto[1]	auto[1]	auto[1]	126	1			T10	2		T17	2		T19	4
all_values[3]	auto[0]	auto[0]	auto[0]	146	1			T10	2		T17	5		T19	2
all_values[3]	auto[0]	auto[0]	auto[1]	56	1			T17	2		T21	2		T30	2
all_values[3]	auto[0]	auto[1]	auto[0]	113	1			T10	2		T17	4		T19	3
all_values[3]	auto[0]	auto[1]	auto[1]	61	1			T19	2		T44	1		T21	1
all_values[3]	auto[1]	auto[0]	auto[1]	147	1			T17	2		T44	4		T30	1
all_values[3]	auto[1]	auto[1]	auto[1]	139	1			T17	4		T19	7		T44	3
all_values[4]	auto[0]	auto[0]	auto[0]	145	1			T10	1		T17	4		T19	6
all_values[4]	auto[0]	auto[0]	auto[1]	61	1			T19	3		T153	3		T33	1
all_values[4]	auto[0]	auto[1]	auto[0]	103	1			T10	1		T17	3		T19	1
all_values[4]	auto[0]	auto[1]	auto[1]	77	1			T10	1		T17	4		T19	2
all_values[4]	auto[1]	auto[0]	auto[1]	142	1			T10	1		T17	5		T19	2
all_values[4]	auto[1]	auto[1]	auto[1]	134	1			T17	1		T44	2		T21	8
all_values[5]	auto[0]	auto[0]	auto[0]	195	1			T10	1		T17	3		T19	6
all_values[5]	auto[0]	auto[1]	auto[0]	198	1			T17	5		T19	5		T44	2
all_values[5]	auto[1]	auto[0]	auto[1]	121	1			T10	3		T17	5		T19	1
all_values[5]	auto[1]	auto[1]	auto[1]	148	1			T17	4		T19	2		T44	2
all_values[6]	auto[0]	auto[0]	auto[0]	136	1			T10	3		T17	6		T19	2
all_values[6]	auto[0]	auto[0]	auto[1]	69	1			T19	3		T44	1		T30	2
all_values[6]	auto[0]	auto[1]	auto[0]	107	1			T17	3		T19	1		T21	8
all_values[6]	auto[0]	auto[1]	auto[1]	68	1			T17	1		T44	2		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	133	1			T10	1		T17	3		T19	5
all_values[6]	auto[1]	auto[1]	auto[1]	149	1			T17	4		T19	3		T44	3
all_values[7]	auto[0]	auto[0]	auto[0]	160	1			T10	1		T19	3		T44	1
all_values[7]	auto[0]	auto[0]	auto[1]	53	1			T10	1		T19	2		T44	3
all_values[7]	auto[0]	auto[1]	auto[0]	113	1			T17	5		T19	1		T44	1
all_values[7]	auto[0]	auto[1]	auto[1]	58	1			T17	3		T19	2		T44	1
all_values[7]	auto[1]	auto[0]	auto[1]	154	1			T10	2		T17	5		T19	5
all_values[7]	auto[1]	auto[1]	auto[1]	124	1			T17	4		T19	1		T44	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal