Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1892

1

T4

5

T5

8

T10

3

auto[1]

1892

1

T4

4

T5

11

T10

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2151

1

T4

7

T5

14

T10

5

auto[1]

1633

1

T4

2

T5

5

T26

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2961

1

T4

8

T5

12

T10

2

auto[1]

823

1

T4

1

T5

7

T10

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	749	1			T4	2		T5	8		T10	1
valid[1]	750	1			T4	3		T5	1		T11	1
valid[2]	766	1			T4	1		T5	5		T10	1
valid[3]	733	1			T4	2		T5	2		T10	2
valid[4]	786	1			T4	1		T5	3		T10	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	139	1			T4	2		T5	2		T10	1
auto[0]	auto[0]	valid[0]	auto[1]	144	1			T5	1		T26	1		T27	2
auto[0]	auto[0]	valid[1]	auto[0]	123	1			T4	1		T12	1		T13	1
auto[0]	auto[0]	valid[1]	auto[1]	165	1			T27	6		T88	3		T130	3
auto[0]	auto[0]	valid[2]	auto[0]	124	1			T12	3		T13	2		T26	2
auto[0]	auto[0]	valid[2]	auto[1]	165	1			T27	3		T87	3		T88	5
auto[0]	auto[0]	valid[3]	auto[0]	143	1			T4	1		T10	1		T11	2
auto[0]	auto[0]	valid[3]	auto[1]	172	1			T27	7		T87	4		T88	4
auto[0]	auto[0]	valid[4]	auto[0]	133	1			T11	2		T12	1		T13	2
auto[0]	auto[0]	valid[4]	auto[1]	166	1			T4	1		T26	1		T27	3
auto[0]	auto[1]	valid[0]	auto[0]	131	1			T5	1		T11	1		T13	2
auto[0]	auto[1]	valid[0]	auto[1]	175	1			T5	2		T27	4		T87	2
auto[0]	auto[1]	valid[1]	auto[0]	138	1			T4	1		T11	1		T12	1
auto[0]	auto[1]	valid[1]	auto[1]	176	1			T4	1		T27	2		T87	2
auto[0]	auto[1]	valid[2]	auto[0]	138	1			T4	1		T5	2		T11	2
auto[0]	auto[1]	valid[2]	auto[1]	152	1			T27	2		T87	1		T88	2
auto[0]	auto[1]	valid[3]	auto[0]	124	1			T5	1		T11	1		T12	1
auto[0]	auto[1]	valid[3]	auto[1]	144	1			T5	1		T26	1		T27	2
auto[0]	auto[1]	valid[4]	auto[0]	135	1			T5	1		T11	1		T12	1
auto[0]	auto[1]	valid[4]	auto[1]	174	1			T5	1		T26	1		T27	8
auto[1]	auto[0]	valid[0]	auto[0]	79	1			T5	2		T11	1		T26	3
auto[1]	auto[0]	valid[1]	auto[0]	75	1			T26	2		T29	1		T52	1
auto[1]	auto[0]	valid[2]	auto[0]	101	1			T5	3		T13	1		T26	1
auto[1]	auto[0]	valid[3]	auto[0]	77	1			T18	2		T60	1		T19	1
auto[1]	auto[0]	valid[4]	auto[0]	86	1			T10	1		T11	1		T13	2
auto[1]	auto[1]	valid[0]	auto[0]	81	1			T12	1		T52	1		T18	1
auto[1]	auto[1]	valid[1]	auto[0]	73	1			T5	1		T13	1		T26	2
auto[1]	auto[1]	valid[2]	auto[0]	86	1			T10	1		T13	1		T26	2
auto[1]	auto[1]	valid[3]	auto[0]	73	1			T4	1		T10	1		T12	3
auto[1]	auto[1]	valid[4]	auto[0]	92	1			T5	1		T11	1		T12	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal