Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52536

1

T4

243

T5

447

T6

1

auto[1]

16742

1

T4

65

T5

92

T10

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50214

1

T4

216

T5

347

T6

1

auto[1]

19064

1

T4

92

T5

192

T10

34

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35631	1			T4	154		T5	283		T6	1
others[1]	5945	1			T4	25		T5	42		T10	6
others[2]	5847	1			T4	31		T5	45		T10	8
others[3]	6632	1			T4	32		T5	64		T10	14
interest[1]	3798	1			T4	21		T5	28		T10	3
interest[4]	23364	1			T4	96		T5	188		T6	1
interest[64]	11425	1			T4	45		T5	77		T10	19

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17005	1			T4	79		T5	140		T6	1
auto[0]	auto[0]	others[1]	2864	1			T4	10		T5	19		T10	6
auto[0]	auto[0]	others[2]	2853	1			T4	14		T5	24		T10	7
auto[0]	auto[0]	others[3]	3288	1			T4	13		T5	26		T10	10
auto[0]	auto[0]	interest[1]	1821	1			T4	7		T5	15		T10	2
auto[0]	auto[0]	interest[4]	11082	1			T4	48		T5	93		T6	1
auto[0]	auto[0]	interest[64]	5641	1			T4	28		T5	31		T10	13
auto[0]	auto[1]	others[0]	8849	1			T4	30		T5	47		T10	4
auto[0]	auto[1]	others[1]	1413	1			T4	5		T5	8		T26	6
auto[0]	auto[1]	others[2]	1379	1			T4	9		T5	8		T26	5
auto[0]	auto[1]	others[3]	1527	1			T4	9		T5	14		T26	7
auto[0]	auto[1]	interest[1]	883	1			T4	6		T5	4		T26	2
auto[0]	auto[1]	interest[4]	5857	1			T4	20		T5	30		T10	3
auto[0]	auto[1]	interest[64]	2691	1			T4	6		T5	11		T26	5
auto[1]	auto[0]	others[0]	9777	1			T4	45		T5	96		T10	22
auto[1]	auto[0]	others[1]	1668	1			T4	10		T5	15		T11	17
auto[1]	auto[0]	others[2]	1615	1			T4	8		T5	13		T10	1
auto[1]	auto[0]	others[3]	1817	1			T4	10		T5	24		T10	4
auto[1]	auto[0]	interest[1]	1094	1			T4	8		T5	9		T10	1
auto[1]	auto[0]	interest[4]	6425	1			T4	28		T5	65		T10	16
auto[1]	auto[0]	interest[64]	3093	1			T4	11		T5	35		T10	6

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal