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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1149
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T1039 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3542644406 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:54 PM PDT 24 36652609 ps
T119 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4039959033 Jul 17 05:24:21 PM PDT 24 Jul 17 05:24:25 PM PDT 24 206847518 ps
T1040 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3473196750 Jul 17 05:24:08 PM PDT 24 Jul 17 05:24:10 PM PDT 24 22025628 ps
T103 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1601940895 Jul 17 05:23:49 PM PDT 24 Jul 17 05:23:54 PM PDT 24 220511832 ps
T113 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3755137412 Jul 17 05:23:37 PM PDT 24 Jul 17 05:23:41 PM PDT 24 105115203 ps
T1041 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1938375694 Jul 17 05:25:44 PM PDT 24 Jul 17 05:25:46 PM PDT 24 12889034 ps
T120 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3759248350 Jul 17 05:23:40 PM PDT 24 Jul 17 05:23:42 PM PDT 24 47977776 ps
T121 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1672159311 Jul 17 05:23:35 PM PDT 24 Jul 17 05:23:59 PM PDT 24 326547004 ps
T122 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2244828434 Jul 17 05:23:34 PM PDT 24 Jul 17 05:23:37 PM PDT 24 52839106 ps
T1042 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1055239219 Jul 17 05:23:53 PM PDT 24 Jul 17 05:23:56 PM PDT 24 14348129 ps
T107 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1092766903 Jul 17 05:24:58 PM PDT 24 Jul 17 05:25:03 PM PDT 24 162286904 ps
T1043 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.139834649 Jul 17 05:23:34 PM PDT 24 Jul 17 05:23:36 PM PDT 24 14717470 ps
T1044 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.504557910 Jul 17 05:24:05 PM PDT 24 Jul 17 05:24:08 PM PDT 24 106967941 ps
T123 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3175001437 Jul 17 05:24:22 PM PDT 24 Jul 17 05:24:26 PM PDT 24 75592132 ps
T1045 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4196608966 Jul 17 05:23:38 PM PDT 24 Jul 17 05:23:39 PM PDT 24 39093402 ps
T1046 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1708556726 Jul 17 05:24:02 PM PDT 24 Jul 17 05:24:05 PM PDT 24 13971974 ps
T1047 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1705687520 Jul 17 05:25:24 PM PDT 24 Jul 17 05:25:26 PM PDT 24 24208139 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2957979907 Jul 17 05:23:43 PM PDT 24 Jul 17 05:23:44 PM PDT 24 39392464 ps
T104 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1416313046 Jul 17 05:23:51 PM PDT 24 Jul 17 05:24:05 PM PDT 24 754736334 ps
T124 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2724768233 Jul 17 05:24:22 PM PDT 24 Jul 17 05:24:26 PM PDT 24 76629707 ps
T116 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1869187041 Jul 17 05:23:49 PM PDT 24 Jul 17 05:23:57 PM PDT 24 373967969 ps
T1049 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2341889531 Jul 17 05:25:03 PM PDT 24 Jul 17 05:25:08 PM PDT 24 641046552 ps
T1050 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1065268751 Jul 17 05:23:22 PM PDT 24 Jul 17 05:23:31 PM PDT 24 107546772 ps
T86 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.58551139 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:54 PM PDT 24 192098165 ps
T1051 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2793449606 Jul 17 05:25:38 PM PDT 24 Jul 17 05:25:40 PM PDT 24 38808142 ps
T111 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2592186963 Jul 17 05:23:52 PM PDT 24 Jul 17 05:23:58 PM PDT 24 135716751 ps
T1052 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1368442813 Jul 17 05:24:03 PM PDT 24 Jul 17 05:24:05 PM PDT 24 31724460 ps
T1053 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2275089831 Jul 17 05:25:04 PM PDT 24 Jul 17 05:25:07 PM PDT 24 31145663 ps
T1054 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2806993492 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:52 PM PDT 24 10693783 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1363667923 Jul 17 05:24:57 PM PDT 24 Jul 17 05:24:59 PM PDT 24 59513653 ps
T1056 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2400806962 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:53 PM PDT 24 19325918 ps
T1057 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2934961733 Jul 17 05:23:52 PM PDT 24 Jul 17 05:23:57 PM PDT 24 30048367 ps
T1058 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1544627816 Jul 17 05:25:29 PM PDT 24 Jul 17 05:25:31 PM PDT 24 23519262 ps
T1059 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3952955583 Jul 17 05:23:53 PM PDT 24 Jul 17 05:23:57 PM PDT 24 100488645 ps
T1060 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4081814534 Jul 17 05:24:36 PM PDT 24 Jul 17 05:24:38 PM PDT 24 42367052 ps
T1061 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1183374118 Jul 17 05:23:52 PM PDT 24 Jul 17 05:23:57 PM PDT 24 43369869 ps
T1062 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2301370952 Jul 17 05:23:49 PM PDT 24 Jul 17 05:23:51 PM PDT 24 98375169 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.474226169 Jul 17 05:23:35 PM PDT 24 Jul 17 05:23:38 PM PDT 24 92040879 ps
T1064 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3035043727 Jul 17 05:25:58 PM PDT 24 Jul 17 05:26:00 PM PDT 24 46290299 ps
T108 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3203162317 Jul 17 05:23:39 PM PDT 24 Jul 17 05:23:44 PM PDT 24 572903274 ps
T1065 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.7618939 Jul 17 05:25:34 PM PDT 24 Jul 17 05:25:36 PM PDT 24 48454882 ps
T1066 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1428483701 Jul 17 05:24:01 PM PDT 24 Jul 17 05:24:04 PM PDT 24 14190042 ps
T125 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1680387796 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:53 PM PDT 24 106304527 ps
T1067 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3778856191 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:54 PM PDT 24 74162379 ps
T161 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4038680509 Jul 17 05:24:30 PM PDT 24 Jul 17 05:24:39 PM PDT 24 403974399 ps
T1068 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1530810608 Jul 17 05:23:50 PM PDT 24 Jul 17 05:24:04 PM PDT 24 2182508052 ps
T1069 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.704613772 Jul 17 05:24:30 PM PDT 24 Jul 17 05:24:35 PM PDT 24 314872428 ps
T112 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1493495936 Jul 17 05:25:10 PM PDT 24 Jul 17 05:25:15 PM PDT 24 27583905 ps
T1070 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4224697238 Jul 17 05:26:52 PM PDT 24 Jul 17 05:26:58 PM PDT 24 87523428 ps
T126 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2356018281 Jul 17 05:24:54 PM PDT 24 Jul 17 05:24:58 PM PDT 24 99573229 ps
T1071 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3871377500 Jul 17 05:23:53 PM PDT 24 Jul 17 05:23:58 PM PDT 24 188794110 ps
T150 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2227952037 Jul 17 05:23:40 PM PDT 24 Jul 17 05:23:45 PM PDT 24 594883297 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2903229414 Jul 17 05:23:44 PM PDT 24 Jul 17 05:23:49 PM PDT 24 178668250 ps
T1073 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1698329052 Jul 17 05:23:40 PM PDT 24 Jul 17 05:23:45 PM PDT 24 319794056 ps
T109 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1860027467 Jul 17 05:25:06 PM PDT 24 Jul 17 05:25:09 PM PDT 24 65759078 ps
T1074 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1700848282 Jul 17 05:24:35 PM PDT 24 Jul 17 05:24:38 PM PDT 24 47065907 ps
T1075 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.47368510 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:56 PM PDT 24 225036972 ps
T143 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4250538269 Jul 17 05:23:51 PM PDT 24 Jul 17 05:24:12 PM PDT 24 938693082 ps
T1076 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.902775880 Jul 17 05:25:09 PM PDT 24 Jul 17 05:25:14 PM PDT 24 31512029 ps
T1077 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2228008634 Jul 17 05:23:52 PM PDT 24 Jul 17 05:23:58 PM PDT 24 351185579 ps
T1078 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2993651483 Jul 17 05:23:21 PM PDT 24 Jul 17 05:23:24 PM PDT 24 36448365 ps
T127 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.957745200 Jul 17 05:24:52 PM PDT 24 Jul 17 05:25:27 PM PDT 24 535342000 ps
T1079 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4281826737 Jul 17 05:23:49 PM PDT 24 Jul 17 05:23:53 PM PDT 24 98717766 ps
T1080 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4184181797 Jul 17 05:25:44 PM PDT 24 Jul 17 05:25:46 PM PDT 24 13994272 ps
T110 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.292475132 Jul 17 05:24:12 PM PDT 24 Jul 17 05:24:19 PM PDT 24 201089880 ps
T1081 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1453675900 Jul 17 05:24:04 PM PDT 24 Jul 17 05:24:06 PM PDT 24 66168248 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.971260382 Jul 17 05:23:49 PM PDT 24 Jul 17 05:23:54 PM PDT 24 57231015 ps
T1083 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2410052407 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:56 PM PDT 24 62439946 ps
T1084 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1287151474 Jul 17 05:24:31 PM PDT 24 Jul 17 05:24:34 PM PDT 24 190621275 ps
T160 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2689249085 Jul 17 05:23:45 PM PDT 24 Jul 17 05:23:52 PM PDT 24 210375218 ps
T158 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2742771141 Jul 17 05:23:52 PM PDT 24 Jul 17 05:23:59 PM PDT 24 62059373 ps
T1085 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2352997999 Jul 17 05:24:00 PM PDT 24 Jul 17 05:24:04 PM PDT 24 145062038 ps
T1086 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1407081917 Jul 17 05:24:18 PM PDT 24 Jul 17 05:24:20 PM PDT 24 20847233 ps
T144 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4210666507 Jul 17 05:24:06 PM PDT 24 Jul 17 05:24:14 PM PDT 24 487690135 ps
T1087 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.810610469 Jul 17 05:24:07 PM PDT 24 Jul 17 05:24:09 PM PDT 24 148971447 ps
T1088 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3437061524 Jul 17 05:25:32 PM PDT 24 Jul 17 05:25:35 PM PDT 24 98359016 ps
T1089 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3363418454 Jul 17 05:23:53 PM PDT 24 Jul 17 05:23:59 PM PDT 24 579406062 ps
T1090 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1177738862 Jul 17 05:24:01 PM PDT 24 Jul 17 05:24:05 PM PDT 24 226236550 ps
T1091 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2713905838 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:55 PM PDT 24 133502283 ps
T165 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1130191551 Jul 17 05:23:49 PM PDT 24 Jul 17 05:24:09 PM PDT 24 299505811 ps
T1092 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3616619868 Jul 17 05:23:52 PM PDT 24 Jul 17 05:23:58 PM PDT 24 188362296 ps
T163 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.427067438 Jul 17 05:23:35 PM PDT 24 Jul 17 05:23:53 PM PDT 24 574650157 ps
T145 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3251776406 Jul 17 05:24:57 PM PDT 24 Jul 17 05:25:23 PM PDT 24 2836128492 ps
T146 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1855493717 Jul 17 05:23:53 PM PDT 24 Jul 17 05:24:20 PM PDT 24 20564523764 ps
T1093 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1665379708 Jul 17 05:24:01 PM PDT 24 Jul 17 05:24:07 PM PDT 24 155279838 ps
T1094 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3387400777 Jul 17 05:23:44 PM PDT 24 Jul 17 05:23:46 PM PDT 24 12893041 ps
T147 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2488139784 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:55 PM PDT 24 587725506 ps
T149 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1978176132 Jul 17 05:24:30 PM PDT 24 Jul 17 05:24:34 PM PDT 24 267244880 ps
T1095 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3954595842 Jul 17 05:23:47 PM PDT 24 Jul 17 05:23:50 PM PDT 24 451953427 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1669852586 Jul 17 05:23:46 PM PDT 24 Jul 17 05:23:48 PM PDT 24 31809491 ps
T148 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2242242722 Jul 17 05:23:53 PM PDT 24 Jul 17 05:23:57 PM PDT 24 62226422 ps
T1097 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2481851126 Jul 17 05:25:18 PM PDT 24 Jul 17 05:25:20 PM PDT 24 14698920 ps
T1098 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4189862335 Jul 17 05:24:06 PM PDT 24 Jul 17 05:24:07 PM PDT 24 54948896 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3831662116 Jul 17 05:23:21 PM PDT 24 Jul 17 05:23:24 PM PDT 24 105839395 ps
T1100 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2791945229 Jul 17 05:23:59 PM PDT 24 Jul 17 05:24:01 PM PDT 24 16531577 ps
T1101 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.271863175 Jul 17 05:24:52 PM PDT 24 Jul 17 05:24:55 PM PDT 24 16026176 ps
T1102 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2716315893 Jul 17 05:24:00 PM PDT 24 Jul 17 05:24:03 PM PDT 24 89072415 ps
T1103 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3240846228 Jul 17 05:26:51 PM PDT 24 Jul 17 05:26:58 PM PDT 24 21578821 ps
T1104 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.17574458 Jul 17 05:23:50 PM PDT 24 Jul 17 05:24:05 PM PDT 24 1638355905 ps
T154 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3807239922 Jul 17 05:23:49 PM PDT 24 Jul 17 05:23:51 PM PDT 24 50216616 ps
T1105 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2295547491 Jul 17 05:23:53 PM PDT 24 Jul 17 05:24:00 PM PDT 24 70292753 ps
T1106 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3096927760 Jul 17 05:25:23 PM PDT 24 Jul 17 05:25:27 PM PDT 24 356181366 ps
T155 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1903738984 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:56 PM PDT 24 117470084 ps
T1107 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3196307273 Jul 17 05:23:52 PM PDT 24 Jul 17 05:23:57 PM PDT 24 133311276 ps
T1108 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2235290383 Jul 17 05:23:37 PM PDT 24 Jul 17 05:23:40 PM PDT 24 148662173 ps
T1109 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2774678804 Jul 17 05:24:22 PM PDT 24 Jul 17 05:24:28 PM PDT 24 366722197 ps
T1110 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1711939172 Jul 17 05:23:46 PM PDT 24 Jul 17 05:24:23 PM PDT 24 9347480654 ps
T162 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2947659439 Jul 17 05:25:13 PM PDT 24 Jul 17 05:25:29 PM PDT 24 409688126 ps
T1111 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3817122974 Jul 17 05:23:47 PM PDT 24 Jul 17 05:24:03 PM PDT 24 606522961 ps
T1112 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2992672864 Jul 17 05:24:08 PM PDT 24 Jul 17 05:24:10 PM PDT 24 37719793 ps
T1113 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1255575178 Jul 17 05:24:29 PM PDT 24 Jul 17 05:24:34 PM PDT 24 108248511 ps
T1114 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3791595372 Jul 17 05:23:52 PM PDT 24 Jul 17 05:23:55 PM PDT 24 41278069 ps
T1115 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2089775973 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:57 PM PDT 24 224419306 ps
T1116 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4147835864 Jul 17 05:24:05 PM PDT 24 Jul 17 05:24:07 PM PDT 24 15428901 ps
T1117 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1965559412 Jul 17 05:26:00 PM PDT 24 Jul 17 05:26:02 PM PDT 24 20301467 ps
T164 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.390639498 Jul 17 05:24:15 PM PDT 24 Jul 17 05:24:34 PM PDT 24 304641687 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3869960986 Jul 17 05:25:16 PM PDT 24 Jul 17 05:25:40 PM PDT 24 4229425679 ps
T1119 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2347416510 Jul 17 05:23:50 PM PDT 24 Jul 17 05:24:00 PM PDT 24 1226211234 ps
T1120 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1117084363 Jul 17 05:24:04 PM PDT 24 Jul 17 05:24:06 PM PDT 24 14106501 ps
T1121 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1509955387 Jul 17 05:23:35 PM PDT 24 Jul 17 05:23:48 PM PDT 24 199367551 ps
T1122 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3520905741 Jul 17 05:26:50 PM PDT 24 Jul 17 05:26:57 PM PDT 24 26008015 ps
T1123 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.536267347 Jul 17 05:23:48 PM PDT 24 Jul 17 05:24:10 PM PDT 24 927235659 ps
T159 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.497469667 Jul 17 05:23:52 PM PDT 24 Jul 17 05:23:58 PM PDT 24 127366081 ps
T1124 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1730255367 Jul 17 05:24:10 PM PDT 24 Jul 17 05:24:14 PM PDT 24 43653781 ps
T1125 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.611141795 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:55 PM PDT 24 255790085 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3575144048 Jul 17 05:23:43 PM PDT 24 Jul 17 05:23:46 PM PDT 24 139597776 ps
T1127 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4141863362 Jul 17 05:24:00 PM PDT 24 Jul 17 05:24:03 PM PDT 24 14078738 ps
T1128 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1431178185 Jul 17 05:24:13 PM PDT 24 Jul 17 05:24:15 PM PDT 24 50728173 ps
T1129 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4270598054 Jul 17 05:23:51 PM PDT 24 Jul 17 05:23:56 PM PDT 24 120119612 ps
T1130 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3775197187 Jul 17 05:23:53 PM PDT 24 Jul 17 05:23:57 PM PDT 24 131126189 ps
T1131 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.385522737 Jul 17 05:23:53 PM PDT 24 Jul 17 05:23:57 PM PDT 24 54692294 ps
T1132 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.813773736 Jul 17 05:23:40 PM PDT 24 Jul 17 05:24:04 PM PDT 24 5828643366 ps
T1133 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1575766516 Jul 17 05:24:03 PM PDT 24 Jul 17 05:24:05 PM PDT 24 82513533 ps
T1134 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4231540332 Jul 17 05:24:18 PM PDT 24 Jul 17 05:24:21 PM PDT 24 39306077 ps
T1135 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.942371897 Jul 17 05:24:15 PM PDT 24 Jul 17 05:24:18 PM PDT 24 63005684 ps
T1136 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1321355376 Jul 17 05:24:12 PM PDT 24 Jul 17 05:24:15 PM PDT 24 23745346 ps
T1137 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1531126798 Jul 17 05:23:49 PM PDT 24 Jul 17 05:24:14 PM PDT 24 3796484589 ps
T1138 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2668345227 Jul 17 05:23:50 PM PDT 24 Jul 17 05:23:54 PM PDT 24 13687327 ps
T1139 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.333895152 Jul 17 05:25:32 PM PDT 24 Jul 17 05:25:37 PM PDT 24 632782639 ps
T1140 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2504702755 Jul 17 05:24:00 PM PDT 24 Jul 17 05:24:03 PM PDT 24 22624451 ps
T1141 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.220221537 Jul 17 05:26:53 PM PDT 24 Jul 17 05:27:00 PM PDT 24 93511475 ps
T1142 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2250403921 Jul 17 05:23:37 PM PDT 24 Jul 17 05:23:40 PM PDT 24 152406654 ps
T1143 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2672355769 Jul 17 05:23:52 PM PDT 24 Jul 17 05:24:04 PM PDT 24 715637550 ps
T1144 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3372196600 Jul 17 05:25:32 PM PDT 24 Jul 17 05:25:55 PM PDT 24 917986391 ps
T1145 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2108961605 Jul 17 05:24:57 PM PDT 24 Jul 17 05:25:00 PM PDT 24 29388401 ps
T1146 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1881098813 Jul 17 05:23:39 PM PDT 24 Jul 17 05:23:44 PM PDT 24 53321901 ps
T1147 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4267948759 Jul 17 05:24:08 PM PDT 24 Jul 17 05:24:10 PM PDT 24 18559853 ps
T1148 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2371578764 Jul 17 05:24:31 PM PDT 24 Jul 17 05:24:34 PM PDT 24 111891789 ps
T1149 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1705026787 Jul 17 05:24:01 PM PDT 24 Jul 17 05:24:04 PM PDT 24 16751377 ps

Test location /workspace/coverage/default/49.spi_device_stress_all.1608708450
Short name T10
Test name
Test status
Simulation time 2386896802 ps
CPU time 54.01 seconds
Started Jul 17 05:31:17 PM PDT 24
Finished Jul 17 05:32:12 PM PDT 24
Peak memory 266448 kb
Host smart-6b6f1e31-6b14-41eb-97d6-456c1a441e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608708450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1608708450
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1979791297
Short name T41
Test name
Test status
Simulation time 35169197360 ps
CPU time 196.85 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:31:31 PM PDT 24
Peak memory 268180 kb
Host smart-4702beb5-4cc0-4596-8975-ff62ef878b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979791297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1979791297
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.781083415
Short name T12
Test name
Test status
Simulation time 3983928555 ps
CPU time 19.74 seconds
Started Jul 17 05:33:11 PM PDT 24
Finished Jul 17 05:33:32 PM PDT 24
Peak memory 221204 kb
Host smart-ad4f0287-2c41-4262-bee2-b135fb1b7c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781083415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.781083415
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2807270833
Short name T18
Test name
Test status
Simulation time 429206292447 ps
CPU time 694.39 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:40:54 PM PDT 24
Peak memory 284116 kb
Host smart-177d6023-4bdd-422b-a709-d84b3ed0acc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807270833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2807270833
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.779371671
Short name T115
Test name
Test status
Simulation time 575329029 ps
CPU time 3.71 seconds
Started Jul 17 05:24:00 PM PDT 24
Finished Jul 17 05:24:05 PM PDT 24
Peak memory 217628 kb
Host smart-fb3c9962-4987-420f-b207-44eaae900643
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779371671 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.779371671
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3603826513
Short name T19
Test name
Test status
Simulation time 19127365181 ps
CPU time 71.19 seconds
Started Jul 17 05:30:56 PM PDT 24
Finished Jul 17 05:32:09 PM PDT 24
Peak memory 250188 kb
Host smart-c26577cb-cda5-49be-bf8f-f29058c8fb96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603826513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3603826513
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.779677215
Short name T23
Test name
Test status
Simulation time 167997442515 ps
CPU time 680.29 seconds
Started Jul 17 05:27:46 PM PDT 24
Finished Jul 17 05:39:08 PM PDT 24
Peak memory 282928 kb
Host smart-5f4f6bf4-45c9-4bf1-a1ef-49823f2516be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779677215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.779677215
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2526341634
Short name T69
Test name
Test status
Simulation time 18208581 ps
CPU time 0.74 seconds
Started Jul 17 05:27:36 PM PDT 24
Finished Jul 17 05:27:38 PM PDT 24
Peak memory 217084 kb
Host smart-1e7ecb31-4005-466f-8864-abb5903fa86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526341634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2526341634
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3171366764
Short name T22
Test name
Test status
Simulation time 125516716293 ps
CPU time 886.75 seconds
Started Jul 17 05:29:06 PM PDT 24
Finished Jul 17 05:43:54 PM PDT 24
Peak memory 285988 kb
Host smart-b7d18032-735a-407c-a501-acab1d54dfe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171366764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3171366764
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3402676777
Short name T54
Test name
Test status
Simulation time 402233269447 ps
CPU time 849.79 seconds
Started Jul 17 05:28:38 PM PDT 24
Finished Jul 17 05:42:50 PM PDT 24
Peak memory 289412 kb
Host smart-0ad65ae3-99bc-4224-85ed-4e6cdcd9af77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402676777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3402676777
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.72468337
Short name T100
Test name
Test status
Simulation time 422578752 ps
CPU time 12.44 seconds
Started Jul 17 05:24:57 PM PDT 24
Finished Jul 17 05:25:10 PM PDT 24
Peak memory 215956 kb
Host smart-a7c6c57b-1d2b-49d2-b9af-7ef59821890d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72468337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_t
l_intg_err.72468337
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3649853521
Short name T133
Test name
Test status
Simulation time 45907079215 ps
CPU time 35.78 seconds
Started Jul 17 05:28:51 PM PDT 24
Finished Jul 17 05:29:28 PM PDT 24
Peak memory 242120 kb
Host smart-57ec9baa-c831-4833-82a2-a6edd8eae1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649853521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3649853521
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2087452381
Short name T68
Test name
Test status
Simulation time 31535864 ps
CPU time 0.72 seconds
Started Jul 17 05:28:02 PM PDT 24
Finished Jul 17 05:28:05 PM PDT 24
Peak memory 206340 kb
Host smart-927a2d32-795a-4f62-9a87-8c5c44c9e9d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087452381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2087452381
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3362203442
Short name T47
Test name
Test status
Simulation time 317485893084 ps
CPU time 598.2 seconds
Started Jul 17 05:28:33 PM PDT 24
Finished Jul 17 05:38:31 PM PDT 24
Peak memory 265696 kb
Host smart-1bf9cd79-539b-433a-a08f-9e974882829e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362203442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3362203442
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3119071155
Short name T21
Test name
Test status
Simulation time 3273140401 ps
CPU time 68.39 seconds
Started Jul 17 05:31:18 PM PDT 24
Finished Jul 17 05:32:28 PM PDT 24
Peak memory 257144 kb
Host smart-c795e639-7598-438e-b2f6-1671aff04d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119071155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3119071155
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.235905172
Short name T8
Test name
Test status
Simulation time 5228772746 ps
CPU time 98.03 seconds
Started Jul 17 05:28:53 PM PDT 24
Finished Jul 17 05:30:32 PM PDT 24
Peak memory 274248 kb
Host smart-acce53fa-17e9-4189-83e5-20472ae3bb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235905172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.235905172
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1092766903
Short name T107
Test name
Test status
Simulation time 162286904 ps
CPU time 4.17 seconds
Started Jul 17 05:24:58 PM PDT 24
Finished Jul 17 05:25:03 PM PDT 24
Peak memory 215748 kb
Host smart-91819e22-94a1-438f-8368-5e6df69d2efe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092766903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
092766903
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.58551139
Short name T86
Test name
Test status
Simulation time 192098165 ps
CPU time 1.47 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:54 PM PDT 24
Peak memory 217476 kb
Host smart-fbfbeca9-2a11-4d6c-9c49-c92ba0556ee6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58551139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
hw_reset.58551139
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.910814648
Short name T33
Test name
Test status
Simulation time 143979725076 ps
CPU time 294.35 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:35:16 PM PDT 24
Peak memory 271620 kb
Host smart-7964cc4d-ea8c-421f-b91c-a75b8893f805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910814648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.910814648
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2719624724
Short name T25
Test name
Test status
Simulation time 31588995 ps
CPU time 1.04 seconds
Started Jul 17 05:30:06 PM PDT 24
Finished Jul 17 05:30:07 PM PDT 24
Peak memory 218920 kb
Host smart-26802da9-5025-4218-a5e3-e39d0128845a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719624724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2719624724
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2948893228
Short name T179
Test name
Test status
Simulation time 83512424130 ps
CPU time 803.22 seconds
Started Jul 17 05:28:51 PM PDT 24
Finished Jul 17 05:42:16 PM PDT 24
Peak memory 259124 kb
Host smart-aea48743-d8f1-4770-86ef-569f93d84d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948893228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2948893228
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3237037854
Short name T72
Test name
Test status
Simulation time 146503643 ps
CPU time 1.1 seconds
Started Jul 17 05:29:34 PM PDT 24
Finished Jul 17 05:29:36 PM PDT 24
Peak memory 236320 kb
Host smart-08a4d135-c0c0-4ef1-a766-c2b9a78ef8a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237037854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3237037854
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.155312160
Short name T175
Test name
Test status
Simulation time 13143594901 ps
CPU time 161.23 seconds
Started Jul 17 05:31:34 PM PDT 24
Finished Jul 17 05:34:17 PM PDT 24
Peak memory 250904 kb
Host smart-4ed0c14a-30e1-48c5-8920-c2871dae5861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155312160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.155312160
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2759182900
Short name T44
Test name
Test status
Simulation time 24793330994 ps
CPU time 183.03 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:36:59 PM PDT 24
Peak memory 267640 kb
Host smart-c8f10659-4ba9-4d03-81eb-54a22dcf480a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759182900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2759182900
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3420064445
Short name T91
Test name
Test status
Simulation time 4822864276 ps
CPU time 38.26 seconds
Started Jul 17 05:29:07 PM PDT 24
Finished Jul 17 05:29:46 PM PDT 24
Peak memory 234280 kb
Host smart-013a1720-447f-4cf0-a7b3-80c9486061c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420064445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3420064445
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2589188928
Short name T151
Test name
Test status
Simulation time 3517418725 ps
CPU time 83.2 seconds
Started Jul 17 05:30:28 PM PDT 24
Finished Jul 17 05:31:54 PM PDT 24
Peak memory 251644 kb
Host smart-324cffe2-3c94-43d5-b5ea-efa45d9085fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589188928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2589188928
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2118880991
Short name T177
Test name
Test status
Simulation time 21435884963 ps
CPU time 101.43 seconds
Started Jul 17 05:28:26 PM PDT 24
Finished Jul 17 05:30:08 PM PDT 24
Peak memory 269064 kb
Host smart-96c73dde-ea49-47ce-a6d5-423ba9d150ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118880991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2118880991
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3456504577
Short name T20
Test name
Test status
Simulation time 18603576144 ps
CPU time 138.74 seconds
Started Jul 17 05:31:10 PM PDT 24
Finished Jul 17 05:33:30 PM PDT 24
Peak memory 258596 kb
Host smart-56bf988f-bd3e-469b-b373-c6aad2755507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456504577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3456504577
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.390639498
Short name T164
Test name
Test status
Simulation time 304641687 ps
CPU time 18.32 seconds
Started Jul 17 05:24:15 PM PDT 24
Finished Jul 17 05:24:34 PM PDT 24
Peak memory 215744 kb
Host smart-d2f8699c-e3ef-433d-b66f-774f4e1b63d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390639498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.390639498
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2731010393
Short name T240
Test name
Test status
Simulation time 54777802012 ps
CPU time 441.72 seconds
Started Jul 17 05:31:34 PM PDT 24
Finished Jul 17 05:38:57 PM PDT 24
Peak memory 264956 kb
Host smart-f3d7033b-5d89-480f-87c1-5b5225e36f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731010393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2731010393
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.910793191
Short name T251
Test name
Test status
Simulation time 123839159280 ps
CPU time 487.94 seconds
Started Jul 17 05:31:58 PM PDT 24
Finished Jul 17 05:40:07 PM PDT 24
Peak memory 314056 kb
Host smart-9a380dc1-bea6-4332-bbfd-e6991524f9a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910793191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.910793191
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3137334188
Short name T5
Test name
Test status
Simulation time 15013816783 ps
CPU time 48.37 seconds
Started Jul 17 05:30:29 PM PDT 24
Finished Jul 17 05:31:19 PM PDT 24
Peak memory 225488 kb
Host smart-9f347d70-aaab-4273-8eee-d690bf634ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137334188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3137334188
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2742771141
Short name T158
Test name
Test status
Simulation time 62059373 ps
CPU time 3.95 seconds
Started Jul 17 05:23:52 PM PDT 24
Finished Jul 17 05:23:59 PM PDT 24
Peak memory 215588 kb
Host smart-3c4a2e70-7382-4316-8fb3-b97c825cf00d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742771141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2742771141
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1376252996
Short name T46
Test name
Test status
Simulation time 285778985285 ps
CPU time 210.07 seconds
Started Jul 17 05:27:45 PM PDT 24
Finished Jul 17 05:31:17 PM PDT 24
Peak memory 256644 kb
Host smart-530a21fe-40a5-4ec0-befa-d0e2b8e6c7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376252996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1376252996
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1379697119
Short name T271
Test name
Test status
Simulation time 2007759393 ps
CPU time 8.72 seconds
Started Jul 17 05:28:57 PM PDT 24
Finished Jul 17 05:29:07 PM PDT 24
Peak memory 225576 kb
Host smart-ca8418ed-378b-4ea5-b4cd-1e5a0e9d53d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379697119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1379697119
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1245672502
Short name T198
Test name
Test status
Simulation time 62844317012 ps
CPU time 447.84 seconds
Started Jul 17 05:34:11 PM PDT 24
Finished Jul 17 05:41:43 PM PDT 24
Peak memory 251696 kb
Host smart-4b30db68-578a-457d-a22c-e7cd05fe1772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245672502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1245672502
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3736178830
Short name T239
Test name
Test status
Simulation time 123832438652 ps
CPU time 117.38 seconds
Started Jul 17 05:29:31 PM PDT 24
Finished Jul 17 05:31:29 PM PDT 24
Peak memory 268268 kb
Host smart-74b1d1a8-0563-4ff7-846f-4588e0d91f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736178830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3736178830
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1855493717
Short name T146
Test name
Test status
Simulation time 20564523764 ps
CPU time 24.41 seconds
Started Jul 17 05:23:53 PM PDT 24
Finished Jul 17 05:24:20 PM PDT 24
Peak memory 215580 kb
Host smart-369ab1e9-23d8-41e0-9b53-b16565f02a44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855493717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1855493717
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2653952993
Short name T176
Test name
Test status
Simulation time 9433064168 ps
CPU time 137.41 seconds
Started Jul 17 05:28:11 PM PDT 24
Finished Jul 17 05:30:33 PM PDT 24
Peak memory 258632 kb
Host smart-0d4ee6bf-04d4-49d8-bf80-8fcfe691181f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653952993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2653952993
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3305104045
Short name T280
Test name
Test status
Simulation time 142863382182 ps
CPU time 278.08 seconds
Started Jul 17 05:28:20 PM PDT 24
Finished Jul 17 05:32:59 PM PDT 24
Peak memory 258596 kb
Host smart-c4b02640-fe4f-4a00-9e0c-5b171acc283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305104045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3305104045
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2605686180
Short name T535
Test name
Test status
Simulation time 18913349518 ps
CPU time 163.81 seconds
Started Jul 17 05:30:27 PM PDT 24
Finished Jul 17 05:33:12 PM PDT 24
Peak memory 250428 kb
Host smart-a5fa9da7-9a25-4314-b594-f8b9dab9b282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605686180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2605686180
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.667981398
Short name T254
Test name
Test status
Simulation time 18568287971 ps
CPU time 184.72 seconds
Started Jul 17 05:29:29 PM PDT 24
Finished Jul 17 05:32:35 PM PDT 24
Peak memory 274200 kb
Host smart-aabadcd7-8f4d-491d-b575-faf3ec6f93be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667981398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.667981398
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3725497777
Short name T1006
Test name
Test status
Simulation time 593587903 ps
CPU time 4.29 seconds
Started Jul 17 05:28:05 PM PDT 24
Finished Jul 17 05:28:12 PM PDT 24
Peak memory 233680 kb
Host smart-c769f401-c97d-4e3a-a0a1-086c262b41af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725497777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3725497777
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1601940895
Short name T103
Test name
Test status
Simulation time 220511832 ps
CPU time 3.59 seconds
Started Jul 17 05:23:49 PM PDT 24
Finished Jul 17 05:23:54 PM PDT 24
Peak memory 215784 kb
Host smart-bd85cda3-a910-48fa-ab93-b2027e67ed72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601940895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1601940895
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2268177571
Short name T49
Test name
Test status
Simulation time 160218427 ps
CPU time 3.74 seconds
Started Jul 17 05:28:04 PM PDT 24
Finished Jul 17 05:28:09 PM PDT 24
Peak memory 233648 kb
Host smart-33e5da77-6527-4867-ae89-5e8f422f99b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268177571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2268177571
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1065268751
Short name T1050
Test name
Test status
Simulation time 107546772 ps
CPU time 7.31 seconds
Started Jul 17 05:23:22 PM PDT 24
Finished Jul 17 05:23:31 PM PDT 24
Peak memory 215480 kb
Host smart-555ef57f-c270-4727-99f3-21ad284edd08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065268751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1065268751
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3251776406
Short name T145
Test name
Test status
Simulation time 2836128492 ps
CPU time 24.67 seconds
Started Jul 17 05:24:57 PM PDT 24
Finished Jul 17 05:25:23 PM PDT 24
Peak memory 207336 kb
Host smart-9c7c34dd-df1d-4350-a123-e019a36ba03a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251776406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3251776406
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2993651483
Short name T1078
Test name
Test status
Simulation time 36448365 ps
CPU time 0.99 seconds
Started Jul 17 05:23:21 PM PDT 24
Finished Jul 17 05:23:24 PM PDT 24
Peak memory 207020 kb
Host smart-a79a3b96-6eb6-490b-89dc-909404f94267
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993651483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2993651483
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3639139821
Short name T101
Test name
Test status
Simulation time 95957449 ps
CPU time 2.92 seconds
Started Jul 17 05:23:20 PM PDT 24
Finished Jul 17 05:23:24 PM PDT 24
Peak memory 218316 kb
Host smart-24e8fe96-4761-4597-9098-866a96a69c78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639139821 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3639139821
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2108961605
Short name T1145
Test name
Test status
Simulation time 29388401 ps
CPU time 1.84 seconds
Started Jul 17 05:24:57 PM PDT 24
Finished Jul 17 05:25:00 PM PDT 24
Peak memory 215512 kb
Host smart-9945e3f2-0feb-4ea7-8df5-1292c755825d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108961605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
108961605
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1363667923
Short name T1055
Test name
Test status
Simulation time 59513653 ps
CPU time 0.71 seconds
Started Jul 17 05:24:57 PM PDT 24
Finished Jul 17 05:24:59 PM PDT 24
Peak memory 204316 kb
Host smart-78c1e5ce-4619-4cf5-8bdd-f652c61709b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363667923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
363667923
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3831662116
Short name T1099
Test name
Test status
Simulation time 105839395 ps
CPU time 1.77 seconds
Started Jul 17 05:23:21 PM PDT 24
Finished Jul 17 05:23:24 PM PDT 24
Peak memory 215548 kb
Host smart-80519a46-9860-4391-8e43-67258afe9001
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831662116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3831662116
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.650932668
Short name T1026
Test name
Test status
Simulation time 18380994 ps
CPU time 0.7 seconds
Started Jul 17 05:23:20 PM PDT 24
Finished Jul 17 05:23:22 PM PDT 24
Peak memory 203936 kb
Host smart-4b5ceff3-4402-42a9-ab73-367b401331ac
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650932668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.650932668
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.333895152
Short name T1139
Test name
Test status
Simulation time 632782639 ps
CPU time 4.18 seconds
Started Jul 17 05:25:32 PM PDT 24
Finished Jul 17 05:25:37 PM PDT 24
Peak memory 215772 kb
Host smart-3d2e5f6c-9ec9-41a0-9070-49adf071c2b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333895152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.333895152
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1672159311
Short name T121
Test name
Test status
Simulation time 326547004 ps
CPU time 22.52 seconds
Started Jul 17 05:23:35 PM PDT 24
Finished Jul 17 05:23:59 PM PDT 24
Peak memory 207184 kb
Host smart-83d17a31-d3b1-4b71-98e1-ec86ec656027
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672159311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1672159311
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.957745200
Short name T127
Test name
Test status
Simulation time 535342000 ps
CPU time 33.09 seconds
Started Jul 17 05:24:52 PM PDT 24
Finished Jul 17 05:25:27 PM PDT 24
Peak memory 215380 kb
Host smart-1dd62cba-dc0d-4e1c-bc00-6c562397ea9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957745200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.957745200
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2585774333
Short name T85
Test name
Test status
Simulation time 60895208 ps
CPU time 1.17 seconds
Started Jul 17 05:23:35 PM PDT 24
Finished Jul 17 05:23:37 PM PDT 24
Peak memory 207296 kb
Host smart-955d1ea7-55df-4365-8b7c-0077bd23221d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585774333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2585774333
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.474226169
Short name T1063
Test name
Test status
Simulation time 92040879 ps
CPU time 1.67 seconds
Started Jul 17 05:23:35 PM PDT 24
Finished Jul 17 05:23:38 PM PDT 24
Peak memory 215680 kb
Host smart-4f43bfe4-eb1b-4362-9e30-a30152078308
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474226169 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.474226169
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3175001437
Short name T123
Test name
Test status
Simulation time 75592132 ps
CPU time 1.23 seconds
Started Jul 17 05:24:22 PM PDT 24
Finished Jul 17 05:24:26 PM PDT 24
Peak memory 207316 kb
Host smart-c3664123-b916-4284-b94c-3523acf0430b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175001437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
175001437
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1422516395
Short name T1032
Test name
Test status
Simulation time 42754141 ps
CPU time 0.7 seconds
Started Jul 17 05:23:42 PM PDT 24
Finished Jul 17 05:23:43 PM PDT 24
Peak memory 204528 kb
Host smart-b527280a-6c94-4696-8b5a-e4e5d172b7eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422516395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
422516395
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3437061524
Short name T1088
Test name
Test status
Simulation time 98359016 ps
CPU time 2.29 seconds
Started Jul 17 05:25:32 PM PDT 24
Finished Jul 17 05:25:35 PM PDT 24
Peak memory 215764 kb
Host smart-7493778b-1e08-4bfb-a6e5-c82809d0b495
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437061524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3437061524
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4196608966
Short name T1045
Test name
Test status
Simulation time 39093402 ps
CPU time 0.67 seconds
Started Jul 17 05:23:38 PM PDT 24
Finished Jul 17 05:23:39 PM PDT 24
Peak memory 203872 kb
Host smart-d6b9a699-46ab-457d-97d5-d227a156aaa8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196608966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4196608966
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1730255367
Short name T1124
Test name
Test status
Simulation time 43653781 ps
CPU time 2.67 seconds
Started Jul 17 05:24:10 PM PDT 24
Finished Jul 17 05:24:14 PM PDT 24
Peak memory 215580 kb
Host smart-46b0642e-fedd-45af-932c-6f2fa19c45df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730255367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1730255367
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2171462787
Short name T98
Test name
Test status
Simulation time 134313397 ps
CPU time 2.04 seconds
Started Jul 17 05:25:08 PM PDT 24
Finished Jul 17 05:25:13 PM PDT 24
Peak memory 215600 kb
Host smart-db86498b-4caa-4d17-bb8e-2dc7b59a4c57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171462787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
171462787
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1509955387
Short name T1121
Test name
Test status
Simulation time 199367551 ps
CPU time 12.14 seconds
Started Jul 17 05:23:35 PM PDT 24
Finished Jul 17 05:23:48 PM PDT 24
Peak memory 215764 kb
Host smart-ddb13bb0-e60d-464f-89ea-a7df01f41346
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509955387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1509955387
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2228008634
Short name T1077
Test name
Test status
Simulation time 351185579 ps
CPU time 2.76 seconds
Started Jul 17 05:23:52 PM PDT 24
Finished Jul 17 05:23:58 PM PDT 24
Peak memory 216708 kb
Host smart-7368dc95-f939-4698-a41c-82f417fee2f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228008634 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2228008634
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1903738984
Short name T155
Test name
Test status
Simulation time 117470084 ps
CPU time 2.65 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:56 PM PDT 24
Peak memory 207508 kb
Host smart-35eeab45-32d0-4af9-9f4a-d89b571dfd54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903738984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1903738984
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1063148087
Short name T1031
Test name
Test status
Simulation time 79932909 ps
CPU time 0.73 seconds
Started Jul 17 05:23:52 PM PDT 24
Finished Jul 17 05:23:55 PM PDT 24
Peak memory 203896 kb
Host smart-7ea4f25e-036d-4a0b-a68c-8111a8f06252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063148087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1063148087
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2089775973
Short name T1115
Test name
Test status
Simulation time 224419306 ps
CPU time 3.95 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:57 PM PDT 24
Peak memory 215388 kb
Host smart-0644d3a6-81d5-4ee6-9e1c-c63d024138af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089775973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2089775973
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2584104093
Short name T102
Test name
Test status
Simulation time 53868734 ps
CPU time 1.85 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:55 PM PDT 24
Peak memory 215708 kb
Host smart-fc2d2ea6-8d78-42f9-ab13-d0766c409042
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584104093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2584104093
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1869187041
Short name T116
Test name
Test status
Simulation time 373967969 ps
CPU time 6.78 seconds
Started Jul 17 05:23:49 PM PDT 24
Finished Jul 17 05:23:57 PM PDT 24
Peak memory 215884 kb
Host smart-1f1e0b05-9918-445d-b084-90fc42e83523
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869187041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1869187041
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.497469667
Short name T159
Test name
Test status
Simulation time 127366081 ps
CPU time 3.19 seconds
Started Jul 17 05:23:52 PM PDT 24
Finished Jul 17 05:23:58 PM PDT 24
Peak memory 218108 kb
Host smart-f562efb2-482e-4110-a91e-45ecf8d1fcd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497469667 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.497469667
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1872333076
Short name T117
Test name
Test status
Simulation time 46349713 ps
CPU time 1.32 seconds
Started Jul 17 05:23:48 PM PDT 24
Finished Jul 17 05:23:51 PM PDT 24
Peak memory 215536 kb
Host smart-d8802cf5-957b-42c8-ad50-dabdf4b1ed61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872333076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1872333076
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2806993492
Short name T1054
Test name
Test status
Simulation time 10693783 ps
CPU time 0.69 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:52 PM PDT 24
Peak memory 204304 kb
Host smart-e1a175af-61b3-47ae-871b-081b874e2c16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806993492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2806993492
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1183374118
Short name T1061
Test name
Test status
Simulation time 43369869 ps
CPU time 2.6 seconds
Started Jul 17 05:23:52 PM PDT 24
Finished Jul 17 05:23:57 PM PDT 24
Peak memory 215460 kb
Host smart-3e4e02c6-f635-4767-9c65-7c8d8ecbd343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183374118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1183374118
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1530810608
Short name T1068
Test name
Test status
Simulation time 2182508052 ps
CPU time 11.85 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:24:04 PM PDT 24
Peak memory 215644 kb
Host smart-be08d8ab-74d7-41f3-9d36-95abac9ca84b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530810608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1530810608
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4270598054
Short name T1129
Test name
Test status
Simulation time 120119612 ps
CPU time 1.67 seconds
Started Jul 17 05:23:51 PM PDT 24
Finished Jul 17 05:23:56 PM PDT 24
Peak memory 215568 kb
Host smart-7a37da6b-5297-4fab-991e-f51f883f00c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270598054 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4270598054
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.942371897
Short name T1135
Test name
Test status
Simulation time 63005684 ps
CPU time 1.89 seconds
Started Jul 17 05:24:15 PM PDT 24
Finished Jul 17 05:24:18 PM PDT 24
Peak memory 215560 kb
Host smart-2979a1f2-6293-4533-8b06-6c95796d2c36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942371897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.942371897
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3791595372
Short name T1114
Test name
Test status
Simulation time 41278069 ps
CPU time 0.75 seconds
Started Jul 17 05:23:52 PM PDT 24
Finished Jul 17 05:23:55 PM PDT 24
Peak memory 203920 kb
Host smart-c847142f-408f-4b81-9551-2c43f65a5704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791595372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3791595372
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3775197187
Short name T1130
Test name
Test status
Simulation time 131126189 ps
CPU time 2.08 seconds
Started Jul 17 05:23:53 PM PDT 24
Finished Jul 17 05:23:57 PM PDT 24
Peak memory 215508 kb
Host smart-9e5c5878-8c40-4242-b5b8-029ffccc2f12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775197187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3775197187
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3616619868
Short name T1092
Test name
Test status
Simulation time 188362296 ps
CPU time 3.24 seconds
Started Jul 17 05:23:52 PM PDT 24
Finished Jul 17 05:23:58 PM PDT 24
Peak memory 215732 kb
Host smart-d093e2a6-035d-4ae6-b6d8-b719c55746fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616619868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3616619868
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1531126798
Short name T1137
Test name
Test status
Simulation time 3796484589 ps
CPU time 23.32 seconds
Started Jul 17 05:23:49 PM PDT 24
Finished Jul 17 05:24:14 PM PDT 24
Peak memory 216932 kb
Host smart-b7212bd7-402a-45d5-8364-1221cc88c6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531126798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1531126798
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2341889531
Short name T1049
Test name
Test status
Simulation time 641046552 ps
CPU time 3.75 seconds
Started Jul 17 05:25:03 PM PDT 24
Finished Jul 17 05:25:08 PM PDT 24
Peak memory 217612 kb
Host smart-3e0dbe3a-66d8-4851-ab96-db7e17a0da48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341889531 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2341889531
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1978176132
Short name T149
Test name
Test status
Simulation time 267244880 ps
CPU time 1.62 seconds
Started Jul 17 05:24:30 PM PDT 24
Finished Jul 17 05:24:34 PM PDT 24
Peak memory 215544 kb
Host smart-4ad8d03a-cf12-487b-ba1f-0db17c4d530b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978176132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1978176132
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1407081917
Short name T1086
Test name
Test status
Simulation time 20847233 ps
CPU time 0.69 seconds
Started Jul 17 05:24:18 PM PDT 24
Finished Jul 17 05:24:20 PM PDT 24
Peak memory 203992 kb
Host smart-84e3abae-849c-447c-a879-5b3e5e3a1d67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407081917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1407081917
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3952955583
Short name T1059
Test name
Test status
Simulation time 100488645 ps
CPU time 1.82 seconds
Started Jul 17 05:23:53 PM PDT 24
Finished Jul 17 05:23:57 PM PDT 24
Peak memory 215524 kb
Host smart-4a8a04e3-a2ff-4639-9994-556eb947f4ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952955583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3952955583
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.385522737
Short name T1131
Test name
Test status
Simulation time 54692294 ps
CPU time 1.81 seconds
Started Jul 17 05:23:53 PM PDT 24
Finished Jul 17 05:23:57 PM PDT 24
Peak memory 215808 kb
Host smart-9994c7d8-aa04-4aa5-9267-6d0184a53600
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385522737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.385522737
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4250538269
Short name T143
Test name
Test status
Simulation time 938693082 ps
CPU time 18.19 seconds
Started Jul 17 05:23:51 PM PDT 24
Finished Jul 17 05:24:12 PM PDT 24
Peak memory 223680 kb
Host smart-3e99add7-9f33-4c55-884b-4f3e0c94964d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250538269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4250538269
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2242242722
Short name T148
Test name
Test status
Simulation time 62226422 ps
CPU time 1.73 seconds
Started Jul 17 05:23:53 PM PDT 24
Finished Jul 17 05:23:57 PM PDT 24
Peak memory 215576 kb
Host smart-0ff58e07-2af7-4564-9d97-a38f6acf97bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242242722 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2242242722
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4231540332
Short name T1134
Test name
Test status
Simulation time 39306077 ps
CPU time 1.35 seconds
Started Jul 17 05:24:18 PM PDT 24
Finished Jul 17 05:24:21 PM PDT 24
Peak memory 215560 kb
Host smart-2af36a35-eeb3-4311-adbe-c187fce0def9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231540332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4231540332
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2071930625
Short name T1028
Test name
Test status
Simulation time 25299012 ps
CPU time 0.76 seconds
Started Jul 17 05:24:18 PM PDT 24
Finished Jul 17 05:24:21 PM PDT 24
Peak memory 204020 kb
Host smart-1a86986a-e51c-43d1-8ea9-da21931b64d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071930625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2071930625
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2371578764
Short name T1148
Test name
Test status
Simulation time 111891789 ps
CPU time 1.82 seconds
Started Jul 17 05:24:31 PM PDT 24
Finished Jul 17 05:24:34 PM PDT 24
Peak memory 216716 kb
Host smart-f139ef9e-3eb1-4d74-be33-5057e99fc8ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371578764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2371578764
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1255575178
Short name T1113
Test name
Test status
Simulation time 108248511 ps
CPU time 3.57 seconds
Started Jul 17 05:24:29 PM PDT 24
Finished Jul 17 05:24:34 PM PDT 24
Peak memory 215796 kb
Host smart-ea25feea-9035-44d9-8dc8-851ebb2d4048
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255575178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1255575178
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.704613772
Short name T1069
Test name
Test status
Simulation time 314872428 ps
CPU time 2.58 seconds
Started Jul 17 05:24:30 PM PDT 24
Finished Jul 17 05:24:35 PM PDT 24
Peak memory 216752 kb
Host smart-7ecf94cc-2672-4fc6-8207-41409bbae7bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704613772 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.704613772
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2356018281
Short name T126
Test name
Test status
Simulation time 99573229 ps
CPU time 1.98 seconds
Started Jul 17 05:24:54 PM PDT 24
Finished Jul 17 05:24:58 PM PDT 24
Peak memory 215540 kb
Host smart-0a971e87-4080-4743-bc0f-68c0bb96f96d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356018281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2356018281
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2668345227
Short name T1138
Test name
Test status
Simulation time 13687327 ps
CPU time 0.75 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:54 PM PDT 24
Peak memory 203824 kb
Host smart-b0ce348f-1a90-4120-bdad-889d9d6a23bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668345227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2668345227
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3196307273
Short name T1107
Test name
Test status
Simulation time 133311276 ps
CPU time 2.12 seconds
Started Jul 17 05:23:52 PM PDT 24
Finished Jul 17 05:23:57 PM PDT 24
Peak memory 215492 kb
Host smart-b5e26498-c481-4bc0-8ec3-82f0a2279b91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196307273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3196307273
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2295547491
Short name T1105
Test name
Test status
Simulation time 70292753 ps
CPU time 4.27 seconds
Started Jul 17 05:23:53 PM PDT 24
Finished Jul 17 05:24:00 PM PDT 24
Peak memory 216840 kb
Host smart-d3bca054-d78c-423d-b069-a568b9f674a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295547491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2295547491
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2672355769
Short name T1143
Test name
Test status
Simulation time 715637550 ps
CPU time 9 seconds
Started Jul 17 05:23:52 PM PDT 24
Finished Jul 17 05:24:04 PM PDT 24
Peak memory 215960 kb
Host smart-9c115489-bf57-420c-9c4d-fce02dd9dab1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672355769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2672355769
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3787544394
Short name T114
Test name
Test status
Simulation time 1078695477 ps
CPU time 2.82 seconds
Started Jul 17 05:23:53 PM PDT 24
Finished Jul 17 05:23:58 PM PDT 24
Peak memory 217380 kb
Host smart-026a1066-3612-4a9f-808e-1d1c004915af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787544394 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3787544394
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1287151474
Short name T1084
Test name
Test status
Simulation time 190621275 ps
CPU time 1.22 seconds
Started Jul 17 05:24:31 PM PDT 24
Finished Jul 17 05:24:34 PM PDT 24
Peak memory 215544 kb
Host smart-9219afc7-0463-42d7-9040-292c15f9045c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287151474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1287151474
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1055239219
Short name T1042
Test name
Test status
Simulation time 14348129 ps
CPU time 0.76 seconds
Started Jul 17 05:23:53 PM PDT 24
Finished Jul 17 05:23:56 PM PDT 24
Peak memory 203976 kb
Host smart-68280fbd-1993-44ea-94ee-e20b55969c3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055239219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1055239219
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3363418454
Short name T1089
Test name
Test status
Simulation time 579406062 ps
CPU time 3.8 seconds
Started Jul 17 05:23:53 PM PDT 24
Finished Jul 17 05:23:59 PM PDT 24
Peak memory 215404 kb
Host smart-6a062f5d-e31a-4cad-a409-28a53f088adc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363418454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3363418454
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1665379708
Short name T1093
Test name
Test status
Simulation time 155279838 ps
CPU time 3.5 seconds
Started Jul 17 05:24:01 PM PDT 24
Finished Jul 17 05:24:07 PM PDT 24
Peak memory 217968 kb
Host smart-5e0927ca-edfb-4c17-9b1c-cfee3eb5eb6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665379708 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1665379708
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2793449606
Short name T1051
Test name
Test status
Simulation time 38808142 ps
CPU time 1.41 seconds
Started Jul 17 05:25:38 PM PDT 24
Finished Jul 17 05:25:40 PM PDT 24
Peak memory 215572 kb
Host smart-58d60fa3-e937-4818-ab75-312ab10c7a30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793449606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2793449606
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4189862335
Short name T1098
Test name
Test status
Simulation time 54948896 ps
CPU time 0.78 seconds
Started Jul 17 05:24:06 PM PDT 24
Finished Jul 17 05:24:07 PM PDT 24
Peak memory 203892 kb
Host smart-c955ad9a-4194-48c2-a16f-e59d97342f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189862335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4189862335
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.504557910
Short name T1044
Test name
Test status
Simulation time 106967941 ps
CPU time 1.95 seconds
Started Jul 17 05:24:05 PM PDT 24
Finished Jul 17 05:24:08 PM PDT 24
Peak memory 207220 kb
Host smart-2fa693b0-b913-4140-ae7f-354e8e2224cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504557910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.504557910
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3871377500
Short name T1071
Test name
Test status
Simulation time 188794110 ps
CPU time 2.11 seconds
Started Jul 17 05:23:53 PM PDT 24
Finished Jul 17 05:23:58 PM PDT 24
Peak memory 215720 kb
Host smart-4764fb74-54aa-4076-add5-ab16c9382920
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871377500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3871377500
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4038680509
Short name T161
Test name
Test status
Simulation time 403974399 ps
CPU time 6.55 seconds
Started Jul 17 05:24:30 PM PDT 24
Finished Jul 17 05:24:39 PM PDT 24
Peak memory 215476 kb
Host smart-d62ef21d-78c0-4085-9df3-1df43fab2081
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038680509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.4038680509
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.220221537
Short name T1141
Test name
Test status
Simulation time 93511475 ps
CPU time 2.73 seconds
Started Jul 17 05:26:53 PM PDT 24
Finished Jul 17 05:27:00 PM PDT 24
Peak memory 216640 kb
Host smart-883679fe-ff50-431f-97d0-7db90c4c76be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220221537 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.220221537
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3240846228
Short name T1103
Test name
Test status
Simulation time 21578821 ps
CPU time 1.47 seconds
Started Jul 17 05:26:51 PM PDT 24
Finished Jul 17 05:26:58 PM PDT 24
Peak memory 215496 kb
Host smart-eca3bba3-fc24-493c-a1fc-2804716b487b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240846228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3240846228
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1544627816
Short name T1058
Test name
Test status
Simulation time 23519262 ps
CPU time 0.79 seconds
Started Jul 17 05:25:29 PM PDT 24
Finished Jul 17 05:25:31 PM PDT 24
Peak memory 204300 kb
Host smart-faa35c3b-2811-4682-8e5d-09ee14d2c36b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544627816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1544627816
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1079562510
Short name T1025
Test name
Test status
Simulation time 165029174 ps
CPU time 2.01 seconds
Started Jul 17 05:23:59 PM PDT 24
Finished Jul 17 05:24:02 PM PDT 24
Peak memory 215544 kb
Host smart-71a442b4-abbf-4550-b1ba-3835d6d1f75c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079562510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1079562510
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1493495936
Short name T112
Test name
Test status
Simulation time 27583905 ps
CPU time 1.77 seconds
Started Jul 17 05:25:10 PM PDT 24
Finished Jul 17 05:25:15 PM PDT 24
Peak memory 215720 kb
Host smart-ceea12e0-76d5-4971-a46c-6b56509998de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493495936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1493495936
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2947659439
Short name T162
Test name
Test status
Simulation time 409688126 ps
CPU time 12.8 seconds
Started Jul 17 05:25:13 PM PDT 24
Finished Jul 17 05:25:29 PM PDT 24
Peak memory 215992 kb
Host smart-63c50fa7-2382-40cc-95cf-12fe6f597fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947659439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2947659439
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4039959033
Short name T119
Test name
Test status
Simulation time 206847518 ps
CPU time 1.28 seconds
Started Jul 17 05:24:21 PM PDT 24
Finished Jul 17 05:24:25 PM PDT 24
Peak memory 207308 kb
Host smart-8c045c78-a01c-4bc8-aecf-c5e15a04f356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039959033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4039959033
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4004995877
Short name T1038
Test name
Test status
Simulation time 52173816 ps
CPU time 0.73 seconds
Started Jul 17 05:25:09 PM PDT 24
Finished Jul 17 05:25:13 PM PDT 24
Peak memory 203948 kb
Host smart-9790a9a3-4eae-476e-989e-b7690e878a13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004995877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4004995877
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1177738862
Short name T1090
Test name
Test status
Simulation time 226236550 ps
CPU time 1.81 seconds
Started Jul 17 05:24:01 PM PDT 24
Finished Jul 17 05:24:05 PM PDT 24
Peak memory 215524 kb
Host smart-7efbf9a6-2d72-43e5-bac4-ce215d465ca1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177738862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1177738862
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2774678804
Short name T1109
Test name
Test status
Simulation time 366722197 ps
CPU time 4.18 seconds
Started Jul 17 05:24:22 PM PDT 24
Finished Jul 17 05:24:28 PM PDT 24
Peak memory 215904 kb
Host smart-a17db0ee-5a8c-428f-bb50-dbfd5a83b7aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774678804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2774678804
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4210666507
Short name T144
Test name
Test status
Simulation time 487690135 ps
CPU time 7.06 seconds
Started Jul 17 05:24:06 PM PDT 24
Finished Jul 17 05:24:14 PM PDT 24
Peak memory 215692 kb
Host smart-58f1c8e6-07a3-4051-9851-e1a1c6c35853
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210666507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4210666507
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3372196600
Short name T1144
Test name
Test status
Simulation time 917986391 ps
CPU time 21.73 seconds
Started Jul 17 05:25:32 PM PDT 24
Finished Jul 17 05:25:55 PM PDT 24
Peak memory 215784 kb
Host smart-9b3fcd40-ae99-4b87-abe9-4f5974867817
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372196600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3372196600
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1711939172
Short name T1110
Test name
Test status
Simulation time 9347480654 ps
CPU time 36.06 seconds
Started Jul 17 05:23:46 PM PDT 24
Finished Jul 17 05:24:23 PM PDT 24
Peak memory 207372 kb
Host smart-1cfc4cf1-40c0-4f2d-923d-3e0d28c70331
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711939172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1711939172
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3759248350
Short name T120
Test name
Test status
Simulation time 47977776 ps
CPU time 0.97 seconds
Started Jul 17 05:23:40 PM PDT 24
Finished Jul 17 05:23:42 PM PDT 24
Peak memory 207096 kb
Host smart-fb960105-dfd8-448c-b99b-6ab8efa50968
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759248350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3759248350
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3096927760
Short name T1106
Test name
Test status
Simulation time 356181366 ps
CPU time 2.82 seconds
Started Jul 17 05:25:23 PM PDT 24
Finished Jul 17 05:25:27 PM PDT 24
Peak memory 218168 kb
Host smart-60938c82-4ee8-4759-9788-73322f8717b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096927760 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3096927760
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2235290383
Short name T1108
Test name
Test status
Simulation time 148662173 ps
CPU time 2.37 seconds
Started Jul 17 05:23:37 PM PDT 24
Finished Jul 17 05:23:40 PM PDT 24
Peak memory 215428 kb
Host smart-d4004dd4-7cc8-430b-87b4-6232a3198e67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235290383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
235290383
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2748455765
Short name T1034
Test name
Test status
Simulation time 15518184 ps
CPU time 0.77 seconds
Started Jul 17 05:23:44 PM PDT 24
Finished Jul 17 05:23:45 PM PDT 24
Peak memory 204304 kb
Host smart-eeb598bb-3e66-4437-ad28-3500522b69a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748455765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
748455765
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1669852586
Short name T1096
Test name
Test status
Simulation time 31809491 ps
CPU time 1.3 seconds
Started Jul 17 05:23:46 PM PDT 24
Finished Jul 17 05:23:48 PM PDT 24
Peak memory 215520 kb
Host smart-b8436e33-9b15-44f3-896a-9ba8675c74e1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669852586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1669852586
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2957979907
Short name T1048
Test name
Test status
Simulation time 39392464 ps
CPU time 0.66 seconds
Started Jul 17 05:23:43 PM PDT 24
Finished Jul 17 05:23:44 PM PDT 24
Peak memory 204204 kb
Host smart-702ea162-a2b2-41fd-bc87-f2a966b83749
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957979907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2957979907
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2275089831
Short name T1053
Test name
Test status
Simulation time 31145663 ps
CPU time 1.7 seconds
Started Jul 17 05:25:04 PM PDT 24
Finished Jul 17 05:25:07 PM PDT 24
Peak memory 215524 kb
Host smart-66f50908-faba-443c-aa31-c0f5a6105217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275089831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2275089831
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2903229414
Short name T1072
Test name
Test status
Simulation time 178668250 ps
CPU time 4.44 seconds
Started Jul 17 05:23:44 PM PDT 24
Finished Jul 17 05:23:49 PM PDT 24
Peak memory 215736 kb
Host smart-a7452b54-03d1-4e96-acd0-b33d153ef4b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903229414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
903229414
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.813773736
Short name T1132
Test name
Test status
Simulation time 5828643366 ps
CPU time 22.5 seconds
Started Jul 17 05:23:40 PM PDT 24
Finished Jul 17 05:24:04 PM PDT 24
Peak memory 215608 kb
Host smart-bf43ad97-7db9-436e-b062-88560cb270e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813773736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.813773736
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3035043727
Short name T1064
Test name
Test status
Simulation time 46290299 ps
CPU time 0.72 seconds
Started Jul 17 05:25:58 PM PDT 24
Finished Jul 17 05:26:00 PM PDT 24
Peak memory 203920 kb
Host smart-562f6294-40d4-4a0c-84d8-cc009566dcff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035043727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3035043727
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2352997999
Short name T1085
Test name
Test status
Simulation time 145062038 ps
CPU time 0.76 seconds
Started Jul 17 05:24:00 PM PDT 24
Finished Jul 17 05:24:04 PM PDT 24
Peak memory 204304 kb
Host smart-aab3e60f-ce9d-4ee8-ba2a-a425106b2269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352997999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2352997999
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1700848282
Short name T1074
Test name
Test status
Simulation time 47065907 ps
CPU time 0.73 seconds
Started Jul 17 05:24:35 PM PDT 24
Finished Jul 17 05:24:38 PM PDT 24
Peak memory 204268 kb
Host smart-95ff02e3-11ee-429c-96b7-7054c1d7dfaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700848282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1700848282
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2648043118
Short name T1036
Test name
Test status
Simulation time 47836993 ps
CPU time 0.71 seconds
Started Jul 17 05:24:02 PM PDT 24
Finished Jul 17 05:24:04 PM PDT 24
Peak memory 203896 kb
Host smart-d6ce2f15-a9cf-4561-84b9-39c2b794c971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648043118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2648043118
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4224697238
Short name T1070
Test name
Test status
Simulation time 87523428 ps
CPU time 0.78 seconds
Started Jul 17 05:26:52 PM PDT 24
Finished Jul 17 05:26:58 PM PDT 24
Peak memory 203896 kb
Host smart-7a324d91-a206-475d-a1e6-6006a1b945a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224697238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4224697238
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1708556726
Short name T1046
Test name
Test status
Simulation time 13971974 ps
CPU time 0.72 seconds
Started Jul 17 05:24:02 PM PDT 24
Finished Jul 17 05:24:05 PM PDT 24
Peak memory 203956 kb
Host smart-5c0853aa-34ed-4f96-a4a0-c3ba3bcf96dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708556726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1708556726
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1575766516
Short name T1133
Test name
Test status
Simulation time 82513533 ps
CPU time 0.7 seconds
Started Jul 17 05:24:03 PM PDT 24
Finished Jul 17 05:24:05 PM PDT 24
Peak memory 203976 kb
Host smart-5e77b50c-728f-49a4-88fe-929166639936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575766516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1575766516
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4141863362
Short name T1127
Test name
Test status
Simulation time 14078738 ps
CPU time 0.72 seconds
Started Jul 17 05:24:00 PM PDT 24
Finished Jul 17 05:24:03 PM PDT 24
Peak memory 204288 kb
Host smart-b85fe116-a72e-414e-aa05-b8add3973304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141863362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4141863362
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1428483701
Short name T1066
Test name
Test status
Simulation time 14190042 ps
CPU time 0.71 seconds
Started Jul 17 05:24:01 PM PDT 24
Finished Jul 17 05:24:04 PM PDT 24
Peak memory 204208 kb
Host smart-aee99491-2281-49f4-a2b7-d46b5c988e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428483701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1428483701
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2791945229
Short name T1100
Test name
Test status
Simulation time 16531577 ps
CPU time 0.74 seconds
Started Jul 17 05:23:59 PM PDT 24
Finished Jul 17 05:24:01 PM PDT 24
Peak memory 203964 kb
Host smart-d66c7a2b-2b31-406b-ab79-71d6e0a6a9fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791945229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2791945229
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.536267347
Short name T1123
Test name
Test status
Simulation time 927235659 ps
CPU time 21.69 seconds
Started Jul 17 05:23:48 PM PDT 24
Finished Jul 17 05:24:10 PM PDT 24
Peak memory 207296 kb
Host smart-b8038aa6-ce3f-40dc-8b2c-a1e66e603f3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536267347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.536267347
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4118573688
Short name T118
Test name
Test status
Simulation time 1029255599 ps
CPU time 23.77 seconds
Started Jul 17 05:25:59 PM PDT 24
Finished Jul 17 05:26:24 PM PDT 24
Peak memory 207220 kb
Host smart-c7076cf3-fd04-4556-85ff-13d283d69797
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118573688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.4118573688
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2301370952
Short name T1062
Test name
Test status
Simulation time 98375169 ps
CPU time 1.67 seconds
Started Jul 17 05:23:49 PM PDT 24
Finished Jul 17 05:23:51 PM PDT 24
Peak memory 215712 kb
Host smart-2fdf1cc0-5c10-4761-8091-6812d795224d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301370952 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2301370952
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3575144048
Short name T1126
Test name
Test status
Simulation time 139597776 ps
CPU time 2.46 seconds
Started Jul 17 05:23:43 PM PDT 24
Finished Jul 17 05:23:46 PM PDT 24
Peak memory 215492 kb
Host smart-4cbb3d3b-cb5b-49fd-a461-76268992adab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575144048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
575144048
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2721323029
Short name T1033
Test name
Test status
Simulation time 13095403 ps
CPU time 0.77 seconds
Started Jul 17 05:24:29 PM PDT 24
Finished Jul 17 05:24:31 PM PDT 24
Peak memory 204272 kb
Host smart-aa2bccfb-54a1-43c8-ba60-99a765975e34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721323029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
721323029
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1965559412
Short name T1117
Test name
Test status
Simulation time 20301467 ps
CPU time 1.28 seconds
Started Jul 17 05:26:00 PM PDT 24
Finished Jul 17 05:26:02 PM PDT 24
Peak memory 215424 kb
Host smart-d301281a-9ef8-4907-88bb-15814a459428
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965559412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1965559412
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3007709646
Short name T1030
Test name
Test status
Simulation time 20255920 ps
CPU time 0.66 seconds
Started Jul 17 05:25:58 PM PDT 24
Finished Jul 17 05:26:00 PM PDT 24
Peak memory 203836 kb
Host smart-ad8db9d3-0ca5-4d4c-bef6-60aff5f3404e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007709646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3007709646
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3954595842
Short name T1095
Test name
Test status
Simulation time 451953427 ps
CPU time 3.13 seconds
Started Jul 17 05:23:47 PM PDT 24
Finished Jul 17 05:23:50 PM PDT 24
Peak memory 215464 kb
Host smart-dbbd92f1-1fd1-4173-b715-36ef89c51170
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954595842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3954595842
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1860027467
Short name T109
Test name
Test status
Simulation time 65759078 ps
CPU time 2.08 seconds
Started Jul 17 05:25:06 PM PDT 24
Finished Jul 17 05:25:09 PM PDT 24
Peak memory 215748 kb
Host smart-b7c26ee3-d7da-46d0-9b19-e39e31ddec6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860027467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
860027467
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3869960986
Short name T1118
Test name
Test status
Simulation time 4229425679 ps
CPU time 21.65 seconds
Started Jul 17 05:25:16 PM PDT 24
Finished Jul 17 05:25:40 PM PDT 24
Peak memory 215600 kb
Host smart-80347208-1de7-4bf4-9bbe-5bba7af898a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869960986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3869960986
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2716315893
Short name T1102
Test name
Test status
Simulation time 89072415 ps
CPU time 0.78 seconds
Started Jul 17 05:24:00 PM PDT 24
Finished Jul 17 05:24:03 PM PDT 24
Peak memory 204304 kb
Host smart-0f9fbc09-f9db-4d76-bb84-a914e7c8674d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716315893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2716315893
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4147835864
Short name T1116
Test name
Test status
Simulation time 15428901 ps
CPU time 0.71 seconds
Started Jul 17 05:24:05 PM PDT 24
Finished Jul 17 05:24:07 PM PDT 24
Peak memory 203960 kb
Host smart-7164ed78-5197-48dc-9d75-c1f04df5f415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147835864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4147835864
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1156997666
Short name T1029
Test name
Test status
Simulation time 16169272 ps
CPU time 0.68 seconds
Started Jul 17 05:24:07 PM PDT 24
Finished Jul 17 05:24:09 PM PDT 24
Peak memory 203884 kb
Host smart-8ab7346f-dc24-4da0-825a-4ff0361d3c36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156997666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1156997666
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2481851126
Short name T1097
Test name
Test status
Simulation time 14698920 ps
CPU time 0.69 seconds
Started Jul 17 05:25:18 PM PDT 24
Finished Jul 17 05:25:20 PM PDT 24
Peak memory 204228 kb
Host smart-0a147682-9a72-4b40-b4b0-d32aa08d566c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481851126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2481851126
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4081814534
Short name T1060
Test name
Test status
Simulation time 42367052 ps
CPU time 0.68 seconds
Started Jul 17 05:24:36 PM PDT 24
Finished Jul 17 05:24:38 PM PDT 24
Peak memory 204272 kb
Host smart-b88109f5-c6af-427b-a38a-aea74c058fed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081814534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4081814534
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1117084363
Short name T1120
Test name
Test status
Simulation time 14106501 ps
CPU time 0.74 seconds
Started Jul 17 05:24:04 PM PDT 24
Finished Jul 17 05:24:06 PM PDT 24
Peak memory 203988 kb
Host smart-eb2efb89-c2cb-4d21-8ce7-fb78e04da52d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117084363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1117084363
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2504702755
Short name T1140
Test name
Test status
Simulation time 22624451 ps
CPU time 0.71 seconds
Started Jul 17 05:24:00 PM PDT 24
Finished Jul 17 05:24:03 PM PDT 24
Peak memory 203884 kb
Host smart-72202621-c8df-4d01-ad97-ca0b76c87064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504702755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2504702755
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1705687520
Short name T1047
Test name
Test status
Simulation time 24208139 ps
CPU time 0.74 seconds
Started Jul 17 05:25:24 PM PDT 24
Finished Jul 17 05:25:26 PM PDT 24
Peak memory 204004 kb
Host smart-549e14d3-3aef-4d28-ba61-23e6ee46d4f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705687520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1705687520
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1938375694
Short name T1041
Test name
Test status
Simulation time 12889034 ps
CPU time 0.75 seconds
Started Jul 17 05:25:44 PM PDT 24
Finished Jul 17 05:25:46 PM PDT 24
Peak memory 204232 kb
Host smart-b4ddd43d-06b5-467e-8a7e-d7aedf7b3e93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938375694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1938375694
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.810610469
Short name T1087
Test name
Test status
Simulation time 148971447 ps
CPU time 0.71 seconds
Started Jul 17 05:24:07 PM PDT 24
Finished Jul 17 05:24:09 PM PDT 24
Peak memory 203976 kb
Host smart-025911b6-de75-469f-b316-c577b3abe929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810610469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.810610469
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3817122974
Short name T1111
Test name
Test status
Simulation time 606522961 ps
CPU time 15.59 seconds
Started Jul 17 05:23:47 PM PDT 24
Finished Jul 17 05:24:03 PM PDT 24
Peak memory 215536 kb
Host smart-461a0db8-fabf-467d-a706-50ceb8b7e0aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817122974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3817122974
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.17574458
Short name T1104
Test name
Test status
Simulation time 1638355905 ps
CPU time 13.17 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:24:05 PM PDT 24
Peak memory 207292 kb
Host smart-1b1c30f4-9adb-4d36-a763-319a15127a7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17574458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
bit_bash.17574458
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.883118074
Short name T84
Test name
Test status
Simulation time 535989953 ps
CPU time 1.39 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:53 PM PDT 24
Peak memory 207264 kb
Host smart-cc15f5b8-9245-4546-abc9-699a98f06a51
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883118074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.883118074
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3807239922
Short name T154
Test name
Test status
Simulation time 50216616 ps
CPU time 1.55 seconds
Started Jul 17 05:23:49 PM PDT 24
Finished Jul 17 05:23:51 PM PDT 24
Peak memory 215536 kb
Host smart-998abcfb-d100-4cc1-a0c5-c7773122bb19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807239922 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3807239922
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3542644406
Short name T1039
Test name
Test status
Simulation time 36652609 ps
CPU time 1.2 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:54 PM PDT 24
Peak memory 207288 kb
Host smart-a83a299c-bbcb-4d62-900f-213ec09d7b32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542644406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
542644406
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1321355376
Short name T1136
Test name
Test status
Simulation time 23745346 ps
CPU time 0.74 seconds
Started Jul 17 05:24:12 PM PDT 24
Finished Jul 17 05:24:15 PM PDT 24
Peak memory 204276 kb
Host smart-65eb09a7-10fd-43e0-8ef8-84a4adb71e61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321355376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
321355376
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1680387796
Short name T125
Test name
Test status
Simulation time 106304527 ps
CPU time 1.27 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:53 PM PDT 24
Peak memory 215492 kb
Host smart-873d7a0f-fa12-47e8-9059-3146d9004438
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680387796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1680387796
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1431178185
Short name T1128
Test name
Test status
Simulation time 50728173 ps
CPU time 0.66 seconds
Started Jul 17 05:24:13 PM PDT 24
Finished Jul 17 05:24:15 PM PDT 24
Peak memory 204184 kb
Host smart-c930f18d-116b-4eb0-a6ff-4633fa56304f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431178185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1431178185
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.971260382
Short name T1082
Test name
Test status
Simulation time 57231015 ps
CPU time 3.79 seconds
Started Jul 17 05:23:49 PM PDT 24
Finished Jul 17 05:23:54 PM PDT 24
Peak memory 215492 kb
Host smart-40187ce0-6860-4312-8cd6-ba42a793e0ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971260382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.971260382
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.292475132
Short name T110
Test name
Test status
Simulation time 201089880 ps
CPU time 5.14 seconds
Started Jul 17 05:24:12 PM PDT 24
Finished Jul 17 05:24:19 PM PDT 24
Peak memory 215692 kb
Host smart-472a47fc-13d2-4caa-839a-63fcb5c8d565
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292475132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.292475132
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1130191551
Short name T165
Test name
Test status
Simulation time 299505811 ps
CPU time 19.31 seconds
Started Jul 17 05:23:49 PM PDT 24
Finished Jul 17 05:24:09 PM PDT 24
Peak memory 215564 kb
Host smart-7ef0ef18-7dc2-4d15-9321-9401efee3a11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130191551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1130191551
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1368442813
Short name T1052
Test name
Test status
Simulation time 31724460 ps
CPU time 0.72 seconds
Started Jul 17 05:24:03 PM PDT 24
Finished Jul 17 05:24:05 PM PDT 24
Peak memory 203948 kb
Host smart-5a32473a-c8d9-4a22-9359-23c413ab3544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368442813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1368442813
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4267948759
Short name T1147
Test name
Test status
Simulation time 18559853 ps
CPU time 0.71 seconds
Started Jul 17 05:24:08 PM PDT 24
Finished Jul 17 05:24:10 PM PDT 24
Peak memory 203952 kb
Host smart-8debbd82-d3ce-433d-aec4-80719ce87a3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267948759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4267948759
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3473196750
Short name T1040
Test name
Test status
Simulation time 22025628 ps
CPU time 0.76 seconds
Started Jul 17 05:24:08 PM PDT 24
Finished Jul 17 05:24:10 PM PDT 24
Peak memory 203904 kb
Host smart-aac23b95-ca70-4bad-8ed4-47784daac701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473196750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3473196750
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.7618939
Short name T1065
Test name
Test status
Simulation time 48454882 ps
CPU time 0.76 seconds
Started Jul 17 05:25:34 PM PDT 24
Finished Jul 17 05:25:36 PM PDT 24
Peak memory 203984 kb
Host smart-f0b60736-4785-4971-8278-891ce2776a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7618939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.7618939
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2992672864
Short name T1112
Test name
Test status
Simulation time 37719793 ps
CPU time 0.71 seconds
Started Jul 17 05:24:08 PM PDT 24
Finished Jul 17 05:24:10 PM PDT 24
Peak memory 203952 kb
Host smart-30ccf108-2a9c-43d0-8468-7d7bf4a7e2d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992672864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2992672864
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1453675900
Short name T1081
Test name
Test status
Simulation time 66168248 ps
CPU time 0.77 seconds
Started Jul 17 05:24:04 PM PDT 24
Finished Jul 17 05:24:06 PM PDT 24
Peak memory 204024 kb
Host smart-a395deeb-bb68-45e2-a223-81ca5bd17d31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453675900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1453675900
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4184181797
Short name T1080
Test name
Test status
Simulation time 13994272 ps
CPU time 0.71 seconds
Started Jul 17 05:25:44 PM PDT 24
Finished Jul 17 05:25:46 PM PDT 24
Peak memory 204236 kb
Host smart-fab1df0b-3b30-4e19-8129-d6d1ec95431d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184181797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4184181797
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3520905741
Short name T1122
Test name
Test status
Simulation time 26008015 ps
CPU time 0.74 seconds
Started Jul 17 05:26:50 PM PDT 24
Finished Jul 17 05:26:57 PM PDT 24
Peak memory 203880 kb
Host smart-66c128cf-6afb-4757-91c7-d4873596d422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520905741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3520905741
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1705026787
Short name T1149
Test name
Test status
Simulation time 16751377 ps
CPU time 0.74 seconds
Started Jul 17 05:24:01 PM PDT 24
Finished Jul 17 05:24:04 PM PDT 24
Peak memory 203936 kb
Host smart-a770c81c-93ea-46ed-9445-8525bc36a3d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705026787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1705026787
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.606205547
Short name T1027
Test name
Test status
Simulation time 106754738 ps
CPU time 0.71 seconds
Started Jul 17 05:25:33 PM PDT 24
Finished Jul 17 05:25:35 PM PDT 24
Peak memory 204224 kb
Host smart-07d3a211-d28d-4270-945a-df2e323c237d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606205547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.606205547
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4281826737
Short name T1079
Test name
Test status
Simulation time 98717766 ps
CPU time 2.86 seconds
Started Jul 17 05:23:49 PM PDT 24
Finished Jul 17 05:23:53 PM PDT 24
Peak memory 216632 kb
Host smart-faf32442-df19-4539-82a2-f177728613a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281826737 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4281826737
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.611141795
Short name T1125
Test name
Test status
Simulation time 255790085 ps
CPU time 2.2 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:55 PM PDT 24
Peak memory 215476 kb
Host smart-cafb5d5d-14f8-4d14-955c-89cf1ba0a241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611141795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.611141795
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3765801621
Short name T1037
Test name
Test status
Simulation time 13414474 ps
CPU time 0.79 seconds
Started Jul 17 05:23:49 PM PDT 24
Finished Jul 17 05:23:51 PM PDT 24
Peak memory 203884 kb
Host smart-c036a454-44e6-42bb-9ca6-01ad77d087d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765801621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
765801621
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2410052407
Short name T1083
Test name
Test status
Simulation time 62439946 ps
CPU time 3.94 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:56 PM PDT 24
Peak memory 215524 kb
Host smart-2e5c8aad-56b4-42dc-8980-130357f4d353
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410052407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2410052407
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3705756331
Short name T105
Test name
Test status
Simulation time 230144615 ps
CPU time 2.79 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:56 PM PDT 24
Peak memory 215952 kb
Host smart-92cd8f39-9d71-435c-ba5b-6d270e8c13d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705756331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
705756331
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2347416510
Short name T1119
Test name
Test status
Simulation time 1226211234 ps
CPU time 7.58 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:24:00 PM PDT 24
Peak memory 215460 kb
Host smart-018d4e25-5b4c-4470-af8b-bf71b49a3d72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347416510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2347416510
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3755137412
Short name T113
Test name
Test status
Simulation time 105115203 ps
CPU time 3.7 seconds
Started Jul 17 05:23:37 PM PDT 24
Finished Jul 17 05:23:41 PM PDT 24
Peak memory 217456 kb
Host smart-c6a13eca-b6f1-4c23-808a-5d166a73bf2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755137412 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3755137412
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2244828434
Short name T122
Test name
Test status
Simulation time 52839106 ps
CPU time 1.92 seconds
Started Jul 17 05:23:34 PM PDT 24
Finished Jul 17 05:23:37 PM PDT 24
Peak memory 215564 kb
Host smart-e94d397d-d31f-4c94-b346-d35440bb13c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244828434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
244828434
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.271863175
Short name T1101
Test name
Test status
Simulation time 16026176 ps
CPU time 0.72 seconds
Started Jul 17 05:24:52 PM PDT 24
Finished Jul 17 05:24:55 PM PDT 24
Peak memory 203916 kb
Host smart-bff35fa2-b3a2-4c3e-a164-9c03462c9e47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271863175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.271863175
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3462526138
Short name T1035
Test name
Test status
Simulation time 193302327 ps
CPU time 4.38 seconds
Started Jul 17 05:24:29 PM PDT 24
Finished Jul 17 05:24:35 PM PDT 24
Peak memory 215540 kb
Host smart-31a3598f-a998-4ee8-8e94-eaa2418575ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462526138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3462526138
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2227952037
Short name T150
Test name
Test status
Simulation time 594883297 ps
CPU time 3.44 seconds
Started Jul 17 05:23:40 PM PDT 24
Finished Jul 17 05:23:45 PM PDT 24
Peak memory 215704 kb
Host smart-7766fac1-1b5c-4b12-907d-060b9d0ba1a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227952037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
227952037
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.427067438
Short name T163
Test name
Test status
Simulation time 574650157 ps
CPU time 17.1 seconds
Started Jul 17 05:23:35 PM PDT 24
Finished Jul 17 05:23:53 PM PDT 24
Peak memory 215520 kb
Host smart-622bbf01-1492-4aba-82b3-f83800817999
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427067438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.427067438
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1881098813
Short name T1146
Test name
Test status
Simulation time 53321901 ps
CPU time 3.56 seconds
Started Jul 17 05:23:39 PM PDT 24
Finished Jul 17 05:23:44 PM PDT 24
Peak memory 218556 kb
Host smart-6d421286-cc7e-48ea-9244-04de1dc5004c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881098813 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1881098813
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2724768233
Short name T124
Test name
Test status
Simulation time 76629707 ps
CPU time 1.9 seconds
Started Jul 17 05:24:22 PM PDT 24
Finished Jul 17 05:24:26 PM PDT 24
Peak memory 215704 kb
Host smart-5e947ba6-17f2-4622-a060-f0c79be29d75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724768233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
724768233
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.139834649
Short name T1043
Test name
Test status
Simulation time 14717470 ps
CPU time 0.74 seconds
Started Jul 17 05:23:34 PM PDT 24
Finished Jul 17 05:23:36 PM PDT 24
Peak memory 204300 kb
Host smart-e2c26983-faf9-4adc-816a-e17e9bfe5a33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139834649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.139834649
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1698329052
Short name T1073
Test name
Test status
Simulation time 319794056 ps
CPU time 3.98 seconds
Started Jul 17 05:23:40 PM PDT 24
Finished Jul 17 05:23:45 PM PDT 24
Peak memory 215484 kb
Host smart-c4ce3586-82f2-4e5c-9460-7fb72a96d59b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698329052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1698329052
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2250403921
Short name T1142
Test name
Test status
Simulation time 152406654 ps
CPU time 2.15 seconds
Started Jul 17 05:23:37 PM PDT 24
Finished Jul 17 05:23:40 PM PDT 24
Peak memory 216636 kb
Host smart-7b768d2e-bd91-4930-a0fe-6cbebe6248ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250403921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
250403921
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2689249085
Short name T160
Test name
Test status
Simulation time 210375218 ps
CPU time 6.37 seconds
Started Jul 17 05:23:45 PM PDT 24
Finished Jul 17 05:23:52 PM PDT 24
Peak memory 215980 kb
Host smart-a170a5b2-4ff8-4139-91bd-702b98681bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689249085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2689249085
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2713905838
Short name T1091
Test name
Test status
Simulation time 133502283 ps
CPU time 2.94 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:55 PM PDT 24
Peak memory 217976 kb
Host smart-6a52b9d0-7529-4df1-9d7f-7e7ef4764d7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713905838 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2713905838
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.902775880
Short name T1076
Test name
Test status
Simulation time 31512029 ps
CPU time 1.9 seconds
Started Jul 17 05:25:09 PM PDT 24
Finished Jul 17 05:25:14 PM PDT 24
Peak memory 207352 kb
Host smart-1b816929-076a-4af7-89ea-2abf0ddd7b37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902775880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.902775880
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3387400777
Short name T1094
Test name
Test status
Simulation time 12893041 ps
CPU time 0.76 seconds
Started Jul 17 05:23:44 PM PDT 24
Finished Jul 17 05:23:46 PM PDT 24
Peak memory 203952 kb
Host smart-9f9ed24c-bf6c-4ee0-8e3f-e89fbad07ad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387400777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
387400777
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2934961733
Short name T1057
Test name
Test status
Simulation time 30048367 ps
CPU time 1.87 seconds
Started Jul 17 05:23:52 PM PDT 24
Finished Jul 17 05:23:57 PM PDT 24
Peak memory 215480 kb
Host smart-64e42737-fed5-4393-a695-48622a60e467
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934961733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2934961733
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3203162317
Short name T108
Test name
Test status
Simulation time 572903274 ps
CPU time 3.81 seconds
Started Jul 17 05:23:39 PM PDT 24
Finished Jul 17 05:23:44 PM PDT 24
Peak memory 215728 kb
Host smart-50b2c541-7f6f-4329-81d1-69236e66f7a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203162317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
203162317
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4219254342
Short name T99
Test name
Test status
Simulation time 586193164 ps
CPU time 19.02 seconds
Started Jul 17 05:23:44 PM PDT 24
Finished Jul 17 05:24:04 PM PDT 24
Peak memory 215632 kb
Host smart-0a61da27-dad0-4927-a507-674b79b87023
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219254342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4219254342
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.47368510
Short name T1075
Test name
Test status
Simulation time 225036972 ps
CPU time 3.71 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:56 PM PDT 24
Peak memory 217236 kb
Host smart-4322c635-b30c-4eda-bcdb-fb734dc6d559
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47368510 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.47368510
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3778856191
Short name T1067
Test name
Test status
Simulation time 74162379 ps
CPU time 1.36 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:54 PM PDT 24
Peak memory 215460 kb
Host smart-a39bd393-74d7-44c9-b159-00c8b2c62837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778856191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
778856191
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2400806962
Short name T1056
Test name
Test status
Simulation time 19325918 ps
CPU time 0.71 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:53 PM PDT 24
Peak memory 203924 kb
Host smart-cfa1cc62-7cf0-42a2-ad23-0d7565c8caa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400806962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
400806962
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2488139784
Short name T147
Test name
Test status
Simulation time 587725506 ps
CPU time 2.93 seconds
Started Jul 17 05:23:50 PM PDT 24
Finished Jul 17 05:23:55 PM PDT 24
Peak memory 215536 kb
Host smart-d4676bcd-9240-4a8e-9990-9550fdefe645
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488139784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2488139784
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2592186963
Short name T111
Test name
Test status
Simulation time 135716751 ps
CPU time 3.23 seconds
Started Jul 17 05:23:52 PM PDT 24
Finished Jul 17 05:23:58 PM PDT 24
Peak memory 215564 kb
Host smart-5646a77e-0411-4b37-8af2-05d0acd10ce4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592186963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
592186963
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1416313046
Short name T104
Test name
Test status
Simulation time 754736334 ps
CPU time 11.69 seconds
Started Jul 17 05:23:51 PM PDT 24
Finished Jul 17 05:24:05 PM PDT 24
Peak memory 215520 kb
Host smart-adcd92fd-21cf-426b-acc2-0fad61e84e80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416313046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1416313046
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.452867135
Short name T534
Test name
Test status
Simulation time 23834972 ps
CPU time 0.73 seconds
Started Jul 17 05:30:10 PM PDT 24
Finished Jul 17 05:30:11 PM PDT 24
Peak memory 206548 kb
Host smart-1703f471-bdc3-48e1-9c01-3cb4b5e0a3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452867135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.452867135
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.869729297
Short name T827
Test name
Test status
Simulation time 86957351 ps
CPU time 2.3 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:30:24 PM PDT 24
Peak memory 224120 kb
Host smart-d0335add-a648-4675-afed-e0efdefd9559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869729297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.869729297
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.30768045
Short name T1022
Test name
Test status
Simulation time 78776102 ps
CPU time 0.82 seconds
Started Jul 17 05:27:44 PM PDT 24
Finished Jul 17 05:27:46 PM PDT 24
Peak memory 207396 kb
Host smart-ce8e7128-f4b2-47ed-8fd4-81091e40c842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30768045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.30768045
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.251701955
Short name T629
Test name
Test status
Simulation time 2158745305 ps
CPU time 18.49 seconds
Started Jul 17 05:27:46 PM PDT 24
Finished Jul 17 05:28:06 PM PDT 24
Peak memory 233896 kb
Host smart-eaf879d3-88b5-419c-9b5c-0aea58fa3497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251701955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.251701955
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2942759563
Short name T855
Test name
Test status
Simulation time 10509095167 ps
CPU time 85.24 seconds
Started Jul 17 05:29:55 PM PDT 24
Finished Jul 17 05:31:21 PM PDT 24
Peak memory 252644 kb
Host smart-d991c5a4-d0e4-4fc4-9081-49d3304fbf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942759563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2942759563
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2382115244
Short name T998
Test name
Test status
Simulation time 6214367430 ps
CPU time 29.51 seconds
Started Jul 17 05:29:55 PM PDT 24
Finished Jul 17 05:30:26 PM PDT 24
Peak memory 226008 kb
Host smart-e9b4d387-1cca-402c-bedb-e46e3e224c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382115244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2382115244
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2011460916
Short name T267
Test name
Test status
Simulation time 4014159847 ps
CPU time 24.51 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:30:46 PM PDT 24
Peak memory 237560 kb
Host smart-e47be8ca-cdc5-4a27-b1c8-75a829b752bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011460916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2011460916
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.354834685
Short name T491
Test name
Test status
Simulation time 11650455122 ps
CPU time 38.36 seconds
Started Jul 17 05:27:38 PM PDT 24
Finished Jul 17 05:28:18 PM PDT 24
Peak memory 253896 kb
Host smart-30ed6ac6-bab7-464e-af00-aceb61ed70e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354834685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
354834685
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3908400019
Short name T514
Test name
Test status
Simulation time 3923802150 ps
CPU time 4.3 seconds
Started Jul 17 05:27:48 PM PDT 24
Finished Jul 17 05:27:54 PM PDT 24
Peak memory 225652 kb
Host smart-ae761ac3-0a6a-4b4a-80de-cc35c6044b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908400019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3908400019
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1201180212
Short name T444
Test name
Test status
Simulation time 58580020 ps
CPU time 2.15 seconds
Started Jul 17 05:27:47 PM PDT 24
Finished Jul 17 05:27:52 PM PDT 24
Peak memory 224828 kb
Host smart-a78fca52-5464-41f8-ba5b-a72825fc6568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201180212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1201180212
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.633452423
Short name T466
Test name
Test status
Simulation time 2390794474 ps
CPU time 10.72 seconds
Started Jul 17 05:27:47 PM PDT 24
Finished Jul 17 05:28:00 PM PDT 24
Peak memory 233836 kb
Host smart-254e645b-571d-4a2a-894c-bd6e2083c658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633452423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
633452423
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.252360451
Short name T634
Test name
Test status
Simulation time 23282177163 ps
CPU time 13.51 seconds
Started Jul 17 05:29:30 PM PDT 24
Finished Jul 17 05:29:45 PM PDT 24
Peak memory 225680 kb
Host smart-ee2ae844-57de-473b-8d7b-0708a4305cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252360451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.252360451
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.274389654
Short name T996
Test name
Test status
Simulation time 3027708704 ps
CPU time 7.82 seconds
Started Jul 17 05:27:45 PM PDT 24
Finished Jul 17 05:27:55 PM PDT 24
Peak memory 220084 kb
Host smart-2868de1d-e8c9-4652-beaf-b5c9ad67e3c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=274389654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.274389654
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2901752550
Short name T529
Test name
Test status
Simulation time 959678889 ps
CPU time 4.5 seconds
Started Jul 17 05:29:42 PM PDT 24
Finished Jul 17 05:29:48 PM PDT 24
Peak memory 217352 kb
Host smart-98f7a75e-b8f4-4531-9b9c-b1109170cfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901752550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2901752550
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3106937568
Short name T773
Test name
Test status
Simulation time 2643118515 ps
CPU time 10.58 seconds
Started Jul 17 05:27:39 PM PDT 24
Finished Jul 17 05:27:51 PM PDT 24
Peak memory 217396 kb
Host smart-7cbf9459-4ba9-4326-ad92-444506d46d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106937568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3106937568
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3156769634
Short name T829
Test name
Test status
Simulation time 104892832 ps
CPU time 1.21 seconds
Started Jul 17 05:29:38 PM PDT 24
Finished Jul 17 05:29:40 PM PDT 24
Peak memory 208920 kb
Host smart-6249edb6-5a2c-498c-9062-6c7e2eccc965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156769634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3156769634
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2422057014
Short name T774
Test name
Test status
Simulation time 258909914 ps
CPU time 0.94 seconds
Started Jul 17 05:30:28 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 207236 kb
Host smart-7a57e9c2-512a-44b4-9e89-84c1b1e77e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422057014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2422057014
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.394256235
Short name T840
Test name
Test status
Simulation time 282490836 ps
CPU time 7.03 seconds
Started Jul 17 05:29:04 PM PDT 24
Finished Jul 17 05:29:12 PM PDT 24
Peak memory 233744 kb
Host smart-408792d3-1dc6-46cc-a26e-7c21ecfcb27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394256235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.394256235
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3177151922
Short name T804
Test name
Test status
Simulation time 72191255 ps
CPU time 0.73 seconds
Started Jul 17 05:32:48 PM PDT 24
Finished Jul 17 05:32:50 PM PDT 24
Peak memory 206268 kb
Host smart-4b880c45-aafc-4e96-bacc-a44910b63d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177151922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
177151922
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1344114378
Short name T999
Test name
Test status
Simulation time 1466835962 ps
CPU time 14.58 seconds
Started Jul 17 05:29:46 PM PDT 24
Finished Jul 17 05:30:01 PM PDT 24
Peak memory 233684 kb
Host smart-38a8b91d-ccf8-4a10-b24d-be055b8d0937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344114378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1344114378
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2561063189
Short name T584
Test name
Test status
Simulation time 30311302 ps
CPU time 0.77 seconds
Started Jul 17 05:29:58 PM PDT 24
Finished Jul 17 05:30:00 PM PDT 24
Peak memory 207444 kb
Host smart-816f187c-7749-4096-870a-eb118d85d905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561063189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2561063189
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4207024315
Short name T249
Test name
Test status
Simulation time 56091744645 ps
CPU time 388.06 seconds
Started Jul 17 05:32:07 PM PDT 24
Finished Jul 17 05:38:37 PM PDT 24
Peak memory 253632 kb
Host smart-01041d47-d4c8-4636-9cbe-d6099f359195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207024315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4207024315
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3892599385
Short name T539
Test name
Test status
Simulation time 78669746006 ps
CPU time 73.15 seconds
Started Jul 17 05:27:49 PM PDT 24
Finished Jul 17 05:29:05 PM PDT 24
Peak memory 225776 kb
Host smart-0cb35b3e-55dc-477c-aa5e-99d7cf81f1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892599385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3892599385
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3543901607
Short name T588
Test name
Test status
Simulation time 1788836464 ps
CPU time 26.73 seconds
Started Jul 17 05:30:55 PM PDT 24
Finished Jul 17 05:31:23 PM PDT 24
Peak memory 218732 kb
Host smart-e7a8459c-55ef-4dcc-9608-d21069f5e2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543901607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3543901607
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3264196209
Short name T789
Test name
Test status
Simulation time 297862751 ps
CPU time 7.52 seconds
Started Jul 17 05:33:40 PM PDT 24
Finished Jul 17 05:33:49 PM PDT 24
Peak memory 234556 kb
Host smart-5a1773f6-ce7f-46e2-a8af-7ec20dd93c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264196209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3264196209
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2186551624
Short name T170
Test name
Test status
Simulation time 1534672434 ps
CPU time 11.57 seconds
Started Jul 17 05:32:08 PM PDT 24
Finished Jul 17 05:32:20 PM PDT 24
Peak memory 236116 kb
Host smart-ef03bd27-f87f-48a7-902b-12bbe8abff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186551624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2186551624
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3412527119
Short name T915
Test name
Test status
Simulation time 201200369 ps
CPU time 3.63 seconds
Started Jul 17 05:27:55 PM PDT 24
Finished Jul 17 05:28:00 PM PDT 24
Peak memory 233680 kb
Host smart-7222aa01-21ae-4341-af5c-20ca557ac02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412527119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3412527119
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3916555556
Short name T1013
Test name
Test status
Simulation time 4878287553 ps
CPU time 40.27 seconds
Started Jul 17 05:27:55 PM PDT 24
Finished Jul 17 05:28:36 PM PDT 24
Peak memory 241608 kb
Host smart-9ec0552c-3760-4df6-b79f-827da9ccb8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916555556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3916555556
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2154895001
Short name T684
Test name
Test status
Simulation time 92885029 ps
CPU time 1.06 seconds
Started Jul 17 05:29:57 PM PDT 24
Finished Jul 17 05:29:59 PM PDT 24
Peak memory 217596 kb
Host smart-5807a6b7-39ec-4c3c-8e50-3c194b5ad383
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154895001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2154895001
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.737971688
Short name T50
Test name
Test status
Simulation time 1129812813 ps
CPU time 5.26 seconds
Started Jul 17 05:28:50 PM PDT 24
Finished Jul 17 05:28:55 PM PDT 24
Peak memory 225512 kb
Host smart-f1e4a874-0188-41d4-85bf-da1d1d7788f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737971688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
737971688
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.281643362
Short name T552
Test name
Test status
Simulation time 342003533 ps
CPU time 2.98 seconds
Started Jul 17 05:28:36 PM PDT 24
Finished Jul 17 05:28:39 PM PDT 24
Peak memory 225432 kb
Host smart-5e7b36ee-e368-45e0-b652-147f4080214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281643362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.281643362
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4049540643
Short name T141
Test name
Test status
Simulation time 4694467116 ps
CPU time 13.21 seconds
Started Jul 17 05:27:48 PM PDT 24
Finished Jul 17 05:28:04 PM PDT 24
Peak memory 220424 kb
Host smart-e04df7e4-c538-4ff1-a796-5e16c6a8eedc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4049540643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4049540643
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2228394194
Short name T31
Test name
Test status
Simulation time 36898886 ps
CPU time 0.98 seconds
Started Jul 17 05:27:51 PM PDT 24
Finished Jul 17 05:27:53 PM PDT 24
Peak memory 236644 kb
Host smart-a2da49ba-322e-4b1f-9523-1b32dbaa0394
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228394194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2228394194
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.44924944
Short name T890
Test name
Test status
Simulation time 2232889051 ps
CPU time 28.55 seconds
Started Jul 17 05:31:59 PM PDT 24
Finished Jul 17 05:32:28 PM PDT 24
Peak memory 250720 kb
Host smart-af72f1c9-fa8a-46c5-a5d3-d8a6c50e3bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44924944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_
all.44924944
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3384563524
Short name T385
Test name
Test status
Simulation time 13873179786 ps
CPU time 26.14 seconds
Started Jul 17 05:30:06 PM PDT 24
Finished Jul 17 05:30:33 PM PDT 24
Peak memory 217476 kb
Host smart-ceaa2c1b-5a7e-45b3-bdea-8b9e093d0d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384563524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3384563524
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2377326589
Short name T733
Test name
Test status
Simulation time 1559920623 ps
CPU time 6.25 seconds
Started Jul 17 05:28:05 PM PDT 24
Finished Jul 17 05:28:14 PM PDT 24
Peak memory 217308 kb
Host smart-bb8a0b71-1d69-40a1-9b90-6a968209249f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377326589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2377326589
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2564920946
Short name T1018
Test name
Test status
Simulation time 287764877 ps
CPU time 0.94 seconds
Started Jul 17 05:28:36 PM PDT 24
Finished Jul 17 05:28:37 PM PDT 24
Peak memory 207948 kb
Host smart-cdad79ca-1d4a-4b67-ab78-3eac364a8e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564920946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2564920946
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.113813058
Short name T791
Test name
Test status
Simulation time 195325726 ps
CPU time 1.02 seconds
Started Jul 17 05:28:05 PM PDT 24
Finished Jul 17 05:28:09 PM PDT 24
Peak memory 207960 kb
Host smart-0b13743e-9669-4a31-9ec6-a1dc88622ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113813058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.113813058
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3820983097
Short name T636
Test name
Test status
Simulation time 24332764885 ps
CPU time 19.19 seconds
Started Jul 17 05:27:55 PM PDT 24
Finished Jul 17 05:28:15 PM PDT 24
Peak memory 241964 kb
Host smart-bb6d7478-dc9c-431c-a408-79f1c4525d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820983097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3820983097
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.349119365
Short name T594
Test name
Test status
Simulation time 37591624 ps
CPU time 0.72 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:33:57 PM PDT 24
Peak memory 206696 kb
Host smart-9002904e-f8f4-47ab-8231-e8d97b99bb00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349119365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.349119365
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3119227408
Short name T229
Test name
Test status
Simulation time 56689608 ps
CPU time 2.52 seconds
Started Jul 17 05:28:04 PM PDT 24
Finished Jul 17 05:28:09 PM PDT 24
Peak memory 233716 kb
Host smart-89e90fa1-8ffe-421d-8005-c18eaccf7acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119227408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3119227408
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4018026549
Short name T972
Test name
Test status
Simulation time 15761724 ps
CPU time 0.81 seconds
Started Jul 17 05:28:00 PM PDT 24
Finished Jul 17 05:28:03 PM PDT 24
Peak memory 207516 kb
Host smart-5c41270e-8b07-42d3-ab6f-f111b905a292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018026549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4018026549
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3025119296
Short name T248
Test name
Test status
Simulation time 3548046425 ps
CPU time 59.53 seconds
Started Jul 17 05:32:48 PM PDT 24
Finished Jul 17 05:33:49 PM PDT 24
Peak memory 255812 kb
Host smart-40f942a0-7a55-4c32-a375-b57cda89a82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025119296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3025119296
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.653545574
Short name T735
Test name
Test status
Simulation time 44982629003 ps
CPU time 88.54 seconds
Started Jul 17 05:33:44 PM PDT 24
Finished Jul 17 05:35:13 PM PDT 24
Peak memory 267212 kb
Host smart-c666e450-3624-41db-8954-425816c44689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653545574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.653545574
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2384603663
Short name T913
Test name
Test status
Simulation time 7898885937 ps
CPU time 28.77 seconds
Started Jul 17 05:28:08 PM PDT 24
Finished Jul 17 05:28:42 PM PDT 24
Peak memory 218824 kb
Host smart-a1c71d88-853f-4536-8a83-5ce0a1547231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384603663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2384603663
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2226075935
Short name T592
Test name
Test status
Simulation time 71282338 ps
CPU time 2.58 seconds
Started Jul 17 05:28:05 PM PDT 24
Finished Jul 17 05:28:10 PM PDT 24
Peak memory 233720 kb
Host smart-63718c82-b6bd-455c-bcba-f63a9cf9900a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226075935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2226075935
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.134176163
Short name T678
Test name
Test status
Simulation time 84657068511 ps
CPU time 30 seconds
Started Jul 17 05:32:57 PM PDT 24
Finished Jul 17 05:33:29 PM PDT 24
Peak memory 235356 kb
Host smart-adb40a62-4df9-4a87-bbea-195a66309f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134176163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.134176163
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.4276385547
Short name T194
Test name
Test status
Simulation time 1334219476 ps
CPU time 10.31 seconds
Started Jul 17 05:28:06 PM PDT 24
Finished Jul 17 05:28:21 PM PDT 24
Peak memory 233748 kb
Host smart-12e432a2-ce51-4817-afdd-def4b5f3e682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276385547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4276385547
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1144305849
Short name T201
Test name
Test status
Simulation time 12397713529 ps
CPU time 49.96 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:31:11 PM PDT 24
Peak memory 239900 kb
Host smart-ce785829-0b0a-4cc1-a516-6cb0ddd78d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144305849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1144305849
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.139006989
Short name T717
Test name
Test status
Simulation time 17742450 ps
CPU time 1.1 seconds
Started Jul 17 05:30:27 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 217656 kb
Host smart-36e2b446-ef8e-4b95-8435-2cc43a33db0a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139006989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.139006989
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.210176205
Short name T490
Test name
Test status
Simulation time 5641539233 ps
CPU time 9.76 seconds
Started Jul 17 05:32:41 PM PDT 24
Finished Jul 17 05:32:51 PM PDT 24
Peak memory 242064 kb
Host smart-8faf8243-36b3-4942-ac43-c2e901e84cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210176205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.210176205
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2483613597
Short name T439
Test name
Test status
Simulation time 2378812391 ps
CPU time 8.25 seconds
Started Jul 17 05:32:48 PM PDT 24
Finished Jul 17 05:32:57 PM PDT 24
Peak memory 225664 kb
Host smart-ffd58fc4-e16a-475d-b8d7-55c11ac3ca1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483613597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2483613597
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3283160605
Short name T557
Test name
Test status
Simulation time 521977244 ps
CPU time 4.08 seconds
Started Jul 17 05:32:48 PM PDT 24
Finished Jul 17 05:32:53 PM PDT 24
Peak memory 220352 kb
Host smart-37b48988-184c-4fa7-bb5e-9553f098744e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3283160605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3283160605
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.549878381
Short name T982
Test name
Test status
Simulation time 8740207611 ps
CPU time 91.78 seconds
Started Jul 17 05:33:39 PM PDT 24
Finished Jul 17 05:35:12 PM PDT 24
Peak memory 254568 kb
Host smart-b879317e-61cc-4586-abed-4f1c21824c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549878381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.549878381
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1926577334
Short name T366
Test name
Test status
Simulation time 6966396564 ps
CPU time 12.18 seconds
Started Jul 17 05:29:59 PM PDT 24
Finished Jul 17 05:30:12 PM PDT 24
Peak memory 217572 kb
Host smart-3ad549c7-e143-4945-8e20-ab6c9f7d84e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926577334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1926577334
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2844183065
Short name T360
Test name
Test status
Simulation time 1777470649 ps
CPU time 9.4 seconds
Started Jul 17 05:29:59 PM PDT 24
Finished Jul 17 05:30:09 PM PDT 24
Peak memory 217256 kb
Host smart-cc244cd1-4705-4e90-a5c6-ac0234d40bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844183065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2844183065
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1068881586
Short name T680
Test name
Test status
Simulation time 192350303 ps
CPU time 2.11 seconds
Started Jul 17 05:29:07 PM PDT 24
Finished Jul 17 05:29:10 PM PDT 24
Peak memory 217076 kb
Host smart-762b1e0c-2305-4d8c-8c1a-fc78148dd837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068881586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1068881586
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2246437196
Short name T487
Test name
Test status
Simulation time 273061049 ps
CPU time 0.9 seconds
Started Jul 17 05:32:49 PM PDT 24
Finished Jul 17 05:32:51 PM PDT 24
Peak memory 207188 kb
Host smart-db1abb0e-2662-489b-bf83-4a9fb56b10b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246437196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2246437196
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1743650416
Short name T328
Test name
Test status
Simulation time 643166839 ps
CPU time 2.63 seconds
Started Jul 17 05:33:44 PM PDT 24
Finished Jul 17 05:33:48 PM PDT 24
Peak memory 233968 kb
Host smart-3b2814d7-ce85-417d-bc46-eb34dca5ea99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743650416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1743650416
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4264097992
Short name T414
Test name
Test status
Simulation time 11752717 ps
CPU time 0.76 seconds
Started Jul 17 05:29:19 PM PDT 24
Finished Jul 17 05:29:22 PM PDT 24
Peak memory 206728 kb
Host smart-6c07cd5a-20b1-4bda-ae31-c5f9181001cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264097992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4264097992
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2001628718
Short name T803
Test name
Test status
Simulation time 145539469 ps
CPU time 2.31 seconds
Started Jul 17 05:30:13 PM PDT 24
Finished Jul 17 05:30:17 PM PDT 24
Peak memory 225448 kb
Host smart-afb5a4d8-b7b3-459e-86d5-76b447b52be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001628718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2001628718
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3081577634
Short name T1003
Test name
Test status
Simulation time 29317372 ps
CPU time 0.78 seconds
Started Jul 17 05:28:07 PM PDT 24
Finished Jul 17 05:28:12 PM PDT 24
Peak memory 207480 kb
Host smart-a272d9f0-f902-420f-b1ba-f283bbe406f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081577634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3081577634
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2978019827
Short name T755
Test name
Test status
Simulation time 162186206301 ps
CPU time 86.36 seconds
Started Jul 17 05:29:02 PM PDT 24
Finished Jul 17 05:30:29 PM PDT 24
Peak memory 242120 kb
Host smart-d1045cca-3b4b-4c68-a5fd-1d51c2602443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978019827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2978019827
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3619655462
Short name T215
Test name
Test status
Simulation time 4410825721 ps
CPU time 98.24 seconds
Started Jul 17 05:30:21 PM PDT 24
Finished Jul 17 05:32:01 PM PDT 24
Peak memory 250468 kb
Host smart-67d8332d-6ecc-4e8b-9af1-f5f59e256d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619655462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3619655462
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2091784473
Short name T453
Test name
Test status
Simulation time 11605693410 ps
CPU time 46.19 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:31:08 PM PDT 24
Peak memory 241288 kb
Host smart-db09b68b-79ab-4cc5-af8a-ae936af2bdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091784473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2091784473
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1854153230
Short name T205
Test name
Test status
Simulation time 99752072 ps
CPU time 3.21 seconds
Started Jul 17 05:28:17 PM PDT 24
Finished Jul 17 05:28:22 PM PDT 24
Peak memory 233724 kb
Host smart-32159108-1eda-44a2-aba4-8fcd173dab38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854153230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1854153230
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1669174159
Short name T486
Test name
Test status
Simulation time 4525519888 ps
CPU time 65.55 seconds
Started Jul 17 05:30:28 PM PDT 24
Finished Jul 17 05:31:36 PM PDT 24
Peak memory 250232 kb
Host smart-caf1839a-685b-4e5c-b7a0-8462d3272ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669174159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1669174159
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3831605339
Short name T1000
Test name
Test status
Simulation time 460101805 ps
CPU time 2.84 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:28:16 PM PDT 24
Peak memory 233808 kb
Host smart-7b9d2388-361e-413d-ada7-aeec55c34535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831605339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3831605339
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3424556454
Short name T714
Test name
Test status
Simulation time 17032146844 ps
CPU time 39.59 seconds
Started Jul 17 05:28:08 PM PDT 24
Finished Jul 17 05:28:52 PM PDT 24
Peak memory 225644 kb
Host smart-0a0553e1-dda9-4ae9-b675-4a49ec6c4148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424556454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3424556454
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2976302270
Short name T537
Test name
Test status
Simulation time 100709323 ps
CPU time 1.11 seconds
Started Jul 17 05:28:08 PM PDT 24
Finished Jul 17 05:28:14 PM PDT 24
Peak memory 218760 kb
Host smart-a8c485ef-a7b1-4118-9ba7-99bb253f56eb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976302270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2976302270
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1570302720
Short name T424
Test name
Test status
Simulation time 244369689 ps
CPU time 3.17 seconds
Started Jul 17 05:28:15 PM PDT 24
Finished Jul 17 05:28:21 PM PDT 24
Peak memory 233788 kb
Host smart-c1d05e55-1398-43bb-ae5b-b2f7d0f3646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570302720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1570302720
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2619885211
Short name T929
Test name
Test status
Simulation time 1169577244 ps
CPU time 4.43 seconds
Started Jul 17 05:29:02 PM PDT 24
Finished Jul 17 05:29:07 PM PDT 24
Peak memory 224268 kb
Host smart-f8daabec-6404-4e17-bc5e-b93f8e45e087
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2619885211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2619885211
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1009744951
Short name T476
Test name
Test status
Simulation time 6510295196 ps
CPU time 11.23 seconds
Started Jul 17 05:29:00 PM PDT 24
Finished Jul 17 05:29:12 PM PDT 24
Peak memory 217468 kb
Host smart-090c8aa0-79a8-4665-a44a-5a63ee129d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009744951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1009744951
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1017910029
Short name T300
Test name
Test status
Simulation time 1466051020 ps
CPU time 3.64 seconds
Started Jul 17 05:32:49 PM PDT 24
Finished Jul 17 05:32:54 PM PDT 24
Peak memory 217096 kb
Host smart-50a4456e-5020-4d39-8b2d-cba8521a6d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017910029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1017910029
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2700907019
Short name T798
Test name
Test status
Simulation time 923094660 ps
CPU time 2.66 seconds
Started Jul 17 05:28:07 PM PDT 24
Finished Jul 17 05:28:14 PM PDT 24
Peak memory 217348 kb
Host smart-b26c6ad6-5f91-4e13-964e-ca5eecf3d3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700907019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2700907019
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1333773989
Short name T613
Test name
Test status
Simulation time 106013725 ps
CPU time 0.76 seconds
Started Jul 17 05:28:06 PM PDT 24
Finished Jul 17 05:28:12 PM PDT 24
Peak memory 207008 kb
Host smart-b899fffe-a399-4cc1-93f3-f0be824a9b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333773989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1333773989
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.403579665
Short name T365
Test name
Test status
Simulation time 1618885510 ps
CPU time 4.81 seconds
Started Jul 17 05:28:15 PM PDT 24
Finished Jul 17 05:28:23 PM PDT 24
Peak memory 225532 kb
Host smart-fafb4a70-618e-4854-bbed-b36711b7c0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403579665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.403579665
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2177138430
Short name T322
Test name
Test status
Simulation time 1816439966 ps
CPU time 10.75 seconds
Started Jul 17 05:33:48 PM PDT 24
Finished Jul 17 05:34:01 PM PDT 24
Peak memory 225580 kb
Host smart-7d36ba70-f014-4de8-b95d-73baa18baded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177138430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2177138430
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2971527177
Short name T384
Test name
Test status
Simulation time 20741156 ps
CPU time 0.76 seconds
Started Jul 17 05:29:17 PM PDT 24
Finished Jul 17 05:29:19 PM PDT 24
Peak memory 207848 kb
Host smart-aa72e78c-2135-437a-8536-48a5a778bd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971527177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2971527177
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2794273617
Short name T211
Test name
Test status
Simulation time 504394483 ps
CPU time 12.73 seconds
Started Jul 17 05:28:11 PM PDT 24
Finished Jul 17 05:28:29 PM PDT 24
Peak memory 240096 kb
Host smart-1189269a-690b-48f9-a4bc-374c3db426f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794273617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2794273617
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2378631812
Short name T36
Test name
Test status
Simulation time 6018183967 ps
CPU time 88.68 seconds
Started Jul 17 05:28:12 PM PDT 24
Finished Jul 17 05:29:45 PM PDT 24
Peak memory 258548 kb
Host smart-e972f91f-a0fc-4ee1-b2ea-6673533257e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378631812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2378631812
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2564926152
Short name T702
Test name
Test status
Simulation time 73276130 ps
CPU time 2.95 seconds
Started Jul 17 05:33:48 PM PDT 24
Finished Jul 17 05:33:53 PM PDT 24
Peak memory 233748 kb
Host smart-5f6bad80-5139-4872-991f-68bda845462c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564926152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2564926152
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3175860994
Short name T884
Test name
Test status
Simulation time 7510557194 ps
CPU time 55.35 seconds
Started Jul 17 05:34:02 PM PDT 24
Finished Jul 17 05:34:58 PM PDT 24
Peak memory 251840 kb
Host smart-e179a782-94b2-45dd-bb46-32942bdc15e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175860994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3175860994
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.969421303
Short name T203
Test name
Test status
Simulation time 1203816255 ps
CPU time 6.15 seconds
Started Jul 17 05:28:12 PM PDT 24
Finished Jul 17 05:28:23 PM PDT 24
Peak memory 225588 kb
Host smart-8419b0b9-5a6b-4678-9967-ac7a5a19cc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969421303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.969421303
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3626320847
Short name T919
Test name
Test status
Simulation time 5162850266 ps
CPU time 13.41 seconds
Started Jul 17 05:28:11 PM PDT 24
Finished Jul 17 05:28:29 PM PDT 24
Peak memory 225672 kb
Host smart-a4ed2e4f-fde8-4ee4-a092-9488b581dc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626320847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3626320847
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3085293554
Short name T543
Test name
Test status
Simulation time 53348454 ps
CPU time 1.09 seconds
Started Jul 17 05:30:29 PM PDT 24
Finished Jul 17 05:30:32 PM PDT 24
Peak memory 217600 kb
Host smart-8d47f84a-a86e-46e9-8c73-1557b991d32a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085293554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3085293554
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.195988206
Short name T807
Test name
Test status
Simulation time 7121103293 ps
CPU time 6.83 seconds
Started Jul 17 05:28:10 PM PDT 24
Finished Jul 17 05:28:22 PM PDT 24
Peak memory 225584 kb
Host smart-3c6259a7-3d26-4f7f-98f1-2ab9abd1d1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195988206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.195988206
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1872220161
Short name T217
Test name
Test status
Simulation time 6465837704 ps
CPU time 12.94 seconds
Started Jul 17 05:28:10 PM PDT 24
Finished Jul 17 05:28:28 PM PDT 24
Peak memory 237900 kb
Host smart-8d6d3947-420a-470e-95ac-625ee45f178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872220161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1872220161
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4265826002
Short name T984
Test name
Test status
Simulation time 313212925 ps
CPU time 4.05 seconds
Started Jul 17 05:28:12 PM PDT 24
Finished Jul 17 05:28:21 PM PDT 24
Peak memory 220464 kb
Host smart-8f686762-898f-47e0-82a9-5920a4796af1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4265826002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4265826002
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2905065022
Short name T1012
Test name
Test status
Simulation time 50109178 ps
CPU time 1.04 seconds
Started Jul 17 05:28:12 PM PDT 24
Finished Jul 17 05:28:18 PM PDT 24
Peak memory 208144 kb
Host smart-1e58d1bd-dc02-463a-9478-2bc93ecb69d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905065022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2905065022
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2733303077
Short name T993
Test name
Test status
Simulation time 228957495 ps
CPU time 3.42 seconds
Started Jul 17 05:27:59 PM PDT 24
Finished Jul 17 05:28:04 PM PDT 24
Peak memory 217476 kb
Host smart-a816e9d4-2475-4f8b-9d9f-3d24983f38d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733303077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2733303077
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2595928278
Short name T332
Test name
Test status
Simulation time 1430340521 ps
CPU time 5.76 seconds
Started Jul 17 05:27:59 PM PDT 24
Finished Jul 17 05:28:07 PM PDT 24
Peak memory 217424 kb
Host smart-af8182f9-a72d-42e7-b139-3522b923fad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595928278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2595928278
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3121995236
Short name T132
Test name
Test status
Simulation time 165521805 ps
CPU time 1.27 seconds
Started Jul 17 05:28:10 PM PDT 24
Finished Jul 17 05:28:16 PM PDT 24
Peak memory 217320 kb
Host smart-db8765a1-98b8-4c9b-896e-a8dd49198e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121995236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3121995236
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1995590279
Short name T815
Test name
Test status
Simulation time 116853639 ps
CPU time 0.9 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:28:15 PM PDT 24
Peak memory 206916 kb
Host smart-a3977d9c-2743-4eb2-81f7-4c9dfa647ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995590279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1995590279
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3522673255
Short name T817
Test name
Test status
Simulation time 22464354801 ps
CPU time 19.15 seconds
Started Jul 17 05:28:10 PM PDT 24
Finished Jul 17 05:28:35 PM PDT 24
Peak memory 250184 kb
Host smart-b5ec0f44-a074-4ab3-a1df-5f587b5281a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522673255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3522673255
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2421477509
Short name T302
Test name
Test status
Simulation time 13319365 ps
CPU time 0.79 seconds
Started Jul 17 05:28:17 PM PDT 24
Finished Jul 17 05:28:20 PM PDT 24
Peak memory 205888 kb
Host smart-084e53cf-b671-4f91-82f6-e75527619d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421477509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2421477509
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3726751838
Short name T942
Test name
Test status
Simulation time 182438772 ps
CPU time 2.3 seconds
Started Jul 17 05:28:07 PM PDT 24
Finished Jul 17 05:28:13 PM PDT 24
Peak memory 233748 kb
Host smart-18649fe0-d143-4a7e-a94a-adfef37604b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726751838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3726751838
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.936029483
Short name T976
Test name
Test status
Simulation time 35011416 ps
CPU time 0.75 seconds
Started Jul 17 05:28:11 PM PDT 24
Finished Jul 17 05:28:17 PM PDT 24
Peak memory 207484 kb
Host smart-543491db-c6c1-4047-813c-439ed5750be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936029483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.936029483
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1013622341
Short name T620
Test name
Test status
Simulation time 6682890307 ps
CPU time 34.25 seconds
Started Jul 17 05:28:07 PM PDT 24
Finished Jul 17 05:28:46 PM PDT 24
Peak memory 250252 kb
Host smart-939d0393-41f7-42b6-a61a-9e62cb96edc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013622341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1013622341
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1015077998
Short name T854
Test name
Test status
Simulation time 93322368108 ps
CPU time 216.14 seconds
Started Jul 17 05:28:15 PM PDT 24
Finished Jul 17 05:31:54 PM PDT 24
Peak memory 250716 kb
Host smart-fc2c8cac-fd49-4160-a92f-78cf57d5a1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015077998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1015077998
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2891268407
Short name T181
Test name
Test status
Simulation time 73426563470 ps
CPU time 672.69 seconds
Started Jul 17 05:28:03 PM PDT 24
Finished Jul 17 05:39:17 PM PDT 24
Peak memory 266552 kb
Host smart-29250588-c6f9-434c-a81a-d22e1e4dacbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891268407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2891268407
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2471272648
Short name T825
Test name
Test status
Simulation time 15969570602 ps
CPU time 108.53 seconds
Started Jul 17 05:28:07 PM PDT 24
Finished Jul 17 05:30:00 PM PDT 24
Peak memory 251988 kb
Host smart-7550a527-ecdc-4966-b896-c442077486de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471272648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2471272648
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3199128117
Short name T896
Test name
Test status
Simulation time 15385854643 ps
CPU time 21.75 seconds
Started Jul 17 05:28:07 PM PDT 24
Finished Jul 17 05:28:33 PM PDT 24
Peak memory 225872 kb
Host smart-a7cb83fa-9a33-4505-a36a-c9aafb26bf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199128117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3199128117
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3594121692
Short name T586
Test name
Test status
Simulation time 25271065710 ps
CPU time 57.78 seconds
Started Jul 17 05:28:51 PM PDT 24
Finished Jul 17 05:29:50 PM PDT 24
Peak memory 233936 kb
Host smart-1a032db0-9447-4664-ada4-34c61ac8fabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594121692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3594121692
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3372426291
Short name T34
Test name
Test status
Simulation time 182162267 ps
CPU time 1.05 seconds
Started Jul 17 05:33:42 PM PDT 24
Finished Jul 17 05:33:44 PM PDT 24
Peak memory 218944 kb
Host smart-8bd447bb-e6be-4a37-9b9e-4151902bdd2e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372426291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3372426291
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2875668104
Short name T402
Test name
Test status
Simulation time 1618093152 ps
CPU time 7.74 seconds
Started Jul 17 05:28:08 PM PDT 24
Finished Jul 17 05:28:21 PM PDT 24
Peak memory 238508 kb
Host smart-2c29bda6-647a-487f-b245-a84c5d3bda32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875668104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2875668104
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1282550760
Short name T948
Test name
Test status
Simulation time 1059274037 ps
CPU time 6.15 seconds
Started Jul 17 05:28:07 PM PDT 24
Finished Jul 17 05:28:17 PM PDT 24
Peak memory 233752 kb
Host smart-fe915bc2-b278-42ab-aa0d-24d5906a50f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282550760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1282550760
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2798975747
Short name T671
Test name
Test status
Simulation time 5495259527 ps
CPU time 14.08 seconds
Started Jul 17 05:28:07 PM PDT 24
Finished Jul 17 05:28:26 PM PDT 24
Peak memory 222428 kb
Host smart-0204c260-d68c-42d1-a375-cf600f6d8bc2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2798975747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2798975747
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3988786624
Short name T55
Test name
Test status
Simulation time 23298442904 ps
CPU time 188.97 seconds
Started Jul 17 05:28:17 PM PDT 24
Finished Jul 17 05:31:28 PM PDT 24
Peak memory 272664 kb
Host smart-3c3cceaf-23ca-4da9-8b0f-3b00e88702be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988786624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3988786624
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3859156075
Short name T865
Test name
Test status
Simulation time 1538063980 ps
CPU time 12.25 seconds
Started Jul 17 05:28:08 PM PDT 24
Finished Jul 17 05:28:25 PM PDT 24
Peak memory 217644 kb
Host smart-2628bab0-dd52-44c0-8a8f-7bfeef60466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859156075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3859156075
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1679431809
Short name T372
Test name
Test status
Simulation time 6149978667 ps
CPU time 6.67 seconds
Started Jul 17 05:27:59 PM PDT 24
Finished Jul 17 05:28:07 PM PDT 24
Peak memory 217452 kb
Host smart-77363bad-83ca-457b-abcc-77729f8290ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679431809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1679431809
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.171463982
Short name T358
Test name
Test status
Simulation time 139767234 ps
CPU time 0.76 seconds
Started Jul 17 05:32:57 PM PDT 24
Finished Jul 17 05:33:00 PM PDT 24
Peak memory 206996 kb
Host smart-cf933c92-0556-44f2-88e4-6e7b6ed75106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171463982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.171463982
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3738156947
Short name T794
Test name
Test status
Simulation time 37310393 ps
CPU time 0.69 seconds
Started Jul 17 05:29:07 PM PDT 24
Finished Jul 17 05:29:09 PM PDT 24
Peak memory 206300 kb
Host smart-6bedfc06-47c8-4969-883a-3e95d425013f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738156947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3738156947
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1195792
Short name T673
Test name
Test status
Simulation time 3361337872 ps
CPU time 9.15 seconds
Started Jul 17 05:32:49 PM PDT 24
Finished Jul 17 05:33:00 PM PDT 24
Peak memory 233896 kb
Host smart-5b72812c-b950-4c0f-9d6c-1eb2de17ce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1195792
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3952746691
Short name T388
Test name
Test status
Simulation time 10594959 ps
CPU time 0.7 seconds
Started Jul 17 05:28:11 PM PDT 24
Finished Jul 17 05:28:17 PM PDT 24
Peak memory 206292 kb
Host smart-282aab5e-0afc-4364-bcc2-fb5d34a69a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952746691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3952746691
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1240018637
Short name T651
Test name
Test status
Simulation time 36517708 ps
CPU time 2.36 seconds
Started Jul 17 05:27:59 PM PDT 24
Finished Jul 17 05:28:04 PM PDT 24
Peak memory 233844 kb
Host smart-02c13ae4-03f8-4e88-8a75-8ab24c3a7a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240018637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1240018637
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2804928515
Short name T503
Test name
Test status
Simulation time 22112049 ps
CPU time 0.83 seconds
Started Jul 17 05:30:10 PM PDT 24
Finished Jul 17 05:30:12 PM PDT 24
Peak memory 207712 kb
Host smart-b67ce6d7-4151-4cec-aca7-36c0452e8f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804928515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2804928515
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.143579880
Short name T183
Test name
Test status
Simulation time 9850977583 ps
CPU time 137.91 seconds
Started Jul 17 05:28:10 PM PDT 24
Finished Jul 17 05:30:33 PM PDT 24
Peak memory 270768 kb
Host smart-3e15d6be-59e3-45bf-a12c-e0b4be0aef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143579880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.143579880
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.897342554
Short name T446
Test name
Test status
Simulation time 2915890673 ps
CPU time 41.59 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:28:56 PM PDT 24
Peak memory 252220 kb
Host smart-48ab030b-21ed-4575-b96d-5e77fb7e6c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897342554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.897342554
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2413429038
Short name T58
Test name
Test status
Simulation time 34556864851 ps
CPU time 112.38 seconds
Started Jul 17 05:33:48 PM PDT 24
Finished Jul 17 05:35:42 PM PDT 24
Peak memory 251456 kb
Host smart-8d9c0c0d-dd5d-46cf-b6d3-0c431cf20d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413429038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2413429038
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2263171417
Short name T259
Test name
Test status
Simulation time 5979209263 ps
CPU time 103.68 seconds
Started Jul 17 05:33:48 PM PDT 24
Finished Jul 17 05:35:33 PM PDT 24
Peak memory 271352 kb
Host smart-4bb71c01-f15e-43f4-a94f-5a419c85f805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263171417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2263171417
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1197386388
Short name T637
Test name
Test status
Simulation time 1136084458 ps
CPU time 13.72 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:30:36 PM PDT 24
Peak memory 233492 kb
Host smart-987679ca-7e29-44fc-a19b-20e064b05c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197386388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1197386388
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.903243184
Short name T450
Test name
Test status
Simulation time 101149693 ps
CPU time 3.07 seconds
Started Jul 17 05:27:59 PM PDT 24
Finished Jul 17 05:28:04 PM PDT 24
Peak memory 233744 kb
Host smart-fa4c2706-43c6-4b7f-a1dc-4471ae569bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903243184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.903243184
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1920495989
Short name T814
Test name
Test status
Simulation time 26116991 ps
CPU time 1.03 seconds
Started Jul 17 05:28:03 PM PDT 24
Finished Jul 17 05:28:05 PM PDT 24
Peak memory 217660 kb
Host smart-7aea9298-a52e-4259-9c39-eef429313bef
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920495989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1920495989
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1916127573
Short name T965
Test name
Test status
Simulation time 912140007 ps
CPU time 4.39 seconds
Started Jul 17 05:29:17 PM PDT 24
Finished Jul 17 05:29:22 PM PDT 24
Peak memory 225572 kb
Host smart-96e2355f-267c-49f2-ab22-627c7a4f84f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916127573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1916127573
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1585389272
Short name T922
Test name
Test status
Simulation time 6666760319 ps
CPU time 12.91 seconds
Started Jul 17 05:29:02 PM PDT 24
Finished Jul 17 05:29:16 PM PDT 24
Peak memory 241380 kb
Host smart-d4363c4f-dda1-418a-aa8e-e6b345cb6a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585389272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1585389272
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2856796762
Short name T581
Test name
Test status
Simulation time 451522691 ps
CPU time 6.8 seconds
Started Jul 17 05:28:11 PM PDT 24
Finished Jul 17 05:28:22 PM PDT 24
Peak memory 222468 kb
Host smart-8cc60366-feb0-46c5-a01c-94bbf4ce1ad6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2856796762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2856796762
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2741196010
Short name T848
Test name
Test status
Simulation time 1304664210583 ps
CPU time 628.13 seconds
Started Jul 17 05:28:01 PM PDT 24
Finished Jul 17 05:38:31 PM PDT 24
Peak memory 263660 kb
Host smart-cf934ba1-7014-43d6-8f8c-c6f045b9ad5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741196010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2741196010
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1947541901
Short name T474
Test name
Test status
Simulation time 4931557784 ps
CPU time 32.09 seconds
Started Jul 17 05:29:02 PM PDT 24
Finished Jul 17 05:29:35 PM PDT 24
Peak memory 217476 kb
Host smart-6031eb93-f4c1-4213-ad58-2d6ed9210d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947541901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1947541901
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1399078559
Short name T649
Test name
Test status
Simulation time 32961625 ps
CPU time 0.72 seconds
Started Jul 17 05:29:29 PM PDT 24
Finished Jul 17 05:29:31 PM PDT 24
Peak memory 206596 kb
Host smart-f2e7fcf1-cf3b-437f-a5dc-1f8809068456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399078559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1399078559
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1913687723
Short name T363
Test name
Test status
Simulation time 81076666 ps
CPU time 1 seconds
Started Jul 17 05:28:17 PM PDT 24
Finished Jul 17 05:28:20 PM PDT 24
Peak memory 208896 kb
Host smart-37b3001f-5c74-4b01-a125-5600480bbfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913687723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1913687723
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1580860938
Short name T294
Test name
Test status
Simulation time 40717114 ps
CPU time 0.73 seconds
Started Jul 17 05:29:19 PM PDT 24
Finished Jul 17 05:29:21 PM PDT 24
Peak memory 207008 kb
Host smart-4f9d3cbe-7b57-4a34-8044-785f8b7571f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580860938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1580860938
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4157359975
Short name T959
Test name
Test status
Simulation time 3196353066 ps
CPU time 7.26 seconds
Started Jul 17 05:29:17 PM PDT 24
Finished Jul 17 05:29:25 PM PDT 24
Peak memory 241148 kb
Host smart-e01b4808-0862-4ca9-86c9-8350d908075f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157359975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4157359975
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3842584902
Short name T341
Test name
Test status
Simulation time 25836481 ps
CPU time 0.72 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:28:14 PM PDT 24
Peak memory 206296 kb
Host smart-7fc1a2a3-f567-4849-b95b-bfba51d1b051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842584902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3842584902
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.11818600
Short name T659
Test name
Test status
Simulation time 56215527 ps
CPU time 2.1 seconds
Started Jul 17 05:28:13 PM PDT 24
Finished Jul 17 05:28:19 PM PDT 24
Peak memory 225004 kb
Host smart-c6a08b65-88f5-4ea7-864d-0d29cf0e52e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11818600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.11818600
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.410597965
Short name T633
Test name
Test status
Simulation time 58590142 ps
CPU time 0.78 seconds
Started Jul 17 05:33:48 PM PDT 24
Finished Jul 17 05:33:51 PM PDT 24
Peak memory 206484 kb
Host smart-af3a6153-6b6d-410d-aa7d-f8d35388c5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410597965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.410597965
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1857257316
Short name T61
Test name
Test status
Simulation time 97059494481 ps
CPU time 132.81 seconds
Started Jul 17 05:28:51 PM PDT 24
Finished Jul 17 05:31:06 PM PDT 24
Peak memory 256872 kb
Host smart-30922f20-28ff-4dc1-b63e-f9e002ad257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857257316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1857257316
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1172378510
Short name T83
Test name
Test status
Simulation time 35075025900 ps
CPU time 108.73 seconds
Started Jul 17 05:28:07 PM PDT 24
Finished Jul 17 05:30:01 PM PDT 24
Peak memory 254380 kb
Host smart-788a91e6-83c2-4770-9266-1a70ebdb4c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172378510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1172378510
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.270791066
Short name T716
Test name
Test status
Simulation time 14622634406 ps
CPU time 62.32 seconds
Started Jul 17 05:32:49 PM PDT 24
Finished Jul 17 05:33:53 PM PDT 24
Peak memory 250760 kb
Host smart-91419a1a-8f97-4129-bcd7-ba2d1880a6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270791066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.270791066
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3558225713
Short name T269
Test name
Test status
Simulation time 179267954 ps
CPU time 5.24 seconds
Started Jul 17 05:28:10 PM PDT 24
Finished Jul 17 05:28:21 PM PDT 24
Peak memory 225592 kb
Host smart-f108c0d4-4e6a-4daf-aacd-a85ae037862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558225713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3558225713
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.289623281
Short name T479
Test name
Test status
Simulation time 8479002443 ps
CPU time 73.09 seconds
Started Jul 17 05:28:08 PM PDT 24
Finished Jul 17 05:29:25 PM PDT 24
Peak memory 242124 kb
Host smart-62654e08-4237-443f-a196-745d6f45ddab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289623281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.289623281
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2670180176
Short name T811
Test name
Test status
Simulation time 229850932 ps
CPU time 5.54 seconds
Started Jul 17 05:28:12 PM PDT 24
Finished Jul 17 05:28:22 PM PDT 24
Peak memory 233684 kb
Host smart-f97cd17a-d134-4110-b4f1-9b4264461531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670180176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2670180176
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2386387610
Short name T765
Test name
Test status
Simulation time 280275982 ps
CPU time 2.36 seconds
Started Jul 17 05:28:13 PM PDT 24
Finished Jul 17 05:28:19 PM PDT 24
Peak memory 224984 kb
Host smart-a5541f29-f59c-4f51-8bdb-743de57ef0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386387610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2386387610
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.4106286313
Short name T605
Test name
Test status
Simulation time 93325611 ps
CPU time 1.06 seconds
Started Jul 17 05:33:48 PM PDT 24
Finished Jul 17 05:33:51 PM PDT 24
Peak memory 217656 kb
Host smart-f2e3fab8-fc83-4c06-9c66-93c9c626e68d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106286313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.4106286313
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2260997613
Short name T540
Test name
Test status
Simulation time 12965852405 ps
CPU time 10.74 seconds
Started Jul 17 05:28:13 PM PDT 24
Finished Jul 17 05:28:28 PM PDT 24
Peak memory 233808 kb
Host smart-bd69566d-8303-4845-be90-878aa429a3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260997613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2260997613
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3528935420
Short name T195
Test name
Test status
Simulation time 1257576346 ps
CPU time 8.65 seconds
Started Jul 17 05:28:11 PM PDT 24
Finished Jul 17 05:28:24 PM PDT 24
Peak memory 233720 kb
Host smart-cdf06b83-fbb4-4a42-917a-fb9a4a685e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528935420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3528935420
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2516061526
Short name T16
Test name
Test status
Simulation time 674815192 ps
CPU time 4.3 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:28:18 PM PDT 24
Peak memory 223540 kb
Host smart-3542926d-8840-4d9d-a9ba-fec4ce003aff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2516061526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2516061526
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3175042966
Short name T964
Test name
Test status
Simulation time 117735887682 ps
CPU time 198.38 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:33:40 PM PDT 24
Peak memory 256604 kb
Host smart-134350ce-ec65-401d-b59f-797dbe4f9bb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175042966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3175042966
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2966858366
Short name T504
Test name
Test status
Simulation time 51028033 ps
CPU time 0.72 seconds
Started Jul 17 05:33:49 PM PDT 24
Finished Jul 17 05:33:51 PM PDT 24
Peak memory 206640 kb
Host smart-738b2c5c-cec6-490e-b5ef-9b4378317e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966858366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2966858366
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3015418762
Short name T712
Test name
Test status
Simulation time 11707743523 ps
CPU time 13.41 seconds
Started Jul 17 05:33:48 PM PDT 24
Finished Jul 17 05:34:04 PM PDT 24
Peak memory 217500 kb
Host smart-ddaad52f-e589-4444-9c8c-ed88b75ff3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015418762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3015418762
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1469917983
Short name T378
Test name
Test status
Simulation time 73877899 ps
CPU time 1.46 seconds
Started Jul 17 05:28:11 PM PDT 24
Finished Jul 17 05:28:18 PM PDT 24
Peak memory 209060 kb
Host smart-03362bf7-0980-4903-ace4-41d51e9b5aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469917983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1469917983
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.877467055
Short name T413
Test name
Test status
Simulation time 1361794990 ps
CPU time 0.95 seconds
Started Jul 17 05:28:12 PM PDT 24
Finished Jul 17 05:28:18 PM PDT 24
Peak memory 207952 kb
Host smart-cb37d301-08ef-45e0-b75d-f496718b704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877467055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.877467055
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.867791427
Short name T610
Test name
Test status
Simulation time 211097932 ps
CPU time 2.79 seconds
Started Jul 17 05:28:10 PM PDT 24
Finished Jul 17 05:28:18 PM PDT 24
Peak memory 233792 kb
Host smart-f8fb0724-4703-45c3-8eed-9fab9bb91146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867791427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.867791427
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.537212383
Short name T893
Test name
Test status
Simulation time 13986532 ps
CPU time 0.72 seconds
Started Jul 17 05:28:20 PM PDT 24
Finished Jul 17 05:28:22 PM PDT 24
Peak memory 206380 kb
Host smart-6215003b-8716-465a-be81-8bdb8b75cd3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537212383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.537212383
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1190269120
Short name T983
Test name
Test status
Simulation time 205320187 ps
CPU time 4.01 seconds
Started Jul 17 05:28:15 PM PDT 24
Finished Jul 17 05:28:22 PM PDT 24
Peak memory 225536 kb
Host smart-32cdca30-c291-4783-b867-89d699ecbd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190269120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1190269120
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.732980247
Short name T428
Test name
Test status
Simulation time 36715667 ps
CPU time 0.79 seconds
Started Jul 17 05:28:10 PM PDT 24
Finished Jul 17 05:28:16 PM PDT 24
Peak memory 207544 kb
Host smart-d9c69ba6-71a5-414e-9e6a-4f72b8aab1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732980247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.732980247
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.597586020
Short name T180
Test name
Test status
Simulation time 2120640719 ps
CPU time 24.07 seconds
Started Jul 17 05:30:29 PM PDT 24
Finished Jul 17 05:30:55 PM PDT 24
Peak memory 240960 kb
Host smart-ed9e3d61-2598-4afe-b560-7f2d136f7984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597586020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.597586020
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3466742952
Short name T872
Test name
Test status
Simulation time 119811258454 ps
CPU time 191.63 seconds
Started Jul 17 05:30:28 PM PDT 24
Finished Jul 17 05:33:42 PM PDT 24
Peak memory 253660 kb
Host smart-031e99e4-1f4d-40ed-89b7-394396597706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466742952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3466742952
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4242289369
Short name T1021
Test name
Test status
Simulation time 111301014 ps
CPU time 4.27 seconds
Started Jul 17 05:28:17 PM PDT 24
Finished Jul 17 05:28:23 PM PDT 24
Peak memory 225192 kb
Host smart-354aec30-7652-4f2e-8fb1-d9181ed7da3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242289369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4242289369
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1145226662
Short name T167
Test name
Test status
Simulation time 224715274420 ps
CPU time 426.76 seconds
Started Jul 17 05:29:02 PM PDT 24
Finished Jul 17 05:36:10 PM PDT 24
Peak memory 256444 kb
Host smart-ab8afd09-f586-4a8e-9027-1c56da9b973d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145226662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1145226662
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4097540505
Short name T379
Test name
Test status
Simulation time 138994655 ps
CPU time 3.07 seconds
Started Jul 17 05:28:17 PM PDT 24
Finished Jul 17 05:28:22 PM PDT 24
Peak memory 233672 kb
Host smart-f9227b7a-54a0-48cc-8c99-d9be05f279cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097540505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4097540505
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.687881668
Short name T790
Test name
Test status
Simulation time 12177742371 ps
CPU time 114.82 seconds
Started Jul 17 05:28:03 PM PDT 24
Finished Jul 17 05:29:59 PM PDT 24
Peak memory 233904 kb
Host smart-f804b824-78e5-4ab8-a9f8-9be85e4e3d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687881668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.687881668
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.4064564573
Short name T35
Test name
Test status
Simulation time 38688988 ps
CPU time 1.12 seconds
Started Jul 17 05:28:08 PM PDT 24
Finished Jul 17 05:28:14 PM PDT 24
Peak memory 217864 kb
Host smart-5d9f5f8a-4d0d-4c7a-ab8b-725ff162f0bb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064564573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.4064564573
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2504935023
Short name T234
Test name
Test status
Simulation time 500228141 ps
CPU time 8.43 seconds
Started Jul 17 05:28:17 PM PDT 24
Finished Jul 17 05:28:27 PM PDT 24
Peak memory 250072 kb
Host smart-bde3d0bd-69f8-40f3-a817-c2b512d86db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504935023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2504935023
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.877930877
Short name T787
Test name
Test status
Simulation time 21072781123 ps
CPU time 19.17 seconds
Started Jul 17 05:30:17 PM PDT 24
Finished Jul 17 05:30:37 PM PDT 24
Peak memory 237568 kb
Host smart-d981d685-35f0-458e-9155-a8c04f349cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877930877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.877930877
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2412014364
Short name T551
Test name
Test status
Simulation time 1922390605 ps
CPU time 6.47 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:29:26 PM PDT 24
Peak memory 222456 kb
Host smart-c55fac82-157b-4377-80c1-58b8cacd40a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2412014364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2412014364
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2370850220
Short name T60
Test name
Test status
Simulation time 2685802379 ps
CPU time 18.63 seconds
Started Jul 17 05:30:12 PM PDT 24
Finished Jul 17 05:30:31 PM PDT 24
Peak memory 217412 kb
Host smart-1e448e19-477b-4529-834b-949b5c956807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370850220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2370850220
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2534305277
Short name T87
Test name
Test status
Simulation time 1836568403 ps
CPU time 3.41 seconds
Started Jul 17 05:28:07 PM PDT 24
Finished Jul 17 05:28:14 PM PDT 24
Peak memory 217556 kb
Host smart-8373c461-2878-4ef6-8b1c-a9610a280076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534305277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2534305277
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.4279265624
Short name T614
Test name
Test status
Simulation time 162658889 ps
CPU time 0.9 seconds
Started Jul 17 05:28:08 PM PDT 24
Finished Jul 17 05:28:13 PM PDT 24
Peak memory 208028 kb
Host smart-42984ad9-a603-4cc5-8be2-954eca98e558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279265624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4279265624
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1632840354
Short name T930
Test name
Test status
Simulation time 84998571 ps
CPU time 0.78 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:28:15 PM PDT 24
Peak memory 206920 kb
Host smart-37456c62-4719-43d1-b2b5-85940242b894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632840354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1632840354
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1407593063
Short name T949
Test name
Test status
Simulation time 8790959853 ps
CPU time 6.64 seconds
Started Jul 17 05:30:11 PM PDT 24
Finished Jul 17 05:30:19 PM PDT 24
Peak memory 233804 kb
Host smart-2cf480bf-3a42-4abd-a641-d3bd7ad1d12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407593063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1407593063
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1028001413
Short name T572
Test name
Test status
Simulation time 40977273 ps
CPU time 0.71 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:28:14 PM PDT 24
Peak memory 205760 kb
Host smart-96f9a7b5-6a81-4837-940a-8d228b25852e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028001413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1028001413
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2930177047
Short name T830
Test name
Test status
Simulation time 375796708 ps
CPU time 3.91 seconds
Started Jul 17 05:28:21 PM PDT 24
Finished Jul 17 05:28:27 PM PDT 24
Peak memory 233756 kb
Host smart-dd525369-3d80-4a50-a7d7-8715023770fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930177047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2930177047
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2907500876
Short name T801
Test name
Test status
Simulation time 15530366 ps
CPU time 0.77 seconds
Started Jul 17 05:28:21 PM PDT 24
Finished Jul 17 05:28:22 PM PDT 24
Peak memory 207512 kb
Host smart-a88406f6-0c07-4b1d-9c0d-caf70f9f42f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907500876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2907500876
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2112599515
Short name T438
Test name
Test status
Simulation time 20631462 ps
CPU time 0.74 seconds
Started Jul 17 05:28:06 PM PDT 24
Finished Jul 17 05:28:12 PM PDT 24
Peak memory 216848 kb
Host smart-823d409c-c059-47b6-8425-d0d626384f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112599515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2112599515
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2798873921
Short name T843
Test name
Test status
Simulation time 55518226688 ps
CPU time 138.13 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:30:32 PM PDT 24
Peak memory 257552 kb
Host smart-e5c67818-22a5-4458-84d3-c3b5d6a1d22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798873921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2798873921
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3779420966
Short name T891
Test name
Test status
Simulation time 7155014076 ps
CPU time 29.03 seconds
Started Jul 17 05:28:11 PM PDT 24
Finished Jul 17 05:28:45 PM PDT 24
Peak memory 225612 kb
Host smart-b9441eea-9952-4368-ba4b-3a1721097ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779420966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3779420966
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.4107865745
Short name T546
Test name
Test status
Simulation time 64308805589 ps
CPU time 126.2 seconds
Started Jul 17 05:30:29 PM PDT 24
Finished Jul 17 05:32:37 PM PDT 24
Peak memory 255644 kb
Host smart-091b7eac-141f-4e92-ba48-0ead5cb03bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107865745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.4107865745
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1324010504
Short name T641
Test name
Test status
Simulation time 847162154 ps
CPU time 5.68 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:28:20 PM PDT 24
Peak memory 233712 kb
Host smart-ca8d72b3-ed01-42d1-85b2-2b47760a36d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324010504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1324010504
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.4066152349
Short name T563
Test name
Test status
Simulation time 41256431432 ps
CPU time 89.6 seconds
Started Jul 17 05:28:20 PM PDT 24
Finished Jul 17 05:29:51 PM PDT 24
Peak memory 233896 kb
Host smart-9f448cac-ee47-4956-b7d1-0a8b076f6861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066152349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4066152349
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2226506324
Short name T747
Test name
Test status
Simulation time 28242855 ps
CPU time 1.05 seconds
Started Jul 17 05:30:27 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 217656 kb
Host smart-1a52738f-5425-45fd-8e89-b52e1d69bfed
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226506324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2226506324
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3932894824
Short name T1008
Test name
Test status
Simulation time 8058094773 ps
CPU time 6.15 seconds
Started Jul 17 05:28:20 PM PDT 24
Finished Jul 17 05:28:28 PM PDT 24
Peak memory 241540 kb
Host smart-082b3bc2-ed08-4737-9188-c359fd57b00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932894824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3932894824
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2470520396
Short name T631
Test name
Test status
Simulation time 31657920 ps
CPU time 2.47 seconds
Started Jul 17 05:28:21 PM PDT 24
Finished Jul 17 05:28:25 PM PDT 24
Peak memory 233532 kb
Host smart-6143f773-631f-48e0-84ac-4a4e56787380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470520396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2470520396
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1524605262
Short name T297
Test name
Test status
Simulation time 3866011051 ps
CPU time 6.6 seconds
Started Jul 17 05:28:15 PM PDT 24
Finished Jul 17 05:28:24 PM PDT 24
Peak memory 224124 kb
Host smart-7c741be2-3a34-4952-8705-6ee44e0f4cff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1524605262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1524605262
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2079640449
Short name T818
Test name
Test status
Simulation time 10008707087 ps
CPU time 82.57 seconds
Started Jul 17 05:30:25 PM PDT 24
Finished Jul 17 05:31:49 PM PDT 24
Peak memory 252524 kb
Host smart-a69abba2-3b45-4161-9ab1-25a4041ba009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079640449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2079640449
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.62768766
Short name T3
Test name
Test status
Simulation time 28326271 ps
CPU time 0.71 seconds
Started Jul 17 05:29:59 PM PDT 24
Finished Jul 17 05:30:01 PM PDT 24
Peak memory 206552 kb
Host smart-19bec100-9658-4f3c-a2b5-6e80de2d8849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62768766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.62768766
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3503521835
Short name T569
Test name
Test status
Simulation time 2507149944 ps
CPU time 11.34 seconds
Started Jul 17 05:28:11 PM PDT 24
Finished Jul 17 05:28:28 PM PDT 24
Peak memory 217540 kb
Host smart-1de1ee3f-a9f8-4aec-9b5a-ca7fe84075e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503521835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3503521835
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4061688647
Short name T352
Test name
Test status
Simulation time 390396040 ps
CPU time 3.06 seconds
Started Jul 17 05:28:20 PM PDT 24
Finished Jul 17 05:28:24 PM PDT 24
Peak memory 217392 kb
Host smart-3d51578c-2df8-4ec2-ab0a-9b0ece5cc463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061688647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4061688647
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.896200227
Short name T421
Test name
Test status
Simulation time 52108877 ps
CPU time 0.84 seconds
Started Jul 17 05:30:28 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 206960 kb
Host smart-f6d0a1fc-5618-4d66-8405-9fcf742c406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896200227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.896200227
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1835162522
Short name T523
Test name
Test status
Simulation time 5480136301 ps
CPU time 4.73 seconds
Started Jul 17 05:29:15 PM PDT 24
Finished Jul 17 05:29:21 PM PDT 24
Peak memory 225704 kb
Host smart-5de8ff3d-901e-4fe4-bae2-ef41e21ebd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835162522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1835162522
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2156739276
Short name T894
Test name
Test status
Simulation time 28615915 ps
CPU time 0.75 seconds
Started Jul 17 05:30:42 PM PDT 24
Finished Jul 17 05:30:43 PM PDT 24
Peak memory 205804 kb
Host smart-3b9d17c2-7b7b-4d17-a5bb-aa827d825753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156739276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2156739276
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3623181735
Short name T321
Test name
Test status
Simulation time 466533747 ps
CPU time 4.19 seconds
Started Jul 17 05:28:26 PM PDT 24
Finished Jul 17 05:28:31 PM PDT 24
Peak memory 225532 kb
Host smart-cd536aeb-86ed-4ce6-9dd4-3945fa74adda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623181735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3623181735
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3184704947
Short name T518
Test name
Test status
Simulation time 36047695 ps
CPU time 0.73 seconds
Started Jul 17 05:28:11 PM PDT 24
Finished Jul 17 05:28:17 PM PDT 24
Peak memory 206440 kb
Host smart-c134389a-6efa-4748-b32b-28b220a0950c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184704947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3184704947
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1722632213
Short name T834
Test name
Test status
Simulation time 36850613011 ps
CPU time 25.39 seconds
Started Jul 17 05:28:23 PM PDT 24
Finished Jul 17 05:28:49 PM PDT 24
Peak memory 242080 kb
Host smart-d66e3f37-3833-488b-a950-dee6a37b529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722632213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1722632213
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1841103364
Short name T642
Test name
Test status
Simulation time 8970770166 ps
CPU time 15.21 seconds
Started Jul 17 05:33:53 PM PDT 24
Finished Jul 17 05:34:12 PM PDT 24
Peak memory 242012 kb
Host smart-4cb98934-84ec-4d60-8e51-136c3c1f9dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841103364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1841103364
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2141669383
Short name T688
Test name
Test status
Simulation time 96521721929 ps
CPU time 183.12 seconds
Started Jul 17 05:28:24 PM PDT 24
Finished Jul 17 05:31:27 PM PDT 24
Peak memory 253120 kb
Host smart-805633df-0ca2-4aca-b1a2-93688579d46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141669383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2141669383
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2649889775
Short name T994
Test name
Test status
Simulation time 767069571 ps
CPU time 3.89 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:33:59 PM PDT 24
Peak memory 225596 kb
Host smart-43c18dbc-f130-42c5-b60c-d877cb9d503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649889775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2649889775
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.992526761
Short name T192
Test name
Test status
Simulation time 19254098057 ps
CPU time 24.95 seconds
Started Jul 17 05:30:43 PM PDT 24
Finished Jul 17 05:31:08 PM PDT 24
Peak memory 252728 kb
Host smart-dc526872-ce45-495a-bdd4-3cc7f132a77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992526761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.992526761
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2651936840
Short name T426
Test name
Test status
Simulation time 31244489 ps
CPU time 1.01 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:28:15 PM PDT 24
Peak memory 218868 kb
Host smart-af7978ee-89ce-4a87-871c-02aeb5644500
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651936840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2651936840
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1890303462
Short name T658
Test name
Test status
Simulation time 22259566299 ps
CPU time 13.39 seconds
Started Jul 17 05:29:07 PM PDT 24
Finished Jul 17 05:29:22 PM PDT 24
Peak memory 233884 kb
Host smart-c2ce9687-40c3-4efc-8de3-372abcc532bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890303462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1890303462
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.72365219
Short name T445
Test name
Test status
Simulation time 743404302 ps
CPU time 3.57 seconds
Started Jul 17 05:29:59 PM PDT 24
Finished Jul 17 05:30:04 PM PDT 24
Peak memory 225504 kb
Host smart-b3d66c3a-2416-4162-b6a5-93616b03fe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72365219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.72365219
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1636918627
Short name T495
Test name
Test status
Simulation time 2772856964 ps
CPU time 8.21 seconds
Started Jul 17 05:28:27 PM PDT 24
Finished Jul 17 05:28:36 PM PDT 24
Peak memory 223120 kb
Host smart-4134ff5b-1f54-41df-98e6-db3ef6910227
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1636918627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1636918627
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.78692986
Short name T136
Test name
Test status
Simulation time 137540458488 ps
CPU time 648.93 seconds
Started Jul 17 05:29:19 PM PDT 24
Finished Jul 17 05:40:10 PM PDT 24
Peak memory 266356 kb
Host smart-5f623887-e268-4b29-948b-6b21ed90e084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78692986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress
_all.78692986
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3238446612
Short name T510
Test name
Test status
Simulation time 4894252992 ps
CPU time 16.68 seconds
Started Jul 17 05:28:19 PM PDT 24
Finished Jul 17 05:28:37 PM PDT 24
Peak memory 221500 kb
Host smart-25d16d3b-5417-41cb-a3d5-a6ede94a92e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238446612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3238446612
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2671780647
Short name T79
Test name
Test status
Simulation time 786254523 ps
CPU time 4.41 seconds
Started Jul 17 05:28:21 PM PDT 24
Finished Jul 17 05:28:26 PM PDT 24
Peak memory 217384 kb
Host smart-2a326ab4-3dd9-415f-81f9-bf43d33d1c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671780647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2671780647
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.629272741
Short name T991
Test name
Test status
Simulation time 123965020 ps
CPU time 1.02 seconds
Started Jul 17 05:28:38 PM PDT 24
Finished Jul 17 05:28:41 PM PDT 24
Peak memory 208180 kb
Host smart-7eaca140-f299-4a47-9c94-f57611f3ed33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629272741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.629272741
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2748274721
Short name T560
Test name
Test status
Simulation time 37211779 ps
CPU time 0.89 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:28:15 PM PDT 24
Peak memory 207940 kb
Host smart-a190f7d4-cfe7-42dc-bbc9-c75a37bc04be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748274721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2748274721
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3107256986
Short name T45
Test name
Test status
Simulation time 9860359226 ps
CPU time 17.93 seconds
Started Jul 17 05:30:40 PM PDT 24
Finished Jul 17 05:30:59 PM PDT 24
Peak memory 225656 kb
Host smart-34183c20-cf3f-4632-bab2-f156c07f482b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107256986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3107256986
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2489507668
Short name T81
Test name
Test status
Simulation time 13101978 ps
CPU time 0.78 seconds
Started Jul 17 05:28:38 PM PDT 24
Finished Jul 17 05:28:41 PM PDT 24
Peak memory 205804 kb
Host smart-516bb05b-d3cc-40fd-81a5-59e3d00131ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489507668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2489507668
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3211139740
Short name T676
Test name
Test status
Simulation time 1222356939 ps
CPU time 5.26 seconds
Started Jul 17 05:30:23 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 233704 kb
Host smart-0af86adc-230c-4df2-8f1e-8e8a4f42cb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211139740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3211139740
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.306025294
Short name T528
Test name
Test status
Simulation time 19298179 ps
CPU time 0.74 seconds
Started Jul 17 05:30:23 PM PDT 24
Finished Jul 17 05:30:25 PM PDT 24
Peak memory 206376 kb
Host smart-c631ff93-341e-43b7-99a5-3481dfafa8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306025294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.306025294
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.551423793
Short name T464
Test name
Test status
Simulation time 3442301483 ps
CPU time 68.35 seconds
Started Jul 17 05:29:15 PM PDT 24
Finished Jul 17 05:30:25 PM PDT 24
Peak memory 258476 kb
Host smart-f752a4bf-7a70-4b63-a209-a5d25326aad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551423793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.551423793
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2513953896
Short name T762
Test name
Test status
Simulation time 79739644157 ps
CPU time 210.84 seconds
Started Jul 17 05:28:24 PM PDT 24
Finished Jul 17 05:31:56 PM PDT 24
Peak memory 258504 kb
Host smart-c42a4ab0-e5da-4660-b82f-6d59eb84b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513953896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2513953896
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2947170199
Short name T38
Test name
Test status
Simulation time 1392157950 ps
CPU time 17.84 seconds
Started Jul 17 05:28:39 PM PDT 24
Finished Jul 17 05:28:58 PM PDT 24
Peak memory 235340 kb
Host smart-4c71df3d-230d-4d54-8515-e16bd52ab197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947170199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2947170199
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2715120175
Short name T590
Test name
Test status
Simulation time 7154342594 ps
CPU time 92.74 seconds
Started Jul 17 05:29:15 PM PDT 24
Finished Jul 17 05:30:48 PM PDT 24
Peak memory 251412 kb
Host smart-ead7e57a-9ca6-47b7-9f69-3b4fcace2221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715120175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2715120175
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3904486731
Short name T708
Test name
Test status
Simulation time 180584614 ps
CPU time 5.71 seconds
Started Jul 17 05:30:31 PM PDT 24
Finished Jul 17 05:30:37 PM PDT 24
Peak memory 225548 kb
Host smart-d6074569-e644-4e00-a36b-ff0865be23b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904486731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3904486731
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.690683975
Short name T918
Test name
Test status
Simulation time 228749997 ps
CPU time 6.62 seconds
Started Jul 17 05:28:29 PM PDT 24
Finished Jul 17 05:28:36 PM PDT 24
Peak memory 233776 kb
Host smart-5b5810fc-4036-4866-a27b-6aceaa5a3029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690683975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.690683975
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1969946792
Short name T314
Test name
Test status
Simulation time 33658523 ps
CPU time 1.08 seconds
Started Jul 17 05:31:26 PM PDT 24
Finished Jul 17 05:31:29 PM PDT 24
Peak memory 218852 kb
Host smart-084cd69f-0468-42a7-b1b9-333d9c87e935
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969946792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1969946792
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.244396039
Short name T643
Test name
Test status
Simulation time 1559548482 ps
CPU time 4.7 seconds
Started Jul 17 05:30:43 PM PDT 24
Finished Jul 17 05:30:48 PM PDT 24
Peak memory 235940 kb
Host smart-37210c5a-dec1-4ed4-9e2e-a48c6e8d3620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244396039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.244396039
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1260217311
Short name T427
Test name
Test status
Simulation time 109515754 ps
CPU time 2.21 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:29:22 PM PDT 24
Peak memory 225216 kb
Host smart-e87100f9-d8f4-45fa-8db0-2eb5cba8d352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260217311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1260217311
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.691690690
Short name T423
Test name
Test status
Simulation time 579019991 ps
CPU time 5.44 seconds
Started Jul 17 05:29:14 PM PDT 24
Finished Jul 17 05:29:20 PM PDT 24
Peak memory 223596 kb
Host smart-ec2b66cd-be74-446e-b340-c6cb25bef042
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=691690690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.691690690
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.875104259
Short name T273
Test name
Test status
Simulation time 49670617637 ps
CPU time 27.77 seconds
Started Jul 17 05:28:27 PM PDT 24
Finished Jul 17 05:28:55 PM PDT 24
Peak memory 217468 kb
Host smart-aa328aa2-3879-4799-8ebd-b6bb447ab2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875104259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.875104259
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1795740019
Short name T373
Test name
Test status
Simulation time 2550550130 ps
CPU time 2.29 seconds
Started Jul 17 05:28:28 PM PDT 24
Finished Jul 17 05:28:31 PM PDT 24
Peak memory 209040 kb
Host smart-7e3549e7-5fa8-4a21-83a5-ab4d9529fc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795740019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1795740019
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2734510923
Short name T333
Test name
Test status
Simulation time 102011407 ps
CPU time 1.24 seconds
Started Jul 17 05:32:39 PM PDT 24
Finished Jul 17 05:32:41 PM PDT 24
Peak memory 208824 kb
Host smart-6c3cce21-412a-4c78-adfa-2e56557f4a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734510923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2734510923
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.147723708
Short name T571
Test name
Test status
Simulation time 320675690 ps
CPU time 0.87 seconds
Started Jul 17 05:30:23 PM PDT 24
Finished Jul 17 05:30:25 PM PDT 24
Peak memory 207968 kb
Host smart-b0cdb27f-a1f1-4105-812f-3cb443430671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147723708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.147723708
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3644140937
Short name T443
Test name
Test status
Simulation time 660488735 ps
CPU time 5.82 seconds
Started Jul 17 05:28:28 PM PDT 24
Finished Jul 17 05:28:35 PM PDT 24
Peak memory 233720 kb
Host smart-a3320941-dc09-4019-8659-4d0052678f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644140937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3644140937
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2516319370
Short name T618
Test name
Test status
Simulation time 21908805 ps
CPU time 0.7 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:30:22 PM PDT 24
Peak memory 206328 kb
Host smart-d2f59a4e-6ed7-4f13-8c42-4256f819cce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516319370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
516319370
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.910573348
Short name T319
Test name
Test status
Simulation time 121443176 ps
CPU time 4.34 seconds
Started Jul 17 05:27:47 PM PDT 24
Finished Jul 17 05:27:54 PM PDT 24
Peak memory 233768 kb
Host smart-e067a825-163d-4ae8-8fd8-11a5c203aa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910573348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.910573348
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2923433823
Short name T471
Test name
Test status
Simulation time 48339121 ps
CPU time 0.77 seconds
Started Jul 17 05:27:51 PM PDT 24
Finished Jul 17 05:27:53 PM PDT 24
Peak memory 207504 kb
Host smart-0b7639df-14ff-4d37-9ee9-9f6299b1ea2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923433823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2923433823
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1888998103
Short name T616
Test name
Test status
Simulation time 9243244183 ps
CPU time 87.44 seconds
Started Jul 17 05:29:19 PM PDT 24
Finished Jul 17 05:30:48 PM PDT 24
Peak memory 256124 kb
Host smart-5e4a50e5-f9ab-4573-a91d-c31bb7e4b893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888998103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1888998103
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3886572854
Short name T140
Test name
Test status
Simulation time 416633474 ps
CPU time 6.4 seconds
Started Jul 17 05:30:27 PM PDT 24
Finished Jul 17 05:30:35 PM PDT 24
Peak memory 233844 kb
Host smart-0be069a0-abc6-4956-b82e-ef4b2da63a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886572854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3886572854
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3628251072
Short name T1002
Test name
Test status
Simulation time 39546755709 ps
CPU time 258.63 seconds
Started Jul 17 05:27:44 PM PDT 24
Finished Jul 17 05:32:04 PM PDT 24
Peak memory 258356 kb
Host smart-30839ecc-60a7-4b60-a53f-ab0e613bc57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628251072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3628251072
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2674015016
Short name T396
Test name
Test status
Simulation time 758038259 ps
CPU time 4.83 seconds
Started Jul 17 05:27:42 PM PDT 24
Finished Jul 17 05:27:48 PM PDT 24
Peak memory 233764 kb
Host smart-98a926f9-1892-40e3-bd10-54f1480b4963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674015016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2674015016
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2372814995
Short name T860
Test name
Test status
Simulation time 15159791670 ps
CPU time 74.97 seconds
Started Jul 17 05:30:27 PM PDT 24
Finished Jul 17 05:31:44 PM PDT 24
Peak memory 233888 kb
Host smart-8aba4089-cada-4e42-a629-4cd8a841f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372814995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2372814995
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1227803322
Short name T839
Test name
Test status
Simulation time 16696430 ps
CPU time 1.12 seconds
Started Jul 17 05:27:51 PM PDT 24
Finished Jul 17 05:27:54 PM PDT 24
Peak memory 217536 kb
Host smart-387b6bd3-2284-4af5-9f0c-03fe19a59153
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227803322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1227803322
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3598616074
Short name T329
Test name
Test status
Simulation time 52551261 ps
CPU time 2.24 seconds
Started Jul 17 05:33:31 PM PDT 24
Finished Jul 17 05:33:34 PM PDT 24
Peak memory 224920 kb
Host smart-f42b2d1e-e4f9-45e1-a879-d3e82ac64055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598616074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3598616074
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.460913391
Short name T292
Test name
Test status
Simulation time 138802795 ps
CPU time 2.2 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:30:23 PM PDT 24
Peak memory 224164 kb
Host smart-a04172f0-4155-4de2-b2e8-6732b202f153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460913391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.460913391
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3696558813
Short name T356
Test name
Test status
Simulation time 1258064653 ps
CPU time 8.52 seconds
Started Jul 17 05:29:37 PM PDT 24
Finished Jul 17 05:29:47 PM PDT 24
Peak memory 223828 kb
Host smart-910b230e-c75f-437e-97bc-37a98b015d9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3696558813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3696558813
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1624410294
Short name T73
Test name
Test status
Simulation time 89876099 ps
CPU time 1.3 seconds
Started Jul 17 05:29:55 PM PDT 24
Finished Jul 17 05:29:58 PM PDT 24
Peak memory 237628 kb
Host smart-ad5965cd-4df1-4090-99d0-028f4b488069
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624410294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1624410294
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3167360805
Short name T57
Test name
Test status
Simulation time 126262343293 ps
CPU time 590.18 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:39:11 PM PDT 24
Peak memory 288556 kb
Host smart-e202257b-aab8-4108-9f2b-1cde93dffd08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167360805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3167360805
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1248002
Short name T381
Test name
Test status
Simulation time 1693164440 ps
CPU time 10.46 seconds
Started Jul 17 05:27:44 PM PDT 24
Finished Jul 17 05:27:56 PM PDT 24
Peak memory 217312 kb
Host smart-dd34209e-73af-4ead-be95-51904d63787c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1248002
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1465097738
Short name T1005
Test name
Test status
Simulation time 1662184249 ps
CPU time 3.04 seconds
Started Jul 17 05:27:52 PM PDT 24
Finished Jul 17 05:27:56 PM PDT 24
Peak memory 217384 kb
Host smart-cbdae7f3-c348-42bb-8934-dc0fea6a419b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465097738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1465097738
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2340834383
Short name T809
Test name
Test status
Simulation time 33225823 ps
CPU time 1.29 seconds
Started Jul 17 05:27:44 PM PDT 24
Finished Jul 17 05:27:47 PM PDT 24
Peak memory 217300 kb
Host smart-d00a28c4-0803-48d4-aa82-6cc77493371a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340834383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2340834383
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3061158680
Short name T382
Test name
Test status
Simulation time 90907719 ps
CPU time 0.77 seconds
Started Jul 17 05:32:50 PM PDT 24
Finished Jul 17 05:32:52 PM PDT 24
Peak memory 206944 kb
Host smart-060266df-ee3a-4c9b-8ac2-97a38ce801a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061158680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3061158680
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2719815845
Short name T776
Test name
Test status
Simulation time 2608866576 ps
CPU time 3.1 seconds
Started Jul 17 05:27:45 PM PDT 24
Finished Jul 17 05:27:50 PM PDT 24
Peak memory 233836 kb
Host smart-a1ba78ca-60ef-46a0-b364-1e3ea26fe53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719815845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2719815845
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2724131523
Short name T398
Test name
Test status
Simulation time 18458830 ps
CPU time 0.7 seconds
Started Jul 17 05:28:49 PM PDT 24
Finished Jul 17 05:28:50 PM PDT 24
Peak memory 206344 kb
Host smart-bc69a2a3-1a13-4f99-81ea-b3bd5426bd34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724131523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2724131523
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1316364627
Short name T404
Test name
Test status
Simulation time 330775299 ps
CPU time 4.14 seconds
Started Jul 17 05:28:27 PM PDT 24
Finished Jul 17 05:28:32 PM PDT 24
Peak memory 225512 kb
Host smart-89aa89a8-f220-4f85-9dd9-49edad2cbc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316364627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1316364627
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2438313913
Short name T820
Test name
Test status
Simulation time 39435306 ps
CPU time 0.76 seconds
Started Jul 17 05:28:29 PM PDT 24
Finished Jul 17 05:28:31 PM PDT 24
Peak memory 207812 kb
Host smart-ee8e2fa0-aa34-48a4-b683-66284367ec4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438313913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2438313913
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3298795130
Short name T933
Test name
Test status
Simulation time 161851915 ps
CPU time 4.25 seconds
Started Jul 17 05:30:43 PM PDT 24
Finished Jul 17 05:30:48 PM PDT 24
Peak memory 233844 kb
Host smart-a10e4528-0509-4dee-8561-941b7a17078a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298795130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3298795130
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1079410968
Short name T247
Test name
Test status
Simulation time 27044882256 ps
CPU time 62.7 seconds
Started Jul 17 05:28:53 PM PDT 24
Finished Jul 17 05:29:57 PM PDT 24
Peak memory 238276 kb
Host smart-cd48baf7-d589-49e9-b4be-74d3e35b44c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079410968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1079410968
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3455315484
Short name T879
Test name
Test status
Simulation time 837308026 ps
CPU time 5.26 seconds
Started Jul 17 05:28:39 PM PDT 24
Finished Jul 17 05:28:45 PM PDT 24
Peak memory 233788 kb
Host smart-b27466ce-6653-424c-b941-57f1e9dc9119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455315484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3455315484
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.944198266
Short name T781
Test name
Test status
Simulation time 10204642542 ps
CPU time 27.25 seconds
Started Jul 17 05:28:29 PM PDT 24
Finished Jul 17 05:28:57 PM PDT 24
Peak memory 242092 kb
Host smart-022dbbd0-eecc-4311-a276-e44211d85d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944198266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.944198266
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4227082560
Short name T519
Test name
Test status
Simulation time 664444962 ps
CPU time 10.69 seconds
Started Jul 17 05:28:28 PM PDT 24
Finished Jul 17 05:28:40 PM PDT 24
Peak memory 233832 kb
Host smart-417ddf53-8359-4033-a3c8-bd92d257b057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227082560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4227082560
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1379561975
Short name T845
Test name
Test status
Simulation time 225182577 ps
CPU time 5.41 seconds
Started Jul 17 05:28:29 PM PDT 24
Finished Jul 17 05:28:35 PM PDT 24
Peak memory 225608 kb
Host smart-561e5282-3470-4796-b2c8-423ec68f7cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379561975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1379561975
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3088290115
Short name T515
Test name
Test status
Simulation time 1588588625 ps
CPU time 8.18 seconds
Started Jul 17 05:28:39 PM PDT 24
Finished Jul 17 05:28:48 PM PDT 24
Peak memory 241212 kb
Host smart-938761ac-aef2-463d-8097-38c571be1b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088290115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3088290115
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3688487002
Short name T512
Test name
Test status
Simulation time 5400390998 ps
CPU time 11.18 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:34:07 PM PDT 24
Peak memory 225680 kb
Host smart-12fda79d-c233-4a36-819d-c9d8e47fc6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688487002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3688487002
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2242207611
Short name T953
Test name
Test status
Simulation time 5191653340 ps
CPU time 12.62 seconds
Started Jul 17 05:32:37 PM PDT 24
Finished Jul 17 05:32:51 PM PDT 24
Peak memory 224020 kb
Host smart-718283d2-5b25-4fd1-892d-7cdfa82257f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2242207611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2242207611
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.4275092699
Short name T250
Test name
Test status
Simulation time 58465387931 ps
CPU time 544.11 seconds
Started Jul 17 05:33:54 PM PDT 24
Finished Jul 17 05:43:02 PM PDT 24
Peak memory 274936 kb
Host smart-37328d99-65b2-4ac7-b027-e8cf00b05b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275092699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.4275092699
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4069282289
Short name T278
Test name
Test status
Simulation time 41828987250 ps
CPU time 47.42 seconds
Started Jul 17 05:32:39 PM PDT 24
Finished Jul 17 05:33:27 PM PDT 24
Peak memory 217488 kb
Host smart-289073a2-6f92-4ca5-b1f2-886bd8ee4366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069282289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4069282289
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.410702629
Short name T937
Test name
Test status
Simulation time 981229850 ps
CPU time 2.19 seconds
Started Jul 17 05:28:22 PM PDT 24
Finished Jul 17 05:28:25 PM PDT 24
Peak memory 217300 kb
Host smart-a2810e8b-5e35-43cf-8ec3-8b7bf3675dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410702629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.410702629
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.851022307
Short name T795
Test name
Test status
Simulation time 60548369 ps
CPU time 1.21 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:33:55 PM PDT 24
Peak memory 208532 kb
Host smart-04d85d80-718b-4888-9076-0fbb72b90455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851022307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.851022307
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2189090426
Short name T348
Test name
Test status
Simulation time 406121565 ps
CPU time 1.05 seconds
Started Jul 17 05:28:38 PM PDT 24
Finished Jul 17 05:28:41 PM PDT 24
Peak memory 207288 kb
Host smart-e9fec724-8648-4e20-9a58-eaf792a2ed31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189090426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2189090426
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.786065263
Short name T172
Test name
Test status
Simulation time 2014560038 ps
CPU time 12.2 seconds
Started Jul 17 05:28:39 PM PDT 24
Finished Jul 17 05:28:52 PM PDT 24
Peak memory 225548 kb
Host smart-ff788a1b-5271-48f1-97f9-2b5140e3b243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786065263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.786065263
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3008820552
Short name T696
Test name
Test status
Simulation time 13758591 ps
CPU time 0.69 seconds
Started Jul 17 05:28:51 PM PDT 24
Finished Jul 17 05:28:54 PM PDT 24
Peak memory 206692 kb
Host smart-cdc49a8d-5559-4285-b6b2-b186f7b16166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008820552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3008820552
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1607671017
Short name T914
Test name
Test status
Simulation time 64706977 ps
CPU time 2.53 seconds
Started Jul 17 05:28:59 PM PDT 24
Finished Jul 17 05:29:02 PM PDT 24
Peak memory 233772 kb
Host smart-6ac4520e-aa00-44e3-ae7c-36574463786b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607671017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1607671017
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.882728056
Short name T690
Test name
Test status
Simulation time 20561196 ps
CPU time 0.79 seconds
Started Jul 17 05:28:57 PM PDT 24
Finished Jul 17 05:28:59 PM PDT 24
Peak memory 207476 kb
Host smart-073b7b74-f45c-4ac0-b93a-653465194c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882728056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.882728056
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3072856446
Short name T604
Test name
Test status
Simulation time 174494188 ps
CPU time 0.93 seconds
Started Jul 17 05:28:59 PM PDT 24
Finished Jul 17 05:29:02 PM PDT 24
Peak memory 217108 kb
Host smart-67ccc493-d2f9-4402-a42c-80e48e62b82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072856446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3072856446
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1241045377
Short name T200
Test name
Test status
Simulation time 14766603975 ps
CPU time 176.02 seconds
Started Jul 17 05:28:56 PM PDT 24
Finished Jul 17 05:31:53 PM PDT 24
Peak memory 265504 kb
Host smart-980df3f3-7462-41f9-a39b-3fad3cbc4f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241045377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1241045377
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4106094798
Short name T924
Test name
Test status
Simulation time 499168152 ps
CPU time 3.14 seconds
Started Jul 17 05:32:30 PM PDT 24
Finished Jul 17 05:32:34 PM PDT 24
Peak memory 219796 kb
Host smart-8d822d8c-eb08-4290-b263-820ef476cf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106094798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4106094798
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3670241644
Short name T224
Test name
Test status
Simulation time 576025127 ps
CPU time 4.91 seconds
Started Jul 17 05:32:37 PM PDT 24
Finished Jul 17 05:32:43 PM PDT 24
Peak memory 225504 kb
Host smart-74028aec-70d1-451f-bd9d-8e062dc70a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670241644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3670241644
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1269911813
Short name T645
Test name
Test status
Simulation time 5981764650 ps
CPU time 6.17 seconds
Started Jul 17 05:28:59 PM PDT 24
Finished Jul 17 05:29:06 PM PDT 24
Peak memory 235308 kb
Host smart-839383b8-8652-4d3c-83cd-31d78028d821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269911813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1269911813
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3993060754
Short name T853
Test name
Test status
Simulation time 1326073627 ps
CPU time 8.23 seconds
Started Jul 17 05:28:51 PM PDT 24
Finished Jul 17 05:29:01 PM PDT 24
Peak memory 233796 kb
Host smart-98fc1a1f-3767-405e-9f1a-7da03609cc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993060754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3993060754
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2414096957
Short name T418
Test name
Test status
Simulation time 8709010261 ps
CPU time 10.46 seconds
Started Jul 17 05:33:10 PM PDT 24
Finished Jul 17 05:33:21 PM PDT 24
Peak memory 224336 kb
Host smart-56c1d589-df74-4288-9481-b873d224fb96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2414096957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2414096957
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.140408319
Short name T754
Test name
Test status
Simulation time 4186818462 ps
CPU time 55.89 seconds
Started Jul 17 05:28:51 PM PDT 24
Finished Jul 17 05:29:47 PM PDT 24
Peak memory 257812 kb
Host smart-53aa765a-cb90-4dfb-af98-fa81ef9ff956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140408319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.140408319
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2160372331
Short name T857
Test name
Test status
Simulation time 35730252009 ps
CPU time 33.38 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:29:53 PM PDT 24
Peak memory 216768 kb
Host smart-112e128d-d4d2-4455-b659-8f8fffd54ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160372331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2160372331
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3822237211
Short name T973
Test name
Test status
Simulation time 775888859 ps
CPU time 6.09 seconds
Started Jul 17 05:28:51 PM PDT 24
Finished Jul 17 05:28:58 PM PDT 24
Peak memory 217284 kb
Host smart-a85a5092-5b5e-4190-895a-5ea8d68c7eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822237211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3822237211
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.553306912
Short name T928
Test name
Test status
Simulation time 489284119 ps
CPU time 5.52 seconds
Started Jul 17 05:33:53 PM PDT 24
Finished Jul 17 05:34:03 PM PDT 24
Peak memory 217236 kb
Host smart-ee025d7b-97d1-416b-8f55-8bfdab123540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553306912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.553306912
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1103409243
Short name T600
Test name
Test status
Simulation time 16652376 ps
CPU time 0.77 seconds
Started Jul 17 05:32:37 PM PDT 24
Finished Jul 17 05:32:39 PM PDT 24
Peak memory 206928 kb
Host smart-b6619845-6197-40a6-a3e2-c01682e5bec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103409243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1103409243
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3693408930
Short name T435
Test name
Test status
Simulation time 217391026 ps
CPU time 3.76 seconds
Started Jul 17 05:28:52 PM PDT 24
Finished Jul 17 05:28:58 PM PDT 24
Peak memory 238028 kb
Host smart-f0886604-823b-4115-9f8f-078a92dd5ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693408930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3693408930
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.22301500
Short name T1009
Test name
Test status
Simulation time 14384563 ps
CPU time 0.72 seconds
Started Jul 17 05:29:06 PM PDT 24
Finished Jul 17 05:29:07 PM PDT 24
Peak memory 205808 kb
Host smart-b0a012fb-15d3-47b4-ba44-15c8c5228518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22301500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.22301500
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3395351219
Short name T174
Test name
Test status
Simulation time 1867817334 ps
CPU time 6.2 seconds
Started Jul 17 05:31:26 PM PDT 24
Finished Jul 17 05:31:34 PM PDT 24
Peak memory 233716 kb
Host smart-95a47597-6fc9-405a-bfed-4633de2bd64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395351219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3395351219
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4166991104
Short name T284
Test name
Test status
Simulation time 30312552 ps
CPU time 0.74 seconds
Started Jul 17 05:28:59 PM PDT 24
Finished Jul 17 05:29:00 PM PDT 24
Peak memory 206784 kb
Host smart-5b1592db-ca85-45b1-9341-251ea7dcb990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166991104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4166991104
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.803334283
Short name T575
Test name
Test status
Simulation time 5070520678 ps
CPU time 72.35 seconds
Started Jul 17 05:28:52 PM PDT 24
Finished Jul 17 05:30:06 PM PDT 24
Peak memory 257772 kb
Host smart-7d7365d5-7fca-41cc-806b-830335040ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803334283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.803334283
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1264394149
Short name T955
Test name
Test status
Simulation time 22896586117 ps
CPU time 200.73 seconds
Started Jul 17 05:28:51 PM PDT 24
Finished Jul 17 05:32:12 PM PDT 24
Peak memory 252256 kb
Host smart-a5367a7f-7519-4d16-a8f6-8c4990ebd54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264394149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1264394149
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1430216577
Short name T1015
Test name
Test status
Simulation time 62536203674 ps
CPU time 562.59 seconds
Started Jul 17 05:34:13 PM PDT 24
Finished Jul 17 05:43:40 PM PDT 24
Peak memory 267032 kb
Host smart-29c794b8-2e66-497c-b8d2-cbc548fb7f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430216577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1430216577
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1554545437
Short name T695
Test name
Test status
Simulation time 463007559 ps
CPU time 4.2 seconds
Started Jul 17 05:28:48 PM PDT 24
Finished Jul 17 05:28:53 PM PDT 24
Peak memory 225576 kb
Host smart-f56bc708-adde-43c9-a99f-a874d39096f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554545437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1554545437
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2731509170
Short name T169
Test name
Test status
Simulation time 21783643611 ps
CPU time 66.89 seconds
Started Jul 17 05:33:50 PM PDT 24
Finished Jul 17 05:35:00 PM PDT 24
Peak memory 238140 kb
Host smart-c0c1294d-e7bb-4aac-9421-b10fda8e68a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731509170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2731509170
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.22014999
Short name T190
Test name
Test status
Simulation time 10612930237 ps
CPU time 13.47 seconds
Started Jul 17 05:33:10 PM PDT 24
Finished Jul 17 05:33:24 PM PDT 24
Peak memory 233876 kb
Host smart-168cf7e2-f045-402d-878a-55f6f9221abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22014999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.22014999
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2737287860
Short name T669
Test name
Test status
Simulation time 120935746 ps
CPU time 2.51 seconds
Started Jul 17 05:28:52 PM PDT 24
Finished Jul 17 05:28:56 PM PDT 24
Peak memory 233520 kb
Host smart-f811d42e-4a15-4adb-9ba9-3cb6de44e2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737287860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2737287860
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4215498082
Short name T317
Test name
Test status
Simulation time 2023303686 ps
CPU time 5.31 seconds
Started Jul 17 05:28:54 PM PDT 24
Finished Jul 17 05:29:00 PM PDT 24
Peak memory 225564 kb
Host smart-ed60834a-fc56-4ff8-8000-a069da86538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215498082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4215498082
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.734731792
Short name T950
Test name
Test status
Simulation time 9234328726 ps
CPU time 16.62 seconds
Started Jul 17 05:28:51 PM PDT 24
Finished Jul 17 05:29:08 PM PDT 24
Peak memory 241680 kb
Host smart-362afbb9-2b5d-404b-bc2a-0a8781f041fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734731792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.734731792
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.725553940
Short name T739
Test name
Test status
Simulation time 974689984 ps
CPU time 5.08 seconds
Started Jul 17 05:33:53 PM PDT 24
Finished Jul 17 05:34:02 PM PDT 24
Peak memory 222564 kb
Host smart-a1944760-60c8-4370-bd04-bb06e24b4022
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=725553940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.725553940
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.802378006
Short name T883
Test name
Test status
Simulation time 24979963634 ps
CPU time 74.2 seconds
Started Jul 17 05:33:03 PM PDT 24
Finished Jul 17 05:34:18 PM PDT 24
Peak memory 242184 kb
Host smart-f230509b-4318-4030-b786-b3ba0d466b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802378006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.802378006
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2103193113
Short name T761
Test name
Test status
Simulation time 21953476099 ps
CPU time 31.98 seconds
Started Jul 17 05:28:57 PM PDT 24
Finished Jul 17 05:29:30 PM PDT 24
Peak memory 217460 kb
Host smart-9b56689d-c4e4-48d2-8bc4-466a3b674e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103193113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2103193113
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1390345365
Short name T562
Test name
Test status
Simulation time 25290368 ps
CPU time 0.7 seconds
Started Jul 17 05:28:57 PM PDT 24
Finished Jul 17 05:28:59 PM PDT 24
Peak memory 206596 kb
Host smart-bcbb08dd-569d-41c9-af27-d32974edcdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390345365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1390345365
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3781785527
Short name T346
Test name
Test status
Simulation time 38258342 ps
CPU time 0.73 seconds
Started Jul 17 05:28:51 PM PDT 24
Finished Jul 17 05:28:52 PM PDT 24
Peak memory 206932 kb
Host smart-5556d42d-d9c1-46a3-bd46-d4a6ef2cfbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781785527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3781785527
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.956213101
Short name T767
Test name
Test status
Simulation time 136562826 ps
CPU time 0.86 seconds
Started Jul 17 05:28:59 PM PDT 24
Finished Jul 17 05:29:01 PM PDT 24
Peak memory 206944 kb
Host smart-bae06134-c14d-496d-878e-d06f5beb4168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956213101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.956213101
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1163629744
Short name T878
Test name
Test status
Simulation time 11472874095 ps
CPU time 21.87 seconds
Started Jul 17 05:28:46 PM PDT 24
Finished Jul 17 05:29:09 PM PDT 24
Peak memory 240320 kb
Host smart-59d37512-e82d-424a-a89b-31bb9701aec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163629744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1163629744
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.781736132
Short name T1
Test name
Test status
Simulation time 18403115 ps
CPU time 0.71 seconds
Started Jul 17 05:29:09 PM PDT 24
Finished Jul 17 05:29:11 PM PDT 24
Peak memory 205720 kb
Host smart-ed1ca81c-db8a-40e8-9c57-18ed35edd0f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781736132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.781736132
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3694014935
Short name T954
Test name
Test status
Simulation time 12428897523 ps
CPU time 20.83 seconds
Started Jul 17 05:29:13 PM PDT 24
Finished Jul 17 05:29:34 PM PDT 24
Peak memory 233808 kb
Host smart-c1ae9b39-89f1-47e3-9e22-5f240426e803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694014935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3694014935
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1156614260
Short name T417
Test name
Test status
Simulation time 17730866 ps
CPU time 0.76 seconds
Started Jul 17 05:32:51 PM PDT 24
Finished Jul 17 05:32:52 PM PDT 24
Peak memory 207540 kb
Host smart-758a5671-eb24-4942-ac96-f3de68ceeca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156614260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1156614260
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2583895290
Short name T477
Test name
Test status
Simulation time 49255936744 ps
CPU time 104.16 seconds
Started Jul 17 05:32:54 PM PDT 24
Finished Jul 17 05:34:39 PM PDT 24
Peak memory 254888 kb
Host smart-5d233411-ec85-4f6c-990a-d294201523af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583895290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2583895290
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1119034631
Short name T538
Test name
Test status
Simulation time 15539543286 ps
CPU time 28.22 seconds
Started Jul 17 05:29:12 PM PDT 24
Finished Jul 17 05:29:42 PM PDT 24
Peak memory 225792 kb
Host smart-aa7be777-3794-4ac5-80c7-9eff0a2fb336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119034631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1119034631
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3869411267
Short name T223
Test name
Test status
Simulation time 11921232335 ps
CPU time 125.76 seconds
Started Jul 17 05:33:46 PM PDT 24
Finished Jul 17 05:35:53 PM PDT 24
Peak memory 257656 kb
Host smart-feb69e6e-3c13-47fb-a121-0d7b97fd1d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869411267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3869411267
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3774992393
Short name T911
Test name
Test status
Simulation time 3279982811 ps
CPU time 26.3 seconds
Started Jul 17 05:29:13 PM PDT 24
Finished Jul 17 05:29:40 PM PDT 24
Peak memory 225640 kb
Host smart-fbc986b3-e1dc-41fc-a1cf-31d59abeb231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774992393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3774992393
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2284161584
Short name T547
Test name
Test status
Simulation time 187043048 ps
CPU time 3.2 seconds
Started Jul 17 05:30:28 PM PDT 24
Finished Jul 17 05:30:34 PM PDT 24
Peak memory 232980 kb
Host smart-56a7392d-3886-4d7a-ae2c-a871b883e278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284161584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2284161584
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4120944119
Short name T411
Test name
Test status
Simulation time 4439401047 ps
CPU time 26.11 seconds
Started Jul 17 05:29:05 PM PDT 24
Finished Jul 17 05:29:32 PM PDT 24
Peak memory 233812 kb
Host smart-dbb29ffc-7f04-4501-8c63-bca478818b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120944119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4120944119
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1094208446
Short name T768
Test name
Test status
Simulation time 558249255 ps
CPU time 4.67 seconds
Started Jul 17 05:29:16 PM PDT 24
Finished Jul 17 05:29:22 PM PDT 24
Peak memory 225536 kb
Host smart-5eae44d4-a1db-45a6-be9e-30a12368cf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094208446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1094208446
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1200015991
Short name T465
Test name
Test status
Simulation time 320234368 ps
CPU time 3.46 seconds
Started Jul 17 05:30:49 PM PDT 24
Finished Jul 17 05:30:54 PM PDT 24
Peak memory 225540 kb
Host smart-3c227ff4-337c-48ef-b138-b04c0456669e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200015991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1200015991
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1281070568
Short name T932
Test name
Test status
Simulation time 344552288 ps
CPU time 6.68 seconds
Started Jul 17 05:29:11 PM PDT 24
Finished Jul 17 05:29:19 PM PDT 24
Peak memory 223492 kb
Host smart-2bafd4a8-4c34-4e55-843a-a2ff04992f7d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1281070568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1281070568
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3089238152
Short name T349
Test name
Test status
Simulation time 2622001680 ps
CPU time 35.45 seconds
Started Jul 17 05:33:46 PM PDT 24
Finished Jul 17 05:34:22 PM PDT 24
Peak memory 241016 kb
Host smart-58ebed93-083c-4748-8d24-dee871fb6791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089238152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3089238152
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1126142211
Short name T315
Test name
Test status
Simulation time 363604836 ps
CPU time 5.94 seconds
Started Jul 17 05:30:00 PM PDT 24
Finished Jul 17 05:30:07 PM PDT 24
Peak memory 217284 kb
Host smart-89c90c9c-1f23-4854-b35a-223a123b1fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126142211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1126142211
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.800943583
Short name T847
Test name
Test status
Simulation time 5297395867 ps
CPU time 7.95 seconds
Started Jul 17 05:29:12 PM PDT 24
Finished Jul 17 05:29:21 PM PDT 24
Peak memory 217444 kb
Host smart-bf407423-6ea2-4886-a46e-6571f617c994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800943583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.800943583
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3884105534
Short name T343
Test name
Test status
Simulation time 376576221 ps
CPU time 2.65 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:30:24 PM PDT 24
Peak memory 217352 kb
Host smart-c10453bd-a41f-42bb-b594-ab67a0310d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884105534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3884105534
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2662056603
Short name T800
Test name
Test status
Simulation time 300223952 ps
CPU time 0.99 seconds
Started Jul 17 05:33:40 PM PDT 24
Finished Jul 17 05:33:43 PM PDT 24
Peak memory 206936 kb
Host smart-6ac95280-e239-49a1-b50e-ac8640ce791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662056603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2662056603
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3646534885
Short name T75
Test name
Test status
Simulation time 2178497698 ps
CPU time 9.94 seconds
Started Jul 17 05:34:08 PM PDT 24
Finished Jul 17 05:34:19 PM PDT 24
Peak memory 219952 kb
Host smart-dea93480-5bd6-40f7-8962-03b63d3d17be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646534885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3646534885
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2817385157
Short name T561
Test name
Test status
Simulation time 16805468 ps
CPU time 0.75 seconds
Started Jul 17 05:33:43 PM PDT 24
Finished Jul 17 05:33:44 PM PDT 24
Peak memory 205752 kb
Host smart-b416c50e-7ebc-4821-8f09-44d0ce470463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817385157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2817385157
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2557668152
Short name T802
Test name
Test status
Simulation time 482908255 ps
CPU time 2.5 seconds
Started Jul 17 05:29:10 PM PDT 24
Finished Jul 17 05:29:14 PM PDT 24
Peak memory 225464 kb
Host smart-a5673208-61e6-4b6a-a7c7-75861502f20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557668152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2557668152
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3051534236
Short name T624
Test name
Test status
Simulation time 53115654 ps
CPU time 0.74 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:29:21 PM PDT 24
Peak memory 206484 kb
Host smart-0a9627b2-d79c-496e-b355-43c521689cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051534236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3051534236
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1697625305
Short name T42
Test name
Test status
Simulation time 160908799929 ps
CPU time 513.88 seconds
Started Jul 17 05:29:11 PM PDT 24
Finished Jul 17 05:37:45 PM PDT 24
Peak memory 265468 kb
Host smart-7711de6a-1138-49d1-a67c-0747809d4760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697625305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1697625305
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.579451322
Short name T1023
Test name
Test status
Simulation time 3114323989 ps
CPU time 75.64 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:35:10 PM PDT 24
Peak memory 250276 kb
Host smart-ce1d6786-12d4-418f-a448-398459b53546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579451322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.579451322
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1444857406
Short name T451
Test name
Test status
Simulation time 30763966597 ps
CPU time 246.9 seconds
Started Jul 17 05:34:11 PM PDT 24
Finished Jul 17 05:38:22 PM PDT 24
Peak memory 253756 kb
Host smart-0b4aa696-623b-4856-8a09-ec36cf1f660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444857406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1444857406
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.959404975
Short name T877
Test name
Test status
Simulation time 2413086321 ps
CPU time 12.59 seconds
Started Jul 17 05:29:06 PM PDT 24
Finished Jul 17 05:29:19 PM PDT 24
Peak memory 241900 kb
Host smart-2d0d4492-c2d6-48fd-86bc-2968a32370e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959404975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.959404975
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2307376949
Short name T502
Test name
Test status
Simulation time 13422808094 ps
CPU time 109.05 seconds
Started Jul 17 05:29:15 PM PDT 24
Finished Jul 17 05:31:06 PM PDT 24
Peak memory 251368 kb
Host smart-8a09bd93-bcab-4291-9071-cacd932fa8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307376949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2307376949
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.935104040
Short name T568
Test name
Test status
Simulation time 562265790 ps
CPU time 4.3 seconds
Started Jul 17 05:29:11 PM PDT 24
Finished Jul 17 05:29:16 PM PDT 24
Peak memory 225532 kb
Host smart-02c18766-c360-4f6a-bd32-f72d7e0560f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935104040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.935104040
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3739981564
Short name T869
Test name
Test status
Simulation time 3924914248 ps
CPU time 35.29 seconds
Started Jul 17 05:29:15 PM PDT 24
Finished Jul 17 05:29:51 PM PDT 24
Peak memory 233868 kb
Host smart-d5129cac-bdfb-4101-b911-56d7dba0468a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739981564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3739981564
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2661308436
Short name T956
Test name
Test status
Simulation time 1892341641 ps
CPU time 10.74 seconds
Started Jul 17 05:29:05 PM PDT 24
Finished Jul 17 05:29:16 PM PDT 24
Peak memory 236376 kb
Host smart-dfd797a7-06b0-468d-8a93-a063b8ffe51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661308436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2661308436
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3531888516
Short name T233
Test name
Test status
Simulation time 662353129 ps
CPU time 4.54 seconds
Started Jul 17 05:33:53 PM PDT 24
Finished Jul 17 05:34:01 PM PDT 24
Peak memory 233700 kb
Host smart-7c3e641b-f19d-419e-bd0a-fb55f321ad2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531888516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3531888516
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2606281882
Short name T876
Test name
Test status
Simulation time 18925936795 ps
CPU time 19.51 seconds
Started Jul 17 05:29:16 PM PDT 24
Finished Jul 17 05:29:37 PM PDT 24
Peak memory 220752 kb
Host smart-8f047029-2bb6-416e-ba29-ae4196f6606f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2606281882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2606281882
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1990061453
Short name T979
Test name
Test status
Simulation time 81311464346 ps
CPU time 41.93 seconds
Started Jul 17 05:29:13 PM PDT 24
Finished Jul 17 05:29:56 PM PDT 24
Peak memory 217452 kb
Host smart-562aa176-125c-4876-b734-c2a9f4c4c3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990061453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1990061453
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3203650350
Short name T310
Test name
Test status
Simulation time 2233001923 ps
CPU time 4.66 seconds
Started Jul 17 05:29:03 PM PDT 24
Finished Jul 17 05:29:09 PM PDT 24
Peak memory 217492 kb
Host smart-e7c64c24-80e5-4502-ae1b-8afbe1d60274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203650350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3203650350
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3785456041
Short name T337
Test name
Test status
Simulation time 31546985 ps
CPU time 0.67 seconds
Started Jul 17 05:33:10 PM PDT 24
Finished Jul 17 05:33:12 PM PDT 24
Peak memory 206540 kb
Host smart-57246f3f-c010-47e9-849a-caa855b933f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785456041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3785456041
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1259511531
Short name T880
Test name
Test status
Simulation time 56110651 ps
CPU time 0.75 seconds
Started Jul 17 05:29:12 PM PDT 24
Finished Jul 17 05:29:14 PM PDT 24
Peak memory 206908 kb
Host smart-9b5c1cc4-4b72-41c8-8834-1c0e219c2744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259511531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1259511531
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1045799003
Short name T567
Test name
Test status
Simulation time 4190082274 ps
CPU time 5.34 seconds
Started Jul 17 05:29:16 PM PDT 24
Finished Jul 17 05:29:23 PM PDT 24
Peak memory 233796 kb
Host smart-f05269ed-d098-4cf3-b73f-f8b1460a8953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045799003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1045799003
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3005282094
Short name T82
Test name
Test status
Simulation time 15055072 ps
CPU time 0.79 seconds
Started Jul 17 05:29:16 PM PDT 24
Finished Jul 17 05:29:18 PM PDT 24
Peak memory 205720 kb
Host smart-14d06700-1235-4a59-98a9-b0652b92f5fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005282094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3005282094
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2354338062
Short name T498
Test name
Test status
Simulation time 92375312 ps
CPU time 3.41 seconds
Started Jul 17 05:29:15 PM PDT 24
Finished Jul 17 05:29:19 PM PDT 24
Peak memory 225544 kb
Host smart-58207ea3-8c08-4423-b0af-dab10eb05be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354338062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2354338062
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1336223286
Short name T951
Test name
Test status
Simulation time 36951185 ps
CPU time 0.8 seconds
Started Jul 17 05:34:11 PM PDT 24
Finished Jul 17 05:34:16 PM PDT 24
Peak memory 208060 kb
Host smart-4eb62301-6ab7-4c20-b5ad-98d02a6229fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336223286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1336223286
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3269830525
Short name T407
Test name
Test status
Simulation time 64198385318 ps
CPU time 218.69 seconds
Started Jul 17 05:29:12 PM PDT 24
Finished Jul 17 05:32:52 PM PDT 24
Peak memory 250524 kb
Host smart-a31e9940-c7f8-4942-8680-4a28b5161a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269830525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3269830525
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1154231895
Short name T275
Test name
Test status
Simulation time 9958448527 ps
CPU time 28.99 seconds
Started Jul 17 05:29:12 PM PDT 24
Finished Jul 17 05:29:42 PM PDT 24
Peak memory 242172 kb
Host smart-577c4bfa-ed77-4471-ac51-01e0ed56eff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154231895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1154231895
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1122656940
Short name T188
Test name
Test status
Simulation time 73347493726 ps
CPU time 194.71 seconds
Started Jul 17 05:32:37 PM PDT 24
Finished Jul 17 05:35:53 PM PDT 24
Peak memory 258616 kb
Host smart-183b9c33-4cad-4ed5-9f58-90dee9c5e482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122656940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1122656940
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2280279751
Short name T270
Test name
Test status
Simulation time 4141459150 ps
CPU time 17.73 seconds
Started Jul 17 05:33:56 PM PDT 24
Finished Jul 17 05:34:17 PM PDT 24
Peak memory 233900 kb
Host smart-f2083463-3ed9-494e-ab7e-421ed6a4c590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280279751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2280279751
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.4035956560
Short name T219
Test name
Test status
Simulation time 804704566 ps
CPU time 5.85 seconds
Started Jul 17 05:30:48 PM PDT 24
Finished Jul 17 05:30:55 PM PDT 24
Peak memory 225548 kb
Host smart-4d1535ce-20cf-4945-a06b-f16975825cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035956560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.4035956560
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3255182048
Short name T692
Test name
Test status
Simulation time 924923401 ps
CPU time 5.08 seconds
Started Jul 17 05:30:49 PM PDT 24
Finished Jul 17 05:30:55 PM PDT 24
Peak memory 233736 kb
Host smart-54c7b8cb-5593-47d3-85be-561a4eaebbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255182048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3255182048
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.4229781306
Short name T412
Test name
Test status
Simulation time 8361001118 ps
CPU time 73.27 seconds
Started Jul 17 05:29:16 PM PDT 24
Finished Jul 17 05:30:31 PM PDT 24
Peak memory 233780 kb
Host smart-2a2b7f27-03d1-43f8-81cc-a0de86d3b1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229781306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4229781306
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3832244568
Short name T236
Test name
Test status
Simulation time 28343547966 ps
CPU time 32.94 seconds
Started Jul 17 05:29:15 PM PDT 24
Finished Jul 17 05:29:49 PM PDT 24
Peak memory 242012 kb
Host smart-3dba7704-288f-4ee1-8e62-e46c1397ccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832244568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3832244568
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2820501684
Short name T745
Test name
Test status
Simulation time 1199968481 ps
CPU time 8.2 seconds
Started Jul 17 05:33:55 PM PDT 24
Finished Jul 17 05:34:06 PM PDT 24
Peak memory 241436 kb
Host smart-ef48f980-b426-4af7-b021-badaed793dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820501684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2820501684
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3263608720
Short name T958
Test name
Test status
Simulation time 105169199 ps
CPU time 3.54 seconds
Started Jul 17 05:33:55 PM PDT 24
Finished Jul 17 05:34:02 PM PDT 24
Peak memory 221396 kb
Host smart-ddf2c61b-d438-4bb3-991f-2ab36e50765d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3263608720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3263608720
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2039052832
Short name T17
Test name
Test status
Simulation time 139394785 ps
CPU time 1.25 seconds
Started Jul 17 05:29:15 PM PDT 24
Finished Jul 17 05:29:17 PM PDT 24
Peak memory 208052 kb
Host smart-1da41aee-08af-4dd4-9641-ecc1a03ad9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039052832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2039052832
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1669897137
Short name T353
Test name
Test status
Simulation time 2367936820 ps
CPU time 6.82 seconds
Started Jul 17 05:34:08 PM PDT 24
Finished Jul 17 05:34:17 PM PDT 24
Peak memory 217476 kb
Host smart-bd559400-a11c-4e35-8acb-0554b0b6c093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669897137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1669897137
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3064942140
Short name T492
Test name
Test status
Simulation time 230635239 ps
CPU time 2.01 seconds
Started Jul 17 05:29:10 PM PDT 24
Finished Jul 17 05:29:13 PM PDT 24
Peak memory 208872 kb
Host smart-3f601d02-0ebc-4081-b37c-c5adb2181f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064942140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3064942140
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3134441132
Short name T824
Test name
Test status
Simulation time 153821869 ps
CPU time 2.06 seconds
Started Jul 17 05:29:10 PM PDT 24
Finished Jul 17 05:29:13 PM PDT 24
Peak memory 217392 kb
Host smart-b2e7d431-793d-417c-b722-347053490d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134441132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3134441132
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.497266336
Short name T505
Test name
Test status
Simulation time 31416254 ps
CPU time 0.81 seconds
Started Jul 17 05:34:08 PM PDT 24
Finished Jul 17 05:34:10 PM PDT 24
Peak memory 206900 kb
Host smart-202fcfa6-3eb5-4a3a-bb9a-c5241d61e71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497266336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.497266336
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3118249678
Short name T655
Test name
Test status
Simulation time 1863804758 ps
CPU time 4.6 seconds
Started Jul 17 05:33:50 PM PDT 24
Finished Jul 17 05:33:58 PM PDT 24
Peak memory 225444 kb
Host smart-d6e1b5a4-b74e-4fb1-8560-7c85509cfa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118249678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3118249678
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2967832269
Short name T419
Test name
Test status
Simulation time 26997459 ps
CPU time 0.74 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:29:21 PM PDT 24
Peak memory 206360 kb
Host smart-d12e35d6-f231-425a-89f0-b94982e2cdd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967832269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2967832269
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.601350086
Short name T520
Test name
Test status
Simulation time 1289096590 ps
CPU time 10.61 seconds
Started Jul 17 05:29:15 PM PDT 24
Finished Jul 17 05:29:27 PM PDT 24
Peak memory 225556 kb
Host smart-b5fc4f9f-9794-4445-9556-9156bfcee114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601350086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.601350086
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1758605038
Short name T630
Test name
Test status
Simulation time 34363221 ps
CPU time 0.77 seconds
Started Jul 17 05:29:12 PM PDT 24
Finished Jul 17 05:29:13 PM PDT 24
Peak memory 207492 kb
Host smart-b5589c6c-27ad-4f92-8971-ff141d4183f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758605038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1758605038
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.4022410682
Short name T40
Test name
Test status
Simulation time 341482602 ps
CPU time 7.77 seconds
Started Jul 17 05:32:39 PM PDT 24
Finished Jul 17 05:32:48 PM PDT 24
Peak memory 235112 kb
Host smart-3c722db6-3b88-4a9f-b654-f8fc2d93db0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022410682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4022410682
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3966767741
Short name T397
Test name
Test status
Simulation time 100624651393 ps
CPU time 194.98 seconds
Started Jul 17 05:29:11 PM PDT 24
Finished Jul 17 05:32:26 PM PDT 24
Peak memory 264068 kb
Host smart-6ae717e9-8001-46e6-afd8-5bc7e3e08d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966767741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3966767741
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3032359775
Short name T395
Test name
Test status
Simulation time 4835667391 ps
CPU time 68.53 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:30:29 PM PDT 24
Peak memory 250340 kb
Host smart-131f91c1-ef4e-4964-9560-668c1a7ee38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032359775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3032359775
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1794592734
Short name T268
Test name
Test status
Simulation time 7105455566 ps
CPU time 37.6 seconds
Started Jul 17 05:32:37 PM PDT 24
Finished Jul 17 05:33:15 PM PDT 24
Peak memory 242140 kb
Host smart-ee935fd7-70a1-42b6-a494-0fd72eadaa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794592734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1794592734
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1597497948
Short name T166
Test name
Test status
Simulation time 143864755463 ps
CPU time 181.16 seconds
Started Jul 17 05:29:16 PM PDT 24
Finished Jul 17 05:32:19 PM PDT 24
Peak memory 250648 kb
Host smart-c2aa0f66-73eb-413b-b748-f4c6d28e1c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597497948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1597497948
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1417704417
Short name T694
Test name
Test status
Simulation time 1147668158 ps
CPU time 4.72 seconds
Started Jul 17 05:29:16 PM PDT 24
Finished Jul 17 05:29:21 PM PDT 24
Peak memory 225480 kb
Host smart-a2c4d92d-e658-4f49-9ffc-c3d9a0e0e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417704417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1417704417
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2400032068
Short name T316
Test name
Test status
Simulation time 16090788181 ps
CPU time 20.26 seconds
Started Jul 17 05:29:07 PM PDT 24
Finished Jul 17 05:29:28 PM PDT 24
Peak memory 240756 kb
Host smart-2bd3bb7c-37a7-49a7-960c-5ad701864718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400032068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2400032068
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4148382451
Short name T707
Test name
Test status
Simulation time 766935278 ps
CPU time 3.48 seconds
Started Jul 17 05:32:37 PM PDT 24
Finished Jul 17 05:32:41 PM PDT 24
Peak memory 233816 kb
Host smart-84b276f3-006f-427a-989d-fa036a0bdd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148382451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4148382451
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3730673313
Short name T589
Test name
Test status
Simulation time 351253436 ps
CPU time 4.78 seconds
Started Jul 17 05:32:49 PM PDT 24
Finished Jul 17 05:32:55 PM PDT 24
Peak memory 233748 kb
Host smart-651a89ee-db44-4ef8-9e4f-36f8a00b3174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730673313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3730673313
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4002941076
Short name T654
Test name
Test status
Simulation time 1592721397 ps
CPU time 12.93 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:29:33 PM PDT 24
Peak memory 224164 kb
Host smart-7b19e9ac-99f1-4378-88a4-c863881e9301
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4002941076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4002941076
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.577234553
Short name T770
Test name
Test status
Simulation time 2311110564 ps
CPU time 28.24 seconds
Started Jul 17 05:29:15 PM PDT 24
Finished Jul 17 05:29:45 PM PDT 24
Peak memory 217732 kb
Host smart-14168484-c8b9-4a70-9009-e8569f4d98d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577234553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.577234553
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1041039368
Short name T720
Test name
Test status
Simulation time 4341027297 ps
CPU time 9.81 seconds
Started Jul 17 05:30:49 PM PDT 24
Finished Jul 17 05:31:00 PM PDT 24
Peak memory 217480 kb
Host smart-1148504f-c997-401d-885e-5843b44edda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041039368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1041039368
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.591043694
Short name T653
Test name
Test status
Simulation time 180789015 ps
CPU time 2.07 seconds
Started Jul 17 05:29:16 PM PDT 24
Finished Jul 17 05:29:19 PM PDT 24
Peak memory 217296 kb
Host smart-9014bb65-3fce-47e8-8529-08e4d33f4359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591043694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.591043694
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1570759086
Short name T548
Test name
Test status
Simulation time 60916366 ps
CPU time 0.86 seconds
Started Jul 17 05:32:39 PM PDT 24
Finished Jul 17 05:32:41 PM PDT 24
Peak memory 206908 kb
Host smart-b29c8dce-eb79-419a-bedb-d12890af2049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570759086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1570759086
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.102965591
Short name T509
Test name
Test status
Simulation time 11205926518 ps
CPU time 10.68 seconds
Started Jul 17 05:32:37 PM PDT 24
Finished Jul 17 05:32:48 PM PDT 24
Peak memory 241836 kb
Host smart-eea6732b-52e1-436b-b853-9884a7b60b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102965591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.102965591
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4232095956
Short name T399
Test name
Test status
Simulation time 101231013 ps
CPU time 0.72 seconds
Started Jul 17 05:32:55 PM PDT 24
Finished Jul 17 05:32:58 PM PDT 24
Peak memory 206348 kb
Host smart-e3699073-90a2-4c27-b47a-64ea305ef9f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232095956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4232095956
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1886304126
Short name T431
Test name
Test status
Simulation time 2463415582 ps
CPU time 6.59 seconds
Started Jul 17 05:29:26 PM PDT 24
Finished Jul 17 05:29:34 PM PDT 24
Peak memory 225672 kb
Host smart-332c58b2-ef8b-418f-ad1c-751776f95515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886304126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1886304126
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3735185787
Short name T14
Test name
Test status
Simulation time 41547004 ps
CPU time 0.78 seconds
Started Jul 17 05:29:09 PM PDT 24
Finished Jul 17 05:29:10 PM PDT 24
Peak memory 207516 kb
Host smart-ce97012c-3f44-409b-ad25-cc1103b66e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735185787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3735185787
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3959623693
Short name T52
Test name
Test status
Simulation time 20021946742 ps
CPU time 196.49 seconds
Started Jul 17 05:29:17 PM PDT 24
Finished Jul 17 05:32:34 PM PDT 24
Peak memory 255748 kb
Host smart-574e5dc0-0199-403e-8a1c-7fd8e75548b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959623693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3959623693
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2410640588
Short name T496
Test name
Test status
Simulation time 104618009426 ps
CPU time 141.65 seconds
Started Jul 17 05:29:16 PM PDT 24
Finished Jul 17 05:31:39 PM PDT 24
Peak memory 250736 kb
Host smart-b9a17b5d-0f08-4bcd-94b8-ebda00d626f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410640588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2410640588
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3401133405
Short name T106
Test name
Test status
Simulation time 3646782648 ps
CPU time 27.55 seconds
Started Jul 17 05:29:25 PM PDT 24
Finished Jul 17 05:29:54 PM PDT 24
Peak memory 250232 kb
Host smart-f7a9bb77-dfc5-433b-aabd-01eaaf3850d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401133405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3401133405
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2074910943
Short name T870
Test name
Test status
Simulation time 70418001831 ps
CPU time 180.15 seconds
Started Jul 17 05:29:29 PM PDT 24
Finished Jul 17 05:32:30 PM PDT 24
Peak memory 261900 kb
Host smart-53651a36-c4f4-4391-a5ef-1ea2640bf642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074910943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2074910943
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.635632048
Short name T974
Test name
Test status
Simulation time 997347659 ps
CPU time 5.32 seconds
Started Jul 17 05:29:17 PM PDT 24
Finished Jul 17 05:29:25 PM PDT 24
Peak memory 225452 kb
Host smart-9acfe04a-e84d-4f5a-bf70-b39f7dfd8d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635632048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.635632048
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1633411419
Short name T704
Test name
Test status
Simulation time 49515851290 ps
CPU time 79.21 seconds
Started Jul 17 05:29:29 PM PDT 24
Finished Jul 17 05:30:49 PM PDT 24
Peak memory 250276 kb
Host smart-b935edc4-e096-43bf-9b4c-46977d5a517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633411419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1633411419
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3269220984
Short name T595
Test name
Test status
Simulation time 7955087263 ps
CPU time 23.4 seconds
Started Jul 17 05:34:11 PM PDT 24
Finished Jul 17 05:34:39 PM PDT 24
Peak memory 234108 kb
Host smart-abe4467a-9a1f-45a8-92dc-835f54a8118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269220984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3269220984
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1099147959
Short name T778
Test name
Test status
Simulation time 1205391486 ps
CPU time 2.78 seconds
Started Jul 17 05:34:13 PM PDT 24
Finished Jul 17 05:34:19 PM PDT 24
Peak memory 225556 kb
Host smart-b23bcaba-0527-4bc9-9f78-9c268ac0cfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099147959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1099147959
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2167632376
Short name T39
Test name
Test status
Simulation time 7839133018 ps
CPU time 15.24 seconds
Started Jul 17 05:33:50 PM PDT 24
Finished Jul 17 05:34:08 PM PDT 24
Peak memory 223952 kb
Host smart-9de8c875-b7b4-4969-a4f1-d4eda9ead03f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2167632376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2167632376
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3363988256
Short name T258
Test name
Test status
Simulation time 165910884637 ps
CPU time 532.92 seconds
Started Jul 17 05:29:29 PM PDT 24
Finished Jul 17 05:38:23 PM PDT 24
Peak memory 283084 kb
Host smart-d9084812-7ba4-47a2-9171-e590d2cfd268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363988256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3363988256
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3564442310
Short name T897
Test name
Test status
Simulation time 5585931546 ps
CPU time 15.18 seconds
Started Jul 17 05:34:14 PM PDT 24
Finished Jul 17 05:34:32 PM PDT 24
Peak memory 217456 kb
Host smart-5da1c45d-2111-45d1-8811-df9dad8f6286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564442310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3564442310
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3964544168
Short name T675
Test name
Test status
Simulation time 7832916707 ps
CPU time 24.07 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:29:44 PM PDT 24
Peak memory 217368 kb
Host smart-5848a5a4-3a68-4365-a776-7bd472e61be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964544168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3964544168
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1094920239
Short name T662
Test name
Test status
Simulation time 407867738 ps
CPU time 2.88 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:29:23 PM PDT 24
Peak memory 217284 kb
Host smart-35df4bde-6ed1-4252-bbc2-ca789ecef4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094920239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1094920239
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3181908910
Short name T325
Test name
Test status
Simulation time 139781911 ps
CPU time 0.83 seconds
Started Jul 17 05:29:25 PM PDT 24
Finished Jul 17 05:29:27 PM PDT 24
Peak memory 206904 kb
Host smart-cf30ec3a-6058-4f3e-bbaa-fc076bc6ee26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181908910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3181908910
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.818347474
Short name T909
Test name
Test status
Simulation time 2510564139 ps
CPU time 3.98 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:34:00 PM PDT 24
Peak memory 225568 kb
Host smart-318e6e94-d449-4247-9f82-f663a78a407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818347474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.818347474
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3814094615
Short name T331
Test name
Test status
Simulation time 16008525 ps
CPU time 0.72 seconds
Started Jul 17 05:29:20 PM PDT 24
Finished Jul 17 05:29:22 PM PDT 24
Peak memory 206340 kb
Host smart-222933e8-febb-4271-ac32-7166c2d66a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814094615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3814094615
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.24876413
Short name T513
Test name
Test status
Simulation time 175843720 ps
CPU time 2.85 seconds
Started Jul 17 05:32:55 PM PDT 24
Finished Jul 17 05:32:59 PM PDT 24
Peak memory 225396 kb
Host smart-866721c2-0d91-40f3-8410-2ccc390e501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24876413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.24876413
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4270075473
Short name T952
Test name
Test status
Simulation time 20902033 ps
CPU time 0.76 seconds
Started Jul 17 05:29:19 PM PDT 24
Finished Jul 17 05:29:22 PM PDT 24
Peak memory 207484 kb
Host smart-ff104765-20e3-4485-8868-31fdb8ee3087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270075473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4270075473
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1041653344
Short name T244
Test name
Test status
Simulation time 83821267300 ps
CPU time 102.14 seconds
Started Jul 17 05:34:13 PM PDT 24
Finished Jul 17 05:35:59 PM PDT 24
Peak memory 251940 kb
Host smart-f159a02c-0ac0-44d0-ad1a-1e0e2c12af8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041653344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1041653344
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3990006217
Short name T256
Test name
Test status
Simulation time 816528373 ps
CPU time 14.43 seconds
Started Jul 17 05:32:55 PM PDT 24
Finished Jul 17 05:33:10 PM PDT 24
Peak memory 250280 kb
Host smart-dacd3235-b0a0-4ec1-9aa5-c55432ba13e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990006217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3990006217
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1130755306
Short name T674
Test name
Test status
Simulation time 2774112907 ps
CPU time 59.5 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:30:20 PM PDT 24
Peak memory 250368 kb
Host smart-1f162859-6e69-4882-80a2-26e783ccab3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130755306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1130755306
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2135306577
Short name T822
Test name
Test status
Simulation time 572963750 ps
CPU time 13.22 seconds
Started Jul 17 05:29:26 PM PDT 24
Finished Jul 17 05:29:40 PM PDT 24
Peak memory 233720 kb
Host smart-3c1f4206-c3c2-4e68-b7ce-814f210e1e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135306577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2135306577
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.646567549
Short name T703
Test name
Test status
Simulation time 423502658 ps
CPU time 6.02 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:34:02 PM PDT 24
Peak memory 233676 kb
Host smart-05c25287-e293-4cde-a9f0-a32350c95a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646567549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.646567549
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1659430284
Short name T15
Test name
Test status
Simulation time 710423657 ps
CPU time 7.33 seconds
Started Jul 17 05:33:53 PM PDT 24
Finished Jul 17 05:34:05 PM PDT 24
Peak memory 233596 kb
Host smart-6df3b1fb-5857-41fc-936a-beee635af225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659430284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1659430284
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3096281636
Short name T207
Test name
Test status
Simulation time 4434707444 ps
CPU time 14.67 seconds
Started Jul 17 05:29:29 PM PDT 24
Finished Jul 17 05:29:45 PM PDT 24
Peak memory 242048 kb
Host smart-6467c9ca-a902-4d7f-b8d7-b559423094e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096281636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3096281636
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.589454880
Short name T420
Test name
Test status
Simulation time 2084130425 ps
CPU time 9.9 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:34:05 PM PDT 24
Peak memory 225536 kb
Host smart-26a871b3-0a7c-4f97-889c-af32719b741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589454880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.589454880
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1081184319
Short name T606
Test name
Test status
Simulation time 130830631 ps
CPU time 2.55 seconds
Started Jul 17 05:29:26 PM PDT 24
Finished Jul 17 05:29:29 PM PDT 24
Peak memory 233424 kb
Host smart-815cf8ca-d9da-4bf7-bcb2-45a94b24d2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081184319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1081184319
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.256918057
Short name T383
Test name
Test status
Simulation time 985835824 ps
CPU time 11.09 seconds
Started Jul 17 05:29:19 PM PDT 24
Finished Jul 17 05:29:32 PM PDT 24
Peak memory 223184 kb
Host smart-900b5b36-00de-4fa6-82d5-1438401a9226
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=256918057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.256918057
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.4172596077
Short name T758
Test name
Test status
Simulation time 23597456988 ps
CPU time 151.28 seconds
Started Jul 17 05:32:55 PM PDT 24
Finished Jul 17 05:35:28 PM PDT 24
Peak memory 265448 kb
Host smart-2debf984-e9c5-4d4f-b137-286018cfbc7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172596077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.4172596077
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.194918224
Short name T842
Test name
Test status
Simulation time 14278837 ps
CPU time 0.87 seconds
Started Jul 17 05:32:37 PM PDT 24
Finished Jul 17 05:32:39 PM PDT 24
Peak memory 206948 kb
Host smart-a376c035-6242-4c63-9a7f-5ed0fad418f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194918224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.194918224
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1556670240
Short name T871
Test name
Test status
Simulation time 1577113644 ps
CPU time 6.54 seconds
Started Jul 17 05:29:29 PM PDT 24
Finished Jul 17 05:29:37 PM PDT 24
Peak memory 217216 kb
Host smart-8c53b843-ad20-4248-a029-4f7360929b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556670240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1556670240
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3097957086
Short name T334
Test name
Test status
Simulation time 65809518 ps
CPU time 0.98 seconds
Started Jul 17 05:29:17 PM PDT 24
Finished Jul 17 05:29:20 PM PDT 24
Peak memory 207964 kb
Host smart-bd83d508-6aa2-4cbb-be90-072d7d87e92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097957086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3097957086
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1859254030
Short name T587
Test name
Test status
Simulation time 14676272 ps
CPU time 0.73 seconds
Started Jul 17 05:29:21 PM PDT 24
Finished Jul 17 05:29:23 PM PDT 24
Peak memory 206936 kb
Host smart-faee995a-8c26-4c7c-9de6-6f7ac4b419fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859254030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1859254030
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.561319365
Short name T507
Test name
Test status
Simulation time 6476277636 ps
CPU time 19.59 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:29:40 PM PDT 24
Peak memory 233932 kb
Host smart-8543e830-9452-433e-a149-c56e578df76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561319365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.561319365
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1566436426
Short name T887
Test name
Test status
Simulation time 18974184 ps
CPU time 0.71 seconds
Started Jul 17 05:32:55 PM PDT 24
Finished Jul 17 05:32:57 PM PDT 24
Peak memory 206684 kb
Host smart-c13f33fa-0af1-4d68-a7fd-5dbb0a6d062f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566436426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1566436426
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2846146549
Short name T434
Test name
Test status
Simulation time 113852330 ps
CPU time 2.39 seconds
Started Jul 17 05:34:13 PM PDT 24
Finished Jul 17 05:34:19 PM PDT 24
Peak memory 225108 kb
Host smart-730d67a1-5898-4bd1-becd-d30166443eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846146549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2846146549
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.38483920
Short name T290
Test name
Test status
Simulation time 16375967 ps
CPU time 0.77 seconds
Started Jul 17 05:33:55 PM PDT 24
Finished Jul 17 05:33:59 PM PDT 24
Peak memory 207372 kb
Host smart-3b16e0a3-3ff7-44b2-9f7f-ee42f8004fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38483920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.38483920
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2742923144
Short name T263
Test name
Test status
Simulation time 24211154521 ps
CPU time 132.69 seconds
Started Jul 17 05:33:55 PM PDT 24
Finished Jul 17 05:36:11 PM PDT 24
Peak memory 266836 kb
Host smart-4f68e3b2-ced2-496e-ac59-124581d916e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742923144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2742923144
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.339884376
Short name T260
Test name
Test status
Simulation time 72355724903 ps
CPU time 644.75 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:44:57 PM PDT 24
Peak memory 274824 kb
Host smart-4525ce24-9773-4881-9ae1-2f6ddc6233c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339884376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.339884376
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1206673994
Short name T677
Test name
Test status
Simulation time 47825935163 ps
CPU time 119.7 seconds
Started Jul 17 05:34:13 PM PDT 24
Finished Jul 17 05:36:17 PM PDT 24
Peak memory 256812 kb
Host smart-48839c38-3fab-4f9f-bf82-90facac0054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206673994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1206673994
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1232393670
Short name T437
Test name
Test status
Simulation time 490403743 ps
CPU time 6.04 seconds
Started Jul 17 05:33:56 PM PDT 24
Finished Jul 17 05:34:04 PM PDT 24
Peak memory 225420 kb
Host smart-0fc62eec-b2fa-4fa4-ba7e-39673780d596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232393670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1232393670
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2234832467
Short name T941
Test name
Test status
Simulation time 1012199575 ps
CPU time 13.54 seconds
Started Jul 17 05:34:13 PM PDT 24
Finished Jul 17 05:34:30 PM PDT 24
Peak memory 233772 kb
Host smart-e38ba478-bb9a-4a3d-8d99-07ad2f249f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234832467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2234832467
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4206314683
Short name T90
Test name
Test status
Simulation time 595845317 ps
CPU time 3.97 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:34:00 PM PDT 24
Peak memory 225372 kb
Host smart-64f71323-984f-4301-ae58-6a1ae9d3412d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206314683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4206314683
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2598555169
Short name T775
Test name
Test status
Simulation time 9313422199 ps
CPU time 25.75 seconds
Started Jul 17 05:32:37 PM PDT 24
Finished Jul 17 05:33:04 PM PDT 24
Peak memory 233808 kb
Host smart-a2038871-1d98-485f-a278-14d6db03c2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598555169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2598555169
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.901904930
Short name T497
Test name
Test status
Simulation time 181616950956 ps
CPU time 24.61 seconds
Started Jul 17 05:32:35 PM PDT 24
Finished Jul 17 05:33:00 PM PDT 24
Peak memory 225696 kb
Host smart-347870e1-ec00-49b8-91cf-5648fb956c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901904930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.901904930
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1476562418
Short name T230
Test name
Test status
Simulation time 14243133592 ps
CPU time 13.09 seconds
Started Jul 17 05:29:26 PM PDT 24
Finished Jul 17 05:29:40 PM PDT 24
Peak memory 225644 kb
Host smart-b9ae50b2-4599-4ba6-a2b7-7c5014aab5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476562418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1476562418
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.908142217
Short name T555
Test name
Test status
Simulation time 110763831 ps
CPU time 3.08 seconds
Started Jul 17 05:29:17 PM PDT 24
Finished Jul 17 05:29:22 PM PDT 24
Peak memory 223540 kb
Host smart-465b64b7-de53-429d-a641-8cb2a00794c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=908142217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.908142217
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1347533033
Short name T182
Test name
Test status
Simulation time 65700617833 ps
CPU time 356.25 seconds
Started Jul 17 05:29:21 PM PDT 24
Finished Jul 17 05:35:18 PM PDT 24
Peak memory 267140 kb
Host smart-8d932926-241f-4831-a5c9-c87497ad9e80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347533033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1347533033
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3536560038
Short name T350
Test name
Test status
Simulation time 8923759366 ps
CPU time 24.62 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:29:44 PM PDT 24
Peak memory 217540 kb
Host smart-cedee8fd-d76f-4909-a1ee-278e66a4a033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536560038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3536560038
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4224796374
Short name T357
Test name
Test status
Simulation time 27029332 ps
CPU time 0.73 seconds
Started Jul 17 05:29:16 PM PDT 24
Finished Jul 17 05:29:18 PM PDT 24
Peak memory 206620 kb
Host smart-d501625d-3904-4168-ad5f-3814c37ecb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224796374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4224796374
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2857831768
Short name T923
Test name
Test status
Simulation time 173056110 ps
CPU time 1.85 seconds
Started Jul 17 05:34:14 PM PDT 24
Finished Jul 17 05:34:19 PM PDT 24
Peak memory 217400 kb
Host smart-6b4b4b46-ab8f-4a07-a9a3-f4a7f464c138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857831768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2857831768
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3048553121
Short name T729
Test name
Test status
Simulation time 45195407 ps
CPU time 0.79 seconds
Started Jul 17 05:29:29 PM PDT 24
Finished Jul 17 05:29:31 PM PDT 24
Peak memory 206860 kb
Host smart-1da1cd45-51fe-4fa3-ac72-d16893c715f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048553121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3048553121
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2911802953
Short name T189
Test name
Test status
Simulation time 17503714422 ps
CPU time 28.44 seconds
Started Jul 17 05:29:18 PM PDT 24
Finished Jul 17 05:29:48 PM PDT 24
Peak memory 250368 kb
Host smart-e30e30f7-48ab-4324-bf90-12c740c24286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911802953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2911802953
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.114213411
Short name T713
Test name
Test status
Simulation time 16493907 ps
CPU time 0.71 seconds
Started Jul 17 05:27:48 PM PDT 24
Finished Jul 17 05:27:51 PM PDT 24
Peak memory 205776 kb
Host smart-f50b400e-feae-4b64-b334-7cfeda4160bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114213411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.114213411
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4041534045
Short name T296
Test name
Test status
Simulation time 19008855 ps
CPU time 0.82 seconds
Started Jul 17 05:30:21 PM PDT 24
Finished Jul 17 05:30:24 PM PDT 24
Peak memory 208012 kb
Host smart-40287b21-09d6-41a9-84af-c45f9b66ed7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041534045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4041534045
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1456991292
Short name T185
Test name
Test status
Simulation time 128198769949 ps
CPU time 219.53 seconds
Started Jul 17 05:27:48 PM PDT 24
Finished Jul 17 05:31:30 PM PDT 24
Peak memory 250112 kb
Host smart-26e3b94c-a311-4852-b188-105a0b850060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456991292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1456991292
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1643382543
Short name T796
Test name
Test status
Simulation time 17674661488 ps
CPU time 131.03 seconds
Started Jul 17 05:27:48 PM PDT 24
Finished Jul 17 05:30:01 PM PDT 24
Peak memory 269520 kb
Host smart-c2797ccc-e3e3-4fa6-9264-0afbac51ca33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643382543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1643382543
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.910862474
Short name T13
Test name
Test status
Simulation time 5251368180 ps
CPU time 66.3 seconds
Started Jul 17 05:27:49 PM PDT 24
Finished Jul 17 05:28:57 PM PDT 24
Peak memory 239936 kb
Host smart-64647ae0-3c27-46c5-bad5-c3bd972cddfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910862474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
910862474
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1961013831
Short name T596
Test name
Test status
Simulation time 120350879 ps
CPU time 2.57 seconds
Started Jul 17 05:28:18 PM PDT 24
Finished Jul 17 05:28:22 PM PDT 24
Peak memory 233728 kb
Host smart-1db97953-bcd1-4b8a-96d3-9e161c380e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961013831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1961013831
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1776706597
Short name T206
Test name
Test status
Simulation time 28066850401 ps
CPU time 196.59 seconds
Started Jul 17 05:27:56 PM PDT 24
Finished Jul 17 05:31:14 PM PDT 24
Peak memory 240272 kb
Host smart-970ec480-1b2e-4240-995a-9899d309b7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776706597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1776706597
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3185655519
Short name T324
Test name
Test status
Simulation time 35262741 ps
CPU time 2.48 seconds
Started Jul 17 05:28:05 PM PDT 24
Finished Jul 17 05:28:10 PM PDT 24
Peak memory 233336 kb
Host smart-8ad5d2d6-1f38-4bff-86db-15269b11fb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185655519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3185655519
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.284638195
Short name T559
Test name
Test status
Simulation time 1433983788 ps
CPU time 5.04 seconds
Started Jul 17 05:28:36 PM PDT 24
Finished Jul 17 05:28:41 PM PDT 24
Peak memory 233660 kb
Host smart-22eb5ac0-5379-4e20-b469-9d86f2f2a39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284638195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.284638195
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2227293065
Short name T536
Test name
Test status
Simulation time 57521333 ps
CPU time 1.12 seconds
Started Jul 17 05:27:46 PM PDT 24
Finished Jul 17 05:27:49 PM PDT 24
Peak memory 217668 kb
Host smart-96a502ab-84f6-4875-b3cc-2bb1d466efcd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227293065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2227293065
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2063907575
Short name T369
Test name
Test status
Simulation time 352454993 ps
CPU time 7.38 seconds
Started Jul 17 05:32:44 PM PDT 24
Finished Jul 17 05:32:52 PM PDT 24
Peak memory 233744 kb
Host smart-f9e73591-1f07-4041-96cf-9e546ce87051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063907575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2063907575
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1726251378
Short name T327
Test name
Test status
Simulation time 765223499 ps
CPU time 8.29 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:34:03 PM PDT 24
Peak memory 223252 kb
Host smart-6d7865c9-cadb-4095-bfc1-65292a6542a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1726251378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1726251378
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2762605566
Short name T71
Test name
Test status
Simulation time 247319134 ps
CPU time 1.13 seconds
Started Jul 17 05:29:44 PM PDT 24
Finished Jul 17 05:29:47 PM PDT 24
Peak memory 236360 kb
Host smart-2ffaf193-2307-4eca-b3f4-8cc377f65415
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762605566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2762605566
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3979507988
Short name T682
Test name
Test status
Simulation time 36780332 ps
CPU time 0.72 seconds
Started Jul 17 05:32:44 PM PDT 24
Finished Jul 17 05:32:45 PM PDT 24
Peak memory 206556 kb
Host smart-d953762b-d48b-4c39-8325-c3c3aafddc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979507988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3979507988
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3407724297
Short name T756
Test name
Test status
Simulation time 310295949 ps
CPU time 2.23 seconds
Started Jul 17 05:28:15 PM PDT 24
Finished Jul 17 05:28:20 PM PDT 24
Peak memory 217284 kb
Host smart-e8da2df9-9965-4d02-b9fa-c12b21a546fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407724297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3407724297
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.302613961
Short name T963
Test name
Test status
Simulation time 66512631 ps
CPU time 1.69 seconds
Started Jul 17 05:29:57 PM PDT 24
Finished Jul 17 05:30:00 PM PDT 24
Peak memory 217284 kb
Host smart-faf2ac82-8956-45ea-97bf-426a474ceaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302613961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.302613961
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1927030392
Short name T687
Test name
Test status
Simulation time 41921209 ps
CPU time 0.8 seconds
Started Jul 17 05:29:57 PM PDT 24
Finished Jul 17 05:29:59 PM PDT 24
Peak memory 206904 kb
Host smart-bce10d50-4b0a-47af-9ead-4947f343054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927030392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1927030392
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.4272273183
Short name T9
Test name
Test status
Simulation time 122909060 ps
CPU time 2.5 seconds
Started Jul 17 05:28:05 PM PDT 24
Finished Jul 17 05:28:10 PM PDT 24
Peak memory 225284 kb
Host smart-4f925746-a5d3-45a1-b6a4-881e512ed99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272273183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4272273183
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3939537415
Short name T376
Test name
Test status
Simulation time 18670153 ps
CPU time 0.73 seconds
Started Jul 17 05:29:32 PM PDT 24
Finished Jul 17 05:29:34 PM PDT 24
Peak memory 206368 kb
Host smart-03c35b0d-679d-4b5a-9e29-1d371d8517da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939537415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3939537415
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.766339292
Short name T92
Test name
Test status
Simulation time 777046489 ps
CPU time 3.01 seconds
Started Jul 17 05:32:54 PM PDT 24
Finished Jul 17 05:32:58 PM PDT 24
Peak memory 233676 kb
Host smart-517cdaf6-405d-4f7a-adff-804405fd8a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766339292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.766339292
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1904644120
Short name T995
Test name
Test status
Simulation time 123968226 ps
CPU time 0.86 seconds
Started Jul 17 05:29:22 PM PDT 24
Finished Jul 17 05:29:24 PM PDT 24
Peak memory 207816 kb
Host smart-a0574001-903e-4480-bbcd-d3f89bdc24c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904644120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1904644120
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2820700111
Short name T550
Test name
Test status
Simulation time 71928035486 ps
CPU time 197.08 seconds
Started Jul 17 05:29:40 PM PDT 24
Finished Jul 17 05:32:59 PM PDT 24
Peak memory 250420 kb
Host smart-5c1ac31e-744e-49ef-b93f-5b272063cf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820700111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2820700111
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3112661160
Short name T242
Test name
Test status
Simulation time 9196722940 ps
CPU time 149.94 seconds
Started Jul 17 05:29:40 PM PDT 24
Finished Jul 17 05:32:12 PM PDT 24
Peak memory 253968 kb
Host smart-418b658e-259a-4878-b415-897a043fe84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112661160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3112661160
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2915640441
Short name T666
Test name
Test status
Simulation time 479813607 ps
CPU time 11.36 seconds
Started Jul 17 05:29:32 PM PDT 24
Finished Jul 17 05:29:44 PM PDT 24
Peak memory 225536 kb
Host smart-0faa6328-d37f-4567-8749-b365ca7a56df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915640441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2915640441
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2441562780
Short name T526
Test name
Test status
Simulation time 5654526991 ps
CPU time 71.2 seconds
Started Jul 17 05:29:32 PM PDT 24
Finished Jul 17 05:30:44 PM PDT 24
Peak memory 250292 kb
Host smart-6d2c3758-2360-4011-bfde-dc9be3904125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441562780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2441562780
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.702420725
Short name T1010
Test name
Test status
Simulation time 100064789 ps
CPU time 3.57 seconds
Started Jul 17 05:29:25 PM PDT 24
Finished Jul 17 05:29:30 PM PDT 24
Peak memory 233804 kb
Host smart-0100193d-f42a-4320-b221-4373a0fc2132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702420725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.702420725
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4228757019
Short name T623
Test name
Test status
Simulation time 86278545945 ps
CPU time 70.6 seconds
Started Jul 17 05:29:32 PM PDT 24
Finished Jul 17 05:30:43 PM PDT 24
Peak memory 250232 kb
Host smart-a3395a23-5012-4a21-baa0-984b7e583fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228757019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4228757019
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.575128575
Short name T910
Test name
Test status
Simulation time 5863207645 ps
CPU time 9.5 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:34:21 PM PDT 24
Peak memory 225532 kb
Host smart-a29bbc8d-4955-4b21-b782-e194c427f72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575128575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.575128575
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2871569363
Short name T449
Test name
Test status
Simulation time 11167494887 ps
CPU time 13.19 seconds
Started Jul 17 05:29:22 PM PDT 24
Finished Jul 17 05:29:36 PM PDT 24
Peak memory 241764 kb
Host smart-f86c3a47-c25a-4fca-8fbe-7566328b6b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871569363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2871569363
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.847872536
Short name T326
Test name
Test status
Simulation time 793701978 ps
CPU time 4.65 seconds
Started Jul 17 05:29:40 PM PDT 24
Finished Jul 17 05:29:46 PM PDT 24
Peak memory 219968 kb
Host smart-c67a1f8e-11f3-4271-917f-329206364d1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=847872536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.847872536
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1353535424
Short name T612
Test name
Test status
Simulation time 46237658 ps
CPU time 1.03 seconds
Started Jul 17 05:29:40 PM PDT 24
Finished Jul 17 05:29:42 PM PDT 24
Peak memory 207752 kb
Host smart-df80d94f-d585-4dcb-be66-2b5c7fc2020a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353535424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1353535424
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3523254830
Short name T482
Test name
Test status
Simulation time 5035261620 ps
CPU time 31.56 seconds
Started Jul 17 05:33:54 PM PDT 24
Finished Jul 17 05:34:29 PM PDT 24
Peak memory 217368 kb
Host smart-079c40df-51d6-4711-84c7-7dbb9c942f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523254830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3523254830
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1466511436
Short name T130
Test name
Test status
Simulation time 7281128096 ps
CPU time 13.66 seconds
Started Jul 17 05:34:10 PM PDT 24
Finished Jul 17 05:34:26 PM PDT 24
Peak memory 217348 kb
Host smart-7425a296-4aa9-4b71-97e5-e3b2a267cb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466511436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1466511436
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1774680252
Short name T344
Test name
Test status
Simulation time 96515771 ps
CPU time 1.14 seconds
Started Jul 17 05:29:17 PM PDT 24
Finished Jul 17 05:29:19 PM PDT 24
Peak memory 209060 kb
Host smart-e6ad873f-ec8a-4ee4-8ea5-9fcbb4641d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774680252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1774680252
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4269417338
Short name T283
Test name
Test status
Simulation time 176882308 ps
CPU time 0.84 seconds
Started Jul 17 05:34:14 PM PDT 24
Finished Jul 17 05:34:18 PM PDT 24
Peak memory 207004 kb
Host smart-e9e70ad6-763a-475a-8b48-a0f7ac098bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269417338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4269417338
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3949119615
Short name T367
Test name
Test status
Simulation time 276973569 ps
CPU time 4.92 seconds
Started Jul 17 05:29:31 PM PDT 24
Finished Jul 17 05:29:37 PM PDT 24
Peak memory 225552 kb
Host smart-59636356-c4d8-4a5a-ba46-b01bdb8c7db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949119615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3949119615
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2450337138
Short name T307
Test name
Test status
Simulation time 47969397 ps
CPU time 0.75 seconds
Started Jul 17 05:29:38 PM PDT 24
Finished Jul 17 05:29:40 PM PDT 24
Peak memory 205724 kb
Host smart-dac013a5-9d18-48e7-aa70-3c876ee88433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450337138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2450337138
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.580451955
Short name T237
Test name
Test status
Simulation time 300820640 ps
CPU time 3.11 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:34:14 PM PDT 24
Peak memory 233612 kb
Host smart-c64f8254-c1e4-43bf-85c4-140155b0037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580451955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.580451955
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.172379529
Short name T689
Test name
Test status
Simulation time 31096687 ps
CPU time 0.79 seconds
Started Jul 17 05:29:28 PM PDT 24
Finished Jul 17 05:29:30 PM PDT 24
Peak memory 207744 kb
Host smart-881f9ec8-bfca-4bda-a490-f719ddec9fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172379529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.172379529
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.4143069453
Short name T863
Test name
Test status
Simulation time 7039509488 ps
CPU time 68.84 seconds
Started Jul 17 05:30:40 PM PDT 24
Finished Jul 17 05:31:50 PM PDT 24
Peak memory 257844 kb
Host smart-646a90fe-9dbb-4890-bd32-6dcf269ab7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143069453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.4143069453
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.241462599
Short name T433
Test name
Test status
Simulation time 1268264033 ps
CPU time 16.6 seconds
Started Jul 17 05:29:40 PM PDT 24
Finished Jul 17 05:29:58 PM PDT 24
Peak memory 239640 kb
Host smart-261ff1a7-4244-4762-a4a7-368e184dd60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241462599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.241462599
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2206659605
Short name T53
Test name
Test status
Simulation time 17749422041 ps
CPU time 226.42 seconds
Started Jul 17 05:29:39 PM PDT 24
Finished Jul 17 05:33:27 PM PDT 24
Peak memory 252344 kb
Host smart-584e8c9c-be09-4619-8860-f9fa205dab8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206659605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2206659605
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2192123171
Short name T905
Test name
Test status
Simulation time 253672292 ps
CPU time 3.89 seconds
Started Jul 17 05:29:40 PM PDT 24
Finished Jul 17 05:29:46 PM PDT 24
Peak memory 233764 kb
Host smart-6bab5c5a-1a8b-48e6-bd19-30aa7dd8dfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192123171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2192123171
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.488762285
Short name T262
Test name
Test status
Simulation time 15310818159 ps
CPU time 67.43 seconds
Started Jul 17 05:34:01 PM PDT 24
Finished Jul 17 05:35:10 PM PDT 24
Peak memory 251952 kb
Host smart-1bd1d9cf-4ea1-4328-bbff-cfd40bdf2da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488762285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.488762285
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2571357777
Short name T347
Test name
Test status
Simulation time 1317402943 ps
CPU time 7.23 seconds
Started Jul 17 05:29:26 PM PDT 24
Finished Jul 17 05:29:35 PM PDT 24
Peak memory 233720 kb
Host smart-f1bd8b90-4850-45d1-b85d-a2d4ef07fd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571357777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2571357777
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2912857314
Short name T93
Test name
Test status
Simulation time 38226325847 ps
CPU time 60.67 seconds
Started Jul 17 05:29:31 PM PDT 24
Finished Jul 17 05:30:32 PM PDT 24
Peak memory 233816 kb
Host smart-4fce312b-4d50-47be-8961-782efac52929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912857314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2912857314
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2302084322
Short name T975
Test name
Test status
Simulation time 356922460 ps
CPU time 4.25 seconds
Started Jul 17 05:29:27 PM PDT 24
Finished Jul 17 05:29:32 PM PDT 24
Peak memory 225480 kb
Host smart-a3ae0847-668e-428a-a452-8edf6861e4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302084322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2302084322
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3890492669
Short name T78
Test name
Test status
Simulation time 220460236 ps
CPU time 4.53 seconds
Started Jul 17 05:29:41 PM PDT 24
Finished Jul 17 05:29:46 PM PDT 24
Peak memory 225488 kb
Host smart-5913bffa-cd95-4323-ae23-3ff250f3bf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890492669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3890492669
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3627667964
Short name T661
Test name
Test status
Simulation time 1034155452 ps
CPU time 13.58 seconds
Started Jul 17 05:29:41 PM PDT 24
Finished Jul 17 05:29:56 PM PDT 24
Peak memory 222516 kb
Host smart-e33d0402-afdc-40a3-87c5-3accc17cc451
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3627667964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3627667964
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.866389122
Short name T135
Test name
Test status
Simulation time 37618712378 ps
CPU time 268.58 seconds
Started Jul 17 05:29:38 PM PDT 24
Finished Jul 17 05:34:08 PM PDT 24
Peak memory 265200 kb
Host smart-8d5e06c7-9b28-4677-b2f0-05934054351f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866389122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.866389122
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3170815890
Short name T485
Test name
Test status
Simulation time 10897433931 ps
CPU time 18.63 seconds
Started Jul 17 05:29:28 PM PDT 24
Finished Jul 17 05:29:48 PM PDT 24
Peak memory 217460 kb
Host smart-dced1a6d-62f3-4602-90b2-b6e3f3ca178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170815890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3170815890
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.622456172
Short name T881
Test name
Test status
Simulation time 9392290161 ps
CPU time 15.23 seconds
Started Jul 17 05:29:25 PM PDT 24
Finished Jul 17 05:29:41 PM PDT 24
Peak memory 217568 kb
Host smart-33d9892c-0ba7-4db0-80e8-a7222a2b8a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622456172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.622456172
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1752273915
Short name T715
Test name
Test status
Simulation time 213862746 ps
CPU time 5.34 seconds
Started Jul 17 05:29:40 PM PDT 24
Finished Jul 17 05:29:47 PM PDT 24
Peak memory 217316 kb
Host smart-33a6d03e-c2f9-4829-b629-848c11217b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752273915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1752273915
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.277987551
Short name T455
Test name
Test status
Simulation time 53189134 ps
CPU time 0.77 seconds
Started Jul 17 05:29:40 PM PDT 24
Finished Jul 17 05:29:43 PM PDT 24
Peak memory 206908 kb
Host smart-9c491bdd-872a-450c-95ad-eeeb3a9b5b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277987551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.277987551
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.652433936
Short name T216
Test name
Test status
Simulation time 3276498494 ps
CPU time 3.01 seconds
Started Jul 17 05:29:28 PM PDT 24
Finished Jul 17 05:29:33 PM PDT 24
Peak memory 233820 kb
Host smart-9bb89c08-59c6-43be-bd35-8ee1c5ff5a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652433936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.652433936
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.979665266
Short name T831
Test name
Test status
Simulation time 26077295 ps
CPU time 0.67 seconds
Started Jul 17 05:29:51 PM PDT 24
Finished Jul 17 05:29:53 PM PDT 24
Peak memory 206696 kb
Host smart-76258e71-ce38-4e2b-9366-1cd5556a9a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979665266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.979665266
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3959911755
Short name T672
Test name
Test status
Simulation time 484568546 ps
CPU time 2.55 seconds
Started Jul 17 05:29:42 PM PDT 24
Finished Jul 17 05:29:45 PM PDT 24
Peak memory 233540 kb
Host smart-765c19f5-1b2a-485a-84f8-04a1e693398b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959911755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3959911755
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1725262232
Short name T282
Test name
Test status
Simulation time 132246147 ps
CPU time 0.75 seconds
Started Jul 17 05:29:40 PM PDT 24
Finished Jul 17 05:29:42 PM PDT 24
Peak memory 206492 kb
Host smart-e8c430d9-1446-4878-bd01-3fb397b653bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725262232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1725262232
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.586348583
Short name T221
Test name
Test status
Simulation time 994359073542 ps
CPU time 347.27 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:39:52 PM PDT 24
Peak memory 266672 kb
Host smart-5d533659-97b2-4f5f-a12f-00bd1badeb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586348583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.586348583
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3747593789
Short name T157
Test name
Test status
Simulation time 18847190966 ps
CPU time 167.63 seconds
Started Jul 17 05:29:42 PM PDT 24
Finished Jul 17 05:32:31 PM PDT 24
Peak memory 250332 kb
Host smart-f5d61813-79aa-4aa4-8474-f9dc5dbb0ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747593789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3747593789
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.573904553
Short name T681
Test name
Test status
Simulation time 25513681204 ps
CPU time 56.42 seconds
Started Jul 17 05:29:59 PM PDT 24
Finished Jul 17 05:30:57 PM PDT 24
Peak memory 250340 kb
Host smart-49c6092f-7751-4bc6-97f8-ef9f5bd5a8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573904553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.573904553
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.197338278
Short name T212
Test name
Test status
Simulation time 840510871 ps
CPU time 3.61 seconds
Started Jul 17 05:29:38 PM PDT 24
Finished Jul 17 05:29:42 PM PDT 24
Peak memory 241992 kb
Host smart-6cee6e95-0875-42a0-be46-bb1ed56a9a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197338278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.197338278
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2221756526
Short name T227
Test name
Test status
Simulation time 135539124913 ps
CPU time 281.34 seconds
Started Jul 17 05:30:55 PM PDT 24
Finished Jul 17 05:35:38 PM PDT 24
Peak memory 266672 kb
Host smart-631e7084-9c34-416c-9885-7d002f26975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221756526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2221756526
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2889557873
Short name T178
Test name
Test status
Simulation time 3490369204 ps
CPU time 8.4 seconds
Started Jul 17 05:29:40 PM PDT 24
Finished Jul 17 05:29:50 PM PDT 24
Peak memory 225700 kb
Host smart-88cbf617-4d5d-4f0c-8d99-d1c657a0a3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889557873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2889557873
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3011150368
Short name T806
Test name
Test status
Simulation time 1939457191 ps
CPU time 11.02 seconds
Started Jul 17 05:29:42 PM PDT 24
Finished Jul 17 05:29:54 PM PDT 24
Peak memory 233784 kb
Host smart-33289183-9e5e-471a-851a-48650adb2eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011150368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3011150368
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1063450420
Short name T342
Test name
Test status
Simulation time 433890302 ps
CPU time 2.84 seconds
Started Jul 17 05:29:42 PM PDT 24
Finished Jul 17 05:29:46 PM PDT 24
Peak memory 225512 kb
Host smart-4c478229-1460-480c-8220-f380ea078bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063450420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1063450420
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1721675403
Short name T225
Test name
Test status
Simulation time 5218314815 ps
CPU time 5.14 seconds
Started Jul 17 05:29:42 PM PDT 24
Finished Jul 17 05:29:49 PM PDT 24
Peak memory 225548 kb
Host smart-a98a2241-d8a4-4f2a-bfcd-8a55237c7093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721675403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1721675403
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1943170997
Short name T409
Test name
Test status
Simulation time 240413349 ps
CPU time 3.27 seconds
Started Jul 17 05:33:24 PM PDT 24
Finished Jul 17 05:33:28 PM PDT 24
Peak memory 223560 kb
Host smart-fa0fac6e-e899-465f-88f5-b033c6fd0ea7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1943170997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1943170997
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4198545242
Short name T152
Test name
Test status
Simulation time 52709967485 ps
CPU time 304.92 seconds
Started Jul 17 05:29:55 PM PDT 24
Finished Jul 17 05:35:01 PM PDT 24
Peak memory 265692 kb
Host smart-b9d3da63-1a8c-410e-8f99-450a37074fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198545242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4198545242
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2964309994
Short name T656
Test name
Test status
Simulation time 3650956731 ps
CPU time 27.52 seconds
Started Jul 17 05:29:43 PM PDT 24
Finished Jul 17 05:30:11 PM PDT 24
Peak memory 217436 kb
Host smart-7d5d48ed-038f-4bd2-95d5-c81a285d4b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964309994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2964309994
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2498337575
Short name T700
Test name
Test status
Simulation time 804257773 ps
CPU time 1.83 seconds
Started Jul 17 05:29:43 PM PDT 24
Finished Jul 17 05:29:46 PM PDT 24
Peak memory 208892 kb
Host smart-b5e17ecc-f7e7-4242-896b-4b7fcf5d162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498337575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2498337575
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1610943143
Short name T780
Test name
Test status
Simulation time 60609277 ps
CPU time 1.51 seconds
Started Jul 17 05:29:39 PM PDT 24
Finished Jul 17 05:29:42 PM PDT 24
Peak memory 217380 kb
Host smart-949b1460-d3f2-43be-b433-513d9ae77461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610943143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1610943143
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2687754425
Short name T971
Test name
Test status
Simulation time 395252103 ps
CPU time 1.13 seconds
Started Jul 17 05:29:43 PM PDT 24
Finished Jul 17 05:29:45 PM PDT 24
Peak memory 207432 kb
Host smart-501b55bd-6cf6-42a6-a0a2-8cc4cfc429b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687754425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2687754425
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.967679419
Short name T2
Test name
Test status
Simulation time 1863797557 ps
CPU time 13.95 seconds
Started Jul 17 05:29:42 PM PDT 24
Finished Jul 17 05:29:57 PM PDT 24
Peak memory 233752 kb
Host smart-9b4c683d-f142-432b-b490-5efc9ecdba7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967679419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.967679419
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1794195881
Short name T481
Test name
Test status
Simulation time 14528302 ps
CPU time 0.78 seconds
Started Jul 17 05:30:00 PM PDT 24
Finished Jul 17 05:30:03 PM PDT 24
Peak memory 206288 kb
Host smart-33e7e79d-26b4-452b-ba7e-630f53e064df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794195881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1794195881
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2184124955
Short name T603
Test name
Test status
Simulation time 96845230 ps
CPU time 2.3 seconds
Started Jul 17 05:29:55 PM PDT 24
Finished Jul 17 05:29:58 PM PDT 24
Peak memory 233436 kb
Host smart-727d178b-db34-4b3d-bfcc-4925b30b537f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184124955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2184124955
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.512726817
Short name T591
Test name
Test status
Simulation time 182960441 ps
CPU time 0.76 seconds
Started Jul 17 05:29:50 PM PDT 24
Finished Jul 17 05:29:51 PM PDT 24
Peak memory 207520 kb
Host smart-ebee5b64-11e6-4c32-81ac-0858f47085b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512726817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.512726817
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2982066256
Short name T238
Test name
Test status
Simulation time 800722091899 ps
CPU time 402.4 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:40:37 PM PDT 24
Peak memory 268188 kb
Host smart-f2a78ffe-003b-41e2-94a6-9a7c5e251d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982066256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2982066256
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1978879008
Short name T838
Test name
Test status
Simulation time 19708820445 ps
CPU time 103.7 seconds
Started Jul 17 05:29:59 PM PDT 24
Finished Jul 17 05:31:44 PM PDT 24
Peak memory 258500 kb
Host smart-a998f6c0-07ed-4239-9349-fefc72053c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978879008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1978879008
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1711893589
Short name T777
Test name
Test status
Simulation time 6083002423 ps
CPU time 62.89 seconds
Started Jul 17 05:29:51 PM PDT 24
Finished Jul 17 05:30:55 PM PDT 24
Peak memory 250380 kb
Host smart-6507d38a-92af-4e4e-98f0-5dc3db00092e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711893589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1711893589
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3010544948
Short name T852
Test name
Test status
Simulation time 227809099 ps
CPU time 3.21 seconds
Started Jul 17 05:29:49 PM PDT 24
Finished Jul 17 05:29:53 PM PDT 24
Peak memory 234012 kb
Host smart-f38fc74f-d2c4-411d-a169-daa8644aa7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010544948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3010544948
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3524326332
Short name T1007
Test name
Test status
Simulation time 36383030921 ps
CPU time 64.06 seconds
Started Jul 17 05:30:00 PM PDT 24
Finished Jul 17 05:31:06 PM PDT 24
Peak memory 240412 kb
Host smart-475a49c5-9f59-42f6-b455-89e0dc362abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524326332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3524326332
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3143819545
Short name T525
Test name
Test status
Simulation time 5522168766 ps
CPU time 20.19 seconds
Started Jul 17 05:29:50 PM PDT 24
Finished Jul 17 05:30:12 PM PDT 24
Peak memory 233852 kb
Host smart-cec44b76-69b5-4ea3-bb50-f91e54d3c112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143819545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3143819545
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2447278277
Short name T544
Test name
Test status
Simulation time 929267101 ps
CPU time 11.15 seconds
Started Jul 17 05:29:50 PM PDT 24
Finished Jul 17 05:30:03 PM PDT 24
Peak memory 225564 kb
Host smart-71821726-c540-4531-97e4-bdfce87988a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447278277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2447278277
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3491851656
Short name T841
Test name
Test status
Simulation time 129182941 ps
CPU time 2.3 seconds
Started Jul 17 05:29:51 PM PDT 24
Finished Jul 17 05:29:54 PM PDT 24
Peak memory 224564 kb
Host smart-3e1cdaf3-f971-493a-b521-7b0526b399fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491851656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3491851656
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1253890153
Short name T650
Test name
Test status
Simulation time 2749938826 ps
CPU time 6.54 seconds
Started Jul 17 05:29:55 PM PDT 24
Finished Jul 17 05:30:02 PM PDT 24
Peak memory 233452 kb
Host smart-e16a3233-0b20-4735-bd94-3f9c003ae114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253890153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1253890153
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.825534244
Short name T1004
Test name
Test status
Simulation time 92107807 ps
CPU time 3.87 seconds
Started Jul 17 05:29:49 PM PDT 24
Finished Jul 17 05:29:54 PM PDT 24
Peak memory 223708 kb
Host smart-b6244c3e-de2e-4f7b-b598-b299182d880d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=825534244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.825534244
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1487548245
Short name T970
Test name
Test status
Simulation time 32447160677 ps
CPU time 317.92 seconds
Started Jul 17 05:32:36 PM PDT 24
Finished Jul 17 05:37:55 PM PDT 24
Peak memory 257012 kb
Host smart-58a657d3-ce4e-40e6-9151-6c4dac12fe52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487548245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1487548245
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2777356427
Short name T741
Test name
Test status
Simulation time 27163048 ps
CPU time 0.77 seconds
Started Jul 17 05:29:49 PM PDT 24
Finished Jul 17 05:29:50 PM PDT 24
Peak memory 206888 kb
Host smart-d51210eb-a127-433b-b408-87d1225497d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777356427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2777356427
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1235479540
Short name T27
Test name
Test status
Simulation time 8750221093 ps
CPU time 19.75 seconds
Started Jul 17 05:29:51 PM PDT 24
Finished Jul 17 05:30:12 PM PDT 24
Peak memory 217544 kb
Host smart-5f55b8bb-b6a2-41d9-a14e-199004250d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235479540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1235479540
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3564008765
Short name T6
Test name
Test status
Simulation time 51893453 ps
CPU time 0.75 seconds
Started Jul 17 05:29:50 PM PDT 24
Finished Jul 17 05:29:52 PM PDT 24
Peak memory 206972 kb
Host smart-cb8f1a49-e299-44b1-9439-dc263a7b2548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564008765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3564008765
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1527756821
Short name T957
Test name
Test status
Simulation time 59922858 ps
CPU time 0.91 seconds
Started Jul 17 05:29:52 PM PDT 24
Finished Jul 17 05:29:54 PM PDT 24
Peak memory 206900 kb
Host smart-0cc11545-3961-4031-989e-0ee21c04d8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527756821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1527756821
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4006172174
Short name T440
Test name
Test status
Simulation time 7401367118 ps
CPU time 26.78 seconds
Started Jul 17 05:29:59 PM PDT 24
Finished Jul 17 05:30:27 PM PDT 24
Peak memory 241960 kb
Host smart-ef73cbd8-5b7a-4f35-9ed5-8836cede91b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006172174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4006172174
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1566169262
Short name T522
Test name
Test status
Simulation time 11677538 ps
CPU time 0.72 seconds
Started Jul 17 05:30:02 PM PDT 24
Finished Jul 17 05:30:05 PM PDT 24
Peak memory 206376 kb
Host smart-f3537266-4b82-45a0-86e2-3e2027b31183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566169262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1566169262
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3538365788
Short name T632
Test name
Test status
Simulation time 300962792 ps
CPU time 4.34 seconds
Started Jul 17 05:29:54 PM PDT 24
Finished Jul 17 05:29:59 PM PDT 24
Peak memory 233772 kb
Host smart-658c434a-e97a-4f3c-a1cc-1f09db3951d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538365788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3538365788
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.756850965
Short name T67
Test name
Test status
Simulation time 33937278 ps
CPU time 0.76 seconds
Started Jul 17 05:29:51 PM PDT 24
Finished Jul 17 05:29:53 PM PDT 24
Peak memory 207460 kb
Host smart-710d47e7-ba05-45c0-a0bf-95dc8280f296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756850965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.756850965
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1689184742
Short name T311
Test name
Test status
Simulation time 2967003326 ps
CPU time 9.83 seconds
Started Jul 17 05:30:01 PM PDT 24
Finished Jul 17 05:30:12 PM PDT 24
Peak memory 236684 kb
Host smart-e2c7d534-9942-4546-8026-8e94379af95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689184742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1689184742
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3325253829
Short name T246
Test name
Test status
Simulation time 76851612689 ps
CPU time 197.69 seconds
Started Jul 17 05:30:03 PM PDT 24
Finished Jul 17 05:33:22 PM PDT 24
Peak memory 266692 kb
Host smart-154053c3-50c0-4b9a-8281-36f0baaf4d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325253829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3325253829
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2661741355
Short name T553
Test name
Test status
Simulation time 25798660092 ps
CPU time 208.29 seconds
Started Jul 17 05:30:01 PM PDT 24
Finished Jul 17 05:33:31 PM PDT 24
Peak memory 258048 kb
Host smart-06b4f4a7-2fdd-4f29-8eec-f31cca9f628c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661741355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2661741355
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.453493591
Short name T272
Test name
Test status
Simulation time 4856876643 ps
CPU time 8.72 seconds
Started Jul 17 05:30:03 PM PDT 24
Finished Jul 17 05:30:13 PM PDT 24
Peak memory 242084 kb
Host smart-079543dc-ddb5-4841-be10-93c974b1e421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453493591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.453493591
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1488272572
Short name T784
Test name
Test status
Simulation time 22920857145 ps
CPU time 111.22 seconds
Started Jul 17 05:30:02 PM PDT 24
Finished Jul 17 05:31:54 PM PDT 24
Peak memory 254596 kb
Host smart-29d563a7-708e-4627-a117-20c667db0837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488272572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1488272572
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3612841649
Short name T934
Test name
Test status
Simulation time 1989727731 ps
CPU time 17.24 seconds
Started Jul 17 05:29:55 PM PDT 24
Finished Jul 17 05:30:13 PM PDT 24
Peak memory 233736 kb
Host smart-89ae9663-839a-4415-9560-c01dc9a5181e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612841649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3612841649
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1973133743
Short name T683
Test name
Test status
Simulation time 504427791 ps
CPU time 6.73 seconds
Started Jul 17 05:33:41 PM PDT 24
Finished Jul 17 05:33:49 PM PDT 24
Peak memory 220840 kb
Host smart-628a80b6-0815-47ca-b3a9-afdb269ec94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973133743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1973133743
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.868998210
Short name T640
Test name
Test status
Simulation time 1474036152 ps
CPU time 11.22 seconds
Started Jul 17 05:29:55 PM PDT 24
Finished Jul 17 05:30:07 PM PDT 24
Peak memory 241428 kb
Host smart-644cea8d-92fc-4b3b-8a7f-e10b9cbd0f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868998210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.868998210
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.827542150
Short name T377
Test name
Test status
Simulation time 3794615383 ps
CPU time 8.73 seconds
Started Jul 17 05:29:54 PM PDT 24
Finished Jul 17 05:30:04 PM PDT 24
Peak memory 233856 kb
Host smart-05797a0c-5187-4c93-9b3e-ade42db8aeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827542150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.827542150
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.210626607
Short name T65
Test name
Test status
Simulation time 344898954 ps
CPU time 5.37 seconds
Started Jul 17 05:30:01 PM PDT 24
Finished Jul 17 05:30:08 PM PDT 24
Peak memory 221624 kb
Host smart-5a386c3a-77d9-4500-9346-74cd032c9186
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=210626607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.210626607
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2510834586
Short name T199
Test name
Test status
Simulation time 10101254520 ps
CPU time 71.57 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:35:07 PM PDT 24
Peak memory 250396 kb
Host smart-4de79814-4c54-4586-9a18-c606eda5f1bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510834586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2510834586
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4108040605
Short name T946
Test name
Test status
Simulation time 14039555080 ps
CPU time 23.54 seconds
Started Jul 17 05:33:44 PM PDT 24
Finished Jul 17 05:34:08 PM PDT 24
Peak memory 217408 kb
Host smart-94733a74-227b-4f1d-8505-ea22e3659482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108040605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4108040605
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.379491091
Short name T813
Test name
Test status
Simulation time 2425002832 ps
CPU time 4.27 seconds
Started Jul 17 05:29:51 PM PDT 24
Finished Jul 17 05:29:56 PM PDT 24
Peak memory 217404 kb
Host smart-1b0fd849-570f-42b0-a626-8a3f3b1e7a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379491091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.379491091
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.652055443
Short name T556
Test name
Test status
Simulation time 807890135 ps
CPU time 2.74 seconds
Started Jul 17 05:29:51 PM PDT 24
Finished Jul 17 05:29:55 PM PDT 24
Peak memory 217364 kb
Host smart-68f2d663-8cdf-4e54-bb23-4f8645694190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652055443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.652055443
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4026646787
Short name T574
Test name
Test status
Simulation time 68027534 ps
CPU time 0.94 seconds
Started Jul 17 05:29:50 PM PDT 24
Finished Jul 17 05:29:51 PM PDT 24
Peak memory 208324 kb
Host smart-00c035c1-de65-42db-8162-c104f444252e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026646787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4026646787
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3140193882
Short name T532
Test name
Test status
Simulation time 9857674372 ps
CPU time 29.11 seconds
Started Jul 17 05:29:54 PM PDT 24
Finished Jul 17 05:30:24 PM PDT 24
Peak memory 225672 kb
Host smart-af79b40d-2571-478b-8498-0e83e9b664eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140193882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3140193882
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.597845193
Short name T626
Test name
Test status
Simulation time 17780895 ps
CPU time 0.76 seconds
Started Jul 17 05:30:06 PM PDT 24
Finished Jul 17 05:30:08 PM PDT 24
Peak memory 206284 kb
Host smart-5bcfb604-343f-4fd9-b476-ec2be9e675ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597845193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.597845193
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2571979406
Short name T679
Test name
Test status
Simulation time 359415873 ps
CPU time 3.9 seconds
Started Jul 17 05:30:02 PM PDT 24
Finished Jul 17 05:30:07 PM PDT 24
Peak memory 233760 kb
Host smart-fa01e54e-126d-4904-8122-bd711c3988fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571979406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2571979406
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.4052631604
Short name T541
Test name
Test status
Simulation time 73439954 ps
CPU time 0.79 seconds
Started Jul 17 05:30:06 PM PDT 24
Finished Jul 17 05:30:07 PM PDT 24
Peak memory 207444 kb
Host smart-01bbc411-c393-4545-ab13-682ab9b1b28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052631604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4052631604
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1501758006
Short name T511
Test name
Test status
Simulation time 1910074486 ps
CPU time 37.13 seconds
Started Jul 17 05:30:04 PM PDT 24
Finished Jul 17 05:30:43 PM PDT 24
Peak memory 250436 kb
Host smart-97eaffca-33f5-4753-b0d6-c92ea51c8187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501758006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1501758006
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1882967814
Short name T759
Test name
Test status
Simulation time 853343280 ps
CPU time 5.4 seconds
Started Jul 17 05:33:49 PM PDT 24
Finished Jul 17 05:33:56 PM PDT 24
Peak memory 218760 kb
Host smart-7378ce6e-eb37-4b3a-b4ed-4120174191fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882967814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1882967814
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3646258870
Short name T56
Test name
Test status
Simulation time 156994146999 ps
CPU time 307.85 seconds
Started Jul 17 05:30:02 PM PDT 24
Finished Jul 17 05:35:11 PM PDT 24
Peak memory 254644 kb
Host smart-9be84afc-3be5-48cf-b037-19152ed31f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646258870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3646258870
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3711654794
Short name T782
Test name
Test status
Simulation time 543631688 ps
CPU time 2.93 seconds
Started Jul 17 05:30:08 PM PDT 24
Finished Jul 17 05:30:12 PM PDT 24
Peak memory 233660 kb
Host smart-0216743e-4148-426b-be88-1ba55a015766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711654794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3711654794
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3948947414
Short name T908
Test name
Test status
Simulation time 21552860221 ps
CPU time 116.51 seconds
Started Jul 17 05:30:02 PM PDT 24
Finished Jul 17 05:32:00 PM PDT 24
Peak memory 242084 kb
Host smart-f2a2fa8e-5ce1-4fd1-8b9b-96483ea3cf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948947414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3948947414
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.320336680
Short name T628
Test name
Test status
Simulation time 12870018934 ps
CPU time 14.05 seconds
Started Jul 17 05:30:03 PM PDT 24
Finished Jul 17 05:30:19 PM PDT 24
Peak memory 233944 kb
Host smart-00e6a8db-0c4e-4a41-9519-340080ac776e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320336680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.320336680
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.750761303
Short name T570
Test name
Test status
Simulation time 211740701 ps
CPU time 5.21 seconds
Started Jul 17 05:30:03 PM PDT 24
Finished Jul 17 05:30:10 PM PDT 24
Peak memory 233740 kb
Host smart-2115a589-5d0d-412e-9f2e-ef2458d4d3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750761303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.750761303
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.756136849
Short name T900
Test name
Test status
Simulation time 35318029830 ps
CPU time 15.75 seconds
Started Jul 17 05:30:02 PM PDT 24
Finished Jul 17 05:30:19 PM PDT 24
Peak memory 225696 kb
Host smart-1ffa3653-193e-49b7-a65c-a80b5cad3d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756136849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.756136849
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1315419708
Short name T197
Test name
Test status
Simulation time 3025254075 ps
CPU time 9.7 seconds
Started Jul 17 05:30:01 PM PDT 24
Finished Jul 17 05:30:12 PM PDT 24
Peak memory 250144 kb
Host smart-a8da9bad-c08f-47e5-aee0-7133d8c84fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315419708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1315419708
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2354443455
Short name T448
Test name
Test status
Simulation time 1361663192 ps
CPU time 8.76 seconds
Started Jul 17 05:32:52 PM PDT 24
Finished Jul 17 05:33:01 PM PDT 24
Peak memory 223592 kb
Host smart-bdc10cac-202b-4697-9958-488c061d5295
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2354443455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2354443455
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1280221022
Short name T615
Test name
Test status
Simulation time 7655738251 ps
CPU time 69.91 seconds
Started Jul 17 05:30:01 PM PDT 24
Finished Jul 17 05:31:12 PM PDT 24
Peak memory 262988 kb
Host smart-45eac33d-82a1-4624-afc2-5d264d56e505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280221022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1280221022
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2985586939
Short name T320
Test name
Test status
Simulation time 6049254091 ps
CPU time 6.8 seconds
Started Jul 17 05:30:04 PM PDT 24
Finished Jul 17 05:30:12 PM PDT 24
Peak memory 217484 kb
Host smart-333d7697-f33d-47d8-85ee-152279f19cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985586939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2985586939
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.355576989
Short name T429
Test name
Test status
Simulation time 3217190067 ps
CPU time 7.29 seconds
Started Jul 17 05:30:05 PM PDT 24
Finished Jul 17 05:30:13 PM PDT 24
Peak memory 217436 kb
Host smart-5c66dca3-7b33-4b72-b16b-00c3d3c30d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355576989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.355576989
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3863082985
Short name T597
Test name
Test status
Simulation time 138949874 ps
CPU time 3.56 seconds
Started Jul 17 05:30:01 PM PDT 24
Finished Jul 17 05:30:06 PM PDT 24
Peak memory 217380 kb
Host smart-f7e2e834-f513-44ea-b1f1-1db0be6523d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863082985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3863082985
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4234438276
Short name T549
Test name
Test status
Simulation time 82721565 ps
CPU time 1.13 seconds
Started Jul 17 05:30:01 PM PDT 24
Finished Jul 17 05:30:04 PM PDT 24
Peak memory 207924 kb
Host smart-150dfdb8-a2cf-4f36-87ad-7d376dd68ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234438276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4234438276
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2756026793
Short name T607
Test name
Test status
Simulation time 17308127138 ps
CPU time 14.77 seconds
Started Jul 17 05:30:01 PM PDT 24
Finished Jul 17 05:30:17 PM PDT 24
Peak memory 225636 kb
Host smart-30bb8bbc-b5cd-4611-8818-4f3c134b86f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756026793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2756026793
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2341847773
Short name T74
Test name
Test status
Simulation time 21281903 ps
CPU time 0.71 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:34:06 PM PDT 24
Peak memory 206280 kb
Host smart-0f6b5c36-9399-4db0-92d3-0c5dc2d0a966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341847773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2341847773
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2996304442
Short name T1024
Test name
Test status
Simulation time 192050441 ps
CPU time 2.37 seconds
Started Jul 17 05:30:03 PM PDT 24
Finished Jul 17 05:30:07 PM PDT 24
Peak memory 233524 kb
Host smart-05df6f13-c38d-4cf9-9dcd-cc15c38a40a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996304442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2996304442
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.806209801
Short name T306
Test name
Test status
Simulation time 13133894 ps
CPU time 0.78 seconds
Started Jul 17 05:30:02 PM PDT 24
Finished Jul 17 05:30:04 PM PDT 24
Peak memory 206488 kb
Host smart-6bf3bc7f-1232-4daf-85a6-ec2f25495f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806209801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.806209801
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3991714680
Short name T257
Test name
Test status
Simulation time 21520270436 ps
CPU time 180.13 seconds
Started Jul 17 05:30:15 PM PDT 24
Finished Jul 17 05:33:16 PM PDT 24
Peak memory 252112 kb
Host smart-d8902c25-e139-4c5f-8655-d63bbf68f039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991714680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3991714680
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.4201276213
Short name T186
Test name
Test status
Simulation time 56512202650 ps
CPU time 76.21 seconds
Started Jul 17 05:34:02 PM PDT 24
Finished Jul 17 05:35:19 PM PDT 24
Peak memory 242112 kb
Host smart-32fee2f3-47be-449e-9756-69fd18c864ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201276213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.4201276213
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.155961388
Short name T370
Test name
Test status
Simulation time 2259617758 ps
CPU time 13.77 seconds
Started Jul 17 05:30:14 PM PDT 24
Finished Jul 17 05:30:29 PM PDT 24
Peak memory 225816 kb
Host smart-8308a76d-e3a1-4e77-8ce6-b4bd1e37a903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155961388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.155961388
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3404409419
Short name T128
Test name
Test status
Simulation time 655369150 ps
CPU time 8.35 seconds
Started Jul 17 05:30:04 PM PDT 24
Finished Jul 17 05:30:14 PM PDT 24
Peak memory 250104 kb
Host smart-83a4a479-72c9-4b17-b658-3d5f913b97cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404409419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3404409419
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.4108535792
Short name T51
Test name
Test status
Simulation time 100412066019 ps
CPU time 338.68 seconds
Started Jul 17 05:30:15 PM PDT 24
Finished Jul 17 05:35:55 PM PDT 24
Peak memory 263336 kb
Host smart-39608187-86c5-466b-8408-a655ce359ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108535792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.4108535792
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.946267372
Short name T698
Test name
Test status
Simulation time 8291169056 ps
CPU time 26.06 seconds
Started Jul 17 05:30:02 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 225716 kb
Host smart-7b68d6db-3605-4022-82db-a3ea2405151a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946267372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.946267372
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2939016685
Short name T131
Test name
Test status
Simulation time 2579331541 ps
CPU time 12.95 seconds
Started Jul 17 05:30:05 PM PDT 24
Finished Jul 17 05:30:19 PM PDT 24
Peak memory 242048 kb
Host smart-8546017d-c0fe-4b34-8b86-68bfbc3a894c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939016685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2939016685
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3992962909
Short name T598
Test name
Test status
Simulation time 3063756000 ps
CPU time 12.25 seconds
Started Jul 17 05:30:03 PM PDT 24
Finished Jul 17 05:30:17 PM PDT 24
Peak memory 233908 kb
Host smart-94abca32-44fd-47fb-a0f6-18e6abf92f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992962909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3992962909
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.611189411
Short name T493
Test name
Test status
Simulation time 15190300353 ps
CPU time 18.24 seconds
Started Jul 17 05:30:02 PM PDT 24
Finished Jul 17 05:30:22 PM PDT 24
Peak memory 225720 kb
Host smart-2a0b972f-1e5b-4e62-9474-b5642dff8ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611189411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.611189411
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.196849480
Short name T480
Test name
Test status
Simulation time 1564218570 ps
CPU time 7.26 seconds
Started Jul 17 05:30:14 PM PDT 24
Finished Jul 17 05:30:23 PM PDT 24
Peak memory 221232 kb
Host smart-fa1514b6-51f9-4477-876b-0d5667da81c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=196849480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.196849480
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2031993832
Short name T599
Test name
Test status
Simulation time 54538782330 ps
CPU time 130.42 seconds
Started Jul 17 05:30:19 PM PDT 24
Finished Jul 17 05:32:30 PM PDT 24
Peak memory 260572 kb
Host smart-4e95abb1-beae-4ef3-bcf1-fa045cf28ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031993832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2031993832
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3317164954
Short name T276
Test name
Test status
Simulation time 1200686650 ps
CPU time 11.12 seconds
Started Jul 17 05:30:08 PM PDT 24
Finished Jul 17 05:30:20 PM PDT 24
Peak memory 217208 kb
Host smart-450babc5-8344-4c44-9f80-48f46680c6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317164954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3317164954
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.111368315
Short name T752
Test name
Test status
Simulation time 20669381684 ps
CPU time 13.03 seconds
Started Jul 17 05:32:55 PM PDT 24
Finished Jul 17 05:33:09 PM PDT 24
Peak memory 217444 kb
Host smart-f47e3e17-50c4-42f8-9b7b-9094e3b86a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111368315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.111368315
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2879216197
Short name T29
Test name
Test status
Simulation time 230058494 ps
CPU time 7.54 seconds
Started Jul 17 05:33:48 PM PDT 24
Finished Jul 17 05:33:57 PM PDT 24
Peak memory 217320 kb
Host smart-7a22bd78-3572-4ce7-988a-473b5cc82420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879216197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2879216197
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.649539750
Short name T861
Test name
Test status
Simulation time 77597197 ps
CPU time 0.76 seconds
Started Jul 17 05:30:08 PM PDT 24
Finished Jul 17 05:30:10 PM PDT 24
Peak memory 206888 kb
Host smart-9bcd4ddb-1a97-4757-b32d-1db52d07d4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649539750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.649539750
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.673704819
Short name T458
Test name
Test status
Simulation time 6434524363 ps
CPU time 20.24 seconds
Started Jul 17 05:30:08 PM PDT 24
Finished Jul 17 05:30:29 PM PDT 24
Peak memory 233780 kb
Host smart-32736fa1-d6a6-47b0-b1ce-1f55a8bd550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673704819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.673704819
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2816830807
Short name T500
Test name
Test status
Simulation time 65120202 ps
CPU time 0.71 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:30:23 PM PDT 24
Peak memory 206268 kb
Host smart-e6917a02-0838-49bb-810a-e3b574750778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816830807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2816830807
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3253745776
Short name T1016
Test name
Test status
Simulation time 123206241 ps
CPU time 2.65 seconds
Started Jul 17 05:30:13 PM PDT 24
Finished Jul 17 05:30:17 PM PDT 24
Peak memory 233504 kb
Host smart-574bf35b-dd36-440d-83ba-cb45521ee550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253745776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3253745776
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3862059324
Short name T665
Test name
Test status
Simulation time 18314368 ps
CPU time 0.74 seconds
Started Jul 17 05:30:12 PM PDT 24
Finished Jul 17 05:30:14 PM PDT 24
Peak memory 207812 kb
Host smart-d75f8875-8114-4505-b537-a263cf2ddfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862059324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3862059324
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.4201172395
Short name T859
Test name
Test status
Simulation time 1146576377 ps
CPU time 14.46 seconds
Started Jul 17 05:30:13 PM PDT 24
Finished Jul 17 05:30:28 PM PDT 24
Peak memory 233800 kb
Host smart-b98979a3-aeed-4ce9-a701-9d1779dd6204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201172395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4201172395
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1054049784
Short name T193
Test name
Test status
Simulation time 50842867509 ps
CPU time 235.4 seconds
Started Jul 17 05:33:48 PM PDT 24
Finished Jul 17 05:37:46 PM PDT 24
Peak memory 257940 kb
Host smart-c158885a-92c4-425e-9c8e-6b3b481ea27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054049784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1054049784
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1597880153
Short name T621
Test name
Test status
Simulation time 98135288799 ps
CPU time 205.47 seconds
Started Jul 17 05:30:15 PM PDT 24
Finished Jul 17 05:33:42 PM PDT 24
Peak memory 250312 kb
Host smart-8da5047e-3bb0-46dd-bbbd-ed405033c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597880153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1597880153
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1219850057
Short name T962
Test name
Test status
Simulation time 1907480226 ps
CPU time 8.03 seconds
Started Jul 17 05:30:15 PM PDT 24
Finished Jul 17 05:30:24 PM PDT 24
Peak memory 236148 kb
Host smart-01ca6eac-619b-4015-8226-d51f7509d9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219850057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1219850057
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1678742113
Short name T252
Test name
Test status
Simulation time 104613214152 ps
CPU time 213.09 seconds
Started Jul 17 05:30:13 PM PDT 24
Finished Jul 17 05:33:48 PM PDT 24
Peak memory 264420 kb
Host smart-451a0600-ee96-4f72-a9aa-70d2dbec435a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678742113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1678742113
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.968026745
Short name T862
Test name
Test status
Simulation time 17891103692 ps
CPU time 19.01 seconds
Started Jul 17 05:33:13 PM PDT 24
Finished Jul 17 05:33:33 PM PDT 24
Peak memory 233832 kb
Host smart-dc92d0b5-d853-4b0c-9d61-2830033e2382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968026745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.968026745
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3581227322
Short name T808
Test name
Test status
Simulation time 12725340851 ps
CPU time 35.1 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:30:57 PM PDT 24
Peak memory 233036 kb
Host smart-914c9976-b462-4301-9a13-ce583ae52bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581227322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3581227322
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1869640718
Short name T726
Test name
Test status
Simulation time 679149430 ps
CPU time 4.28 seconds
Started Jul 17 05:30:15 PM PDT 24
Finished Jul 17 05:30:20 PM PDT 24
Peak memory 233720 kb
Host smart-a677a90f-78cb-49d5-8d9d-e97474e3f8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869640718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1869640718
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2815000722
Short name T925
Test name
Test status
Simulation time 24404699506 ps
CPU time 10.73 seconds
Started Jul 17 05:33:46 PM PDT 24
Finished Jul 17 05:33:58 PM PDT 24
Peak memory 233800 kb
Host smart-e091263a-83f0-493b-b11e-2bb662984a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815000722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2815000722
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1073435553
Short name T609
Test name
Test status
Simulation time 88628179 ps
CPU time 3.68 seconds
Started Jul 17 05:30:16 PM PDT 24
Finished Jul 17 05:30:20 PM PDT 24
Peak memory 224084 kb
Host smart-16c36e0e-2daf-435a-a9e8-611271248531
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1073435553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1073435553
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.303962811
Short name T960
Test name
Test status
Simulation time 93683131 ps
CPU time 1.09 seconds
Started Jul 17 05:34:12 PM PDT 24
Finished Jul 17 05:34:17 PM PDT 24
Peak memory 206936 kb
Host smart-5eff8498-a42f-4c06-a295-f92552edcd4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303962811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.303962811
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4216804276
Short name T345
Test name
Test status
Simulation time 14512168 ps
CPU time 0.74 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:30:23 PM PDT 24
Peak memory 206596 kb
Host smart-a6e675e8-9425-4845-97da-3b8bcc9e073b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216804276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4216804276
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1730950324
Short name T718
Test name
Test status
Simulation time 17037695746 ps
CPU time 3.65 seconds
Started Jul 17 05:30:15 PM PDT 24
Finished Jul 17 05:30:20 PM PDT 24
Peak memory 217064 kb
Host smart-2f17dddf-f0d0-4bdd-98d2-5a3216a0c65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730950324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1730950324
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3711782380
Short name T868
Test name
Test status
Simulation time 165383793 ps
CPU time 1.09 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:30:23 PM PDT 24
Peak memory 208888 kb
Host smart-45a9ee85-e405-4f44-9079-32aba0a85ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711782380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3711782380
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.746582228
Short name T484
Test name
Test status
Simulation time 20468954 ps
CPU time 0.82 seconds
Started Jul 17 05:30:13 PM PDT 24
Finished Jul 17 05:30:15 PM PDT 24
Peak memory 206808 kb
Host smart-5988e2da-0892-4d14-b073-f4e6117d9535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746582228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.746582228
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.190894784
Short name T985
Test name
Test status
Simulation time 4921935810 ps
CPU time 9.77 seconds
Started Jul 17 05:33:11 PM PDT 24
Finished Jul 17 05:33:22 PM PDT 24
Peak memory 225692 kb
Host smart-06651375-c25a-4c12-9f23-a2e2dfcbbaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190894784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.190894784
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2922916315
Short name T400
Test name
Test status
Simulation time 13136420 ps
CPU time 0.71 seconds
Started Jul 17 05:30:27 PM PDT 24
Finished Jul 17 05:30:29 PM PDT 24
Peak memory 205804 kb
Host smart-889d2a33-626e-4de2-b589-3ef05956cfb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922916315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2922916315
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1373873432
Short name T968
Test name
Test status
Simulation time 230629152 ps
CPU time 3.49 seconds
Started Jul 17 05:33:39 PM PDT 24
Finished Jul 17 05:33:44 PM PDT 24
Peak memory 233740 kb
Host smart-7648439a-61ca-4cfb-a523-9d8c3f51ea92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373873432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1373873432
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2019162814
Short name T361
Test name
Test status
Simulation time 24956717 ps
CPU time 0.82 seconds
Started Jul 17 05:30:13 PM PDT 24
Finished Jul 17 05:30:15 PM PDT 24
Peak memory 207704 kb
Host smart-5179ba92-63e4-4061-b1c2-859a8cb64cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019162814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2019162814
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2645709739
Short name T231
Test name
Test status
Simulation time 3401063041 ps
CPU time 38.23 seconds
Started Jul 17 05:30:25 PM PDT 24
Finished Jul 17 05:31:05 PM PDT 24
Peak memory 254932 kb
Host smart-d3a52a00-43b3-4eef-85c2-69328558f712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645709739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2645709739
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2797920948
Short name T4
Test name
Test status
Simulation time 24962473591 ps
CPU time 237.43 seconds
Started Jul 17 05:30:26 PM PDT 24
Finished Jul 17 05:34:25 PM PDT 24
Peak memory 253508 kb
Host smart-445e9f68-cfd4-40e6-8431-c799b7ea9ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797920948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2797920948
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4065302064
Short name T521
Test name
Test status
Simulation time 1108483849 ps
CPU time 8.25 seconds
Started Jul 17 05:30:26 PM PDT 24
Finished Jul 17 05:30:36 PM PDT 24
Peak memory 233784 kb
Host smart-c340d48a-6ff0-4f9a-83f0-ebe23290a0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065302064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4065302064
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2225117691
Short name T168
Test name
Test status
Simulation time 8696324697 ps
CPU time 53.94 seconds
Started Jul 17 05:30:26 PM PDT 24
Finished Jul 17 05:31:21 PM PDT 24
Peak memory 252016 kb
Host smart-016ae231-f63f-4c28-8f11-db2804e9be97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225117691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2225117691
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.4239643542
Short name T686
Test name
Test status
Simulation time 2642881105 ps
CPU time 20.9 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:34:16 PM PDT 24
Peak memory 233896 kb
Host smart-9336bb93-401e-4906-9249-dd3c498f5bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239643542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.4239643542
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3086187439
Short name T184
Test name
Test status
Simulation time 23458870780 ps
CPU time 98.1 seconds
Started Jul 17 05:30:29 PM PDT 24
Finished Jul 17 05:32:09 PM PDT 24
Peak memory 252556 kb
Host smart-2009271b-faf2-438f-8b30-6bdb5367b60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086187439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3086187439
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3380517169
Short name T907
Test name
Test status
Simulation time 8589417546 ps
CPU time 9.63 seconds
Started Jul 17 05:30:15 PM PDT 24
Finished Jul 17 05:30:26 PM PDT 24
Peak memory 235224 kb
Host smart-4b3b5aeb-f472-4d93-9915-c7c740a09114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380517169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3380517169
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1978576061
Short name T77
Test name
Test status
Simulation time 3745338020 ps
CPU time 5.18 seconds
Started Jul 17 05:30:14 PM PDT 24
Finished Jul 17 05:30:20 PM PDT 24
Peak memory 233840 kb
Host smart-4dfae7a2-54ab-417d-8fe0-9563ce4e70c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978576061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1978576061
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4253040454
Short name T738
Test name
Test status
Simulation time 5630732271 ps
CPU time 6.06 seconds
Started Jul 17 05:30:43 PM PDT 24
Finished Jul 17 05:30:50 PM PDT 24
Peak memory 224540 kb
Host smart-4625c33f-952b-4565-b52e-f53e438e21af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4253040454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4253040454
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1424403504
Short name T475
Test name
Test status
Simulation time 20642947534 ps
CPU time 164.45 seconds
Started Jul 17 05:30:25 PM PDT 24
Finished Jul 17 05:33:11 PM PDT 24
Peak memory 241056 kb
Host smart-b3cfc685-e9f1-4578-a3e0-92da7b45409f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424403504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1424403504
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.999452947
Short name T524
Test name
Test status
Simulation time 5999120507 ps
CPU time 12.82 seconds
Started Jul 17 05:30:12 PM PDT 24
Finished Jul 17 05:30:26 PM PDT 24
Peak memory 217440 kb
Host smart-a4863146-2917-4c52-811e-ea33052284d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999452947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.999452947
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.530770590
Short name T461
Test name
Test status
Simulation time 462573284 ps
CPU time 1.74 seconds
Started Jul 17 05:30:13 PM PDT 24
Finished Jul 17 05:30:16 PM PDT 24
Peak memory 208960 kb
Host smart-34cf601b-3e83-47e8-9f0f-52df3c6915a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530770590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.530770590
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3262928268
Short name T667
Test name
Test status
Simulation time 114321729 ps
CPU time 1.26 seconds
Started Jul 17 05:30:14 PM PDT 24
Finished Jul 17 05:30:16 PM PDT 24
Peak memory 207996 kb
Host smart-558b3291-e25b-42f9-9ed6-a7e39068bbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262928268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3262928268
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1685920247
Short name T967
Test name
Test status
Simulation time 60879369 ps
CPU time 0.95 seconds
Started Jul 17 05:30:12 PM PDT 24
Finished Jul 17 05:30:14 PM PDT 24
Peak memory 206948 kb
Host smart-f943de78-41c3-4d4c-9a5c-991d511830a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685920247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1685920247
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.209626418
Short name T664
Test name
Test status
Simulation time 10528525968 ps
CPU time 25.92 seconds
Started Jul 17 05:30:25 PM PDT 24
Finished Jul 17 05:30:52 PM PDT 24
Peak memory 233884 kb
Host smart-398ede98-76ef-4ce9-834c-8890d03a7281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209626418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.209626418
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.620880084
Short name T947
Test name
Test status
Simulation time 11553741 ps
CPU time 0.68 seconds
Started Jul 17 05:30:25 PM PDT 24
Finished Jul 17 05:30:26 PM PDT 24
Peak memory 205788 kb
Host smart-d13f0a24-6f31-456e-b2d9-8a6167890028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620880084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.620880084
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.4151588146
Short name T220
Test name
Test status
Simulation time 680109443 ps
CPU time 5.65 seconds
Started Jul 17 05:33:07 PM PDT 24
Finished Jul 17 05:33:13 PM PDT 24
Peak memory 233744 kb
Host smart-9c476d3f-8d33-4a59-a2ee-0691cdf6a658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151588146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4151588146
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1561072909
Short name T749
Test name
Test status
Simulation time 43056566 ps
CPU time 0.8 seconds
Started Jul 17 05:30:28 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 207508 kb
Host smart-6ae70d7a-2190-48f8-a623-b7687a1b6854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561072909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1561072909
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2583986717
Short name T298
Test name
Test status
Simulation time 31115824 ps
CPU time 0.8 seconds
Started Jul 17 05:33:38 PM PDT 24
Finished Jul 17 05:33:40 PM PDT 24
Peak memory 216888 kb
Host smart-c92286b7-956c-41dc-85e7-643f3732a70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583986717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2583986717
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2505633960
Short name T173
Test name
Test status
Simulation time 41749811481 ps
CPU time 183.97 seconds
Started Jul 17 05:30:25 PM PDT 24
Finished Jul 17 05:33:30 PM PDT 24
Peak memory 250428 kb
Host smart-0f3b4e92-dc6c-4cea-98f2-0bf7a49fba01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505633960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2505633960
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1097100641
Short name T823
Test name
Test status
Simulation time 20903932358 ps
CPU time 54.03 seconds
Started Jul 17 05:33:39 PM PDT 24
Finished Jul 17 05:34:35 PM PDT 24
Peak memory 250372 kb
Host smart-aa0a8ea4-b88c-4070-8f8e-ab7aa18d4ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097100641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1097100641
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4165590859
Short name T208
Test name
Test status
Simulation time 980303221 ps
CPU time 12.52 seconds
Started Jul 17 05:30:26 PM PDT 24
Finished Jul 17 05:30:40 PM PDT 24
Peak memory 241924 kb
Host smart-c3528832-3417-4605-8363-e9f19064ae58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165590859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4165590859
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2551342421
Short name T727
Test name
Test status
Simulation time 77303455381 ps
CPU time 159.53 seconds
Started Jul 17 05:30:25 PM PDT 24
Finished Jul 17 05:33:06 PM PDT 24
Peak memory 258116 kb
Host smart-5c7a060c-9cdb-4ca6-8ef2-a941bfa7b1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551342421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2551342421
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.645420257
Short name T906
Test name
Test status
Simulation time 1483926616 ps
CPU time 13.16 seconds
Started Jul 17 05:30:25 PM PDT 24
Finished Jul 17 05:30:39 PM PDT 24
Peak memory 225516 kb
Host smart-81d62300-62b2-45cf-aa46-13d36a9e8382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645420257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.645420257
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2597367545
Short name T1014
Test name
Test status
Simulation time 2944908257 ps
CPU time 12.83 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:34:18 PM PDT 24
Peak memory 233848 kb
Host smart-33fa560b-6ed1-49b3-b2b8-1b7074964c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597367545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2597367545
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3471354898
Short name T750
Test name
Test status
Simulation time 5968604466 ps
CPU time 9.34 seconds
Started Jul 17 05:30:26 PM PDT 24
Finished Jul 17 05:30:36 PM PDT 24
Peak memory 233876 kb
Host smart-fba4e47b-7d8f-48f1-a7a5-e03d89cb150d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471354898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3471354898
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.169278851
Short name T699
Test name
Test status
Simulation time 955184882 ps
CPU time 5.07 seconds
Started Jul 17 05:30:24 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 225524 kb
Host smart-930c8a71-8c8a-456c-b219-92ec76164c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169278851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.169278851
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1872049113
Short name T648
Test name
Test status
Simulation time 389334103 ps
CPU time 5.18 seconds
Started Jul 17 05:30:24 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 224116 kb
Host smart-ffdec920-4b70-4dc4-adf7-2181a4a539ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1872049113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1872049113
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.251049814
Short name T454
Test name
Test status
Simulation time 1464733256 ps
CPU time 6.91 seconds
Started Jul 17 05:30:28 PM PDT 24
Finished Jul 17 05:30:37 PM PDT 24
Peak memory 217604 kb
Host smart-7062e5a2-df69-49b2-9c8a-f063a57445e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251049814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.251049814
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1910738557
Short name T393
Test name
Test status
Simulation time 4822731904 ps
CPU time 3.27 seconds
Started Jul 17 05:30:26 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 217428 kb
Host smart-b0702cea-f0a3-4c24-b7cd-badbe8c0b1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910738557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1910738557
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1851040673
Short name T977
Test name
Test status
Simulation time 26086947 ps
CPU time 0.98 seconds
Started Jul 17 05:33:42 PM PDT 24
Finished Jul 17 05:33:44 PM PDT 24
Peak memory 208016 kb
Host smart-04c4758c-04ff-4581-9518-5526df9bdd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851040673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1851040673
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.4175416781
Short name T313
Test name
Test status
Simulation time 36086640 ps
CPU time 0.82 seconds
Started Jul 17 05:30:26 PM PDT 24
Finished Jul 17 05:30:28 PM PDT 24
Peak memory 206916 kb
Host smart-422b533d-6c68-4ead-a450-5176b3e32278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175416781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.4175416781
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3992131994
Short name T601
Test name
Test status
Simulation time 2680303381 ps
CPU time 10.54 seconds
Started Jul 17 05:30:25 PM PDT 24
Finished Jul 17 05:30:37 PM PDT 24
Peak memory 225660 kb
Host smart-81113cb0-01c4-4024-9f87-9da11978b75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992131994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3992131994
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1172829506
Short name T386
Test name
Test status
Simulation time 22701710 ps
CPU time 0.73 seconds
Started Jul 17 05:27:48 PM PDT 24
Finished Jul 17 05:27:51 PM PDT 24
Peak memory 206344 kb
Host smart-21c12ca7-cb30-4e21-a5ff-f1955280649d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172829506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
172829506
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3783810301
Short name T608
Test name
Test status
Simulation time 2384996993 ps
CPU time 9.8 seconds
Started Jul 17 05:30:24 PM PDT 24
Finished Jul 17 05:30:34 PM PDT 24
Peak memory 233888 kb
Host smart-bb837cb0-c76e-43f0-902b-e04e1a2217e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783810301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3783810301
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.4090457835
Short name T389
Test name
Test status
Simulation time 14563867 ps
CPU time 0.8 seconds
Started Jul 17 05:31:58 PM PDT 24
Finished Jul 17 05:32:00 PM PDT 24
Peak memory 207516 kb
Host smart-20d7b67c-42ac-42c2-b5f1-6e3a4eeda3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090457835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4090457835
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.636059838
Short name T456
Test name
Test status
Simulation time 15645194218 ps
CPU time 95.92 seconds
Started Jul 17 05:27:44 PM PDT 24
Finished Jul 17 05:29:22 PM PDT 24
Peak memory 240256 kb
Host smart-7b76095d-2f00-4381-b724-e64523ba9fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636059838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.636059838
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.546767117
Short name T577
Test name
Test status
Simulation time 15011180050 ps
CPU time 60.97 seconds
Started Jul 17 05:29:20 PM PDT 24
Finished Jul 17 05:30:23 PM PDT 24
Peak memory 249524 kb
Host smart-48716c5c-5a56-4a92-b4a7-ff0d701698c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546767117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.546767117
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.109411031
Short name T990
Test name
Test status
Simulation time 13369958255 ps
CPU time 32.38 seconds
Started Jul 17 05:29:30 PM PDT 24
Finished Jul 17 05:30:04 PM PDT 24
Peak memory 233996 kb
Host smart-2f0bc4c1-a663-4c2a-a370-5e34b61d4390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109411031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
109411031
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.4048869413
Short name T874
Test name
Test status
Simulation time 144690861 ps
CPU time 3.06 seconds
Started Jul 17 05:30:44 PM PDT 24
Finished Jul 17 05:30:48 PM PDT 24
Peak memory 225724 kb
Host smart-11e4680f-837b-43bf-852b-db6ed818cdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048869413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.4048869413
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.4138142121
Short name T769
Test name
Test status
Simulation time 65735610291 ps
CPU time 219.62 seconds
Started Jul 17 05:27:48 PM PDT 24
Finished Jul 17 05:31:30 PM PDT 24
Peak memory 250720 kb
Host smart-26401b30-1325-400f-b131-a4bac773db71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138142121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.4138142121
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4162437704
Short name T917
Test name
Test status
Simulation time 831477742 ps
CPU time 4.81 seconds
Started Jul 17 05:30:27 PM PDT 24
Finished Jul 17 05:30:33 PM PDT 24
Peak memory 225676 kb
Host smart-0800dd58-9abc-45ae-96a6-a0227da92ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162437704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4162437704
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.141670492
Short name T210
Test name
Test status
Simulation time 6063282847 ps
CPU time 55.31 seconds
Started Jul 17 05:33:50 PM PDT 24
Finished Jul 17 05:34:48 PM PDT 24
Peak memory 252064 kb
Host smart-c607e63f-86e2-4646-ad3b-528551a5589b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141670492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.141670492
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2690562608
Short name T374
Test name
Test status
Simulation time 40489293 ps
CPU time 1.09 seconds
Started Jul 17 05:29:44 PM PDT 24
Finished Jul 17 05:29:47 PM PDT 24
Peak memory 217628 kb
Host smart-c3065eaa-4fde-4d8d-a7b4-564a3d12a2c8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690562608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2690562608
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2228697940
Short name T578
Test name
Test status
Simulation time 8866474486 ps
CPU time 8.83 seconds
Started Jul 17 05:30:28 PM PDT 24
Finished Jul 17 05:30:39 PM PDT 24
Peak memory 225920 kb
Host smart-eb72f401-9e5c-415e-8632-1dce34d35753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228697940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2228697940
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2354159780
Short name T889
Test name
Test status
Simulation time 6338049719 ps
CPU time 10.54 seconds
Started Jul 17 05:32:50 PM PDT 24
Finished Jul 17 05:33:01 PM PDT 24
Peak memory 233852 kb
Host smart-80c6266c-b2e2-4d8c-b913-b0570534f82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354159780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2354159780
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.206563116
Short name T469
Test name
Test status
Simulation time 3407701642 ps
CPU time 13.48 seconds
Started Jul 17 05:27:47 PM PDT 24
Finished Jul 17 05:28:03 PM PDT 24
Peak memory 222972 kb
Host smart-9ec8c4de-6ede-4a0a-a0e0-b543fec2f726
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=206563116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.206563116
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1688968394
Short name T70
Test name
Test status
Simulation time 76682004 ps
CPU time 1.02 seconds
Started Jul 17 05:29:37 PM PDT 24
Finished Jul 17 05:29:40 PM PDT 24
Peak memory 236312 kb
Host smart-f05bb0a8-e031-467b-b3aa-9c9b8645ffb3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688968394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1688968394
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1794150901
Short name T245
Test name
Test status
Simulation time 74233954829 ps
CPU time 139.94 seconds
Started Jul 17 05:27:41 PM PDT 24
Finished Jul 17 05:30:02 PM PDT 24
Peak memory 273280 kb
Host smart-51129ebc-d9b1-4114-84b5-0c0c9cfc7be6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794150901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1794150901
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3320209426
Short name T28
Test name
Test status
Simulation time 5630269061 ps
CPU time 27.11 seconds
Started Jul 17 05:27:52 PM PDT 24
Finished Jul 17 05:28:20 PM PDT 24
Peak memory 219240 kb
Host smart-7a0666ca-4aa1-4032-aef1-e82b97f959e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320209426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3320209426
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3624315491
Short name T88
Test name
Test status
Simulation time 2793383472 ps
CPU time 11.16 seconds
Started Jul 17 05:27:49 PM PDT 24
Finished Jul 17 05:28:02 PM PDT 24
Peak memory 217364 kb
Host smart-4d4d6688-f702-407d-b6e0-a4fa119acddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624315491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3624315491
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3974584755
Short name T295
Test name
Test status
Simulation time 17343776 ps
CPU time 0.87 seconds
Started Jul 17 05:30:28 PM PDT 24
Finished Jul 17 05:30:32 PM PDT 24
Peak memory 207996 kb
Host smart-824e7761-cc75-4565-8432-85fbf5e3569c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974584755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3974584755
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2891012967
Short name T303
Test name
Test status
Simulation time 55354066 ps
CPU time 0.81 seconds
Started Jul 17 05:27:52 PM PDT 24
Finished Jul 17 05:27:54 PM PDT 24
Peak memory 206980 kb
Host smart-db67ed8a-b2c2-4607-88c8-b9774963bcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891012967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2891012967
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.377048438
Short name T866
Test name
Test status
Simulation time 799645981 ps
CPU time 2.2 seconds
Started Jul 17 05:29:59 PM PDT 24
Finished Jul 17 05:30:03 PM PDT 24
Peak memory 225272 kb
Host smart-e57d3da2-3962-46b6-ad18-00cb31b3b722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377048438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.377048438
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4234063132
Short name T837
Test name
Test status
Simulation time 32809827 ps
CPU time 0.69 seconds
Started Jul 17 05:30:43 PM PDT 24
Finished Jul 17 05:30:45 PM PDT 24
Peak memory 206284 kb
Host smart-3c08fef6-90fc-4948-96c4-0576b0379e31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234063132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4234063132
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1866204600
Short name T646
Test name
Test status
Simulation time 412473844 ps
CPU time 2.9 seconds
Started Jul 17 05:33:49 PM PDT 24
Finished Jul 17 05:33:53 PM PDT 24
Peak memory 225612 kb
Host smart-cc244387-3e44-4798-8521-1fddbb3d96e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866204600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1866204600
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3819167100
Short name T566
Test name
Test status
Simulation time 27849494 ps
CPU time 0.78 seconds
Started Jul 17 05:30:26 PM PDT 24
Finished Jul 17 05:30:28 PM PDT 24
Peak memory 207792 kb
Host smart-ea823a3d-b879-45d7-9a4d-5e0d599c8910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819167100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3819167100
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.141056612
Short name T253
Test name
Test status
Simulation time 663139530924 ps
CPU time 440.69 seconds
Started Jul 17 05:30:36 PM PDT 24
Finished Jul 17 05:37:58 PM PDT 24
Peak memory 266460 kb
Host smart-51650e70-d5d4-409b-8bba-1ed162d40a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141056612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.141056612
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1396153136
Short name T723
Test name
Test status
Simulation time 104108648230 ps
CPU time 200.43 seconds
Started Jul 17 05:33:07 PM PDT 24
Finished Jul 17 05:36:29 PM PDT 24
Peak memory 251360 kb
Host smart-d69fe10a-4f24-4ae4-a8a7-8281153f79a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396153136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1396153136
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2747968739
Short name T243
Test name
Test status
Simulation time 14063847995 ps
CPU time 112.14 seconds
Started Jul 17 05:30:35 PM PDT 24
Finished Jul 17 05:32:28 PM PDT 24
Peak memory 262944 kb
Host smart-6e704dd5-ad0c-4563-8282-dd45bdcebcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747968739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2747968739
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3751036581
Short name T291
Test name
Test status
Simulation time 187921459 ps
CPU time 3.9 seconds
Started Jul 17 05:30:40 PM PDT 24
Finished Jul 17 05:30:45 PM PDT 24
Peak memory 233772 kb
Host smart-4eb16957-0489-4d36-bc3f-c1752dc14878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751036581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3751036581
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1715000216
Short name T64
Test name
Test status
Simulation time 2980838694 ps
CPU time 50.13 seconds
Started Jul 17 05:33:50 PM PDT 24
Finished Jul 17 05:34:42 PM PDT 24
Peak memory 252248 kb
Host smart-5205c233-b4eb-4d63-bb78-e307b04f230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715000216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1715000216
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.768163771
Short name T410
Test name
Test status
Simulation time 3130539580 ps
CPU time 10.12 seconds
Started Jul 17 05:33:00 PM PDT 24
Finished Jul 17 05:33:12 PM PDT 24
Peak memory 233892 kb
Host smart-bb5521ca-21a9-4219-9cb9-512aa4b8c443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768163771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.768163771
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1999340499
Short name T705
Test name
Test status
Simulation time 6076637101 ps
CPU time 68.81 seconds
Started Jul 17 05:30:41 PM PDT 24
Finished Jul 17 05:31:51 PM PDT 24
Peak memory 233836 kb
Host smart-dc324934-731d-41f9-9c63-5e7cedd4d4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999340499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1999340499
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.628262771
Short name T478
Test name
Test status
Simulation time 272326859 ps
CPU time 5.75 seconds
Started Jul 17 05:33:09 PM PDT 24
Finished Jul 17 05:33:15 PM PDT 24
Peak memory 225512 kb
Host smart-ff8fbb83-bdcb-44ac-9439-d12df3cffe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628262771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.628262771
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.34669458
Short name T96
Test name
Test status
Simulation time 13022539233 ps
CPU time 20.33 seconds
Started Jul 17 05:30:38 PM PDT 24
Finished Jul 17 05:30:58 PM PDT 24
Peak memory 233768 kb
Host smart-70ee050f-2237-44fd-a69b-da012a88c960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34669458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.34669458
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3843485019
Short name T836
Test name
Test status
Simulation time 492245709 ps
CPU time 5.98 seconds
Started Jul 17 05:33:11 PM PDT 24
Finished Jul 17 05:33:18 PM PDT 24
Peak memory 219980 kb
Host smart-b3d848e9-ff00-4721-9803-23b58eba7fef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3843485019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3843485019
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.618038418
Short name T30
Test name
Test status
Simulation time 49989795561 ps
CPU time 283.42 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:38:48 PM PDT 24
Peak memory 258168 kb
Host smart-17b4d38d-76ab-4774-9280-479bd45cf7b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618038418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.618038418
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2894105660
Short name T734
Test name
Test status
Simulation time 25688035445 ps
CPU time 23.5 seconds
Started Jul 17 05:32:55 PM PDT 24
Finished Jul 17 05:33:20 PM PDT 24
Peak memory 217464 kb
Host smart-55c88eef-de36-438f-a71d-d77d9014a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894105660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2894105660
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2132423032
Short name T442
Test name
Test status
Simulation time 3593468938 ps
CPU time 8.46 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:34:04 PM PDT 24
Peak memory 217404 kb
Host smart-965ed477-96d0-4efe-8623-0a01447938e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132423032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2132423032
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.781963514
Short name T460
Test name
Test status
Simulation time 117272177 ps
CPU time 1.84 seconds
Started Jul 17 05:30:38 PM PDT 24
Finished Jul 17 05:30:40 PM PDT 24
Peak memory 217528 kb
Host smart-57a07f37-3d4d-4327-ba13-364211c0454b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781963514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.781963514
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3948307734
Short name T1001
Test name
Test status
Simulation time 359952248 ps
CPU time 0.93 seconds
Started Jul 17 05:33:38 PM PDT 24
Finished Jul 17 05:33:40 PM PDT 24
Peak memory 206936 kb
Host smart-d565e3f3-b95b-405a-ab15-b66d5f3a0f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948307734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3948307734
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1848399202
Short name T364
Test name
Test status
Simulation time 5619504553 ps
CPU time 19.82 seconds
Started Jul 17 05:30:41 PM PDT 24
Finished Jul 17 05:31:02 PM PDT 24
Peak memory 233800 kb
Host smart-dd0e465c-2d6f-484c-82df-3a63fdbb3e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848399202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1848399202
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2425794746
Short name T339
Test name
Test status
Simulation time 27133951 ps
CPU time 0.71 seconds
Started Jul 17 05:30:37 PM PDT 24
Finished Jul 17 05:30:38 PM PDT 24
Peak memory 205784 kb
Host smart-71fca5a0-c7d0-4f98-b7ed-4a4b99731565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425794746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2425794746
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.194719416
Short name T80
Test name
Test status
Simulation time 35581382 ps
CPU time 2.25 seconds
Started Jul 17 05:30:38 PM PDT 24
Finished Jul 17 05:30:41 PM PDT 24
Peak memory 225500 kb
Host smart-966b012c-550b-471d-ada8-5a5367ed2d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194719416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.194719416
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.401278406
Short name T846
Test name
Test status
Simulation time 32797236 ps
CPU time 0.78 seconds
Started Jul 17 05:30:40 PM PDT 24
Finished Jul 17 05:30:41 PM PDT 24
Peak memory 207476 kb
Host smart-d7716d6c-0d92-4b4c-9b90-9fe3ab8fa709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401278406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.401278406
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2419493778
Short name T425
Test name
Test status
Simulation time 44230750 ps
CPU time 0.77 seconds
Started Jul 17 05:30:36 PM PDT 24
Finished Jul 17 05:30:37 PM PDT 24
Peak memory 217064 kb
Host smart-a1c46c8e-ca50-4f70-a22e-a3fc215a70de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419493778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2419493778
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.455734349
Short name T757
Test name
Test status
Simulation time 5913297397 ps
CPU time 93.1 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:35:45 PM PDT 24
Peak memory 251460 kb
Host smart-b65ccb7c-854b-4612-98a3-3ba89db69a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455734349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.455734349
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1378131667
Short name T403
Test name
Test status
Simulation time 8861224875 ps
CPU time 47.41 seconds
Started Jul 17 05:30:41 PM PDT 24
Finished Jul 17 05:31:30 PM PDT 24
Peak memory 218880 kb
Host smart-282a93f9-bdbb-4e9a-91ca-9f83157dfab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378131667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1378131667
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3603512829
Short name T62
Test name
Test status
Simulation time 986924115 ps
CPU time 6.31 seconds
Started Jul 17 05:30:39 PM PDT 24
Finished Jul 17 05:30:46 PM PDT 24
Peak memory 233764 kb
Host smart-ac3924e4-e29b-4869-86aa-c1b807f96d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603512829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3603512829
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.154355987
Short name T187
Test name
Test status
Simulation time 4500657489 ps
CPU time 61.24 seconds
Started Jul 17 05:30:40 PM PDT 24
Finished Jul 17 05:31:42 PM PDT 24
Peak memory 256392 kb
Host smart-7380e85e-a24a-4978-88ee-4051824dafd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154355987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.154355987
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1355664197
Short name T892
Test name
Test status
Simulation time 221521226 ps
CPU time 3.87 seconds
Started Jul 17 05:30:37 PM PDT 24
Finished Jul 17 05:30:41 PM PDT 24
Peak memory 225480 kb
Host smart-a3d28169-cffd-41df-b587-be3128738469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355664197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1355664197
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2590253381
Short name T94
Test name
Test status
Simulation time 463534185 ps
CPU time 10.57 seconds
Started Jul 17 05:30:41 PM PDT 24
Finished Jul 17 05:30:53 PM PDT 24
Peak memory 235156 kb
Host smart-f908a0d6-3f55-46c7-a021-2e24fb5cc24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590253381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2590253381
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1184908825
Short name T312
Test name
Test status
Simulation time 103870324 ps
CPU time 2.3 seconds
Started Jul 17 05:30:44 PM PDT 24
Finished Jul 17 05:30:48 PM PDT 24
Peak memory 224952 kb
Host smart-337525dd-89e1-48cc-bb4f-1ebbe69f4e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184908825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1184908825
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2064272766
Short name T489
Test name
Test status
Simulation time 124575772 ps
CPU time 2.57 seconds
Started Jul 17 05:30:40 PM PDT 24
Finished Jul 17 05:30:44 PM PDT 24
Peak memory 233456 kb
Host smart-124c5731-0733-4ff3-82fe-8287dce36307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064272766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2064272766
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2248182390
Short name T619
Test name
Test status
Simulation time 2767900590 ps
CPU time 12.35 seconds
Started Jul 17 05:33:54 PM PDT 24
Finished Jul 17 05:34:10 PM PDT 24
Peak memory 220068 kb
Host smart-0b1ee185-7c76-4e17-9c4b-8bbebdf6068c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2248182390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2248182390
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1227499178
Short name T392
Test name
Test status
Simulation time 108210714260 ps
CPU time 303.09 seconds
Started Jul 17 05:30:38 PM PDT 24
Finished Jul 17 05:35:42 PM PDT 24
Peak memory 258232 kb
Host smart-f2b4bc87-2ef0-4490-b7cd-89d002e21f7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227499178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1227499178
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1113184761
Short name T338
Test name
Test status
Simulation time 4193720371 ps
CPU time 25.98 seconds
Started Jul 17 05:31:14 PM PDT 24
Finished Jul 17 05:31:41 PM PDT 24
Peak memory 217444 kb
Host smart-f5b1f3b5-ef93-4f20-8863-66b495851ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113184761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1113184761
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2442556890
Short name T299
Test name
Test status
Simulation time 2155231207 ps
CPU time 3.92 seconds
Started Jul 17 05:30:40 PM PDT 24
Finished Jul 17 05:30:45 PM PDT 24
Peak memory 217504 kb
Host smart-ab95c704-90c4-43c0-a089-210594563e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442556890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2442556890
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2279590352
Short name T748
Test name
Test status
Simulation time 42668159 ps
CPU time 0.97 seconds
Started Jul 17 05:30:44 PM PDT 24
Finished Jul 17 05:30:46 PM PDT 24
Peak memory 208028 kb
Host smart-5c0fb9d6-c7df-4776-8b1f-cbca49e2238d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279590352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2279590352
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3070967148
Short name T992
Test name
Test status
Simulation time 86631913 ps
CPU time 0.88 seconds
Started Jul 17 05:30:39 PM PDT 24
Finished Jul 17 05:30:41 PM PDT 24
Peak memory 206904 kb
Host smart-7a8ca51f-61c8-49b0-843b-a715de80451a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070967148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3070967148
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2331751434
Short name T764
Test name
Test status
Simulation time 26397425192 ps
CPU time 21.44 seconds
Started Jul 17 05:30:38 PM PDT 24
Finished Jul 17 05:31:00 PM PDT 24
Peak memory 236136 kb
Host smart-80d1e66e-d416-4c3d-8903-83ea6c6425db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331751434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2331751434
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.715635016
Short name T832
Test name
Test status
Simulation time 48722697 ps
CPU time 0.7 seconds
Started Jul 17 05:34:09 PM PDT 24
Finished Jul 17 05:34:12 PM PDT 24
Peak memory 206340 kb
Host smart-6d2b7941-d9dc-44bf-a107-b8761f76dce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715635016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.715635016
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1049957541
Short name T746
Test name
Test status
Simulation time 796666287 ps
CPU time 6.32 seconds
Started Jul 17 05:30:42 PM PDT 24
Finished Jul 17 05:30:49 PM PDT 24
Peak memory 225548 kb
Host smart-c3ae14be-a22c-4f91-bdb1-0728998756f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049957541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1049957541
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2554727574
Short name T134
Test name
Test status
Simulation time 37986880 ps
CPU time 0.81 seconds
Started Jul 17 05:30:39 PM PDT 24
Finished Jul 17 05:30:41 PM PDT 24
Peak memory 207532 kb
Host smart-9525ec63-3f52-4540-9f25-7ecc2c153d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554727574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2554727574
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1884391623
Short name T218
Test name
Test status
Simulation time 50861581338 ps
CPU time 374.32 seconds
Started Jul 17 05:33:29 PM PDT 24
Finished Jul 17 05:39:44 PM PDT 24
Peak memory 264180 kb
Host smart-760c5adc-a982-40ea-9598-6d40340f8419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884391623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1884391623
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4132363958
Short name T691
Test name
Test status
Simulation time 201440750674 ps
CPU time 261.25 seconds
Started Jul 17 05:30:43 PM PDT 24
Finished Jul 17 05:35:05 PM PDT 24
Peak memory 252608 kb
Host smart-380e8cba-826b-4800-9c24-a9a05ed1fbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132363958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4132363958
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.674966796
Short name T517
Test name
Test status
Simulation time 103720484446 ps
CPU time 71.22 seconds
Started Jul 17 05:30:40 PM PDT 24
Finished Jul 17 05:31:52 PM PDT 24
Peak memory 258184 kb
Host smart-c32a342e-4758-47e5-b4fa-b2cff2ae6c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674966796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.674966796
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3612962110
Short name T387
Test name
Test status
Simulation time 220247282 ps
CPU time 5.4 seconds
Started Jul 17 05:33:46 PM PDT 24
Finished Jul 17 05:33:53 PM PDT 24
Peak memory 233760 kb
Host smart-bc8b41c6-cfd1-4fe4-91a7-b0e451f200bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612962110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3612962110
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1052835298
Short name T786
Test name
Test status
Simulation time 192632837017 ps
CPU time 233.39 seconds
Started Jul 17 05:30:39 PM PDT 24
Finished Jul 17 05:34:33 PM PDT 24
Peak memory 256428 kb
Host smart-6124e3dc-00f2-48e3-9a58-e796ea25379e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052835298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1052835298
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3647273751
Short name T191
Test name
Test status
Simulation time 713275061 ps
CPU time 6.37 seconds
Started Jul 17 05:30:42 PM PDT 24
Finished Jul 17 05:30:49 PM PDT 24
Peak memory 225544 kb
Host smart-420ccf45-57c1-4e8f-917b-0abbcafabed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647273751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3647273751
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3013006055
Short name T663
Test name
Test status
Simulation time 6868757588 ps
CPU time 39.61 seconds
Started Jul 17 05:33:54 PM PDT 24
Finished Jul 17 05:34:38 PM PDT 24
Peak memory 241184 kb
Host smart-0625f5f6-74ad-4239-ab6f-c228facd4c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013006055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3013006055
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1440852391
Short name T635
Test name
Test status
Simulation time 149087008 ps
CPU time 3.02 seconds
Started Jul 17 05:30:40 PM PDT 24
Finished Jul 17 05:30:44 PM PDT 24
Peak memory 225540 kb
Host smart-31d37089-791f-4d16-8f75-e193e882de57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440852391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1440852391
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3845292623
Short name T573
Test name
Test status
Simulation time 566729322 ps
CPU time 3.83 seconds
Started Jul 17 05:33:45 PM PDT 24
Finished Jul 17 05:33:49 PM PDT 24
Peak memory 233784 kb
Host smart-f1b50ec3-e1cd-4835-b93c-13ee7f3e2c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845292623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3845292623
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3771740013
Short name T473
Test name
Test status
Simulation time 2895141973 ps
CPU time 13.12 seconds
Started Jul 17 05:33:54 PM PDT 24
Finished Jul 17 05:34:11 PM PDT 24
Peak memory 223356 kb
Host smart-15e65f9e-ba52-4e68-b9ad-7b16723596f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3771740013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3771740013
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.181893346
Short name T886
Test name
Test status
Simulation time 4204178309 ps
CPU time 27.2 seconds
Started Jul 17 05:30:41 PM PDT 24
Finished Jul 17 05:31:10 PM PDT 24
Peak memory 242176 kb
Host smart-e0aedd3f-98f1-4d5c-b270-9f65c4f4f3d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181893346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.181893346
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1370370203
Short name T792
Test name
Test status
Simulation time 906268273 ps
CPU time 3.01 seconds
Started Jul 17 05:30:43 PM PDT 24
Finished Jul 17 05:30:47 PM PDT 24
Peak memory 217408 kb
Host smart-81096831-d900-4a22-a561-0dd811b85de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370370203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1370370203
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3353689287
Short name T797
Test name
Test status
Simulation time 88705796 ps
CPU time 1.33 seconds
Started Jul 17 05:30:49 PM PDT 24
Finished Jul 17 05:30:52 PM PDT 24
Peak memory 208844 kb
Host smart-8131ea29-4db3-4b43-b659-396c5a0a8f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353689287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3353689287
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2993526201
Short name T279
Test name
Test status
Simulation time 87931573 ps
CPU time 1.51 seconds
Started Jul 17 05:30:45 PM PDT 24
Finished Jul 17 05:30:47 PM PDT 24
Peak memory 209136 kb
Host smart-85fe131e-1889-4b20-8080-9b578ad92255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993526201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2993526201
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2217925743
Short name T819
Test name
Test status
Simulation time 21161516 ps
CPU time 0.77 seconds
Started Jul 17 05:34:10 PM PDT 24
Finished Jul 17 05:34:14 PM PDT 24
Peak memory 206932 kb
Host smart-186815db-1975-412f-b323-aaa3bde582be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217925743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2217925743
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2035378757
Short name T701
Test name
Test status
Simulation time 4948762122 ps
CPU time 8.16 seconds
Started Jul 17 05:33:30 PM PDT 24
Finished Jul 17 05:33:39 PM PDT 24
Peak memory 242080 kb
Host smart-f104ecef-cf9e-4919-af2c-de2961d053ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035378757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2035378757
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.540361613
Short name T501
Test name
Test status
Simulation time 48116192 ps
CPU time 0.74 seconds
Started Jul 17 05:30:56 PM PDT 24
Finished Jul 17 05:30:58 PM PDT 24
Peak memory 206368 kb
Host smart-d89ba4be-0df8-4a15-9871-538dddc8bf78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540361613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.540361613
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.440443005
Short name T805
Test name
Test status
Simulation time 136960492 ps
CPU time 2.83 seconds
Started Jul 17 05:30:55 PM PDT 24
Finished Jul 17 05:31:00 PM PDT 24
Peak memory 233652 kb
Host smart-c1bd97bf-0356-4aeb-a5cc-b681cb054f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440443005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.440443005
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.739500762
Short name T579
Test name
Test status
Simulation time 15604057 ps
CPU time 0.76 seconds
Started Jul 17 05:30:48 PM PDT 24
Finished Jul 17 05:30:49 PM PDT 24
Peak memory 207812 kb
Host smart-1d14d29b-d3a1-4c45-a780-8b0370d72341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739500762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.739500762
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1407580345
Short name T214
Test name
Test status
Simulation time 11048184353 ps
CPU time 79.87 seconds
Started Jul 17 05:33:31 PM PDT 24
Finished Jul 17 05:34:52 PM PDT 24
Peak memory 250256 kb
Host smart-252551ed-6c12-4939-9a5e-03827f094dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407580345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1407580345
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1987979227
Short name T196
Test name
Test status
Simulation time 152306507212 ps
CPU time 310.46 seconds
Started Jul 17 05:30:54 PM PDT 24
Finished Jul 17 05:36:05 PM PDT 24
Peak memory 253040 kb
Host smart-8ef7a94e-d612-4cd6-88e2-599702ecca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987979227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1987979227
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3361264576
Short name T721
Test name
Test status
Simulation time 3252937350 ps
CPU time 63.16 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:32:12 PM PDT 24
Peak memory 254052 kb
Host smart-55ff0aa7-77c6-45ef-b2e6-e70da004e99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361264576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3361264576
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3511030659
Short name T743
Test name
Test status
Simulation time 390180768 ps
CPU time 4.4 seconds
Started Jul 17 05:34:04 PM PDT 24
Finished Jul 17 05:34:10 PM PDT 24
Peak memory 233992 kb
Host smart-ccb5b489-1a24-4122-a2d7-c2b4ab320f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511030659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3511030659
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2366084890
Short name T494
Test name
Test status
Simulation time 498079006918 ps
CPU time 243.78 seconds
Started Jul 17 05:30:59 PM PDT 24
Finished Jul 17 05:35:03 PM PDT 24
Peak memory 250232 kb
Host smart-17220c7f-0ca1-4194-bbd4-322508ba91af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366084890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2366084890
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2818278147
Short name T432
Test name
Test status
Simulation time 370279334 ps
CPU time 3.13 seconds
Started Jul 17 05:30:57 PM PDT 24
Finished Jul 17 05:31:02 PM PDT 24
Peak memory 225484 kb
Host smart-8cfb7b31-63df-45bc-919b-e132e46dba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818278147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2818278147
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2398652118
Short name T1020
Test name
Test status
Simulation time 1147730373 ps
CPU time 14.97 seconds
Started Jul 17 05:33:50 PM PDT 24
Finished Jul 17 05:34:08 PM PDT 24
Peak memory 233760 kb
Host smart-4d5c39d9-0d72-4d6c-809b-ed5cfa956e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398652118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2398652118
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3486433323
Short name T457
Test name
Test status
Simulation time 4467981332 ps
CPU time 15.1 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:31:25 PM PDT 24
Peak memory 233692 kb
Host smart-56ca1de3-89bb-4080-825e-c837e45ad973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486433323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3486433323
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.201680638
Short name T468
Test name
Test status
Simulation time 6611299634 ps
CPU time 7.12 seconds
Started Jul 17 05:33:07 PM PDT 24
Finished Jul 17 05:33:15 PM PDT 24
Peak memory 225624 kb
Host smart-cb10de08-2a5f-44a8-833f-bceac8e1ea0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201680638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.201680638
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.240357046
Short name T308
Test name
Test status
Simulation time 572848065 ps
CPU time 4.81 seconds
Started Jul 17 05:33:07 PM PDT 24
Finished Jul 17 05:33:13 PM PDT 24
Peak memory 223464 kb
Host smart-da1dea31-0d02-47e2-b4b9-c8a5adf5e2ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=240357046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.240357046
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2622409775
Short name T980
Test name
Test status
Simulation time 9046919184 ps
CPU time 22.27 seconds
Started Jul 17 05:30:56 PM PDT 24
Finished Jul 17 05:31:20 PM PDT 24
Peak memory 217484 kb
Host smart-e9a2a0b1-a0da-45b1-ae68-696e3fc9a21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622409775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2622409775
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2669596760
Short name T730
Test name
Test status
Simulation time 1316879902 ps
CPU time 5.22 seconds
Started Jul 17 05:30:57 PM PDT 24
Finished Jul 17 05:31:03 PM PDT 24
Peak memory 217324 kb
Host smart-c0cf94a8-57ca-4c82-9547-8816ccd6983f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669596760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2669596760
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3421336542
Short name T888
Test name
Test status
Simulation time 143047413 ps
CPU time 1.83 seconds
Started Jul 17 05:30:54 PM PDT 24
Finished Jul 17 05:30:57 PM PDT 24
Peak memory 217332 kb
Host smart-e578286a-2c21-462f-b21d-dd04a2446640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421336542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3421336542
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3890369556
Short name T916
Test name
Test status
Simulation time 51818541 ps
CPU time 0.82 seconds
Started Jul 17 05:31:00 PM PDT 24
Finished Jul 17 05:31:01 PM PDT 24
Peak memory 206900 kb
Host smart-1c82f4b0-08bc-4b89-b968-aba8ac8e7503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890369556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3890369556
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.4009710467
Short name T981
Test name
Test status
Simulation time 624557096 ps
CPU time 12.29 seconds
Started Jul 17 05:30:57 PM PDT 24
Finished Jul 17 05:31:11 PM PDT 24
Peak memory 253312 kb
Host smart-7151240b-34d0-49bc-8cfe-cbf67a001502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009710467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.4009710467
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2907597074
Short name T24
Test name
Test status
Simulation time 35060381 ps
CPU time 0.73 seconds
Started Jul 17 05:30:55 PM PDT 24
Finished Jul 17 05:30:57 PM PDT 24
Peak memory 205764 kb
Host smart-4985b275-14ee-463b-be0c-47e4db2dd29a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907597074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2907597074
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.4167881793
Short name T647
Test name
Test status
Simulation time 273419513 ps
CPU time 3.12 seconds
Started Jul 17 05:34:04 PM PDT 24
Finished Jul 17 05:34:09 PM PDT 24
Peak memory 233716 kb
Host smart-07956224-9aff-49c5-b996-2e51f42f12bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167881793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4167881793
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1306908037
Short name T961
Test name
Test status
Simulation time 64363113 ps
CPU time 0.78 seconds
Started Jul 17 05:33:29 PM PDT 24
Finished Jul 17 05:33:30 PM PDT 24
Peak memory 207812 kb
Host smart-47b5f144-c16a-4899-9fa9-57f616ac644e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306908037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1306908037
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3072333024
Short name T222
Test name
Test status
Simulation time 7034342773 ps
CPU time 24.19 seconds
Started Jul 17 05:31:00 PM PDT 24
Finished Jul 17 05:31:25 PM PDT 24
Peak memory 250160 kb
Host smart-8978633a-a84c-4b58-87d4-d4b70a70c8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072333024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3072333024
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1761594959
Short name T43
Test name
Test status
Simulation time 13662948145 ps
CPU time 51.47 seconds
Started Jul 17 05:31:01 PM PDT 24
Finished Jul 17 05:31:53 PM PDT 24
Peak memory 250344 kb
Host smart-0d9de2f3-eb75-4ae6-8e39-f7ed4184d87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761594959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1761594959
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.279429727
Short name T912
Test name
Test status
Simulation time 3981123145 ps
CPU time 63.93 seconds
Started Jul 17 05:33:09 PM PDT 24
Finished Jul 17 05:34:14 PM PDT 24
Peak memory 242136 kb
Host smart-5757bc7c-2d2f-496e-81fe-4cec89b91b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279429727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.279429727
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2881242055
Short name T265
Test name
Test status
Simulation time 661014820 ps
CPU time 15.17 seconds
Started Jul 17 05:30:58 PM PDT 24
Finished Jul 17 05:31:14 PM PDT 24
Peak memory 233432 kb
Host smart-dbd58b5a-960c-4db4-9d6c-d3fc04b98838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881242055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2881242055
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3525060295
Short name T668
Test name
Test status
Simulation time 56978575256 ps
CPU time 66.02 seconds
Started Jul 17 05:30:57 PM PDT 24
Finished Jul 17 05:32:05 PM PDT 24
Peak memory 237708 kb
Host smart-025d0542-761c-42a3-aa9a-e4b9e53280c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525060295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3525060295
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2847288646
Short name T209
Test name
Test status
Simulation time 61312270 ps
CPU time 2.3 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:31:11 PM PDT 24
Peak memory 233764 kb
Host smart-13e7b7bd-36d4-47fc-b9e2-906f8deb0aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847288646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2847288646
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2735367481
Short name T97
Test name
Test status
Simulation time 19278056230 ps
CPU time 16.42 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:31:26 PM PDT 24
Peak memory 234956 kb
Host smart-4bd23979-ae50-4c2d-a350-53a493698f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735367481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2735367481
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3369739807
Short name T235
Test name
Test status
Simulation time 954931844 ps
CPU time 6.02 seconds
Started Jul 17 05:30:55 PM PDT 24
Finished Jul 17 05:31:02 PM PDT 24
Peak memory 233708 kb
Host smart-95f85715-5668-4df3-8446-ce83d3638111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369739807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3369739807
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2903407650
Short name T833
Test name
Test status
Simulation time 1608838655 ps
CPU time 6.35 seconds
Started Jul 17 05:34:12 PM PDT 24
Finished Jul 17 05:34:23 PM PDT 24
Peak memory 225552 kb
Host smart-264c2617-3508-49a8-9bce-1364b96deac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903407650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2903407650
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1234827556
Short name T760
Test name
Test status
Simulation time 1121623806 ps
CPU time 9.29 seconds
Started Jul 17 05:30:59 PM PDT 24
Finished Jul 17 05:31:09 PM PDT 24
Peak memory 223264 kb
Host smart-f5ecab84-b516-4dac-bbe7-81b968eddd47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1234827556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1234827556
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.186892824
Short name T693
Test name
Test status
Simulation time 9058483584 ps
CPU time 219.34 seconds
Started Jul 17 05:30:56 PM PDT 24
Finished Jul 17 05:34:37 PM PDT 24
Peak memory 287532 kb
Host smart-34945e76-384b-4eed-b1f1-2f0dd09c182e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186892824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.186892824
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2274329983
Short name T766
Test name
Test status
Simulation time 11777619 ps
CPU time 0.72 seconds
Started Jul 17 05:30:56 PM PDT 24
Finished Jul 17 05:30:59 PM PDT 24
Peak memory 206628 kb
Host smart-cfd005f3-00ed-49a0-82f1-45a281b9a58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274329983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2274329983
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2303390037
Short name T844
Test name
Test status
Simulation time 2659658603 ps
CPU time 7.04 seconds
Started Jul 17 05:31:01 PM PDT 24
Finished Jul 17 05:31:09 PM PDT 24
Peak memory 217480 kb
Host smart-a0dbb53a-fa72-4ace-92eb-ff149dbc05b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303390037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2303390037
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.499651446
Short name T706
Test name
Test status
Simulation time 181660939 ps
CPU time 1.17 seconds
Started Jul 17 05:30:56 PM PDT 24
Finished Jul 17 05:30:58 PM PDT 24
Peak memory 208964 kb
Host smart-d464b90f-e48d-41f4-a8e2-097775002f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499651446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.499651446
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4260730567
Short name T340
Test name
Test status
Simulation time 157834760 ps
CPU time 0.78 seconds
Started Jul 17 05:33:34 PM PDT 24
Finished Jul 17 05:33:36 PM PDT 24
Peak memory 206944 kb
Host smart-5e429858-9db4-49a8-b193-05a4cceccba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260730567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4260730567
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3303999635
Short name T156
Test name
Test status
Simulation time 216746140 ps
CPU time 4.9 seconds
Started Jul 17 05:34:12 PM PDT 24
Finished Jul 17 05:34:21 PM PDT 24
Peak memory 233788 kb
Host smart-c45d8bf0-b8b4-4d5c-ad71-7e0a2ad283d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303999635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3303999635
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.682178704
Short name T751
Test name
Test status
Simulation time 39783592 ps
CPU time 0.72 seconds
Started Jul 17 05:31:17 PM PDT 24
Finished Jul 17 05:31:19 PM PDT 24
Peak memory 205716 kb
Host smart-c96d84ce-a6ca-41c5-9308-85e1875555ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682178704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.682178704
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3848010523
Short name T576
Test name
Test status
Simulation time 242698769 ps
CPU time 2.2 seconds
Started Jul 17 05:31:09 PM PDT 24
Finished Jul 17 05:31:13 PM PDT 24
Peak memory 225508 kb
Host smart-403b5fa4-8b43-47e5-8670-7a0340a8417a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848010523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3848010523
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.94584687
Short name T793
Test name
Test status
Simulation time 15295962 ps
CPU time 0.76 seconds
Started Jul 17 05:30:58 PM PDT 24
Finished Jul 17 05:31:00 PM PDT 24
Peak memory 207492 kb
Host smart-cdcdf3f5-142a-4694-b48e-262d8d13bc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94584687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.94584687
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1652305390
Short name T506
Test name
Test status
Simulation time 14484871365 ps
CPU time 31.7 seconds
Started Jul 17 05:31:06 PM PDT 24
Finished Jul 17 05:31:39 PM PDT 24
Peak memory 242028 kb
Host smart-5a1ff338-d2f8-4c8b-bc0c-bb402148f7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652305390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1652305390
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2843523924
Short name T921
Test name
Test status
Simulation time 15165150515 ps
CPU time 31.37 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:31:41 PM PDT 24
Peak memory 240804 kb
Host smart-ff28cce3-f049-4ecb-b9d9-06949191321f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843523924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2843523924
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1389662188
Short name T901
Test name
Test status
Simulation time 163691837016 ps
CPU time 235.61 seconds
Started Jul 17 05:31:09 PM PDT 24
Finished Jul 17 05:35:07 PM PDT 24
Peak memory 250320 kb
Host smart-e83e71ec-7e25-482d-aaa8-1a85779b40c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389662188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1389662188
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3084816865
Short name T266
Test name
Test status
Simulation time 3895999563 ps
CPU time 23.6 seconds
Started Jul 17 05:31:06 PM PDT 24
Finished Jul 17 05:31:31 PM PDT 24
Peak memory 242056 kb
Host smart-7f37f203-ceb7-49b1-a63a-23ae8845ce1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084816865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3084816865
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1364824525
Short name T336
Test name
Test status
Simulation time 7913586326 ps
CPU time 16.58 seconds
Started Jul 17 05:31:18 PM PDT 24
Finished Jul 17 05:31:35 PM PDT 24
Peak memory 225628 kb
Host smart-96be8de4-4945-40ed-88be-e2f61d38c767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364824525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1364824525
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2434817166
Short name T875
Test name
Test status
Simulation time 385747174 ps
CPU time 7.56 seconds
Started Jul 17 05:33:08 PM PDT 24
Finished Jul 17 05:33:16 PM PDT 24
Peak memory 225544 kb
Host smart-614c669d-ddf3-414e-b9c1-3db8d2c74680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434817166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2434817166
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2906810757
Short name T719
Test name
Test status
Simulation time 9769438273 ps
CPU time 67.92 seconds
Started Jul 17 05:30:56 PM PDT 24
Finished Jul 17 05:32:06 PM PDT 24
Peak memory 233908 kb
Host smart-721f9dcc-0a62-447b-b9af-46d247824407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906810757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2906810757
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.246860945
Short name T63
Test name
Test status
Simulation time 7208112656 ps
CPU time 6.68 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:31:16 PM PDT 24
Peak memory 225544 kb
Host smart-17ea7aab-8be4-466a-8b46-983ee4c6a127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246860945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.246860945
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.996428943
Short name T430
Test name
Test status
Simulation time 483860888 ps
CPU time 6.26 seconds
Started Jul 17 05:30:58 PM PDT 24
Finished Jul 17 05:31:05 PM PDT 24
Peak memory 225560 kb
Host smart-7293294c-461b-4884-b90c-cf74036f9947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996428943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.996428943
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.999077160
Short name T904
Test name
Test status
Simulation time 601708757 ps
CPU time 4.49 seconds
Started Jul 17 05:31:09 PM PDT 24
Finished Jul 17 05:31:16 PM PDT 24
Peak memory 221172 kb
Host smart-cc86bfd2-5841-46ac-8ea9-5cefd99262ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=999077160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.999077160
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1575522477
Short name T26
Test name
Test status
Simulation time 3815805464 ps
CPU time 19.71 seconds
Started Jul 17 05:30:59 PM PDT 24
Finished Jul 17 05:31:20 PM PDT 24
Peak memory 217404 kb
Host smart-3a2faa99-8bfa-4fe7-955f-cee044cac25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575522477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1575522477
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3893923098
Short name T288
Test name
Test status
Simulation time 1815482208 ps
CPU time 5.56 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:34:11 PM PDT 24
Peak memory 217284 kb
Host smart-85dc6ef7-08a5-4869-b29a-c26cfeb04d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893923098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3893923098
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2872983137
Short name T309
Test name
Test status
Simulation time 26772128 ps
CPU time 1.32 seconds
Started Jul 17 05:30:56 PM PDT 24
Finished Jul 17 05:30:59 PM PDT 24
Peak memory 209180 kb
Host smart-420ddf80-998e-424e-bc2f-1cf08ed63e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872983137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2872983137
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2649995546
Short name T709
Test name
Test status
Simulation time 182511605 ps
CPU time 0.84 seconds
Started Jul 17 05:34:08 PM PDT 24
Finished Jul 17 05:34:11 PM PDT 24
Peak memory 206936 kb
Host smart-c4e0e687-434b-4342-ab0b-c82edc233c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649995546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2649995546
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2684324945
Short name T202
Test name
Test status
Simulation time 4927516812 ps
CPU time 12.28 seconds
Started Jul 17 05:30:55 PM PDT 24
Finished Jul 17 05:31:09 PM PDT 24
Peak memory 233844 kb
Host smart-da5b8843-2649-46db-90b9-63ebcf20c256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684324945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2684324945
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.753944406
Short name T988
Test name
Test status
Simulation time 16187460 ps
CPU time 0.75 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:31:11 PM PDT 24
Peak memory 206656 kb
Host smart-30274c4c-625a-4f1d-b311-5b28f3b1a7bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753944406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.753944406
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.170848675
Short name T940
Test name
Test status
Simulation time 2274679807 ps
CPU time 5.48 seconds
Started Jul 17 05:31:09 PM PDT 24
Finished Jul 17 05:31:16 PM PDT 24
Peak memory 233884 kb
Host smart-197f724b-5cdb-42de-b0bf-2f66ea717a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170848675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.170848675
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1898167977
Short name T394
Test name
Test status
Simulation time 191475873 ps
CPU time 0.77 seconds
Started Jul 17 05:31:09 PM PDT 24
Finished Jul 17 05:31:11 PM PDT 24
Peak memory 207440 kb
Host smart-c42ae7fc-68b1-4964-9191-b8a6fca1f1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898167977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1898167977
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1255548979
Short name T416
Test name
Test status
Simulation time 6570883420 ps
CPU time 81.93 seconds
Started Jul 17 05:33:10 PM PDT 24
Finished Jul 17 05:34:33 PM PDT 24
Peak memory 255972 kb
Host smart-5392e502-a2cf-44a2-b40e-a3d789727fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255548979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1255548979
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4164557366
Short name T274
Test name
Test status
Simulation time 2468860084 ps
CPU time 26.97 seconds
Started Jul 17 05:31:17 PM PDT 24
Finished Jul 17 05:31:45 PM PDT 24
Peak memory 242176 kb
Host smart-cd9d6dd4-6f4a-4e61-995b-e5d3f3f444b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164557366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4164557366
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2076115941
Short name T470
Test name
Test status
Simulation time 6447796651 ps
CPU time 101.25 seconds
Started Jul 17 05:31:07 PM PDT 24
Finished Jul 17 05:32:49 PM PDT 24
Peak memory 258544 kb
Host smart-0a89e456-1ac5-4fb7-b869-0d6524a5a340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076115941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2076115941
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.435611180
Short name T724
Test name
Test status
Simulation time 1088767321 ps
CPU time 20.76 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:31:31 PM PDT 24
Peak memory 225548 kb
Host smart-392bd211-0d5e-41da-82c9-7e6455aa1751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435611180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.435611180
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.754985958
Short name T812
Test name
Test status
Simulation time 17163774508 ps
CPU time 152.75 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:33:42 PM PDT 24
Peak memory 258480 kb
Host smart-e24593ee-3df1-48cc-b5f0-5010994146d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754985958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.754985958
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1474283029
Short name T625
Test name
Test status
Simulation time 23129925409 ps
CPU time 24.89 seconds
Started Jul 17 05:31:25 PM PDT 24
Finished Jul 17 05:31:52 PM PDT 24
Peak memory 233852 kb
Host smart-99497683-4efc-4fab-8757-d5a8c479432c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474283029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1474283029
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1369160086
Short name T882
Test name
Test status
Simulation time 28151587456 ps
CPU time 56.5 seconds
Started Jul 17 05:33:34 PM PDT 24
Finished Jul 17 05:34:31 PM PDT 24
Peak memory 251800 kb
Host smart-ed413229-3584-4601-9fdc-7ec60d1d5f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369160086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1369160086
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3312107550
Short name T783
Test name
Test status
Simulation time 18695919034 ps
CPU time 17.5 seconds
Started Jul 17 05:31:18 PM PDT 24
Finished Jul 17 05:31:36 PM PDT 24
Peak memory 233792 kb
Host smart-30bad63d-8832-4186-aa2c-71abfa537009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312107550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3312107550
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1430812783
Short name T810
Test name
Test status
Simulation time 5405066279 ps
CPU time 3.18 seconds
Started Jul 17 05:31:07 PM PDT 24
Finished Jul 17 05:31:11 PM PDT 24
Peak memory 225604 kb
Host smart-c66d1b3e-a527-42df-af3a-cf3e9670e71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430812783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1430812783
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2615558965
Short name T736
Test name
Test status
Simulation time 5581872694 ps
CPU time 11.81 seconds
Started Jul 17 05:31:07 PM PDT 24
Finished Jul 17 05:31:20 PM PDT 24
Peak memory 219900 kb
Host smart-62136a23-91c4-4e24-ab7a-364fbcb5cd3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2615558965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2615558965
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4093433344
Short name T763
Test name
Test status
Simulation time 16425541249 ps
CPU time 162.18 seconds
Started Jul 17 05:31:09 PM PDT 24
Finished Jul 17 05:33:53 PM PDT 24
Peak memory 250380 kb
Host smart-9bc33d9d-a21e-42e9-91db-0789a8f191b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093433344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4093433344
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.645947266
Short name T467
Test name
Test status
Simulation time 54546957982 ps
CPU time 10.63 seconds
Started Jul 17 05:31:07 PM PDT 24
Finished Jul 17 05:31:18 PM PDT 24
Peak memory 217496 kb
Host smart-c5d84f19-1f61-41cc-8db8-a1f37aaa598d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645947266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.645947266
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3966756873
Short name T989
Test name
Test status
Simulation time 304480663 ps
CPU time 1.87 seconds
Started Jul 17 05:31:10 PM PDT 24
Finished Jul 17 05:31:14 PM PDT 24
Peak memory 217396 kb
Host smart-d30b1fb7-4041-4f02-8685-f3d8fe80a753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966756873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3966756873
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4071982842
Short name T289
Test name
Test status
Simulation time 101057558 ps
CPU time 0.83 seconds
Started Jul 17 05:31:09 PM PDT 24
Finished Jul 17 05:31:12 PM PDT 24
Peak memory 206992 kb
Host smart-2c994063-ad78-4cb3-b7b2-0581805fcfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071982842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4071982842
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2594289888
Short name T583
Test name
Test status
Simulation time 418194871 ps
CPU time 4.67 seconds
Started Jul 17 05:31:19 PM PDT 24
Finished Jul 17 05:31:24 PM PDT 24
Peak memory 233696 kb
Host smart-4b7293b9-fa75-4edc-a18e-f6243197adcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594289888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2594289888
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2325560811
Short name T318
Test name
Test status
Simulation time 22842853 ps
CPU time 0.75 seconds
Started Jul 17 05:34:13 PM PDT 24
Finished Jul 17 05:34:17 PM PDT 24
Peak memory 206328 kb
Host smart-3cd5e75c-5192-4ede-b75d-cdd59f063579
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325560811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2325560811
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.680299261
Short name T938
Test name
Test status
Simulation time 5730408568 ps
CPU time 14.19 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:31:23 PM PDT 24
Peak memory 225692 kb
Host smart-179b551c-b450-4a2a-b702-df798a33bd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680299261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.680299261
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1759115183
Short name T737
Test name
Test status
Simulation time 59244845 ps
CPU time 0.75 seconds
Started Jul 17 05:31:25 PM PDT 24
Finished Jul 17 05:31:28 PM PDT 24
Peak memory 207444 kb
Host smart-dabbfc97-d9c0-451c-a1a4-0328eb86a8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759115183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1759115183
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4000783435
Short name T213
Test name
Test status
Simulation time 1665129713 ps
CPU time 30.05 seconds
Started Jul 17 05:31:17 PM PDT 24
Finished Jul 17 05:31:48 PM PDT 24
Peak memory 253772 kb
Host smart-1543d406-1cc2-4e34-b7ef-df7b2e05eb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000783435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4000783435
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3914145104
Short name T939
Test name
Test status
Simulation time 203988083725 ps
CPU time 314.37 seconds
Started Jul 17 05:33:54 PM PDT 24
Finished Jul 17 05:39:12 PM PDT 24
Peak memory 258568 kb
Host smart-c8e6ebef-b11e-42f8-86c3-c7cee9fca285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914145104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3914145104
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1976675794
Short name T835
Test name
Test status
Simulation time 600171142803 ps
CPU time 336.77 seconds
Started Jul 17 05:31:25 PM PDT 24
Finished Jul 17 05:37:03 PM PDT 24
Peak memory 253892 kb
Host smart-9445331c-da4c-4c06-8429-f985b15e0a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976675794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1976675794
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.874462159
Short name T142
Test name
Test status
Simulation time 271324513 ps
CPU time 3.11 seconds
Started Jul 17 05:31:09 PM PDT 24
Finished Jul 17 05:31:14 PM PDT 24
Peak memory 225572 kb
Host smart-84f569b5-f699-4d3c-8d91-1ea1bb3f4077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874462159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.874462159
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1487727077
Short name T287
Test name
Test status
Simulation time 65788332 ps
CPU time 0.78 seconds
Started Jul 17 05:31:05 PM PDT 24
Finished Jul 17 05:31:07 PM PDT 24
Peak memory 216820 kb
Host smart-1c8a41c1-02a5-4663-8bfb-c6f86ab131eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487727077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1487727077
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3898937590
Short name T355
Test name
Test status
Simulation time 46706085 ps
CPU time 2.4 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:31:11 PM PDT 24
Peak memory 233760 kb
Host smart-f07fe151-d683-476a-957b-5d42dc9c1102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898937590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3898937590
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2919774220
Short name T903
Test name
Test status
Simulation time 2198193593 ps
CPU time 17.64 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:31:27 PM PDT 24
Peak memory 238980 kb
Host smart-24085461-6caf-4232-bf82-816879d05527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919774220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2919774220
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.897676995
Short name T644
Test name
Test status
Simulation time 1332914825 ps
CPU time 7.28 seconds
Started Jul 17 05:31:08 PM PDT 24
Finished Jul 17 05:31:17 PM PDT 24
Peak memory 249736 kb
Host smart-1530136b-f4c7-4307-8bd4-6cb80c9bbe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897676995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.897676995
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.152137293
Short name T565
Test name
Test status
Simulation time 1574507274 ps
CPU time 3.58 seconds
Started Jul 17 05:31:10 PM PDT 24
Finished Jul 17 05:31:15 PM PDT 24
Peak memory 233764 kb
Host smart-85038228-a841-499b-bdbf-3e7a16562033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152137293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.152137293
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1831248330
Short name T785
Test name
Test status
Simulation time 298934841 ps
CPU time 3.98 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 05:31:27 PM PDT 24
Peak memory 224068 kb
Host smart-9a0e71d9-81d4-4272-aa0e-085a9f071880
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1831248330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1831248330
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2566591660
Short name T139
Test name
Test status
Simulation time 23472518071 ps
CPU time 187.9 seconds
Started Jul 17 05:31:20 PM PDT 24
Finished Jul 17 05:34:29 PM PDT 24
Peak memory 274516 kb
Host smart-46672c5d-2a7a-4862-aac0-64b7373fbfe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566591660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2566591660
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.940584041
Short name T602
Test name
Test status
Simulation time 835361573 ps
CPU time 10.41 seconds
Started Jul 17 05:31:09 PM PDT 24
Finished Jul 17 05:31:22 PM PDT 24
Peak memory 217352 kb
Host smart-cb2d7b81-5815-4495-aa2c-d148b734d1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940584041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.940584041
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.784768944
Short name T816
Test name
Test status
Simulation time 758859660 ps
CPU time 1.96 seconds
Started Jul 17 05:31:18 PM PDT 24
Finished Jul 17 05:31:21 PM PDT 24
Peak memory 208848 kb
Host smart-7d8d5016-2e7b-46b5-824e-6cce9416bc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784768944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.784768944
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1883845220
Short name T611
Test name
Test status
Simulation time 154989116 ps
CPU time 1.92 seconds
Started Jul 17 05:31:18 PM PDT 24
Finished Jul 17 05:31:21 PM PDT 24
Peak memory 217228 kb
Host smart-1c0e4632-c396-4717-96a1-401beeea7c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883845220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1883845220
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.639678438
Short name T657
Test name
Test status
Simulation time 440135048 ps
CPU time 1.1 seconds
Started Jul 17 05:34:03 PM PDT 24
Finished Jul 17 05:34:05 PM PDT 24
Peak memory 207992 kb
Host smart-80814619-8433-4d8e-890e-c941e0bfbf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639678438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.639678438
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1205775471
Short name T670
Test name
Test status
Simulation time 6426975830 ps
CPU time 18.75 seconds
Started Jul 17 05:31:09 PM PDT 24
Finished Jul 17 05:31:29 PM PDT 24
Peak memory 225672 kb
Host smart-b43f8fa5-8f94-4d44-8183-eebd5f722885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205775471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1205775471
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2128170209
Short name T711
Test name
Test status
Simulation time 12284125 ps
CPU time 0.74 seconds
Started Jul 17 05:31:20 PM PDT 24
Finished Jul 17 05:31:22 PM PDT 24
Peak memory 206312 kb
Host smart-87eb33a4-2f5c-4292-a3ea-9af8e9583dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128170209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2128170209
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4262951471
Short name T851
Test name
Test status
Simulation time 93068873 ps
CPU time 3.11 seconds
Started Jul 17 05:31:25 PM PDT 24
Finished Jul 17 05:31:30 PM PDT 24
Peak memory 233672 kb
Host smart-f91640a2-48e1-4442-87da-2fd5b7f285fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262951471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4262951471
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1995080964
Short name T639
Test name
Test status
Simulation time 20306534 ps
CPU time 0.74 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 05:31:23 PM PDT 24
Peak memory 206452 kb
Host smart-332d3187-2e4d-4cef-b3be-b7f907527421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995080964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1995080964
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2428954404
Short name T359
Test name
Test status
Simulation time 3227771550 ps
CPU time 10.93 seconds
Started Jul 17 05:31:23 PM PDT 24
Finished Jul 17 05:31:35 PM PDT 24
Peak memory 225732 kb
Host smart-5bbd8d33-93d9-4cb2-9a83-e9c33819ec00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428954404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2428954404
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3029717157
Short name T508
Test name
Test status
Simulation time 23186576963 ps
CPU time 69.7 seconds
Started Jul 17 05:31:47 PM PDT 24
Finished Jul 17 05:32:58 PM PDT 24
Peak memory 253152 kb
Host smart-53d9fb9b-d736-469d-87af-fa444bcd64a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029717157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3029717157
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.782230537
Short name T740
Test name
Test status
Simulation time 23917225713 ps
CPU time 68.15 seconds
Started Jul 17 05:31:17 PM PDT 24
Finished Jul 17 05:32:27 PM PDT 24
Peak memory 250352 kb
Host smart-4e6e8a43-403e-4f6e-885e-b38c5cf7a922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782230537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.782230537
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.68850884
Short name T351
Test name
Test status
Simulation time 957928495 ps
CPU time 6.18 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 05:31:29 PM PDT 24
Peak memory 241964 kb
Host smart-8e478d05-840d-4002-b911-04b78c51ff8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68850884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.68850884
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1654731407
Short name T660
Test name
Test status
Simulation time 89366930412 ps
CPU time 155.92 seconds
Started Jul 17 05:31:16 PM PDT 24
Finished Jul 17 05:33:53 PM PDT 24
Peak memory 270660 kb
Host smart-694c50bc-fd0b-4215-baed-e5fa5ad29ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654731407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1654731407
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3640549876
Short name T226
Test name
Test status
Simulation time 515917309 ps
CPU time 3.44 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 05:31:26 PM PDT 24
Peak memory 233780 kb
Host smart-23e46e9c-a0dc-44da-ad82-6d0ff7fa3a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640549876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3640549876
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.328229835
Short name T531
Test name
Test status
Simulation time 7897202004 ps
CPU time 83.63 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 05:32:46 PM PDT 24
Peak memory 241972 kb
Host smart-38ff34cc-2618-48d7-9277-fe24975eb2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328229835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.328229835
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.462601509
Short name T463
Test name
Test status
Simulation time 2283239121 ps
CPU time 11.86 seconds
Started Jul 17 05:31:27 PM PDT 24
Finished Jul 17 05:31:40 PM PDT 24
Peak memory 234872 kb
Host smart-67e291ef-243b-4e3c-bb55-8096e4b15d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462601509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.462601509
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3829096902
Short name T638
Test name
Test status
Simulation time 174532889 ps
CPU time 3.55 seconds
Started Jul 17 05:31:20 PM PDT 24
Finished Jul 17 05:31:24 PM PDT 24
Peak memory 225536 kb
Host smart-3b2ff1d6-7292-4e75-a4c4-7af329950ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829096902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3829096902
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1713164774
Short name T323
Test name
Test status
Simulation time 2043825298 ps
CPU time 14.62 seconds
Started Jul 17 05:34:10 PM PDT 24
Finished Jul 17 05:34:29 PM PDT 24
Peak memory 223252 kb
Host smart-66ab2a1e-b0d9-4e34-9f63-4084260bcb1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1713164774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1713164774
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2610717990
Short name T11
Test name
Test status
Simulation time 3453464652 ps
CPU time 34.15 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 05:31:56 PM PDT 24
Peak memory 217504 kb
Host smart-04615bbc-1c51-46f3-a7f8-75e02fbb33f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610717990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2610717990
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.526434189
Short name T335
Test name
Test status
Simulation time 183529675 ps
CPU time 1.14 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 05:31:23 PM PDT 24
Peak memory 208036 kb
Host smart-03e5ee41-b93f-4f2a-8957-17ed539055ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526434189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.526434189
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3157945833
Short name T452
Test name
Test status
Simulation time 75615848 ps
CPU time 0.87 seconds
Started Jul 17 05:33:11 PM PDT 24
Finished Jul 17 05:33:13 PM PDT 24
Peak memory 207980 kb
Host smart-17f33665-5187-48a3-8f17-51ab85c3a952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157945833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3157945833
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.180642162
Short name T943
Test name
Test status
Simulation time 73247831 ps
CPU time 0.91 seconds
Started Jul 17 05:31:19 PM PDT 24
Finished Jul 17 05:31:21 PM PDT 24
Peak memory 206944 kb
Host smart-298255fd-2a00-4cd7-94f0-97997243e9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180642162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.180642162
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1907190820
Short name T462
Test name
Test status
Simulation time 14965315286 ps
CPU time 13.88 seconds
Started Jul 17 05:34:07 PM PDT 24
Finished Jul 17 05:34:22 PM PDT 24
Peak memory 233916 kb
Host smart-cf1db7cc-6b11-4014-818f-a051260c22cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907190820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1907190820
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1043285951
Short name T652
Test name
Test status
Simulation time 36992581 ps
CPU time 0.71 seconds
Started Jul 17 05:33:54 PM PDT 24
Finished Jul 17 05:33:59 PM PDT 24
Peak memory 206356 kb
Host smart-1ff5c2ba-0efa-462b-9257-91092887d782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043285951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1043285951
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2068687336
Short name T7
Test name
Test status
Simulation time 220860709 ps
CPU time 2.46 seconds
Started Jul 17 05:34:12 PM PDT 24
Finished Jul 17 05:34:18 PM PDT 24
Peak memory 225492 kb
Host smart-f479dee5-8ad1-4257-a5c5-adda83664f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068687336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2068687336
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3771675168
Short name T728
Test name
Test status
Simulation time 22930629 ps
CPU time 0.75 seconds
Started Jul 17 05:31:19 PM PDT 24
Finished Jul 17 05:31:21 PM PDT 24
Peak memory 207516 kb
Host smart-233838ee-d430-44ac-8c2a-3dea7865bb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771675168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3771675168
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2298839273
Short name T405
Test name
Test status
Simulation time 5822649304 ps
CPU time 80.08 seconds
Started Jul 17 05:31:22 PM PDT 24
Finished Jul 17 05:32:43 PM PDT 24
Peak memory 269532 kb
Host smart-3af691ed-e22e-49bd-b55d-add15cd41724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298839273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2298839273
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2845985089
Short name T264
Test name
Test status
Simulation time 145770467647 ps
CPU time 284.62 seconds
Started Jul 17 05:31:25 PM PDT 24
Finished Jul 17 05:36:11 PM PDT 24
Peak memory 252580 kb
Host smart-b0664505-4f41-4d19-bc00-6461beda1b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845985089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2845985089
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.91929989
Short name T944
Test name
Test status
Simulation time 10051757670 ps
CPU time 69.5 seconds
Started Jul 17 05:34:11 PM PDT 24
Finished Jul 17 05:35:24 PM PDT 24
Peak memory 250476 kb
Host smart-82c93f85-bc29-471c-b360-920321e68dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91929989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.91929989
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3060696496
Short name T545
Test name
Test status
Simulation time 380056577 ps
CPU time 4.34 seconds
Started Jul 17 05:31:20 PM PDT 24
Finished Jul 17 05:31:25 PM PDT 24
Peak memory 225580 kb
Host smart-179efb9b-e03c-4333-bcf0-3a378c15524b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060696496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3060696496
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2921759121
Short name T241
Test name
Test status
Simulation time 184982601211 ps
CPU time 317.27 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 05:36:39 PM PDT 24
Peak memory 253248 kb
Host smart-aee95afd-c99c-4653-843f-4e9117f536be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921759121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2921759121
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.786143194
Short name T978
Test name
Test status
Simulation time 616254654 ps
CPU time 9.22 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 05:31:32 PM PDT 24
Peak memory 233692 kb
Host smart-33ff46df-d1cf-49e8-b72f-07494a55afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786143194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.786143194
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1455733674
Short name T406
Test name
Test status
Simulation time 901897058 ps
CPU time 9.76 seconds
Started Jul 17 05:34:12 PM PDT 24
Finished Jul 17 05:34:26 PM PDT 24
Peak memory 233816 kb
Host smart-56985abf-3136-452a-a960-bd95abb05f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455733674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1455733674
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.4166865515
Short name T685
Test name
Test status
Simulation time 3320839940 ps
CPU time 5.98 seconds
Started Jul 17 05:34:10 PM PDT 24
Finished Jul 17 05:34:19 PM PDT 24
Peak memory 236276 kb
Host smart-4c271846-6347-4d0d-bf0b-8e95560385cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166865515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.4166865515
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3697540190
Short name T627
Test name
Test status
Simulation time 26967257476 ps
CPU time 19.94 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 05:31:43 PM PDT 24
Peak memory 241680 kb
Host smart-5d61c748-d18e-45d6-95f6-88627a64d0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697540190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3697540190
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1460595071
Short name T285
Test name
Test status
Simulation time 2697732226 ps
CPU time 8.25 seconds
Started Jul 17 05:31:25 PM PDT 24
Finished Jul 17 05:31:34 PM PDT 24
Peak memory 222140 kb
Host smart-73228213-75f7-498d-b2fc-154fa4774a11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1460595071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1460595071
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3051917286
Short name T821
Test name
Test status
Simulation time 2923803439 ps
CPU time 18.82 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 05:31:42 PM PDT 24
Peak memory 221420 kb
Host smart-c8f4b1ce-f9dc-454b-83af-d973538afd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051917286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3051917286
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2278490692
Short name T89
Test name
Test status
Simulation time 248340790 ps
CPU time 1.96 seconds
Started Jul 17 05:31:25 PM PDT 24
Finished Jul 17 05:31:28 PM PDT 24
Peak memory 216228 kb
Host smart-f0b8824c-d9ed-4d13-ac25-08043b2bbbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278490692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2278490692
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.161642692
Short name T408
Test name
Test status
Simulation time 67106123 ps
CPU time 1.32 seconds
Started Jul 17 05:31:20 PM PDT 24
Finished Jul 17 05:31:23 PM PDT 24
Peak memory 217348 kb
Host smart-1f4587e3-4c8a-477f-a404-b0546f77f596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161642692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.161642692
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2014234844
Short name T472
Test name
Test status
Simulation time 30823231 ps
CPU time 0.76 seconds
Started Jul 17 05:31:48 PM PDT 24
Finished Jul 17 05:31:49 PM PDT 24
Peak memory 206928 kb
Host smart-c2626159-6dfd-4050-9335-abe03cb5f927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014234844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2014234844
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2309152959
Short name T772
Test name
Test status
Simulation time 2497543450 ps
CPU time 8.32 seconds
Started Jul 17 05:31:21 PM PDT 24
Finished Jul 17 05:31:31 PM PDT 24
Peak memory 225640 kb
Host smart-afd38da9-0807-476e-9c89-773f84be5617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309152959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2309152959
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2450631260
Short name T304
Test name
Test status
Simulation time 14563202 ps
CPU time 0.76 seconds
Started Jul 17 05:28:50 PM PDT 24
Finished Jul 17 05:28:51 PM PDT 24
Peak memory 206656 kb
Host smart-c50fda5a-716d-4668-824b-54d2e649cb6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450631260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
450631260
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.771199014
Short name T371
Test name
Test status
Simulation time 336017104 ps
CPU time 5.04 seconds
Started Jul 17 05:32:44 PM PDT 24
Finished Jul 17 05:32:50 PM PDT 24
Peak memory 233688 kb
Host smart-65b3154b-f335-4627-8989-adca5a528192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771199014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.771199014
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.224539854
Short name T533
Test name
Test status
Simulation time 58307706 ps
CPU time 0.77 seconds
Started Jul 17 05:27:44 PM PDT 24
Finished Jul 17 05:27:46 PM PDT 24
Peak memory 206484 kb
Host smart-4cd0b5c0-c511-4474-b24a-e4249a66a692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224539854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.224539854
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3602885283
Short name T867
Test name
Test status
Simulation time 24115449797 ps
CPU time 79.79 seconds
Started Jul 17 05:32:43 PM PDT 24
Finished Jul 17 05:34:03 PM PDT 24
Peak memory 265776 kb
Host smart-94531a60-facf-453d-bd11-a46a744e177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602885283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3602885283
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1529123526
Short name T171
Test name
Test status
Simulation time 6429704375 ps
CPU time 39.02 seconds
Started Jul 17 05:27:39 PM PDT 24
Finished Jul 17 05:28:19 PM PDT 24
Peak memory 250704 kb
Host smart-378d9073-086d-497d-bb40-8d364f884665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529123526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1529123526
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4137570197
Short name T261
Test name
Test status
Simulation time 39240736796 ps
CPU time 288.28 seconds
Started Jul 17 05:29:57 PM PDT 24
Finished Jul 17 05:34:46 PM PDT 24
Peak memory 254332 kb
Host smart-80fb6248-33f7-4a37-8db5-ad13f596224e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137570197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4137570197
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2012467937
Short name T849
Test name
Test status
Simulation time 321074759 ps
CPU time 5.83 seconds
Started Jul 17 05:29:58 PM PDT 24
Finished Jul 17 05:30:05 PM PDT 24
Peak memory 241888 kb
Host smart-469ebe5b-e1a2-4599-a022-e0d2297b0354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012467937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2012467937
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.878758871
Short name T986
Test name
Test status
Simulation time 79022025808 ps
CPU time 226.52 seconds
Started Jul 17 05:27:46 PM PDT 24
Finished Jul 17 05:31:35 PM PDT 24
Peak memory 257004 kb
Host smart-14ff02d3-de66-4b44-8956-f7442a9d5a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878758871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
878758871
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1026625764
Short name T286
Test name
Test status
Simulation time 47098651 ps
CPU time 2.54 seconds
Started Jul 17 05:27:45 PM PDT 24
Finished Jul 17 05:27:50 PM PDT 24
Peak memory 233480 kb
Host smart-98297028-e302-4b05-8199-8e1529a5c135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026625764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1026625764
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.988161902
Short name T1019
Test name
Test status
Simulation time 820103871 ps
CPU time 6.39 seconds
Started Jul 17 05:29:31 PM PDT 24
Finished Jul 17 05:29:38 PM PDT 24
Peak memory 233816 kb
Host smart-09ea1bb1-f085-4753-a5c6-68c15df65a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988161902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.988161902
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3360290429
Short name T330
Test name
Test status
Simulation time 44269607 ps
CPU time 1.12 seconds
Started Jul 17 05:27:45 PM PDT 24
Finished Jul 17 05:27:48 PM PDT 24
Peak memory 216248 kb
Host smart-99fa3a8c-9843-44be-8dff-8e5e8453c183
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360290429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3360290429
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2264760097
Short name T945
Test name
Test status
Simulation time 75029372 ps
CPU time 2.28 seconds
Started Jul 17 05:30:27 PM PDT 24
Finished Jul 17 05:30:30 PM PDT 24
Peak memory 225456 kb
Host smart-9a5f5c8b-b136-4af7-9faa-b79403d378a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264760097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2264760097
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3036919043
Short name T459
Test name
Test status
Simulation time 9785300068 ps
CPU time 15.24 seconds
Started Jul 17 05:30:27 PM PDT 24
Finished Jul 17 05:30:43 PM PDT 24
Peak memory 225732 kb
Host smart-dc40de99-7879-4c5d-9dba-b2ae0f217455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036919043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3036919043
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3539951465
Short name T129
Test name
Test status
Simulation time 1345437118 ps
CPU time 11.43 seconds
Started Jul 17 05:30:10 PM PDT 24
Finished Jul 17 05:30:22 PM PDT 24
Peak memory 220336 kb
Host smart-7357d856-3cfc-405b-90d6-06dc2ee7a5d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3539951465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3539951465
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2878052117
Short name T1017
Test name
Test status
Simulation time 32053095044 ps
CPU time 321.5 seconds
Started Jul 17 05:29:56 PM PDT 24
Finished Jul 17 05:35:19 PM PDT 24
Peak memory 282164 kb
Host smart-b9cbd4a5-ad14-49c6-99d1-72e88ac28545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878052117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2878052117
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.95432599
Short name T277
Test name
Test status
Simulation time 18162851000 ps
CPU time 32.27 seconds
Started Jul 17 05:27:48 PM PDT 24
Finished Jul 17 05:28:22 PM PDT 24
Peak memory 217512 kb
Host smart-a06e9b63-f7d5-4572-8ed8-d0761f7eb0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95432599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.95432599
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1949108917
Short name T1011
Test name
Test status
Simulation time 789846263 ps
CPU time 2.56 seconds
Started Jul 17 05:27:47 PM PDT 24
Finished Jul 17 05:27:53 PM PDT 24
Peak memory 217312 kb
Host smart-7739820f-deca-445b-b844-15586be7c2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949108917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1949108917
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3316876977
Short name T732
Test name
Test status
Simulation time 327472067 ps
CPU time 1.16 seconds
Started Jul 17 05:28:36 PM PDT 24
Finished Jul 17 05:28:37 PM PDT 24
Peak memory 207924 kb
Host smart-53996f4f-b2c3-417f-bd9b-88e5ca82a59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316876977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3316876977
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3501178205
Short name T441
Test name
Test status
Simulation time 39005343 ps
CPU time 0.84 seconds
Started Jul 17 05:30:24 PM PDT 24
Finished Jul 17 05:30:26 PM PDT 24
Peak memory 207136 kb
Host smart-9f143547-fcce-46d3-bab5-ce546b04ff26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501178205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3501178205
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3554223869
Short name T527
Test name
Test status
Simulation time 1045395371 ps
CPU time 9.7 seconds
Started Jul 17 05:30:10 PM PDT 24
Finished Jul 17 05:30:20 PM PDT 24
Peak memory 233936 kb
Host smart-d4558477-54bf-41f9-a8cd-594e03011aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554223869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3554223869
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1446353193
Short name T856
Test name
Test status
Simulation time 44476528 ps
CPU time 0.72 seconds
Started Jul 17 05:30:43 PM PDT 24
Finished Jul 17 05:30:45 PM PDT 24
Peak memory 206008 kb
Host smart-d5e97b89-15c8-4927-a87e-3d3e89020634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446353193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
446353193
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3621762163
Short name T585
Test name
Test status
Simulation time 45001737 ps
CPU time 2.88 seconds
Started Jul 17 05:29:44 PM PDT 24
Finished Jul 17 05:29:48 PM PDT 24
Peak memory 233780 kb
Host smart-89824a63-7779-4d18-a564-77d0a826823a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621762163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3621762163
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3820768688
Short name T873
Test name
Test status
Simulation time 50194187 ps
CPU time 0.78 seconds
Started Jul 17 05:28:05 PM PDT 24
Finished Jul 17 05:28:09 PM PDT 24
Peak memory 207464 kb
Host smart-5f1c9d5b-fea4-41ea-8e93-6cb750f991ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820768688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3820768688
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3894117919
Short name T622
Test name
Test status
Simulation time 1092994774 ps
CPU time 19.29 seconds
Started Jul 17 05:32:50 PM PDT 24
Finished Jul 17 05:33:10 PM PDT 24
Peak memory 251608 kb
Host smart-5e7900b2-b5a9-4faf-ae7e-da107e499f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894117919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3894117919
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3263560249
Short name T32
Test name
Test status
Simulation time 26810415543 ps
CPU time 230.6 seconds
Started Jul 17 05:33:39 PM PDT 24
Finished Jul 17 05:37:31 PM PDT 24
Peak memory 253656 kb
Host smart-5f9bac5f-040d-430f-afd3-b6ce847fa2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263560249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3263560249
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2275097040
Short name T899
Test name
Test status
Simulation time 32179065031 ps
CPU time 107.09 seconds
Started Jul 17 05:32:50 PM PDT 24
Finished Jul 17 05:34:38 PM PDT 24
Peak memory 225752 kb
Host smart-fb00b525-bef3-413c-bb88-2ba9335f509d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275097040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2275097040
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.557891663
Short name T281
Test name
Test status
Simulation time 184890284 ps
CPU time 3.2 seconds
Started Jul 17 05:29:44 PM PDT 24
Finished Jul 17 05:29:48 PM PDT 24
Peak memory 225560 kb
Host smart-ac2d49f4-4ccd-4162-9242-5bf1064648c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557891663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.557891663
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3696999559
Short name T375
Test name
Test status
Simulation time 4731150131 ps
CPU time 46.62 seconds
Started Jul 17 05:29:49 PM PDT 24
Finished Jul 17 05:30:37 PM PDT 24
Peak memory 250236 kb
Host smart-57f60319-9e7c-42bf-8514-c5c64d6642d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696999559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3696999559
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3486991050
Short name T554
Test name
Test status
Simulation time 9261475551 ps
CPU time 21.19 seconds
Started Jul 17 05:31:59 PM PDT 24
Finished Jul 17 05:32:21 PM PDT 24
Peak memory 233868 kb
Host smart-0e8a62a2-68a1-47fe-aae2-0a3d3b6efeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486991050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3486991050
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1769128505
Short name T931
Test name
Test status
Simulation time 2111456069 ps
CPU time 11.07 seconds
Started Jul 17 05:29:53 PM PDT 24
Finished Jul 17 05:30:05 PM PDT 24
Peak memory 225512 kb
Host smart-0870d794-5eec-465a-a086-685f16845efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769128505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1769128505
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1414708883
Short name T516
Test name
Test status
Simulation time 33651591 ps
CPU time 1.1 seconds
Started Jul 17 05:28:50 PM PDT 24
Finished Jul 17 05:28:52 PM PDT 24
Peak memory 217588 kb
Host smart-1b2062f9-3d12-4da8-8291-e96d383d60f1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414708883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1414708883
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.875135951
Short name T744
Test name
Test status
Simulation time 106765027 ps
CPU time 2.37 seconds
Started Jul 17 05:30:13 PM PDT 24
Finished Jul 17 05:30:17 PM PDT 24
Peak memory 224160 kb
Host smart-d3aa2859-6e2c-4250-90f5-e7403a1887c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875135951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
875135951
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3173145966
Short name T969
Test name
Test status
Simulation time 5046032971 ps
CPU time 12.46 seconds
Started Jul 17 05:32:07 PM PDT 24
Finished Jul 17 05:32:21 PM PDT 24
Peak memory 225632 kb
Host smart-1f55843f-4116-48ef-b27f-1dc86e214f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173145966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3173145966
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2857599002
Short name T582
Test name
Test status
Simulation time 1387475607 ps
CPU time 3.86 seconds
Started Jul 17 05:27:52 PM PDT 24
Finished Jul 17 05:27:57 PM PDT 24
Peak memory 223224 kb
Host smart-d3332719-8d48-4c9f-8472-b000b0f76b9f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2857599002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2857599002
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1214672658
Short name T153
Test name
Test status
Simulation time 12364032580 ps
CPU time 124.95 seconds
Started Jul 17 05:33:05 PM PDT 24
Finished Jul 17 05:35:11 PM PDT 24
Peak memory 256884 kb
Host smart-da3777e0-4577-475c-9513-cee186d34024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214672658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1214672658
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.154152580
Short name T753
Test name
Test status
Simulation time 12391035640 ps
CPU time 21.28 seconds
Started Jul 17 05:27:55 PM PDT 24
Finished Jul 17 05:28:17 PM PDT 24
Peak memory 217556 kb
Host smart-aed1869d-d37e-48b7-b524-e58691d1ccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154152580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.154152580
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3073632309
Short name T362
Test name
Test status
Simulation time 4287727592 ps
CPU time 13.47 seconds
Started Jul 17 05:27:56 PM PDT 24
Finished Jul 17 05:28:11 PM PDT 24
Peak memory 217452 kb
Host smart-c39d5db6-01ba-446e-8ac6-8c4584d5a60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073632309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3073632309
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2119850259
Short name T895
Test name
Test status
Simulation time 116694286 ps
CPU time 1.45 seconds
Started Jul 17 05:29:07 PM PDT 24
Finished Jul 17 05:29:09 PM PDT 24
Peak memory 217300 kb
Host smart-bff6fa88-df41-4926-be04-e814e19e0d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119850259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2119850259
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.4122525611
Short name T779
Test name
Test status
Simulation time 179436395 ps
CPU time 0.93 seconds
Started Jul 17 05:27:55 PM PDT 24
Finished Jul 17 05:27:57 PM PDT 24
Peak memory 207156 kb
Host smart-fb041d26-4d04-43c4-9f72-af7a5e563d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122525611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.4122525611
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.199686544
Short name T422
Test name
Test status
Simulation time 1707193283 ps
CPU time 8.79 seconds
Started Jul 17 05:29:53 PM PDT 24
Finished Jul 17 05:30:03 PM PDT 24
Peak memory 233712 kb
Host smart-2a49b9d2-bff8-41bb-a24b-e2ac32ed73cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199686544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.199686544
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.83675479
Short name T301
Test name
Test status
Simulation time 53181048 ps
CPU time 0.74 seconds
Started Jul 17 05:29:00 PM PDT 24
Finished Jul 17 05:29:02 PM PDT 24
Peak memory 205716 kb
Host smart-31634a18-d7ff-4e58-85cc-dcbd4d58d0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83675479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.83675479
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2879986230
Short name T731
Test name
Test status
Simulation time 245174390 ps
CPU time 2.48 seconds
Started Jul 17 05:32:48 PM PDT 24
Finished Jul 17 05:32:52 PM PDT 24
Peak memory 225504 kb
Host smart-4b61136c-abed-4f23-85ca-ac94e1f7cd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879986230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2879986230
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.836073409
Short name T380
Test name
Test status
Simulation time 94069692 ps
CPU time 0.84 seconds
Started Jul 17 05:30:29 PM PDT 24
Finished Jul 17 05:30:32 PM PDT 24
Peak memory 208028 kb
Host smart-793eb7c1-19d6-4dee-b54c-059064de6b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836073409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.836073409
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1664692510
Short name T898
Test name
Test status
Simulation time 111206720116 ps
CPU time 218.08 seconds
Started Jul 17 05:27:58 PM PDT 24
Finished Jul 17 05:31:37 PM PDT 24
Peak memory 253276 kb
Host smart-3c1026e5-fb1c-4f33-aa36-c7cf8d37112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664692510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1664692510
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3041571057
Short name T799
Test name
Test status
Simulation time 1825108501 ps
CPU time 31.52 seconds
Started Jul 17 05:30:03 PM PDT 24
Finished Jul 17 05:30:36 PM PDT 24
Peak memory 252196 kb
Host smart-1f9250b3-db27-4d17-8db9-c0f73875ee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041571057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3041571057
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2832563282
Short name T137
Test name
Test status
Simulation time 3771200703 ps
CPU time 61.09 seconds
Started Jul 17 05:27:59 PM PDT 24
Finished Jul 17 05:29:02 PM PDT 24
Peak memory 257344 kb
Host smart-0741ed74-89ce-4eb3-9627-92cc8d409e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832563282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2832563282
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2478148794
Short name T204
Test name
Test status
Simulation time 5767053070 ps
CPU time 21.81 seconds
Started Jul 17 05:28:00 PM PDT 24
Finished Jul 17 05:28:23 PM PDT 24
Peak memory 240212 kb
Host smart-fa2d1e09-92bc-4fd4-b962-748f2436b12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478148794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2478148794
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.613473233
Short name T927
Test name
Test status
Simulation time 13011856 ps
CPU time 0.78 seconds
Started Jul 17 05:30:00 PM PDT 24
Finished Jul 17 05:30:02 PM PDT 24
Peak memory 208640 kb
Host smart-d37136ff-b3f1-4418-8ca8-a3de81d52d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613473233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
613473233
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1285825639
Short name T580
Test name
Test status
Simulation time 509633065 ps
CPU time 4.44 seconds
Started Jul 17 05:27:58 PM PDT 24
Finished Jul 17 05:28:04 PM PDT 24
Peak memory 233776 kb
Host smart-1abedb13-bbf6-4637-9ad0-7e67ef1924ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285825639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1285825639
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1821527598
Short name T401
Test name
Test status
Simulation time 6398474135 ps
CPU time 17.13 seconds
Started Jul 17 05:28:04 PM PDT 24
Finished Jul 17 05:28:23 PM PDT 24
Peak memory 235848 kb
Host smart-7aff328c-9eca-4b9b-bbc7-d16689092b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821527598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1821527598
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1275193070
Short name T368
Test name
Test status
Simulation time 63779858 ps
CPU time 1.15 seconds
Started Jul 17 05:30:29 PM PDT 24
Finished Jul 17 05:30:32 PM PDT 24
Peak memory 217840 kb
Host smart-a2660e82-d79d-46ee-85e7-d4de98541380
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275193070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1275193070
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2493440360
Short name T935
Test name
Test status
Simulation time 255157483 ps
CPU time 3.87 seconds
Started Jul 17 05:33:46 PM PDT 24
Finished Jul 17 05:33:50 PM PDT 24
Peak memory 225580 kb
Host smart-e86f9f5e-a92c-4177-b2f3-97139f5a653f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493440360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2493440360
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.315047994
Short name T447
Test name
Test status
Simulation time 11296433859 ps
CPU time 17.52 seconds
Started Jul 17 05:27:46 PM PDT 24
Finished Jul 17 05:28:06 PM PDT 24
Peak memory 225692 kb
Host smart-a7c878de-7c55-4904-8b89-aa02f44f8306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315047994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.315047994
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3479098441
Short name T558
Test name
Test status
Simulation time 1487390099 ps
CPU time 4.26 seconds
Started Jul 17 05:28:00 PM PDT 24
Finished Jul 17 05:28:06 PM PDT 24
Peak memory 223480 kb
Host smart-05c27c8e-0359-4984-ac28-b8fe67af890c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3479098441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3479098441
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3474511712
Short name T59
Test name
Test status
Simulation time 42719967209 ps
CPU time 406.09 seconds
Started Jul 17 05:28:06 PM PDT 24
Finished Jul 17 05:34:57 PM PDT 24
Peak memory 258116 kb
Host smart-4aa6e3c2-b6ec-4af0-9499-6ea331d11df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474511712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3474511712
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2208769072
Short name T771
Test name
Test status
Simulation time 66035007412 ps
CPU time 23.82 seconds
Started Jul 17 05:29:38 PM PDT 24
Finished Jul 17 05:30:02 PM PDT 24
Peak memory 221108 kb
Host smart-423c7073-f75f-41bc-a8bb-0dfd7376a2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208769072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2208769072
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.975352069
Short name T391
Test name
Test status
Simulation time 4519563189 ps
CPU time 7.8 seconds
Started Jul 17 05:33:31 PM PDT 24
Finished Jul 17 05:33:40 PM PDT 24
Peak memory 217540 kb
Host smart-4175fa01-8c5c-4750-bdec-28adac0e0083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975352069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.975352069
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1736795154
Short name T936
Test name
Test status
Simulation time 35731158 ps
CPU time 0.81 seconds
Started Jul 17 05:27:45 PM PDT 24
Finished Jul 17 05:27:48 PM PDT 24
Peak memory 205628 kb
Host smart-6e2f6aa5-76b4-4841-8919-0cdc41289089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736795154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1736795154
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.381277021
Short name T997
Test name
Test status
Simulation time 30873607 ps
CPU time 0.8 seconds
Started Jul 17 05:29:37 PM PDT 24
Finished Jul 17 05:29:39 PM PDT 24
Peak memory 206936 kb
Host smart-41b32b31-000a-4bb3-beac-cd93f565c87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381277021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.381277021
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2385414677
Short name T483
Test name
Test status
Simulation time 45778983 ps
CPU time 2.41 seconds
Started Jul 17 05:29:51 PM PDT 24
Finished Jul 17 05:29:54 PM PDT 24
Peak memory 225296 kb
Host smart-b769b24f-c623-4725-9db8-c0b2bc175e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385414677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2385414677
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1306738840
Short name T293
Test name
Test status
Simulation time 37522787 ps
CPU time 0.71 seconds
Started Jul 17 05:28:05 PM PDT 24
Finished Jul 17 05:28:09 PM PDT 24
Peak memory 206300 kb
Host smart-7bfabfc6-d649-4449-8660-af58b4f2aaad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306738840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
306738840
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.911041308
Short name T864
Test name
Test status
Simulation time 6315340461 ps
CPU time 16.69 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:30:39 PM PDT 24
Peak memory 233636 kb
Host smart-843c526d-7aee-428d-b771-876285777f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911041308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.911041308
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3171213010
Short name T415
Test name
Test status
Simulation time 23305185 ps
CPU time 0.78 seconds
Started Jul 17 05:28:02 PM PDT 24
Finished Jul 17 05:28:04 PM PDT 24
Peak memory 207464 kb
Host smart-8c91b38c-b412-4649-9457-33db17c7dff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171213010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3171213010
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.374058871
Short name T710
Test name
Test status
Simulation time 25578634668 ps
CPU time 61.87 seconds
Started Jul 17 05:30:03 PM PDT 24
Finished Jul 17 05:31:06 PM PDT 24
Peak memory 242088 kb
Host smart-d30157c9-0e59-44eb-8fbf-b5d369b26dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374058871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.374058871
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1170104311
Short name T966
Test name
Test status
Simulation time 19918904905 ps
CPU time 212.49 seconds
Started Jul 17 05:28:01 PM PDT 24
Finished Jul 17 05:31:35 PM PDT 24
Peak memory 253316 kb
Host smart-3a5c924d-071f-403d-acaf-bca666d895f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170104311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1170104311
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2444020852
Short name T48
Test name
Test status
Simulation time 6236901469 ps
CPU time 75.41 seconds
Started Jul 17 05:32:41 PM PDT 24
Finished Jul 17 05:33:57 PM PDT 24
Peak memory 268712 kb
Host smart-ec96f07e-074c-4cfb-9959-c988b763e28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444020852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2444020852
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.8748596
Short name T617
Test name
Test status
Simulation time 212039582 ps
CPU time 3.26 seconds
Started Jul 17 05:30:08 PM PDT 24
Finished Jul 17 05:30:12 PM PDT 24
Peak memory 233700 kb
Host smart-40dbbef0-c44a-4f27-a4ae-d32e1bb72296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8748596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.8748596
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1038054863
Short name T725
Test name
Test status
Simulation time 1251103290 ps
CPU time 10.52 seconds
Started Jul 17 05:32:48 PM PDT 24
Finished Jul 17 05:33:00 PM PDT 24
Peak memory 225564 kb
Host smart-6b8c832c-5874-4964-97d5-fea54e4e8339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038054863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1038054863
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.101797401
Short name T499
Test name
Test status
Simulation time 127619823 ps
CPU time 4.91 seconds
Started Jul 17 05:28:18 PM PDT 24
Finished Jul 17 05:28:25 PM PDT 24
Peak memory 225544 kb
Host smart-c3b0de7a-4951-4071-afa3-efbf9df63c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101797401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.101797401
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.883147231
Short name T742
Test name
Test status
Simulation time 838647644 ps
CPU time 4.35 seconds
Started Jul 17 05:29:32 PM PDT 24
Finished Jul 17 05:29:37 PM PDT 24
Peak memory 225596 kb
Host smart-12b0317e-1987-4646-ba6b-3a38b20d341a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883147231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.883147231
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2850741760
Short name T926
Test name
Test status
Simulation time 18294865 ps
CPU time 1.03 seconds
Started Jul 17 05:29:07 PM PDT 24
Finished Jul 17 05:29:09 PM PDT 24
Peak memory 218900 kb
Host smart-36cb0103-13e2-4d51-94f9-c2692c72404b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850741760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2850741760
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4115128670
Short name T722
Test name
Test status
Simulation time 4690293106 ps
CPU time 14.42 seconds
Started Jul 17 05:28:01 PM PDT 24
Finished Jul 17 05:28:17 PM PDT 24
Peak memory 233752 kb
Host smart-37324834-8c6a-40eb-85c5-7a32d158c99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115128670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4115128670
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1859239028
Short name T697
Test name
Test status
Simulation time 400726007 ps
CPU time 2.71 seconds
Started Jul 17 05:33:51 PM PDT 24
Finished Jul 17 05:33:58 PM PDT 24
Peak memory 233656 kb
Host smart-9858bb7d-dbce-4418-8ccb-795ec7c867cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859239028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1859239028
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1364615378
Short name T37
Test name
Test status
Simulation time 203229971 ps
CPU time 4.21 seconds
Started Jul 17 05:29:59 PM PDT 24
Finished Jul 17 05:30:04 PM PDT 24
Peak memory 223232 kb
Host smart-7f3eeb04-36ac-482d-8f3c-5523b1bd3af1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1364615378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1364615378
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.306955125
Short name T138
Test name
Test status
Simulation time 5766349661 ps
CPU time 140.49 seconds
Started Jul 17 05:27:59 PM PDT 24
Finished Jul 17 05:30:22 PM PDT 24
Peak memory 258644 kb
Host smart-83275177-df97-45c8-8829-8d5c18ca6e40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306955125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.306955125
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2025313148
Short name T66
Test name
Test status
Simulation time 678703797 ps
CPU time 8.5 seconds
Started Jul 17 05:29:08 PM PDT 24
Finished Jul 17 05:29:17 PM PDT 24
Peak memory 220808 kb
Host smart-91b44ed1-afab-47ad-8123-61f5f78738b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025313148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2025313148
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.825949951
Short name T593
Test name
Test status
Simulation time 1530699389 ps
CPU time 9.05 seconds
Started Jul 17 05:30:08 PM PDT 24
Finished Jul 17 05:30:18 PM PDT 24
Peak memory 217292 kb
Host smart-670cca2d-9dab-4f1b-b349-3a4b4eff4b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825949951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.825949951
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.511258996
Short name T530
Test name
Test status
Simulation time 833361917 ps
CPU time 3.45 seconds
Started Jul 17 05:29:19 PM PDT 24
Finished Jul 17 05:29:24 PM PDT 24
Peak memory 217356 kb
Host smart-4597060e-5944-4dd3-b703-6b075024c98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511258996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.511258996
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3752895909
Short name T390
Test name
Test status
Simulation time 25210137 ps
CPU time 0.8 seconds
Started Jul 17 05:30:20 PM PDT 24
Finished Jul 17 05:30:22 PM PDT 24
Peak memory 206924 kb
Host smart-2cb3df4d-be25-4afc-a984-08f68743aa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752895909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3752895909
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2072181989
Short name T920
Test name
Test status
Simulation time 4383749515 ps
CPU time 9.25 seconds
Started Jul 17 05:33:43 PM PDT 24
Finished Jul 17 05:33:53 PM PDT 24
Peak memory 233876 kb
Host smart-ba10ca8e-ad1f-4411-a58e-dea8f6950c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072181989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2072181989
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2410322452
Short name T436
Test name
Test status
Simulation time 20636039 ps
CPU time 0.76 seconds
Started Jul 17 05:28:06 PM PDT 24
Finished Jul 17 05:28:12 PM PDT 24
Peak memory 206336 kb
Host smart-5d8d1d12-2c61-4ff3-82ec-2af2316176cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410322452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
410322452
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.102141825
Short name T826
Test name
Test status
Simulation time 436986437 ps
CPU time 5.3 seconds
Started Jul 17 05:28:05 PM PDT 24
Finished Jul 17 05:28:13 PM PDT 24
Peak memory 233744 kb
Host smart-ae2d2469-afa9-41f7-9b9f-91efcbb37619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102141825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.102141825
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2232320373
Short name T828
Test name
Test status
Simulation time 39351889 ps
CPU time 0.82 seconds
Started Jul 17 05:29:00 PM PDT 24
Finished Jul 17 05:29:02 PM PDT 24
Peak memory 207448 kb
Host smart-d41ae27a-c5d8-465f-b986-034389cd0ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232320373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2232320373
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2481604833
Short name T76
Test name
Test status
Simulation time 4998840650 ps
CPU time 23.43 seconds
Started Jul 17 05:28:02 PM PDT 24
Finished Jul 17 05:28:27 PM PDT 24
Peak memory 236452 kb
Host smart-0e022ce4-99d4-4a6e-8232-b628a6e868c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481604833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2481604833
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.712029773
Short name T902
Test name
Test status
Simulation time 11467157823 ps
CPU time 106.61 seconds
Started Jul 17 05:28:00 PM PDT 24
Finished Jul 17 05:29:49 PM PDT 24
Peak memory 237280 kb
Host smart-9c824bfe-f6ad-4148-889f-80f7b58d603f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712029773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.712029773
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4030278841
Short name T255
Test name
Test status
Simulation time 122771308118 ps
CPU time 289.42 seconds
Started Jul 17 05:29:07 PM PDT 24
Finished Jul 17 05:33:57 PM PDT 24
Peak memory 274196 kb
Host smart-75c5d852-974c-4460-a5a7-c3417f4fc24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030278841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4030278841
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3093066826
Short name T95
Test name
Test status
Simulation time 287642694 ps
CPU time 6.6 seconds
Started Jul 17 05:32:48 PM PDT 24
Finished Jul 17 05:32:56 PM PDT 24
Peak memory 233820 kb
Host smart-e74f162a-16eb-454e-85df-791e27118afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093066826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3093066826
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3287669360
Short name T788
Test name
Test status
Simulation time 1877165118 ps
CPU time 16.05 seconds
Started Jul 17 05:28:06 PM PDT 24
Finished Jul 17 05:28:26 PM PDT 24
Peak memory 237288 kb
Host smart-38d46f30-12a5-47ec-a5a0-90491335d120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287669360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3287669360
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2768973647
Short name T488
Test name
Test status
Simulation time 131442937 ps
CPU time 2.31 seconds
Started Jul 17 05:32:49 PM PDT 24
Finished Jul 17 05:32:52 PM PDT 24
Peak memory 233480 kb
Host smart-cab14887-d6d5-4805-90bf-ee51e35cd624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768973647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2768973647
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4036384122
Short name T850
Test name
Test status
Simulation time 3077250675 ps
CPU time 24.02 seconds
Started Jul 17 05:29:00 PM PDT 24
Finished Jul 17 05:29:25 PM PDT 24
Peak memory 233884 kb
Host smart-269d9848-1eba-46bc-a577-a182c30db86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036384122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4036384122
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.853890168
Short name T858
Test name
Test status
Simulation time 156886966 ps
CPU time 1.08 seconds
Started Jul 17 05:28:06 PM PDT 24
Finished Jul 17 05:28:12 PM PDT 24
Peak memory 217640 kb
Host smart-7ca3db3c-0b10-4847-9000-bb52fe7e5804
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853890168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.853890168
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2366721105
Short name T564
Test name
Test status
Simulation time 1547611873 ps
CPU time 8.75 seconds
Started Jul 17 05:30:41 PM PDT 24
Finished Jul 17 05:30:51 PM PDT 24
Peak memory 233804 kb
Host smart-9158bcaa-5fbf-494a-be3f-712d1a5e6c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366721105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2366721105
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4189900893
Short name T232
Test name
Test status
Simulation time 525566756 ps
CPU time 4.47 seconds
Started Jul 17 05:29:07 PM PDT 24
Finished Jul 17 05:29:12 PM PDT 24
Peak memory 233656 kb
Host smart-1426e519-7258-4ee8-ae5b-ea6d6b4bcc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189900893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4189900893
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3955892852
Short name T542
Test name
Test status
Simulation time 1806821304 ps
CPU time 5.77 seconds
Started Jul 17 05:33:52 PM PDT 24
Finished Jul 17 05:34:02 PM PDT 24
Peak memory 221464 kb
Host smart-e84c7ba2-6e49-46b3-aaeb-9fc61a62ab53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3955892852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3955892852
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4251710096
Short name T885
Test name
Test status
Simulation time 6319349537 ps
CPU time 22.57 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:28:37 PM PDT 24
Peak memory 217416 kb
Host smart-9d07e8bb-5bf9-4fc8-9403-3ab9444731bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251710096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4251710096
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3663207499
Short name T354
Test name
Test status
Simulation time 170111241 ps
CPU time 1.38 seconds
Started Jul 17 05:27:58 PM PDT 24
Finished Jul 17 05:28:01 PM PDT 24
Peak memory 208928 kb
Host smart-f04c1064-6ccc-485c-937d-ec26a3b0a61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663207499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3663207499
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3442484457
Short name T305
Test name
Test status
Simulation time 78633277 ps
CPU time 1.23 seconds
Started Jul 17 05:28:09 PM PDT 24
Finished Jul 17 05:28:15 PM PDT 24
Peak memory 208912 kb
Host smart-d95154fd-1024-4bed-930c-7f6da65f6027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442484457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3442484457
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3876815039
Short name T987
Test name
Test status
Simulation time 24980608 ps
CPU time 0.81 seconds
Started Jul 17 05:28:06 PM PDT 24
Finished Jul 17 05:28:10 PM PDT 24
Peak memory 206956 kb
Host smart-929db037-06a0-4dc6-8d0b-af89164c9107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876815039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3876815039
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.320761775
Short name T228
Test name
Test status
Simulation time 623634744 ps
CPU time 3.84 seconds
Started Jul 17 05:28:06 PM PDT 24
Finished Jul 17 05:28:13 PM PDT 24
Peak memory 225520 kb
Host smart-99b8ca6e-1a68-4657-8138-241828ca0a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320761775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.320761775
Directory /workspace/9.spi_device_upload/latest
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