Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2382411	1			T1	1		T2	1		T3	1
all_values[1]	2382411	1			T1	1		T2	1		T3	1
all_values[2]	2382411	1			T1	1		T2	1		T3	1
all_values[3]	2382411	1			T1	1		T2	1		T3	1
all_values[4]	2382411	1			T1	1		T2	1		T3	1
all_values[5]	2382411	1			T1	1		T2	1		T3	1
all_values[6]	2382411	1			T1	1		T2	1		T3	1
all_values[7]	2382411	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18510278

1

T1

8

T2

8

T3

8

auto[1]

549010

1

T14

5759

T15

70

T16

62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19035418

1

T1

8

T2

8

T3

8

auto[1]

23870

1

T9

160

T29

230

T31

67

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2293930	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	10900	1			T9	91		T29	133		T31	30
all_values[0]	auto[1]	auto[0]	76907	1			T14	1911		T15	1		T16	8
all_values[0]	auto[1]	auto[1]	674	1			T14	3		T15	4		T16	2
all_values[1]	auto[0]	auto[0]	2282864	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7075	1			T9	58		T29	76		T31	30
all_values[1]	auto[1]	auto[0]	92102	1			T14	2		T15	8		T16	3
all_values[1]	auto[1]	auto[1]	370	1			T14	1		T15	4		T16	3
all_values[2]	auto[0]	auto[0]	2309803	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2725	1			T9	11		T29	21		T31	7
all_values[2]	auto[1]	auto[0]	69645	1			T14	4		T15	6		T16	8
all_values[2]	auto[1]	auto[1]	238	1			T14	4		T15	1		T16	4
all_values[3]	auto[0]	auto[0]	2310834	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	200	1			T14	2		T15	6		T16	1
all_values[3]	auto[1]	auto[0]	71149	1			T14	1909		T15	5		T16	10
all_values[3]	auto[1]	auto[1]	228	1			T14	2		T15	4		T16	3
all_values[4]	auto[0]	auto[0]	2358219	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	188	1			T14	4		T15	2		T19	4
all_values[4]	auto[1]	auto[0]	23836	1			T14	2		T15	7		T16	2
all_values[4]	auto[1]	auto[1]	168	1			T14	1		T15	5		T16	2
all_values[5]	auto[0]	auto[0]	2338577	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	164	1			T14	1		T16	1		T17	1
all_values[5]	auto[1]	auto[0]	43502	1			T14	3		T15	4		T16	2
all_values[5]	auto[1]	auto[1]	168	1			T14	2		T15	6		T16	1
all_values[6]	auto[0]	auto[0]	2329802	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	210	1			T14	5		T15	5		T16	6
all_values[6]	auto[1]	auto[0]	52204	1			T14	1908		T15	5		T16	3
all_values[6]	auto[1]	auto[1]	195	1			T14	4		T17	1		T19	2
all_values[7]	auto[0]	auto[0]	2264573	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	214	1			T14	5		T15	6		T16	2
all_values[7]	auto[1]	auto[0]	117471	1			T14	2		T15	3		T16	10
all_values[7]	auto[1]	auto[1]	153	1			T14	1		T15	7		T16	1