Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33486	1			T2	4		T3	2		T6	2
auto[SpiFlashAddrCfg]	6833	1			T2	4		T9	33		T11	3
auto[SpiFlashAddr3b]	8379	1			T2	2		T9	59		T11	14
auto[SpiFlashAddr4b]	6913	1			T2	6		T7	8		T9	50

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29686

1

T3

2

T6

2

T9

176

auto[1]

25925

1

T2

16

T7

12

T9

154

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29928

1

T2

8

T3

2

T9

160

auto[1]

25683

1

T2

8

T6

2

T7

12

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37722	1			T2	4		T3	2		T6	2
values[1]	1023	1			T9	7		T11	2		T29	4
values[2]	1299	1			T9	8		T11	1		T29	5
values[3]	1344	1			T2	2		T9	7		T29	8
values[4]	1368	1			T9	7		T11	7		T12	2
values[5]	1310	1			T9	9		T11	2		T29	6
values[6]	1358	1			T9	4		T11	2		T29	5
values[7]	1255	1			T9	8		T11	1		T29	7
values[8]	8932	1			T2	10		T7	8		T9	67

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27728

1

T2

16

T3

2

T6

2

auto[1]

27883

1

T9

330

T11

40

T13

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

52512

1

T2

16

T3

2

T6

2

write

3099

1

T9

15

T11

7

T12

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17537

1

T2

8

T7

2

T9

127

valids[0x1]

38074

1

T2

8

T3

2

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1490	1			T2	2		T9	10		T11	2
internal_process_ops[0x5a]	1463	1			T9	12		T11	4		T29	8
internal_process_ops[0x05]	20635	1			T2	2		T6	2		T9	83
internal_process_ops[0x35]	1449	1			T9	11		T29	7		T31	12
internal_process_ops[0x15]	1425	1			T3	2		T7	4		T9	9
internal_process_ops[0x03]	893	1			T9	2		T11	1		T12	2
internal_process_ops[0x0b]	914	1			T2	2		T9	3		T11	1
internal_process_ops[0x3b]	955	1			T2	2		T9	1		T11	1
internal_process_ops[0x6b]	874	1			T7	2		T9	3		T12	2
internal_process_ops[0xbb]	978	1			T2	2		T9	4		T13	2
internal_process_ops[0xeb]	993	1			T9	5		T29	2		T31	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54112

1

T2

16

T3

2

T6

2

auto[1]

1499

1

T9

7

T11

3

T29

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53291

1

T2

16

T3

2

T6

2

auto[1]

2320

1

T9

13

T11

4

T29

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9107

1

T3

2

T6

2

T10

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6317

1

T2

4

T7

4

T35

13

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1737

1

T12

4

T41

4

T35

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1569

1

T2

4

T35

12

T17

31

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2206

1

T12

4

T41

6

T28

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1934

1

T2

2

T35

23

T17

38

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1807

1

T35

8

T48

2

T57

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1604

1

T2

6

T7

8

T35

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

106

1

T17

4

T51

3

T21

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

84

1

T17

1

T18

2

T47

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

100

1

T18

1

T47

7

T19

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

97

1

T17

1

T18

2

T47

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

106

1

T12

4

T17

4

T19

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

63

1

T17

3

T47

1

T60

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

81

1

T47

1

T19

1

T21

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

90

1

T17

5

T47

1

T51

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

84

1

T17

3

T47

1

T51

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

85

1

T17

1

T18

1

T51

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

88

1

T17

2

T18

1

T47

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

90

1

T17

2

T18

4

T47

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

102

1

T35

2

T17

3

T18

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

89

1

T35

1

T47

2

T52

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

76

1

T17

3

T18

1

T47

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

106

1

T17

2

T51

1

T54

6

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8639

1

T9

100

T11

10

T29

51

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8631

1

T9

85

T11

1

T29

30

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1471

1

T9

18

T29

27

T31

11

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1314

1

T9

14

T11

1

T29

13

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1758

1

T9

33

T11

5

T13

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1728

1

T9

22

T11

9

T29

21

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1442

1

T9

18

T11

6

T13

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1248

1

T9

25

T11

1

T29

9

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

111

1

T9

1

T11

4

T40

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

112

1

T9

1

T11

1

T40

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

88

1

T29

3

T40

2

T14

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

94

1

T9

1

T31

1

T40

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

93

1

T29

2

T31

1

T56

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

97

1

T9

1

T29

2

T31

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

110

1

T40

2

T14

1

T15

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

102

1

T11

2

T40

5

T15

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

91

1

T40

1

T14

3

T56

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

93

1

T31

1

T40

1

T14

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

103

1

T9

1

T40

2

T14

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

119

1

T9

3

T40

1

T14

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

120

1

T9

4

T29

5

T31

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

83

1

T40

2

T56

2

T16

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

141

1

T9

2

T29

1

T40

10

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

95

1

T9

1

T29

1

T15

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3363	1			T10	4		T45	6		T34	16
auto[0]	values[0]	valids[0x1]	14500	1			T2	4		T3	2		T6	2
auto[0]	values[1]	valids[0x1]	527	1			T35	2		T17	4		T18	2
auto[0]	values[2]	valids[0x0]	478	1			T41	2		T35	1		T48	2
auto[0]	values[2]	valids[0x1]	245	1			T35	1		T17	2		T47	5
auto[0]	values[3]	valids[0x0]	504	1			T2	2		T35	5		T17	21
auto[0]	values[3]	valids[0x1]	241	1			T35	2		T17	3		T47	1
auto[0]	values[4]	valids[0x0]	494	1			T12	2		T35	2		T55	2
auto[0]	values[4]	valids[0x1]	294	1			T35	5		T50	2		T17	7
auto[0]	values[5]	valids[0x0]	483	1			T35	2		T17	8		T18	1
auto[0]	values[5]	valids[0x1]	224	1			T35	2		T17	5		T18	1
auto[0]	values[6]	valids[0x0]	521	1			T35	1		T46	2		T17	9
auto[0]	values[6]	valids[0x1]	243	1			T28	4		T35	1		T17	2
auto[0]	values[7]	valids[0x0]	429	1			T50	4		T17	6		T18	4
auto[0]	values[7]	valids[0x1]	262	1			T17	9		T47	1		T51	4
auto[0]	values[8]	valids[0x0]	3096	1			T2	6		T7	2		T12	2
auto[0]	values[8]	valids[0x1]	1824	1			T2	4		T7	6		T12	2
auto[1]	values[0]	valids[0x0]	3768	1			T9	64		T11	9		T29	35
auto[1]	values[0]	valids[0x1]	16091	1			T9	149		T11	11		T13	3
auto[1]	values[1]	valids[0x1]	496	1			T9	7		T11	2		T29	4
auto[1]	values[2]	valids[0x0]	350	1			T9	3		T29	5		T40	4
auto[1]	values[2]	valids[0x1]	226	1			T9	5		T11	1		T31	5
auto[1]	values[3]	valids[0x0]	353	1			T9	5		T29	6		T40	3
auto[1]	values[3]	valids[0x1]	246	1			T9	2		T29	2		T31	2
auto[1]	values[4]	valids[0x0]	326	1			T9	3		T11	5		T29	1
auto[1]	values[4]	valids[0x1]	254	1			T9	4		T11	2		T29	6
auto[1]	values[5]	valids[0x0]	370	1			T9	5		T11	2		T29	3
auto[1]	values[5]	valids[0x1]	233	1			T9	4		T29	3		T31	3
auto[1]	values[6]	valids[0x0]	392	1			T9	2		T11	1		T29	4
auto[1]	values[6]	valids[0x1]	202	1			T9	2		T11	1		T29	1
auto[1]	values[7]	valids[0x0]	333	1			T9	5		T11	1		T29	6
auto[1]	values[7]	valids[0x1]	231	1			T9	3		T29	1		T31	5
auto[1]	values[8]	valids[0x0]	2277	1			T9	40		T11	3		T13	2
auto[1]	values[8]	valids[0x1]	1735	1			T9	27		T11	2		T29	17