Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3129635

1

T1

2769

T2

1

T3

1370

auto[1]

30033

1

T9

70

T11

14

T29

24

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

980639

1

T1

2769

T2

1

T3

1370

auto[1]

2179029

1

T6

256

T9

12327

T11

320

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	657345	1			T1	565		T2	1		T3	652
auto[524288:1048575]	344059	1			T1	1317		T9	20		T11	2
auto[1048576:1572863]	397789	1			T1	293		T9	3039		T10	228
auto[1572864:2097151]	366046	1			T1	584		T9	782		T11	6
auto[2097152:2621439]	324362	1			T1	1		T9	657		T11	12
auto[2621440:3145727]	402577	1			T3	716		T9	4867		T13	26
auto[3145728:3670015]	324193	1			T1	9		T3	2		T9	1035
auto[3670016:4194303]	343297	1			T9	282		T11	49		T13	23

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2211936

1

T1

12

T2

1

T3

3

auto[1]

947732

1

T1

2757

T3

1367

T9

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2730538

1

T1

2769

T2

1

T3

1370

auto[1]

429130

1

T9

1419

T11

26

T29

3

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	254308	1			T1	565		T2	1		T3	652
auto[0]	auto[0]	auto[0:524287]	auto[1]	363376	1			T6	256		T9	1699		T11	64
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	101993	1			T1	1317		T9	6		T11	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	192913	1			T9	7		T29	1031		T40	640
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	118213	1			T1	293		T9	10		T10	228
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	212731	1			T9	3023		T29	130		T31	2694
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	102832	1			T1	584		T9	6		T11	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	206237	1			T9	131		T29	384		T31	1604
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	88104	1			T1	1		T9	5		T11	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	170333	1			T9	516		T29	513		T31	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	103841	1			T3	716		T9	5		T13	26
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	238105	1			T9	4179		T29	2		T31	2198
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	100340	1			T1	9		T3	2		T9	7
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	164486	1			T9	1026		T11	256		T29	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	96665	1			T9	3		T11	28		T13	23
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	192026	1			T9	278		T29	129		T31	1285
auto[0]	auto[1]	auto[0:524287]	auto[0]	1720	1			T9	2		T11	2		T29	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	32295	1			T40	1		T35	1597		T56	641
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1891	1			T9	2		T40	5		T15	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	43771	1			T40	1		T15	4171		T56	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1072	1			T14	3		T15	1		T16	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	60410	1			T14	7		T16	256		T17	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1946	1			T11	2		T31	1		T40	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	52600	1			T9	640		T31	393		T40	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	686	1			T9	3		T11	10		T56	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	61441	1			T9	133		T40	128		T56	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	754	1			T40	1		T14	8		T35	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	56476	1			T9	638		T14	1880		T35	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	736	1			T29	1		T31	2		T40	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	54936	1			T31	386		T40	1		T14	771
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1721	1			T9	1		T11	7		T45	25
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	50677	1			T14	299		T15	683		T35	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	560	1			T9	2		T29	1		T40	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	4537	1			T9	5		T40	43		T14	182
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	386	1			T9	2		T29	6		T14	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2273	1			T9	3		T29	5		T14	15
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	332	1			T9	3		T29	1		T31	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	4206	1			T9	3		T29	1		T40	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	334	1			T9	3		T31	1		T40	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1570	1			T9	2		T31	3		T40	26
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	386	1			T29	1		T31	2		T40	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2623	1			T31	14		T40	29		T14	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	366	1			T9	1		T29	2		T40	7
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1973	1			T9	44		T29	2		T40	23
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	384	1			T9	2		T29	1		T31	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2529	1			T29	3		T31	7		T14	15
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	302	1			T11	9		T29	1		T40	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1274	1			T40	32		T14	48		T17	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	80	1			T40	1		T56	1		T17	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	469	1			T40	17		T56	21		T17	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	101	1			T40	1		T15	3		T16	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	731	1			T40	3		T15	23		T16	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	121	1			T14	2		T102	5		T168	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	704	1			T14	21		T60	5		T153	23
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	79	1			T40	1		T18	1		T51	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	448	1			T40	27		T51	2		T152	9
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	120	1			T17	1		T18	1		T102	17
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	669	1			T17	6		T137	1		T168	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	103	1			T56	4		T95	1		T17	9
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	959	1			T56	52		T95	16		T17	63
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	85	1			T31	1		T40	1		T17	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	697	1			T31	7		T40	21		T17	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	78	1			T11	5		T14	1		T35	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	554	1			T14	2		T35	4		T51	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1765220	1			T1	12		T2	1		T3	3
auto[0]	auto[0]	auto[1]	941283	1			T1	2757		T3	1367		T9	2
auto[0]	auto[1]	auto[0]	417396	1			T9	1419		T11	21		T29	3
auto[0]	auto[1]	auto[1]	5736	1			T40	1		T45	190		T15	1
auto[1]	auto[0]	auto[0]	23452	1			T9	70		T11	8		T29	22
auto[1]	auto[0]	auto[1]	583	1			T11	1		T29	2		T40	10
auto[1]	auto[1]	auto[0]	5868	1			T11	4		T31	8		T40	72
auto[1]	auto[1]	auto[1]	130	1			T11	1		T56	2		T17	3