Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2382411	1			T1	1		T2	1		T3	1
all_pins[1]	2382411	1			T1	1		T2	1		T3	1
all_pins[2]	2382411	1			T1	1		T2	1		T3	1
all_pins[3]	2382411	1			T1	1		T2	1		T3	1
all_pins[4]	2382411	1			T1	1		T2	1		T3	1
all_pins[5]	2382411	1			T1	1		T2	1		T3	1
all_pins[6]	2382411	1			T1	1		T2	1		T3	1
all_pins[7]	2382411	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19004963	1			T1	8		T2	8		T3	8
values[0x1]	54325	1			T14	1917		T15	31		T16	16
transitions[0x0=>0x1]	53818	1			T14	1915		T15	23		T16	16
transitions[0x1=>0x0]	53827	1			T14	1915		T15	23		T16	16

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2381659	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	752	1			T14	19		T15	4		T16	2
all_pins[0]	transitions[0x0=>0x1]	585	1			T14	18		T15	4		T16	2
all_pins[0]	transitions[0x1=>0x0]	226	1			T15	4		T16	3		T17	4
all_pins[1]	values[0x0]	2382018	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	393	1			T14	1		T15	4		T16	3
all_pins[1]	transitions[0x0=>0x1]	325	1			T14	1		T15	3		T16	3
all_pins[1]	transitions[0x1=>0x0]	177	1			T14	4		T16	4		T20	1
all_pins[2]	values[0x0]	2382166	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	245	1			T14	4		T15	1		T16	4
all_pins[2]	transitions[0x0=>0x1]	193	1			T14	3		T15	1		T16	4
all_pins[2]	transitions[0x1=>0x0]	176	1			T14	1		T15	4		T16	3
all_pins[3]	values[0x0]	2382183	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	228	1			T14	2		T15	4		T16	3
all_pins[3]	transitions[0x0=>0x1]	167	1			T14	2		T15	1		T16	3
all_pins[3]	transitions[0x1=>0x0]	107	1			T14	1		T15	2		T16	2
all_pins[4]	values[0x0]	2382243	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	168	1			T14	1		T15	5		T16	2
all_pins[4]	transitions[0x0=>0x1]	134	1			T14	1		T15	4		T16	2
all_pins[4]	transitions[0x1=>0x0]	343	1			T14	2		T15	5		T16	1
all_pins[5]	values[0x0]	2382034	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	377	1			T14	2		T15	6		T16	1
all_pins[5]	transitions[0x0=>0x1]	342	1			T14	2		T15	6		T16	1
all_pins[5]	transitions[0x1=>0x0]	51974	1			T14	1887		T17	1		T19	1
all_pins[6]	values[0x0]	2330402	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	52009	1			T14	1887		T17	1		T19	2
all_pins[6]	transitions[0x0=>0x1]	51971	1			T14	1887		T17	1		T19	1
all_pins[6]	transitions[0x1=>0x0]	115	1			T14	1		T15	7		T16	1
all_pins[7]	values[0x0]	2382258	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	153	1			T14	1		T15	7		T16	1
all_pins[7]	transitions[0x0=>0x1]	101	1			T14	1		T15	4		T16	1
all_pins[7]	transitions[0x1=>0x0]	709	1			T14	19		T15	1		T16	2