Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15576

1

T3

2

T6

2

T10

4

auto[1]

12152

1

T2

16

T7

12

T35

54

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4374	1			T41	10		T74	2		T35	20
values[1]	3672	1			T6	2		T17	84		T18	46
values[2]	2921	1			T10	4		T35	20		T46	20
values[3]	3567	1			T55	4		T57	4		T17	23
values[4]	3595	1			T2	16		T7	12		T12	18
values[5]	3224	1			T45	6		T34	16		T35	23
values[6]	3344	1			T3	2		T28	8		T35	20
values[7]	3031	1			T17	45		T47	54		T19	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3717	1			T3	2		T6	2		T48	14
values[1]	3746	1			T2	16		T10	4		T34	16
values[2]	3564	1			T7	12		T41	10		T74	2
values[3]	2921	1			T45	6		T28	8		T46	20
values[4]	3708	1			T55	4		T17	65		T18	25
values[5]	3035	1			T12	18		T50	8		T49	4
values[6]	3505	1			T17	45		T237	10		T47	27
values[7]	3532	1			T35	40		T18	24		T47	37

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	251	1			T51	13		T170	10		T238	12
auto[0]	values[0]	values[1]	293	1			T35	10		T52	39		T21	15
auto[0]	values[0]	values[2]	507	1			T41	10		T74	2		T51	11
auto[0]	values[0]	values[3]	182	1			T17	11		T234	4		T170	18
auto[0]	values[0]	values[4]	333	1			T51	14		T215	9		T239	6
auto[0]	values[0]	values[5]	168	1			T50	8		T17	21		T199	4
auto[0]	values[0]	values[6]	208	1			T51	11		T211	8		T194	4
auto[0]	values[0]	values[7]	275	1			T21	10		T103	11		T152	8
auto[0]	values[1]	values[0]	261	1			T6	2		T19	14		T152	40
auto[0]	values[1]	values[1]	293	1			T18	14		T215	16		T184	23
auto[0]	values[1]	values[2]	99	1			T18	15		T184	43		T240	9
auto[0]	values[1]	values[3]	278	1			T17	31		T47	11		T210	12
auto[0]	values[1]	values[4]	223	1			T103	10		T213	10		T241	138
auto[0]	values[1]	values[5]	356	1			T17	8		T51	20		T60	10
auto[0]	values[1]	values[6]	350	1			T204	24		T224	22		T208	11
auto[0]	values[1]	values[7]	261	1			T208	8		T197	12		T242	4
auto[0]	values[2]	values[0]	110	1			T17	11		T197	23		T170	23
auto[0]	values[2]	values[1]	249	1			T10	4		T47	19		T227	12
auto[0]	values[2]	values[2]	109	1			T19	19		T243	4		T244	6
auto[0]	values[2]	values[3]	215	1			T46	20		T47	26		T245	2
auto[0]	values[2]	values[4]	215	1			T17	6		T219	13		T208	11
auto[0]	values[2]	values[5]	225	1			T17	11		T175	16		T210	12
auto[0]	values[2]	values[6]	455	1			T17	7		T237	10		T215	12
auto[0]	values[2]	values[7]	142	1			T35	10		T19	9		T60	8
auto[0]	values[3]	values[0]	547	1			T17	16		T210	85		T60	9
auto[0]	values[3]	values[1]	227	1			T57	4		T219	14		T246	12
auto[0]	values[3]	values[2]	252	1			T51	6		T19	11		T152	8
auto[0]	values[3]	values[3]	200	1			T103	9		T180	16		T247	14
auto[0]	values[3]	values[4]	232	1			T55	4		T52	30		T210	11
auto[0]	values[3]	values[5]	256	1			T208	9		T248	38		T194	52
auto[0]	values[3]	values[6]	310	1			T103	3		T152	10		T249	12
auto[0]	values[3]	values[7]	227	1			T19	12		T197	23		T170	14
auto[0]	values[4]	values[0]	250	1			T17	9		T60	24		T200	11
auto[0]	values[4]	values[1]	291	1			T35	10		T51	13		T181	16
auto[0]	values[4]	values[2]	267	1			T17	13		T51	29		T193	14
auto[0]	values[4]	values[3]	274	1			T193	19		T250	12		T198	12
auto[0]	values[4]	values[4]	273	1			T18	13		T193	10		T251	2
auto[0]	values[4]	values[5]	292	1			T12	18		T49	4		T51	13
auto[0]	values[4]	values[6]	180	1			T252	8		T60	12		T69	2
auto[0]	values[4]	values[7]	231	1			T253	5		T184	14		T206	12
auto[0]	values[5]	values[0]	125	1			T48	14		T51	13		T60	14
auto[0]	values[5]	values[1]	338	1			T34	16		T35	12		T17	13
auto[0]	values[5]	values[2]	151	1			T152	10		T239	10		T254	12
auto[0]	values[5]	values[3]	150	1			T45	6		T184	4		T213	7
auto[0]	values[5]	values[4]	237	1			T194	7		T170	9		T255	2
auto[0]	values[5]	values[5]	147	1			T52	16		T225	16		T206	18
auto[0]	values[5]	values[6]	124	1			T21	10		T210	28		T184	14
auto[0]	values[5]	values[7]	325	1			T18	17		T193	12		T152	27
auto[0]	values[6]	values[0]	284	1			T3	2		T219	11		T208	6
auto[0]	values[6]	values[1]	298	1			T51	9		T202	16		T103	11
auto[0]	values[6]	values[2]	253	1			T19	14		T176	12		T213	14
auto[0]	values[6]	values[3]	285	1			T28	8		T51	8		T210	13
auto[0]	values[6]	values[4]	177	1			T60	13		T256	8		T185	15
auto[0]	values[6]	values[5]	114	1			T17	8		T18	11		T60	10
auto[0]	values[6]	values[6]	278	1			T47	17		T60	21		T152	13
auto[0]	values[6]	values[7]	252	1			T35	12		T47	24		T197	10
auto[0]	values[7]	values[0]	174	1			T238	10		T257	6		T176	11
auto[0]	values[7]	values[1]	326	1			T19	7		T258	6		T152	9
auto[0]	values[7]	values[2]	186	1			T207	16		T152	15		T215	12
auto[0]	values[7]	values[3]	135	1			T259	26		T218	9		T240	8
auto[0]	values[7]	values[4]	171	1			T17	13		T33	11		T180	14
auto[0]	values[7]	values[5]	278	1			T47	47		T215	12		T230	18
auto[0]	values[7]	values[6]	222	1			T21	7		T210	9		T60	26
auto[0]	values[7]	values[7]	179	1			T210	15		T154	17		T236	36
auto[1]	values[0]	values[0]	341	1			T51	12		T53	12		T170	10
auto[1]	values[0]	values[1]	164	1			T35	10		T52	21		T21	10
auto[1]	values[0]	values[2]	295	1			T51	9		T170	18		T180	89
auto[1]	values[0]	values[3]	91	1			T17	16		T170	8		T213	11
auto[1]	values[0]	values[4]	702	1			T51	6		T215	85		T239	113
auto[1]	values[0]	values[5]	72	1			T17	7		T214	2		T260	14
auto[1]	values[0]	values[6]	280	1			T51	9		T194	39		T180	42
auto[1]	values[0]	values[7]	212	1			T21	11		T103	9		T152	12
auto[1]	values[1]	values[0]	213	1			T19	6		T152	6		T208	45
auto[1]	values[1]	values[1]	165	1			T18	8		T215	7		T184	5
auto[1]	values[1]	values[2]	69	1			T18	9		T184	7		T240	11
auto[1]	values[1]	values[3]	264	1			T17	11		T47	32		T210	13
auto[1]	values[1]	values[4]	154	1			T103	10		T261	6		T213	10
auto[1]	values[1]	values[5]	365	1			T17	34		T51	21		T54	12
auto[1]	values[1]	values[6]	92	1			T208	9		T184	6		T180	8
auto[1]	values[1]	values[7]	229	1			T208	13		T197	9		T176	57
auto[1]	values[2]	values[0]	133	1			T17	15		T197	8		T170	21
auto[1]	values[2]	values[1]	286	1			T47	123		T219	15		T197	4
auto[1]	values[2]	values[2]	86	1			T19	40		T262	10		T263	7
auto[1]	values[2]	values[3]	183	1			T47	3		T33	7		T154	8
auto[1]	values[2]	values[4]	126	1			T17	14		T219	9		T208	9
auto[1]	values[2]	values[5]	102	1			T17	9		T210	8		T103	6
auto[1]	values[2]	values[6]	195	1			T17	38		T215	8		T197	9
auto[1]	values[2]	values[7]	90	1			T35	10		T19	19		T60	12
auto[1]	values[3]	values[0]	194	1			T17	7		T210	1		T60	11
auto[1]	values[3]	values[1]	74	1			T219	8		T173	11		T229	9
auto[1]	values[3]	values[2]	149	1			T51	32		T19	9		T152	12
auto[1]	values[3]	values[3]	123	1			T103	11		T180	14		T247	6
auto[1]	values[3]	values[4]	295	1			T52	6		T210	123		T152	6
auto[1]	values[3]	values[5]	80	1			T208	11		T194	6		T238	6
auto[1]	values[3]	values[6]	247	1			T103	17		T152	10		T264	2
auto[1]	values[3]	values[7]	154	1			T19	8		T197	10		T170	6
auto[1]	values[4]	values[0]	246	1			T17	29		T60	16		T265	24
auto[1]	values[4]	values[1]	139	1			T2	16		T35	15		T51	7
auto[1]	values[4]	values[2]	267	1			T7	12		T17	7		T51	6
auto[1]	values[4]	values[3]	171	1			T193	4		T170	5		T236	11
auto[1]	values[4]	values[4]	153	1			T18	12		T193	10		T201	8
auto[1]	values[4]	values[5]	171	1			T51	8		T186	12		T193	18
auto[1]	values[4]	values[6]	130	1			T266	22		T60	8		T152	8
auto[1]	values[4]	values[7]	260	1			T253	15		T184	7		T206	8
auto[1]	values[5]	values[0]	222	1			T51	8		T60	12		T267	6
auto[1]	values[5]	values[1]	243	1			T35	11		T17	16		T47	7
auto[1]	values[5]	values[2]	173	1			T152	10		T239	98		T214	5
auto[1]	values[5]	values[3]	188	1			T184	18		T213	47		T155	5
auto[1]	values[5]	values[4]	201	1			T194	13		T170	11		T184	6
auto[1]	values[5]	values[5]	123	1			T52	4		T206	7		T226	10
auto[1]	values[5]	values[6]	87	1			T21	10		T210	19		T184	6
auto[1]	values[5]	values[7]	390	1			T18	7		T193	8		T152	31
auto[1]	values[6]	values[0]	196	1			T219	13		T208	14		T240	7
auto[1]	values[6]	values[1]	154	1			T51	12		T103	9		T197	5
auto[1]	values[6]	values[2]	329	1			T19	6		T176	152		T213	6
auto[1]	values[6]	values[3]	117	1			T51	12		T210	10		T226	9
auto[1]	values[6]	values[4]	83	1			T60	7		T185	5		T229	6
auto[1]	values[6]	values[5]	187	1			T17	73		T18	9		T60	16
auto[1]	values[6]	values[6]	135	1			T47	10		T60	8		T152	22
auto[1]	values[6]	values[7]	202	1			T35	8		T47	13		T197	10
auto[1]	values[7]	values[0]	170	1			T238	10		T176	32		T206	7
auto[1]	values[7]	values[1]	206	1			T19	13		T268	12		T152	63
auto[1]	values[7]	values[2]	372	1			T152	60		T215	46		T236	83
auto[1]	values[7]	values[3]	65	1			T218	11		T240	12		T269	6
auto[1]	values[7]	values[4]	133	1			T17	32		T33	9		T180	6
auto[1]	values[7]	values[5]	99	1			T47	7		T215	8		T230	4
auto[1]	values[7]	values[6]	212	1			T21	13		T210	38		T60	5
auto[1]	values[7]	values[7]	103	1			T210	5		T270	18		T154	6