Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	365	1			T35	3		T50	2		T17	2
auto[ReadAddrCrossIntoMailbox]	228	1			T50	2		T17	3		T18	2
auto[ReadAddrCrossOutOfMailbox]	244	1			T35	4		T50	2		T17	3
auto[ReadAddrCrossAllMailbox]	219	1			T50	2		T17	1		T47	1
auto[ReadAddrOutsideMailbox]	3070	1			T2	6		T7	2		T12	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2027

1

T2

3

T7

1

T12

2

auto[1]

2099

1

T2

3

T7

1

T12

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	651	1			T12	2		T35	3		T50	2
read_ops[0x0b]	687	1			T2	2		T48	2		T55	2
read_ops[0x3b]	693	1			T2	2		T35	8		T55	2
read_ops[0x6b]	638	1			T7	2		T12	2		T41	2
read_ops[0xbb]	736	1			T2	2		T35	1		T50	4
read_ops[0xeb]	721	1			T41	2		T35	3		T48	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T50	1		T19	1		T60	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T50	1		T47	1		T21	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	9	1			T52	1		T271	1		T272	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T51	1		T19	1		T215	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T35	2		T152	2		T197	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T51	2		T19	1		T60	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T184	1		T254	1		T273	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T193	1		T152	1		T180	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	250	1			T12	1		T46	1		T17	7
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	249	1			T12	1		T35	1		T46	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T17	1		T51	2		T210	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T19	1		T103	1		T193	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T152	2		T206	1		T180	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T19	1		T193	2		T60	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	13	1			T60	1		T176	1		T206	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T215	1		T208	1		T238	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T50	1		T47	1		T60	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T50	1		T52	1		T19	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	244	1			T2	1		T48	1		T55	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T2	1		T48	1		T55	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T51	2		T21	1		T60	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T35	1		T52	1		T215	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T210	2		T60	1		T170	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T210	1		T60	2		T152	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T17	1		T47	1		T210	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T35	1		T51	1		T52	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T51	1		T52	1		T210	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T211	1		T274	1		T184	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	245	1			T2	1		T35	3		T55	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	264	1			T2	1		T35	3		T55	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T193	1		T65	1		T233	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T18	1		T47	1		T51	4
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T51	1		T197	1		T170	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T47	1		T21	1		T208	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T21	1		T193	1		T180	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T52	1		T19	1		T152	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T193	1		T152	1		T215	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T51	1		T19	1		T152	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	231	1			T7	1		T12	1		T41	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	220	1			T7	1		T12	1		T41	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T224	1		T170	1		T180	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T17	1		T51	1		T224	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T50	1		T17	2		T18	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T50	1		T17	1		T51	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T50	1		T17	2		T197	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T50	1		T152	1		T194	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T17	1		T210	1		T197	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T210	1		T215	1		T239	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T2	1		T17	7		T18	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	268	1			T2	1		T35	1		T17	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T65	1		T233	3		T215	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T35	2		T51	1		T19	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T60	1		T208	1		T275	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T18	1		T19	1		T238	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T47	1		T274	1		T170	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T35	1		T19	1		T152	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T211	1		T242	1		T180	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T211	1		T197	1		T170	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T41	1		T48	1		T46	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T41	1		T48	1		T46	2