Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 0 18 100.00
Crosses 128 0 128 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_data 8 0 8 100.00 100 1 1 0
cp_mask 8 0 8 100.00 100 1 1 0
cp_payload_swap_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 0 128 100.00 100 1 1 0


Summary for Variable cp_data

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_data

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 2923 1 T17 45 T47 43 T186 12
values[1] 3422 1 T2 16 T7 12 T12 18
values[2] 3475 1 T6 2 T17 23 T18 24
values[3] 4007 1 T10 4 T35 43 T50 8
values[4] 3541 1 T28 8 T35 25 T17 103
values[5] 2886 1 T34 16 T48 14 T55 4
values[6] 4103 1 T45 6 T74 2 T35 20
values[7] 3371 1 T3 2 T46 20 T17 55



Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 3815 1 T7 12 T41 10 T35 20
values[1] 3207 1 T10 4 T35 40 T17 26
values[2] 3343 1 T2 16 T6 2 T34 16
values[3] 3139 1 T12 18 T74 2 T28 8
values[4] 2894 1 T17 20 T18 25 T47 80
values[5] 3727 1 T17 119 T51 25 T19 20
values[6] 3504 1 T45 6 T55 4 T57 4
values[7] 4099 1 T3 2 T17 115 T47 24



Summary for Variable cp_payload_swap_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_payload_swap_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27024 1 T2 16 T3 2 T6 2
auto[1] 704 1 T35 1 T17 15 T18 9



Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_payload_swap_encp_datacp_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] values[0] 289 1 T60 20 T198 12 T33 20
auto[0] values[0] values[1] 310 1 T274 16 T184 25 T206 20
auto[0] values[0] values[2] 369 1 T170 51 T154 23 T236 25
auto[0] values[0] values[3] 240 1 T215 20 T261 6 T276 10
auto[0] values[0] values[4] 344 1 T47 42 T186 12 T197 20
auto[0] values[0] values[5] 435 1 T206 21 T213 20 T154 52
auto[0] values[0] values[6] 287 1 T197 20 T154 24 T218 47
auto[0] values[0] values[7] 567 1 T17 42 T193 20 T152 34
auto[0] values[1] values[0] 423 1 T7 12 T41 10 T51 33
auto[0] values[1] values[1] 370 1 T35 20 T17 26 T51 20
auto[0] values[1] values[2] 312 1 T2 16 T17 42 T268 12
auto[0] values[1] values[3] 332 1 T12 18 T49 4 T19 27
auto[0] values[1] values[4] 498 1 T17 19 T47 36 T266 22
auto[0] values[1] values[5] 410 1 T17 78 T238 22 T180 20
auto[0] values[1] values[6] 607 1 T219 20 T190 108 T170 26
auto[0] values[1] values[7] 388 1 T174 20 T219 21 T277 6
auto[0] values[2] values[0] 944 1 T18 24 T47 53 T51 21
auto[0] values[2] values[1] 371 1 T60 76 T264 2 T254 12
auto[0] values[2] values[2] 438 1 T6 2 T51 20 T152 44
auto[0] values[2] values[3] 294 1 T51 20 T19 20 T278 2
auto[0] values[2] values[4] 308 1 T210 20 T234 4 T208 20
auto[0] values[2] values[5] 290 1 T233 12 T155 35 T201 18
auto[0] values[2] values[6] 172 1 T51 20 T139 20 T272 20
auto[0] values[2] values[7] 577 1 T17 23 T47 24 T210 46
auto[0] values[3] values[0] 441 1 T50 8 T47 26 T51 17
auto[0] values[3] values[1] 394 1 T10 4 T35 20 T152 72
auto[0] values[3] values[2] 438 1 T35 23 T103 20 T152 18
auto[0] values[3] values[3] 423 1 T202 16 T69 2 T242 4
auto[0] values[3] values[4] 396 1 T215 106 T194 26 T201 70
auto[0] values[3] values[5] 388 1 T19 20 T279 10 T197 27
auto[0] values[3] values[6] 418 1 T17 28 T280 10 T250 12
auto[0] values[3] values[7] 982 1 T52 38 T60 25 T281 6
auto[0] values[4] values[0] 471 1 T17 45 T282 2 T257 6
auto[0] values[4] values[1] 594 1 T18 17 T52 36 T19 57
auto[0] values[4] values[2] 373 1 T52 32 T227 12 T231 6
auto[0] values[4] values[3] 550 1 T28 8 T35 25 T18 22
auto[0] values[4] values[4] 312 1 T18 22 T51 19 T19 21
auto[0] values[4] values[5] 430 1 T17 37 T210 27 T283 6
auto[0] values[4] values[6] 447 1 T193 18 T152 20 T194 56
auto[0] values[4] values[7] 270 1 T17 20 T230 19 T206 20
auto[0] values[5] values[0] 323 1 T53 8 T184 27 T185 47
auto[0] values[5] values[1] 314 1 T215 57 T265 24 T206 20
auto[0] values[5] values[2] 375 1 T34 16 T48 14 T175 16
auto[0] values[5] values[3] 664 1 T19 21 T215 93 T170 38
auto[0] values[5] values[4] 183 1 T170 20 T284 14 T229 20
auto[0] values[5] values[5] 413 1 T215 22 T206 19 T187 61
auto[0] values[5] values[6] 262 1 T55 4 T21 25 T103 20
auto[0] values[5] values[7] 275 1 T60 20 T152 20 T239 56
auto[0] values[6] values[0] 608 1 T35 19 T52 20 T60 20
auto[0] values[6] values[1] 583 1 T60 20 T215 20 T244 6
auto[0] values[6] values[2] 587 1 T17 20 T51 20 T193 26
auto[0] values[6] values[3] 238 1 T74 2 T237 10 T21 18
auto[0] values[6] values[4] 340 1 T152 38 T248 38 T184 20
auto[0] values[6] values[5] 607 1 T51 24 T207 16 T285 8
auto[0] values[6] values[6] 624 1 T45 6 T57 4 T17 37
auto[0] values[6] values[7] 429 1 T19 20 T103 19 T60 19
auto[0] values[7] values[0] 224 1 T17 27 T286 2 T287 14
auto[0] values[7] values[1] 199 1 T224 22 T213 42 T173 27
auto[0] values[7] values[2] 366 1 T46 20 T18 21 T103 15
auto[0] values[7] values[3] 307 1 T210 81 T184 20 T206 21
auto[0] values[7] values[4] 437 1 T210 22 T152 33 T154 27
auto[0] values[7] values[5] 678 1 T210 23 T170 45 T213 53
auto[0] values[7] values[6] 590 1 T47 29 T19 20 T288 8
auto[0] values[7] values[7] 496 1 T3 2 T17 27 T193 22
auto[1] values[0] values[0] 11 1 T176 1 T289 2 T269 6
auto[1] values[0] values[1] 7 1 T184 1 T83 2 T290 2
auto[1] values[0] values[2] 6 1 T201 2 T291 2 T292 1
auto[1] values[0] values[3] 10 1 T240 1 T196 1 T293 1
auto[1] values[0] values[4] 7 1 T47 1 T294 1 T63 2
auto[1] values[0] values[5] 12 1 T154 2 T226 2 T83 1
auto[1] values[0] values[6] 9 1 T197 1 T154 1 T218 2
auto[1] values[0] values[7] 20 1 T17 3 T152 1 T185 1
auto[1] values[1] values[0] 10 1 T51 2 T103 1 T185 1
auto[1] values[1] values[1] 11 1 T51 1 T193 1 T33 2
auto[1] values[1] values[2] 3 1 T60 2 T219 1 - -
auto[1] values[1] values[3] 15 1 T19 1 T170 1 T180 1
auto[1] values[1] values[4] 15 1 T17 1 T47 1 T184 1
auto[1] values[1] values[5] 5 1 T17 3 T226 1 T295 1
auto[1] values[1] values[6] 18 1 T219 1 T236 5 T296 1
auto[1] values[1] values[7] 5 1 T219 1 T206 1 T36 1
auto[1] values[2] values[0] 25 1 T47 1 T52 1 T54 6
auto[1] values[2] values[1] 6 1 T60 1 T214 2 T139 1
auto[1] values[2] values[2] 9 1 T152 2 T138 3 T297 1
auto[1] values[2] values[3] 1 1 T298 1 - - - -
auto[1] values[2] values[4] 7 1 T197 2 T154 1 T218 1
auto[1] values[2] values[5] 6 1 T201 2 T299 1 T300 2
auto[1] values[2] values[6] 10 1 T272 3 T263 3 T301 3
auto[1] values[2] values[7] 17 1 T210 1 T238 1 T185 1
auto[1] values[3] values[0] 12 1 T47 1 T51 3 T170 1
auto[1] values[3] values[1] 13 1 T197 1 T230 2 T176 2
auto[1] values[3] values[2] 23 1 T152 2 T208 2 T194 1
auto[1] values[3] values[3] 15 1 T206 1 T154 1 T229 2
auto[1] values[3] values[4] 9 1 T215 1 T194 2 T300 3
auto[1] values[3] values[5] 10 1 T197 4 T272 1 T302 3
auto[1] values[3] values[6] 11 1 T17 1 T253 1 T185 3
auto[1] values[3] values[7] 34 1 T52 2 T60 4 T184 1
auto[1] values[4] values[0] 9 1 T294 2 T290 3 T303 1
auto[1] values[4] values[1] 17 1 T18 3 T19 2 T208 2
auto[1] values[4] values[2] 11 1 T52 4 T218 1 T304 2
auto[1] values[4] values[3] 21 1 T47 2 T51 2 T206 2
auto[1] values[4] values[4] 9 1 T18 3 T51 1 T21 2
auto[1] values[4] values[5] 7 1 T17 1 T155 3 T229 2
auto[1] values[4] values[6] 11 1 T193 2 T194 2 T239 2
auto[1] values[4] values[7] 9 1 T230 1 T180 1 T236 2
auto[1] values[5] values[0] 10 1 T53 4 T185 1 T212 1
auto[1] values[5] values[1] 7 1 T215 1 T213 3 T305 2
auto[1] values[5] values[2] 3 1 T306 2 T307 1 - -
auto[1] values[5] values[3] 14 1 T19 1 T215 1 T170 2
auto[1] values[5] values[4] 7 1 T284 4 T195 3 - -
auto[1] values[5] values[5] 15 1 T215 1 T206 1 T241 5
auto[1] values[5] values[6] 13 1 T208 2 T308 2 T185 1
auto[1] values[5] values[7] 8 1 T239 5 T63 1 T295 2
auto[1] values[6] values[0] 11 1 T35 1 T215 1 T309 2
auto[1] values[6] values[1] 6 1 T155 2 T263 1 T310 2
auto[1] values[6] values[2] 15 1 T193 1 T180 4 T213 5
auto[1] values[6] values[3] 4 1 T21 2 T63 2 - -
auto[1] values[6] values[4] 11 1 T218 1 T240 1 T311 6
auto[1] values[6] values[5] 12 1 T51 1 T180 1 T300 1
auto[1] values[6] values[6] 14 1 T17 5 T47 2 T309 3
auto[1] values[6] values[7] 14 1 T103 1 T60 1 T170 1
auto[1] values[7] values[0] 4 1 T17 1 T240 2 T312 1
auto[1] values[7] values[1] 5 1 T192 1 T313 4 - -
auto[1] values[7] values[2] 15 1 T18 3 T103 5 T184 1
auto[1] values[7] values[3] 11 1 T210 5 T206 1 T154 3
auto[1] values[7] values[4] 11 1 T210 1 T152 4 T173 1
auto[1] values[7] values[5] 9 1 T210 2 T170 2 T213 1
auto[1] values[7] values[6] 11 1 T270 2 T218 1 T214 2
auto[1] values[7] values[7] 8 1 T193 1 T152 4 T314 1

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