Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	803	1			T14	11		T15	17		T16	11
all_values[1]	803	1			T14	11		T15	17		T16	11
all_values[2]	803	1			T14	11		T15	17		T16	11
all_values[3]	803	1			T14	11		T15	17		T16	11
all_values[4]	803	1			T14	11		T15	17		T16	11
all_values[5]	803	1			T14	11		T15	17		T16	11
all_values[6]	803	1			T14	11		T15	17		T16	11
all_values[7]	803	1			T14	11		T15	17		T16	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3444

1

T14

46

T15

80

T16

46

auto[1]

2980

1

T14

42

T15

56

T16

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2558

1

T14

34

T15

59

T16

46

auto[1]

3866

1

T14

54

T15

77

T16

42

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3674

1

T14

49

T15

82

T16

58

auto[1]

2750

1

T14

39

T15

54

T16

30

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	157	1			T15	5		T16	5		T17	2
all_values[0]	auto[0]	auto[0]	auto[1]	83	1			T14	1		T15	2		T19	3
all_values[0]	auto[0]	auto[1]	auto[0]	128	1			T14	3		T16	2		T17	2
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T15	3		T16	1		T20	3
all_values[0]	auto[1]	auto[0]	auto[1]	174	1			T14	2		T15	4		T17	1
all_values[0]	auto[1]	auto[1]	auto[1]	180	1			T14	5		T15	3		T16	3
all_values[1]	auto[0]	auto[0]	auto[0]	147	1			T14	1		T15	6		T19	1
all_values[1]	auto[0]	auto[0]	auto[1]	84	1			T14	3		T16	1		T19	1
all_values[1]	auto[0]	auto[1]	auto[0]	150	1			T14	2		T15	4		T16	2
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T14	1		T15	1		T16	1
all_values[1]	auto[1]	auto[0]	auto[1]	196	1			T14	3		T15	3		T16	5
all_values[1]	auto[1]	auto[1]	auto[1]	150	1			T14	1		T15	3		T16	2
all_values[2]	auto[0]	auto[0]	auto[0]	171	1			T14	1		T15	4		T16	1
all_values[2]	auto[0]	auto[0]	auto[1]	59	1			T14	1		T15	2		T17	2
all_values[2]	auto[0]	auto[1]	auto[0]	143	1			T14	2		T15	5		T16	5
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T14	1		T16	2		T19	2
all_values[2]	auto[1]	auto[0]	auto[1]	195	1			T14	2		T15	6		T16	1
all_values[2]	auto[1]	auto[1]	auto[1]	144	1			T14	4		T16	2		T19	1
all_values[3]	auto[0]	auto[0]	auto[0]	137	1			T14	3		T15	3		T16	1
all_values[3]	auto[0]	auto[0]	auto[1]	75	1			T14	1		T15	3		T16	1
all_values[3]	auto[0]	auto[1]	auto[0]	125	1			T14	2		T15	1		T16	4
all_values[3]	auto[0]	auto[1]	auto[1]	105	1			T14	1		T15	2		T16	2
all_values[3]	auto[1]	auto[0]	auto[1]	189	1			T14	2		T15	3		T16	1
all_values[3]	auto[1]	auto[1]	auto[1]	172	1			T14	2		T15	5		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	178	1			T14	3		T15	5		T16	6
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T14	1		T15	1		T19	1
all_values[4]	auto[0]	auto[1]	auto[0]	145	1			T14	2		T15	4		T16	1
all_values[4]	auto[0]	auto[1]	auto[1]	69	1			T15	1		T16	1		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	174	1			T14	4		T15	3		T16	3
all_values[4]	auto[1]	auto[1]	auto[1]	160	1			T14	1		T15	3		T20	2
all_values[5]	auto[0]	auto[0]	auto[0]	240	1			T14	4		T15	5		T16	6
all_values[5]	auto[0]	auto[1]	auto[0]	231	1			T14	4		T15	6		T16	3
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T14	1		T15	2		T17	2
all_values[5]	auto[1]	auto[1]	auto[1]	158	1			T14	2		T15	4		T16	2
all_values[6]	auto[0]	auto[0]	auto[0]	145	1			T14	1		T15	6		T16	3
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T14	1		T15	3		T16	2
all_values[6]	auto[0]	auto[1]	auto[0]	130	1			T14	1		T15	3		T16	1
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T14	3		T15	1		T17	1
all_values[6]	auto[1]	auto[0]	auto[1]	213	1			T14	4		T15	4		T16	4
all_values[6]	auto[1]	auto[1]	auto[1]	150	1			T14	1		T16	1		T19	1
all_values[7]	auto[0]	auto[0]	auto[0]	207	1			T14	3		T15	2		T16	2
all_values[7]	auto[0]	auto[0]	auto[1]	86	1			T14	1		T15	2		T16	1
all_values[7]	auto[0]	auto[1]	auto[0]	124	1			T14	2		T16	4		T17	1
all_values[7]	auto[0]	auto[1]	auto[1]	65	1			T15	2		T19	2		T20	2
all_values[7]	auto[1]	auto[0]	auto[1]	200	1			T14	3		T15	6		T16	3
all_values[7]	auto[1]	auto[1]	auto[1]	121	1			T14	2		T15	5		T16	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal