Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1798

1

T5

5

T8

7

T9

6

auto[1]

1785

1

T5

3

T8

5

T9

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1874

1

T9

10

T29

12

T31

6

auto[1]

1709

1

T5

8

T8

12

T9

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2833

1

T5

8

T8

12

T9

10

auto[1]

750

1

T9

3

T29

7

T31

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	669	1			T5	1		T8	3		T9	2
valid[1]	703	1			T8	2		T9	2		T29	3
valid[2]	740	1			T5	3		T8	2		T9	3
valid[3]	691	1			T5	2		T8	2		T9	2
valid[4]	780	1			T5	2		T8	3		T9	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	89	1			T9	1		T56	1		T17	2
auto[0]	auto[0]	valid[0]	auto[1]	180	1			T5	1		T8	1		T25	1
auto[0]	auto[0]	valid[1]	auto[0]	130	1			T9	1		T31	1		T14	2
auto[0]	auto[0]	valid[1]	auto[1]	175	1			T8	2		T9	1		T29	2
auto[0]	auto[0]	valid[2]	auto[0]	97	1			T29	1		T14	2		T56	1
auto[0]	auto[0]	valid[2]	auto[1]	169	1			T5	2		T31	1		T25	4
auto[0]	auto[0]	valid[3]	auto[0]	101	1			T9	1		T14	1		T24	1
auto[0]	auto[0]	valid[3]	auto[1]	149	1			T5	2		T8	1		T35	1
auto[0]	auto[0]	valid[4]	auto[0]	143	1			T9	1		T29	1		T14	2
auto[0]	auto[0]	valid[4]	auto[1]	194	1			T8	3		T29	1		T31	2
auto[0]	auto[1]	valid[0]	auto[0]	95	1			T9	1		T14	1		T16	1
auto[0]	auto[1]	valid[0]	auto[1]	176	1			T8	2		T31	1		T14	1
auto[0]	auto[1]	valid[1]	auto[0]	108	1			T29	1		T14	2		T17	1
auto[0]	auto[1]	valid[1]	auto[1]	159	1			T15	1		T25	1		T334	2
auto[0]	auto[1]	valid[2]	auto[0]	142	1			T9	1		T14	3		T35	4
auto[0]	auto[1]	valid[2]	auto[1]	153	1			T5	1		T8	2		T9	1
auto[0]	auto[1]	valid[3]	auto[0]	116	1			T31	1		T14	1		T15	1
auto[0]	auto[1]	valid[3]	auto[1]	175	1			T8	1		T31	2		T56	1
auto[0]	auto[1]	valid[4]	auto[0]	103	1			T9	1		T29	2		T14	1
auto[0]	auto[1]	valid[4]	auto[1]	179	1			T5	2		T9	1		T31	1
auto[1]	auto[0]	valid[0]	auto[0]	60	1			T14	1		T27	1		T35	1
auto[1]	auto[0]	valid[1]	auto[0]	66	1			T15	1		T94	2		T17	1
auto[1]	auto[0]	valid[2]	auto[0]	91	1			T29	1		T14	2		T16	1
auto[1]	auto[0]	valid[3]	auto[0]	68	1			T9	1		T14	1		T16	1
auto[1]	auto[0]	valid[4]	auto[0]	86	1			T29	3		T14	1		T16	3
auto[1]	auto[1]	valid[0]	auto[0]	69	1			T29	1		T16	2		T94	1
auto[1]	auto[1]	valid[1]	auto[0]	65	1			T31	3		T16	1		T17	1
auto[1]	auto[1]	valid[2]	auto[0]	88	1			T9	1		T14	1		T35	2
auto[1]	auto[1]	valid[3]	auto[0]	82	1			T29	1		T31	1		T14	1
auto[1]	auto[1]	valid[4]	auto[0]	75	1			T9	1		T29	1		T14	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal