Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48409

1

T9

285

T29

219

T31

207

auto[1]

17952

1

T5

8

T8

243

T9

41

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48757

1

T5

8

T8

243

T9

228

auto[1]

17604

1

T9

98

T29

85

T31

83

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34042	1			T5	8		T8	124		T9	167
others[1]	5588	1			T8	22		T9	30		T29	22
others[2]	5545	1			T8	18		T9	21		T29	25
others[3]	6446	1			T8	18		T9	28		T29	19
interest[1]	3742	1			T8	19		T9	26		T29	9
interest[4]	22310	1			T5	8		T8	91		T9	113
interest[64]	10998	1			T8	42		T9	54		T29	36

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15727	1			T9	103		T29	79		T31	65
auto[0]	auto[0]	others[1]	2611	1			T9	14		T29	11		T31	14
auto[0]	auto[0]	others[2]	2574	1			T9	11		T29	15		T31	13
auto[0]	auto[0]	others[3]	3050	1			T9	13		T29	7		T31	11
auto[0]	auto[0]	interest[1]	1754	1			T9	14		T29	5		T31	4
auto[0]	auto[0]	interest[4]	10237	1			T9	67		T29	52		T31	42
auto[0]	auto[0]	interest[64]	5089	1			T9	32		T29	17		T31	17
auto[0]	auto[1]	others[0]	9358	1			T5	8		T8	124		T9	19
auto[0]	auto[1]	others[1]	1488	1			T8	22		T9	6		T29	4
auto[0]	auto[1]	others[2]	1431	1			T8	18		T9	4		T29	2
auto[0]	auto[1]	others[3]	1649	1			T8	18		T9	5		T29	5
auto[0]	auto[1]	interest[1]	1033	1			T8	19		T9	4		T29	1
auto[0]	auto[1]	interest[4]	6248	1			T5	8		T8	91		T9	15
auto[0]	auto[1]	interest[64]	2993	1			T8	42		T9	3		T29	10
auto[1]	auto[0]	others[0]	8957	1			T9	45		T29	51		T31	44
auto[1]	auto[0]	others[1]	1489	1			T9	10		T29	7		T31	4
auto[1]	auto[0]	others[2]	1540	1			T9	6		T29	8		T31	10
auto[1]	auto[0]	others[3]	1747	1			T9	10		T29	7		T31	2
auto[1]	auto[0]	interest[1]	955	1			T9	8		T29	3		T31	3
auto[1]	auto[0]	interest[4]	5825	1			T9	31		T29	29		T31	26
auto[1]	auto[0]	interest[64]	2916	1			T9	19		T29	9		T31	20

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal