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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.45 94.08 98.62 89.36 97.29 95.43 99.26


Total test records in report: 1151
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T128 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.712630127 Jul 18 05:16:47 PM PDT 24 Jul 18 05:16:50 PM PDT 24 119964457 ps
T1036 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.821614626 Jul 18 05:17:13 PM PDT 24 Jul 18 05:17:17 PM PDT 24 31766440 ps
T110 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1654636132 Jul 18 05:16:38 PM PDT 24 Jul 18 05:16:47 PM PDT 24 65556160 ps
T1037 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.907905393 Jul 18 05:16:32 PM PDT 24 Jul 18 05:16:38 PM PDT 24 13916888 ps
T111 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.613692157 Jul 18 05:17:03 PM PDT 24 Jul 18 05:17:08 PM PDT 24 74774516 ps
T1038 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4004287484 Jul 18 05:16:33 PM PDT 24 Jul 18 05:16:39 PM PDT 24 40024368 ps
T1039 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3044504222 Jul 18 05:16:39 PM PDT 24 Jul 18 05:16:54 PM PDT 24 183864344 ps
T148 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.103471773 Jul 18 05:16:47 PM PDT 24 Jul 18 05:16:56 PM PDT 24 355161766 ps
T151 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2632921057 Jul 18 05:16:48 PM PDT 24 Jul 18 05:17:03 PM PDT 24 1899586282 ps
T121 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2820728027 Jul 18 05:16:54 PM PDT 24 Jul 18 05:17:15 PM PDT 24 589910142 ps
T112 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3429445100 Jul 18 05:16:53 PM PDT 24 Jul 18 05:16:58 PM PDT 24 53478613 ps
T122 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.11442663 Jul 18 05:16:53 PM PDT 24 Jul 18 05:17:03 PM PDT 24 367048902 ps
T1040 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3510247686 Jul 18 05:16:57 PM PDT 24 Jul 18 05:17:00 PM PDT 24 23116459 ps
T1041 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1622148667 Jul 18 05:16:54 PM PDT 24 Jul 18 05:16:58 PM PDT 24 222257458 ps
T1042 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2845080926 Jul 18 05:16:55 PM PDT 24 Jul 18 05:16:59 PM PDT 24 25844281 ps
T129 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.45924519 Jul 18 05:16:55 PM PDT 24 Jul 18 05:17:01 PM PDT 24 221635363 ps
T157 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1104488872 Jul 18 05:17:05 PM PDT 24 Jul 18 05:17:07 PM PDT 24 54724514 ps
T1043 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.209800834 Jul 18 05:16:54 PM PDT 24 Jul 18 05:16:56 PM PDT 24 14103732 ps
T130 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4241351055 Jul 18 05:17:01 PM PDT 24 Jul 18 05:17:04 PM PDT 24 32676700 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1358765643 Jul 18 05:16:37 PM PDT 24 Jul 18 05:16:53 PM PDT 24 190815963 ps
T1045 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.784576428 Jul 18 05:17:11 PM PDT 24 Jul 18 05:17:16 PM PDT 24 353800724 ps
T1046 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.386789820 Jul 18 05:17:01 PM PDT 24 Jul 18 05:17:04 PM PDT 24 97227412 ps
T1047 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1611576338 Jul 18 05:16:54 PM PDT 24 Jul 18 05:16:59 PM PDT 24 105284554 ps
T1048 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.97002089 Jul 18 05:17:01 PM PDT 24 Jul 18 05:17:04 PM PDT 24 53203180 ps
T1049 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2959934836 Jul 18 05:17:13 PM PDT 24 Jul 18 05:17:17 PM PDT 24 54284337 ps
T1050 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1955991715 Jul 18 05:17:13 PM PDT 24 Jul 18 05:17:17 PM PDT 24 16673623 ps
T131 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2240077151 Jul 18 05:17:11 PM PDT 24 Jul 18 05:17:16 PM PDT 24 98954639 ps
T1051 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2928484327 Jul 18 05:16:32 PM PDT 24 Jul 18 05:16:38 PM PDT 24 20749421 ps
T159 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3046953405 Jul 18 05:16:51 PM PDT 24 Jul 18 05:17:10 PM PDT 24 3973930794 ps
T1052 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3963028224 Jul 18 05:16:55 PM PDT 24 Jul 18 05:16:58 PM PDT 24 13160110 ps
T1053 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2561115639 Jul 18 05:16:55 PM PDT 24 Jul 18 05:16:59 PM PDT 24 145279671 ps
T89 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2087590823 Jul 18 05:16:33 PM PDT 24 Jul 18 05:16:39 PM PDT 24 33253717 ps
T132 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1257639551 Jul 18 05:16:34 PM PDT 24 Jul 18 05:16:42 PM PDT 24 66626516 ps
T133 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1042767697 Jul 18 05:16:55 PM PDT 24 Jul 18 05:16:59 PM PDT 24 20955508 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.451231181 Jul 18 05:16:29 PM PDT 24 Jul 18 05:16:38 PM PDT 24 1364643231 ps
T1055 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2763225770 Jul 18 05:16:33 PM PDT 24 Jul 18 05:16:43 PM PDT 24 160497441 ps
T1056 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1265398905 Jul 18 05:16:38 PM PDT 24 Jul 18 05:16:44 PM PDT 24 41007273 ps
T1057 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4038846161 Jul 18 05:17:11 PM PDT 24 Jul 18 05:17:15 PM PDT 24 37902066 ps
T162 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3101109609 Jul 18 05:16:57 PM PDT 24 Jul 18 05:17:11 PM PDT 24 1782717715 ps
T1058 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.192176356 Jul 18 05:17:10 PM PDT 24 Jul 18 05:17:13 PM PDT 24 45768153 ps
T1059 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1735768776 Jul 18 05:16:54 PM PDT 24 Jul 18 05:17:04 PM PDT 24 456358226 ps
T114 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3830079629 Jul 18 05:16:56 PM PDT 24 Jul 18 05:17:03 PM PDT 24 704460741 ps
T1060 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2422131697 Jul 18 05:16:46 PM PDT 24 Jul 18 05:16:48 PM PDT 24 30035557 ps
T134 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1305591455 Jul 18 05:16:55 PM PDT 24 Jul 18 05:17:01 PM PDT 24 137190932 ps
T117 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2716484433 Jul 18 05:16:50 PM PDT 24 Jul 18 05:16:53 PM PDT 24 81874478 ps
T1061 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3390681677 Jul 18 05:16:39 PM PDT 24 Jul 18 05:16:45 PM PDT 24 124197451 ps
T1062 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3763351193 Jul 18 05:17:12 PM PDT 24 Jul 18 05:17:16 PM PDT 24 12075389 ps
T1063 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.43699289 Jul 18 05:26:06 PM PDT 24 Jul 18 05:26:13 PM PDT 24 252406104 ps
T1064 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2305707983 Jul 18 05:16:49 PM PDT 24 Jul 18 05:16:50 PM PDT 24 23824756 ps
T116 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.114738791 Jul 18 05:17:01 PM PDT 24 Jul 18 05:17:05 PM PDT 24 140143055 ps
T163 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3901116197 Jul 18 05:16:54 PM PDT 24 Jul 18 05:17:16 PM PDT 24 572375957 ps
T1065 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2587967980 Jul 18 05:17:12 PM PDT 24 Jul 18 05:17:16 PM PDT 24 14696597 ps
T1066 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2116125681 Jul 18 05:16:52 PM PDT 24 Jul 18 05:16:57 PM PDT 24 344632751 ps
T1067 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2024823448 Jul 18 05:17:10 PM PDT 24 Jul 18 05:17:13 PM PDT 24 304140393 ps
T115 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3102846660 Jul 18 05:16:54 PM PDT 24 Jul 18 05:17:00 PM PDT 24 199015877 ps
T1068 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1695244749 Jul 18 05:16:40 PM PDT 24 Jul 18 05:16:48 PM PDT 24 817308362 ps
T1069 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1356545970 Jul 18 05:16:53 PM PDT 24 Jul 18 05:16:56 PM PDT 24 162668501 ps
T1070 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.973326013 Jul 18 05:16:49 PM PDT 24 Jul 18 05:16:55 PM PDT 24 216958180 ps
T135 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3939341767 Jul 18 05:16:44 PM PDT 24 Jul 18 05:17:08 PM PDT 24 4489619607 ps
T1071 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.762166259 Jul 18 05:17:10 PM PDT 24 Jul 18 05:17:12 PM PDT 24 66431748 ps
T1072 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.891024969 Jul 18 05:17:08 PM PDT 24 Jul 18 05:17:09 PM PDT 24 42716837 ps
T1073 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2595635121 Jul 18 05:16:53 PM PDT 24 Jul 18 05:16:56 PM PDT 24 12761220 ps
T113 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.628177492 Jul 18 05:16:55 PM PDT 24 Jul 18 05:17:04 PM PDT 24 595883402 ps
T1074 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2523157436 Jul 18 05:16:55 PM PDT 24 Jul 18 05:17:03 PM PDT 24 62892661 ps
T118 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3992653976 Jul 18 05:16:32 PM PDT 24 Jul 18 05:16:42 PM PDT 24 1019746594 ps
T160 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3082587402 Jul 18 05:16:52 PM PDT 24 Jul 18 05:17:00 PM PDT 24 212518213 ps
T1075 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2059642923 Jul 18 05:16:39 PM PDT 24 Jul 18 05:17:04 PM PDT 24 332921865 ps
T1076 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1701360206 Jul 18 05:16:32 PM PDT 24 Jul 18 05:16:46 PM PDT 24 1850641373 ps
T136 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.861210781 Jul 18 05:16:30 PM PDT 24 Jul 18 05:16:36 PM PDT 24 82418275 ps
T1077 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1000176027 Jul 18 05:16:39 PM PDT 24 Jul 18 05:16:46 PM PDT 24 201152335 ps
T1078 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2441884119 Jul 18 05:17:12 PM PDT 24 Jul 18 05:17:17 PM PDT 24 11248136 ps
T1079 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.288924565 Jul 18 05:16:39 PM PDT 24 Jul 18 05:16:46 PM PDT 24 41521667 ps
T90 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2028865061 Jul 18 05:16:37 PM PDT 24 Jul 18 05:16:43 PM PDT 24 15010063 ps
T1080 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2702201 Jul 18 05:16:55 PM PDT 24 Jul 18 05:17:00 PM PDT 24 64745630 ps
T1081 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3906030947 Jul 18 05:17:06 PM PDT 24 Jul 18 05:17:20 PM PDT 24 199961966 ps
T1082 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1501400419 Jul 18 05:17:12 PM PDT 24 Jul 18 05:17:17 PM PDT 24 13018609 ps
T1083 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1742908071 Jul 18 05:17:00 PM PDT 24 Jul 18 05:17:09 PM PDT 24 592965905 ps
T1084 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2847964815 Jul 18 05:17:12 PM PDT 24 Jul 18 05:17:16 PM PDT 24 15815774 ps
T1085 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2957416475 Jul 18 05:16:47 PM PDT 24 Jul 18 05:16:51 PM PDT 24 283478722 ps
T1086 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3398570223 Jul 18 05:16:48 PM PDT 24 Jul 18 05:16:56 PM PDT 24 198655081 ps
T1087 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2801176806 Jul 18 05:17:14 PM PDT 24 Jul 18 05:17:18 PM PDT 24 55076739 ps
T1088 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.582724054 Jul 18 05:17:13 PM PDT 24 Jul 18 05:17:18 PM PDT 24 25968346 ps
T91 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1034000635 Jul 18 05:16:39 PM PDT 24 Jul 18 05:16:44 PM PDT 24 27008258 ps
T1089 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1495835216 Jul 18 05:16:35 PM PDT 24 Jul 18 05:16:42 PM PDT 24 247675298 ps
T1090 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2207277932 Jul 18 05:17:13 PM PDT 24 Jul 18 05:17:17 PM PDT 24 43831901 ps
T1091 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3889649075 Jul 18 05:16:38 PM PDT 24 Jul 18 05:17:00 PM PDT 24 3462062021 ps
T1092 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.67886657 Jul 18 05:17:04 PM PDT 24 Jul 18 05:17:06 PM PDT 24 36697222 ps
T161 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.180796994 Jul 18 05:17:12 PM PDT 24 Jul 18 05:17:27 PM PDT 24 2381485253 ps
T1093 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4127187277 Jul 18 05:16:32 PM PDT 24 Jul 18 05:16:38 PM PDT 24 12377321 ps
T1094 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3074745065 Jul 18 05:16:32 PM PDT 24 Jul 18 05:17:00 PM PDT 24 1362534379 ps
T158 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3546020623 Jul 18 05:16:54 PM PDT 24 Jul 18 05:17:00 PM PDT 24 303334123 ps
T1095 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3670115425 Jul 18 05:16:52 PM PDT 24 Jul 18 05:16:55 PM PDT 24 37313114 ps
T1096 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3390356497 Jul 18 05:17:04 PM PDT 24 Jul 18 05:17:06 PM PDT 24 20170576 ps
T1097 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.984865883 Jul 18 05:16:54 PM PDT 24 Jul 18 05:17:00 PM PDT 24 142746560 ps
T1098 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1150018221 Jul 18 05:17:11 PM PDT 24 Jul 18 05:17:15 PM PDT 24 19560126 ps
T1099 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.479204412 Jul 18 05:17:09 PM PDT 24 Jul 18 05:17:10 PM PDT 24 26099361 ps
T1100 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1621537383 Jul 18 05:16:35 PM PDT 24 Jul 18 05:16:41 PM PDT 24 21088660 ps
T1101 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1855027470 Jul 18 05:16:50 PM PDT 24 Jul 18 05:16:53 PM PDT 24 100903121 ps
T1102 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1628596704 Jul 18 05:16:52 PM PDT 24 Jul 18 05:16:56 PM PDT 24 197230867 ps
T1103 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2541796281 Jul 18 05:17:08 PM PDT 24 Jul 18 05:17:10 PM PDT 24 16491842 ps
T1104 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.179602170 Jul 18 05:17:00 PM PDT 24 Jul 18 05:17:04 PM PDT 24 134056742 ps
T93 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3214354904 Jul 18 05:16:44 PM PDT 24 Jul 18 05:16:47 PM PDT 24 36605018 ps
T1105 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3307308652 Jul 18 05:16:39 PM PDT 24 Jul 18 05:16:46 PM PDT 24 95223298 ps
T1106 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2126828466 Jul 18 05:16:43 PM PDT 24 Jul 18 05:16:46 PM PDT 24 49070551 ps
T1107 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2435634851 Jul 18 05:17:05 PM PDT 24 Jul 18 05:17:21 PM PDT 24 6232492993 ps
T1108 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3711978622 Jul 18 05:17:13 PM PDT 24 Jul 18 05:17:17 PM PDT 24 16853918 ps
T1109 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1703777977 Jul 18 05:16:53 PM PDT 24 Jul 18 05:16:58 PM PDT 24 113889164 ps
T1110 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.762256377 Jul 18 05:17:11 PM PDT 24 Jul 18 05:17:14 PM PDT 24 23457608 ps
T1111 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3891658351 Jul 18 05:17:09 PM PDT 24 Jul 18 05:17:10 PM PDT 24 13373667 ps
T1112 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.890263112 Jul 18 05:16:54 PM PDT 24 Jul 18 05:16:57 PM PDT 24 24740832 ps
T1113 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3631968794 Jul 18 05:17:05 PM PDT 24 Jul 18 05:17:07 PM PDT 24 44371490 ps
T1114 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.241745534 Jul 18 05:17:04 PM PDT 24 Jul 18 05:17:06 PM PDT 24 37362152 ps
T1115 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3507603854 Jul 18 05:16:48 PM PDT 24 Jul 18 05:16:51 PM PDT 24 167021647 ps
T1116 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2308332187 Jul 18 05:16:55 PM PDT 24 Jul 18 05:17:03 PM PDT 24 1288955414 ps
T1117 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1602728850 Jul 18 05:17:05 PM PDT 24 Jul 18 05:17:07 PM PDT 24 54392747 ps
T1118 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3038431188 Jul 18 05:16:52 PM PDT 24 Jul 18 05:16:54 PM PDT 24 28444552 ps
T1119 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.702748478 Jul 18 05:16:35 PM PDT 24 Jul 18 05:16:48 PM PDT 24 115190039 ps
T1120 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4071079506 Jul 18 05:16:39 PM PDT 24 Jul 18 05:16:45 PM PDT 24 70889948 ps
T1121 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2253659285 Jul 18 05:16:29 PM PDT 24 Jul 18 05:16:35 PM PDT 24 333155703 ps
T1122 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1971395649 Jul 18 05:16:51 PM PDT 24 Jul 18 05:16:56 PM PDT 24 116981411 ps
T1123 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.921172809 Jul 18 05:17:12 PM PDT 24 Jul 18 05:17:17 PM PDT 24 36204175 ps
T1124 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4172918968 Jul 18 05:16:33 PM PDT 24 Jul 18 05:16:41 PM PDT 24 310771410 ps
T1125 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.758448463 Jul 18 05:16:35 PM PDT 24 Jul 18 05:16:55 PM PDT 24 1257261697 ps
T1126 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1692305161 Jul 18 05:17:05 PM PDT 24 Jul 18 05:17:09 PM PDT 24 661277907 ps
T1127 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2901098327 Jul 18 05:17:12 PM PDT 24 Jul 18 05:17:16 PM PDT 24 35881528 ps
T1128 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1612152149 Jul 18 05:16:54 PM PDT 24 Jul 18 05:16:56 PM PDT 24 35561312 ps
T1129 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.647058521 Jul 18 05:17:10 PM PDT 24 Jul 18 05:17:13 PM PDT 24 100899358 ps
T1130 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2876748532 Jul 18 05:16:40 PM PDT 24 Jul 18 05:16:47 PM PDT 24 534774392 ps
T1131 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.127908476 Jul 18 05:17:02 PM PDT 24 Jul 18 05:17:07 PM PDT 24 339325264 ps
T1132 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3949167813 Jul 18 05:16:50 PM PDT 24 Jul 18 05:16:56 PM PDT 24 607145278 ps
T1133 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1968326872 Jul 18 05:17:08 PM PDT 24 Jul 18 05:17:11 PM PDT 24 27649070 ps
T1134 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2886821763 Jul 18 05:16:40 PM PDT 24 Jul 18 05:16:44 PM PDT 24 10693671 ps
T1135 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.241597331 Jul 18 05:16:33 PM PDT 24 Jul 18 05:16:41 PM PDT 24 28272540 ps
T1136 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3461625364 Jul 18 05:16:54 PM PDT 24 Jul 18 05:16:57 PM PDT 24 118458452 ps
T1137 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1841918241 Jul 18 05:17:12 PM PDT 24 Jul 18 05:17:16 PM PDT 24 19809961 ps
T1138 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3907925604 Jul 18 05:17:04 PM PDT 24 Jul 18 05:17:07 PM PDT 24 159246255 ps
T1139 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3084782556 Jul 18 05:17:10 PM PDT 24 Jul 18 05:17:13 PM PDT 24 84010016 ps
T1140 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3349434520 Jul 18 05:16:55 PM PDT 24 Jul 18 05:17:00 PM PDT 24 22284844 ps
T1141 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.164536318 Jul 18 05:17:11 PM PDT 24 Jul 18 05:17:15 PM PDT 24 18978319 ps
T1142 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3265494352 Jul 18 05:17:12 PM PDT 24 Jul 18 05:17:16 PM PDT 24 47214462 ps
T1143 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.82261711 Jul 18 05:16:30 PM PDT 24 Jul 18 05:16:38 PM PDT 24 518648265 ps
T1144 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1646603799 Jul 18 05:17:00 PM PDT 24 Jul 18 05:17:03 PM PDT 24 13916799 ps
T1145 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3606119705 Jul 18 05:16:49 PM PDT 24 Jul 18 05:16:51 PM PDT 24 17671738 ps
T1146 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.349952729 Jul 18 05:17:06 PM PDT 24 Jul 18 05:17:11 PM PDT 24 321995162 ps
T1147 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2073157108 Jul 18 05:16:35 PM PDT 24 Jul 18 05:16:42 PM PDT 24 48144321 ps
T164 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2537528857 Jul 18 05:16:38 PM PDT 24 Jul 18 05:17:07 PM PDT 24 6058646078 ps
T1148 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4166746349 Jul 18 05:16:30 PM PDT 24 Jul 18 05:16:35 PM PDT 24 132924161 ps
T1149 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3575239233 Jul 18 05:16:34 PM PDT 24 Jul 18 05:17:04 PM PDT 24 5577705023 ps
T1150 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1981107829 Jul 18 05:16:49 PM PDT 24 Jul 18 05:16:51 PM PDT 24 13246637 ps
T1151 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4263604130 Jul 18 05:17:14 PM PDT 24 Jul 18 05:17:18 PM PDT 24 90133761 ps
T92 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2397891502 Jul 18 05:16:32 PM PDT 24 Jul 18 05:16:38 PM PDT 24 66930033 ps

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3550876603
Short name T9
Test name
Test status
Simulation time 13115062015 ps
CPU time 114.75 seconds
Started Jul 18 05:23:47 PM PDT 24
Finished Jul 18 05:25:44 PM PDT 24
Peak memory 246256 kb
Host smart-7e2caa97-190b-4313-b531-ee780ec5ce20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550876603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3550876603
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.4176378567
Short name T35
Test name
Test status
Simulation time 16551517653 ps
CPU time 180.13 seconds
Started Jul 18 05:24:38 PM PDT 24
Finished Jul 18 05:27:40 PM PDT 24
Peak memory 249696 kb
Host smart-7c912f4f-76de-490d-9c66-c091790d7632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176378567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4176378567
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.145322849
Short name T17
Test name
Test status
Simulation time 210585770838 ps
CPU time 531.58 seconds
Started Jul 18 05:24:46 PM PDT 24
Finished Jul 18 05:33:40 PM PDT 24
Peak memory 274224 kb
Host smart-0c823b47-6c1a-4fcd-892d-247f8257a6d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145322849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.145322849
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2707724722
Short name T109
Test name
Test status
Simulation time 2169151486 ps
CPU time 23.45 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:17:21 PM PDT 24
Peak memory 217656 kb
Host smart-1957cc7a-6f48-4665-b66b-c5396367061a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707724722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2707724722
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.4029537584
Short name T152
Test name
Test status
Simulation time 254082535274 ps
CPU time 414.61 seconds
Started Jul 18 05:20:57 PM PDT 24
Finished Jul 18 05:27:53 PM PDT 24
Peak memory 290520 kb
Host smart-24352a21-fbd8-4617-8446-f28b65933ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029537584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.4029537584
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3228353573
Short name T73
Test name
Test status
Simulation time 18849388 ps
CPU time 0.78 seconds
Started Jul 18 05:18:39 PM PDT 24
Finished Jul 18 05:18:42 PM PDT 24
Peak memory 216452 kb
Host smart-e8026758-f2ce-4802-8104-743b6a26a7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228353573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3228353573
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2234563455
Short name T19
Test name
Test status
Simulation time 170214453992 ps
CPU time 312.29 seconds
Started Jul 18 05:23:44 PM PDT 24
Finished Jul 18 05:28:58 PM PDT 24
Peak memory 252160 kb
Host smart-3dfc6622-aa35-4b01-937a-49d5938f7f6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234563455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2234563455
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1394376575
Short name T7
Test name
Test status
Simulation time 9209314324 ps
CPU time 15.31 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:26:03 PM PDT 24
Peak memory 241260 kb
Host smart-192f59a5-9362-4ff0-89b6-03b2c932d6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394376575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1394376575
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2129476739
Short name T154
Test name
Test status
Simulation time 91095481648 ps
CPU time 882.38 seconds
Started Jul 18 05:23:45 PM PDT 24
Finished Jul 18 05:38:29 PM PDT 24
Peak memory 283464 kb
Host smart-25fdfc6f-ce9f-4d07-b385-6cb8d617b5fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129476739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2129476739
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3050080152
Short name T51
Test name
Test status
Simulation time 337949188817 ps
CPU time 712.44 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:37:40 PM PDT 24
Peak memory 266864 kb
Host smart-fadd8a0d-5ca0-418c-bc9e-059746d310f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050080152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3050080152
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.185268380
Short name T60
Test name
Test status
Simulation time 11350712690 ps
CPU time 113.1 seconds
Started Jul 18 05:23:55 PM PDT 24
Finished Jul 18 05:25:49 PM PDT 24
Peak memory 257020 kb
Host smart-f635c5a2-9e61-44f5-a18c-628827e40d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185268380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.185268380
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1288706784
Short name T145
Test name
Test status
Simulation time 3814319840 ps
CPU time 62.48 seconds
Started Jul 18 05:23:30 PM PDT 24
Finished Jul 18 05:24:34 PM PDT 24
Peak memory 235860 kb
Host smart-de6dee20-d9d0-40c6-9b7b-4d1220f868bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288706784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1288706784
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3542709679
Short name T352
Test name
Test status
Simulation time 29132546 ps
CPU time 0.75 seconds
Started Jul 18 05:19:33 PM PDT 24
Finished Jul 18 05:19:38 PM PDT 24
Peak memory 205704 kb
Host smart-0003efad-6f21-4886-bcf9-a7bc16068dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542709679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
542709679
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.708664550
Short name T108
Test name
Test status
Simulation time 2406665215 ps
CPU time 4.05 seconds
Started Jul 18 05:16:51 PM PDT 24
Finished Jul 18 05:16:56 PM PDT 24
Peak memory 217372 kb
Host smart-c4fac319-9bdf-47a6-8c64-f4b66fe1f70e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708664550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.708664550
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.801698041
Short name T52
Test name
Test status
Simulation time 12297351554 ps
CPU time 67.44 seconds
Started Jul 18 05:23:32 PM PDT 24
Finished Jul 18 05:24:41 PM PDT 24
Peak memory 256724 kb
Host smart-6a194773-7f4c-4210-a5da-1ae69db46d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801698041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.801698041
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1343808721
Short name T184
Test name
Test status
Simulation time 141183203711 ps
CPU time 646.68 seconds
Started Jul 18 05:24:51 PM PDT 24
Finished Jul 18 05:35:39 PM PDT 24
Peak memory 273764 kb
Host smart-0d6181ab-f127-45f3-8db4-5b18e34d26bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343808721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1343808721
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3251674289
Short name T219
Test name
Test status
Simulation time 83719329481 ps
CPU time 342.03 seconds
Started Jul 18 05:34:56 PM PDT 24
Finished Jul 18 05:40:41 PM PDT 24
Peak memory 249540 kb
Host smart-52a8ad04-45a5-4538-8c0f-5d8923aeae2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251674289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3251674289
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.712630127
Short name T128
Test name
Test status
Simulation time 119964457 ps
CPU time 2.22 seconds
Started Jul 18 05:16:47 PM PDT 24
Finished Jul 18 05:16:50 PM PDT 24
Peak memory 215984 kb
Host smart-69123eb5-e1be-435f-95d0-6f6f9ca13b6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712630127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.712630127
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1532113388
Short name T201
Test name
Test status
Simulation time 46502480769 ps
CPU time 316.12 seconds
Started Jul 18 05:25:19 PM PDT 24
Finished Jul 18 05:30:36 PM PDT 24
Peak memory 251608 kb
Host smart-0d6dad5f-59d0-4145-b8d4-f31f07c71fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532113388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1532113388
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2163347362
Short name T240
Test name
Test status
Simulation time 135937353641 ps
CPU time 252.1 seconds
Started Jul 18 05:24:18 PM PDT 24
Finished Jul 18 05:28:31 PM PDT 24
Peak memory 250640 kb
Host smart-1f267566-a5a5-4a46-ad30-4be825c3545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163347362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2163347362
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3091222424
Short name T37
Test name
Test status
Simulation time 16583527 ps
CPU time 1.02 seconds
Started Jul 18 05:18:37 PM PDT 24
Finished Jul 18 05:18:40 PM PDT 24
Peak memory 217112 kb
Host smart-04492d2f-12e5-43d2-b4fb-08976cacfcf9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091222424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3091222424
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3015870720
Short name T77
Test name
Test status
Simulation time 395387119 ps
CPU time 1.1 seconds
Started Jul 18 05:18:45 PM PDT 24
Finished Jul 18 05:18:48 PM PDT 24
Peak memory 235852 kb
Host smart-52a8b579-c2ff-48b2-91dc-9ff16d9bc84c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015870720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3015870720
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1027429591
Short name T229
Test name
Test status
Simulation time 28415631102 ps
CPU time 218.73 seconds
Started Jul 18 05:21:19 PM PDT 24
Finished Jul 18 05:24:58 PM PDT 24
Peak memory 257012 kb
Host smart-2fab6494-b405-4a3e-b6bf-c30736f51407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027429591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1027429591
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.872076940
Short name T300
Test name
Test status
Simulation time 305649022737 ps
CPU time 574.31 seconds
Started Jul 18 05:23:00 PM PDT 24
Finished Jul 18 05:32:35 PM PDT 24
Peak memory 265428 kb
Host smart-b366dc74-f3d4-4be5-a4dc-783f596e6b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872076940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.872076940
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.4205489397
Short name T14
Test name
Test status
Simulation time 12060649414 ps
CPU time 130.47 seconds
Started Jul 18 05:24:40 PM PDT 24
Finished Jul 18 05:26:52 PM PDT 24
Peak memory 257684 kb
Host smart-63a4776d-e171-424a-9d23-148be5d0e975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205489397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.4205489397
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.4242899405
Short name T294
Test name
Test status
Simulation time 31020688553 ps
CPU time 271.09 seconds
Started Jul 18 05:23:27 PM PDT 24
Finished Jul 18 05:28:00 PM PDT 24
Peak memory 267796 kb
Host smart-73ede7a0-42fd-42c3-8311-5a6eac3eba98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242899405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.4242899405
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.276098024
Short name T262
Test name
Test status
Simulation time 22916228635 ps
CPU time 37.79 seconds
Started Jul 18 05:24:33 PM PDT 24
Finished Jul 18 05:25:14 PM PDT 24
Peak memory 253000 kb
Host smart-b1aef43d-05c0-4f45-8d4d-de5fc669b0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276098024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.276098024
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3046953405
Short name T159
Test name
Test status
Simulation time 3973930794 ps
CPU time 18.5 seconds
Started Jul 18 05:16:51 PM PDT 24
Finished Jul 18 05:17:10 PM PDT 24
Peak memory 216288 kb
Host smart-5a501656-e23c-434c-b68a-eddc5201226a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046953405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3046953405
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.581994796
Short name T185
Test name
Test status
Simulation time 46838035528 ps
CPU time 392.74 seconds
Started Jul 18 05:24:15 PM PDT 24
Finished Jul 18 05:30:49 PM PDT 24
Peak memory 254180 kb
Host smart-c7c87951-dda7-4713-bc53-ef2e835fa918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581994796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.581994796
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.858964178
Short name T192
Test name
Test status
Simulation time 100502587290 ps
CPU time 444.13 seconds
Started Jul 18 05:25:08 PM PDT 24
Finished Jul 18 05:32:35 PM PDT 24
Peak memory 256216 kb
Host smart-059a4aa4-5277-400d-9cd7-fe71260a9cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858964178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.858964178
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3643605364
Short name T21
Test name
Test status
Simulation time 3958573749 ps
CPU time 49.29 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:26:13 PM PDT 24
Peak memory 257384 kb
Host smart-cf8d3e94-cbb9-4727-8691-faeb628ea1a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643605364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3643605364
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1916657490
Short name T215
Test name
Test status
Simulation time 30173556995 ps
CPU time 96.08 seconds
Started Jul 18 05:22:33 PM PDT 24
Finished Jul 18 05:24:10 PM PDT 24
Peak memory 249608 kb
Host smart-a0381ea1-9696-4ba9-841a-728c357e1686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916657490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1916657490
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.32733200
Short name T329
Test name
Test status
Simulation time 8206967291 ps
CPU time 44.18 seconds
Started Jul 18 05:23:26 PM PDT 24
Finished Jul 18 05:24:11 PM PDT 24
Peak memory 249664 kb
Host smart-cafe8972-d3dd-4cad-af27-e65bcb7b264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32733200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.32733200
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1472981984
Short name T609
Test name
Test status
Simulation time 15784539988 ps
CPU time 20.36 seconds
Started Jul 18 05:24:34 PM PDT 24
Finished Jul 18 05:24:57 PM PDT 24
Peak memory 225004 kb
Host smart-1fb659f0-75ae-48bf-8709-19c4dca4c6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472981984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1472981984
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4105541398
Short name T15
Test name
Test status
Simulation time 2789612873 ps
CPU time 62.07 seconds
Started Jul 18 05:21:15 PM PDT 24
Finished Jul 18 05:22:18 PM PDT 24
Peak memory 257868 kb
Host smart-ff345909-935e-4c21-a488-566674183f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105541398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4105541398
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3142066826
Short name T99
Test name
Test status
Simulation time 1087885879 ps
CPU time 6.32 seconds
Started Jul 18 05:20:06 PM PDT 24
Finished Jul 18 05:20:14 PM PDT 24
Peak memory 224996 kb
Host smart-ac173e38-bd2b-4568-a68b-a8afef52f5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142066826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3142066826
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3992653976
Short name T118
Test name
Test status
Simulation time 1019746594 ps
CPU time 4.26 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:16:42 PM PDT 24
Peak memory 216352 kb
Host smart-f06dcd10-4890-4372-ab40-6aa5407dacc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992653976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
992653976
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3082587402
Short name T160
Test name
Test status
Simulation time 212518213 ps
CPU time 6.46 seconds
Started Jul 18 05:16:52 PM PDT 24
Finished Jul 18 05:17:00 PM PDT 24
Peak memory 216000 kb
Host smart-8dcef44c-ab8a-445c-86ac-d8712f23b07d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082587402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3082587402
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1107917685
Short name T269
Test name
Test status
Simulation time 71834014821 ps
CPU time 131.52 seconds
Started Jul 18 05:19:32 PM PDT 24
Finished Jul 18 05:21:46 PM PDT 24
Peak memory 267640 kb
Host smart-eeaf81a8-2ab4-4709-9ad1-9d0efc0176f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107917685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1107917685
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.383388843
Short name T180
Test name
Test status
Simulation time 147610302155 ps
CPU time 284.62 seconds
Started Jul 18 05:23:04 PM PDT 24
Finished Jul 18 05:27:50 PM PDT 24
Peak memory 252560 kb
Host smart-1e39866a-464d-497d-8aee-39565975af53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383388843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.383388843
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1516346156
Short name T298
Test name
Test status
Simulation time 11776667231 ps
CPU time 198.13 seconds
Started Jul 18 05:23:04 PM PDT 24
Finished Jul 18 05:26:23 PM PDT 24
Peak memory 267472 kb
Host smart-e65eb035-06c9-424c-b95c-add40c861b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516346156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1516346156
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.242046818
Short name T306
Test name
Test status
Simulation time 32165156213 ps
CPU time 84.01 seconds
Started Jul 18 05:24:15 PM PDT 24
Finished Jul 18 05:25:40 PM PDT 24
Peak memory 239980 kb
Host smart-905d2420-00b8-433e-8f7e-6fa868a1ff26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242046818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.242046818
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1539339522
Short name T912
Test name
Test status
Simulation time 2988008893 ps
CPU time 49.13 seconds
Started Jul 18 05:24:49 PM PDT 24
Finished Jul 18 05:25:40 PM PDT 24
Peak memory 224988 kb
Host smart-3be8f43f-3d0a-4b3b-94b6-ec8d27864fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539339522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1539339522
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.980936914
Short name T230
Test name
Test status
Simulation time 19551631974 ps
CPU time 155.74 seconds
Started Jul 18 05:25:09 PM PDT 24
Finished Jul 18 05:27:48 PM PDT 24
Peak memory 233312 kb
Host smart-ca9a4014-b333-455c-afa8-24de272da076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980936914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.980936914
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.267092811
Short name T197
Test name
Test status
Simulation time 11487617465 ps
CPU time 116.28 seconds
Started Jul 18 05:25:24 PM PDT 24
Finished Jul 18 05:27:24 PM PDT 24
Peak memory 257220 kb
Host smart-87d1ec39-2244-45a5-a545-0c7ebe909ca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267092811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.267092811
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3772604882
Short name T170
Test name
Test status
Simulation time 44080344706 ps
CPU time 438.38 seconds
Started Jul 18 05:21:18 PM PDT 24
Finished Jul 18 05:28:37 PM PDT 24
Peak memory 270816 kb
Host smart-eee464f0-9d9c-4eb0-ba08-4ba597038c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772604882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3772604882
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2157903988
Short name T325
Test name
Test status
Simulation time 8138106005 ps
CPU time 19.31 seconds
Started Jul 18 05:18:37 PM PDT 24
Finished Jul 18 05:18:59 PM PDT 24
Peak memory 216712 kb
Host smart-08680fdd-888c-4875-a306-5e4689db7c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157903988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2157903988
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_upload.996630588
Short name T945
Test name
Test status
Simulation time 16014849198 ps
CPU time 26.51 seconds
Started Jul 18 05:21:29 PM PDT 24
Finished Jul 18 05:21:56 PM PDT 24
Peak memory 249496 kb
Host smart-11690ff9-19bf-43e5-922e-52a0bf631ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996630588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.996630588
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2001815243
Short name T239
Test name
Test status
Simulation time 2721267654 ps
CPU time 35.99 seconds
Started Jul 18 05:23:31 PM PDT 24
Finished Jul 18 05:24:08 PM PDT 24
Peak memory 255740 kb
Host smart-77455592-fb2d-49f9-b5b0-398d54689b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001815243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2001815243
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2718091983
Short name T284
Test name
Test status
Simulation time 8533045085 ps
CPU time 10.73 seconds
Started Jul 18 05:24:16 PM PDT 24
Finished Jul 18 05:24:28 PM PDT 24
Peak memory 233260 kb
Host smart-7fa60a78-2a5b-4b66-8631-338494447737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718091983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2718091983
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2021579848
Short name T310
Test name
Test status
Simulation time 2069225023 ps
CPU time 53.9 seconds
Started Jul 18 05:24:30 PM PDT 24
Finished Jul 18 05:25:26 PM PDT 24
Peak memory 257824 kb
Host smart-d87380f8-ccac-4468-83d1-d5db7307a217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021579848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2021579848
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.892719965
Short name T335
Test name
Test status
Simulation time 3087729154 ps
CPU time 66.65 seconds
Started Jul 18 05:24:38 PM PDT 24
Finished Jul 18 05:25:46 PM PDT 24
Peak memory 252032 kb
Host smart-509252b3-aa93-4517-8db8-b23230ce5051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892719965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.892719965
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3437922830
Short name T96
Test name
Test status
Simulation time 14603269098 ps
CPU time 22.33 seconds
Started Jul 18 05:21:15 PM PDT 24
Finished Jul 18 05:21:39 PM PDT 24
Peak memory 241028 kb
Host smart-23f876a4-1e1b-4ce8-92a6-da77b93cbb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437922830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3437922830
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2087590823
Short name T89
Test name
Test status
Simulation time 33253717 ps
CPU time 1.02 seconds
Started Jul 18 05:16:33 PM PDT 24
Finished Jul 18 05:16:39 PM PDT 24
Peak memory 207540 kb
Host smart-6efa6f05-c17e-4f8d-8c09-84b7c7bc181d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087590823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2087590823
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2876748532
Short name T1130
Test name
Test status
Simulation time 534774392 ps
CPU time 3.79 seconds
Started Jul 18 05:16:40 PM PDT 24
Finished Jul 18 05:16:47 PM PDT 24
Peak memory 216240 kb
Host smart-50a3cc20-86d8-4481-b675-4d1a07417fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876748532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
876748532
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3494723848
Short name T266
Test name
Test status
Simulation time 8641271000 ps
CPU time 21.03 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:20:04 PM PDT 24
Peak memory 225028 kb
Host smart-36ab6ab5-f089-4d19-a2a0-83f95228257a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494723848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3494723848
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4263589109
Short name T36
Test name
Test status
Simulation time 219305984204 ps
CPU time 334.17 seconds
Started Jul 18 05:23:56 PM PDT 24
Finished Jul 18 05:29:31 PM PDT 24
Peak memory 266104 kb
Host smart-e093ba34-9960-4a94-81ec-56169ae137dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263589109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4263589109
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2059642923
Short name T1075
Test name
Test status
Simulation time 332921865 ps
CPU time 20.68 seconds
Started Jul 18 05:16:39 PM PDT 24
Finished Jul 18 05:17:04 PM PDT 24
Peak memory 215976 kb
Host smart-a09ed12f-0fcb-44ed-ad13-a4a5c96e7b61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059642923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2059642923
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2632921057
Short name T151
Test name
Test status
Simulation time 1899586282 ps
CPU time 14.15 seconds
Started Jul 18 05:16:48 PM PDT 24
Finished Jul 18 05:17:03 PM PDT 24
Peak memory 207780 kb
Host smart-dae19760-ebaa-42ab-9638-eb5755c0fde2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632921057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2632921057
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1034000635
Short name T91
Test name
Test status
Simulation time 27008258 ps
CPU time 0.94 seconds
Started Jul 18 05:16:39 PM PDT 24
Finished Jul 18 05:16:44 PM PDT 24
Peak memory 207520 kb
Host smart-79f2182a-9c30-410b-89c1-39ea5386ad7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034000635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1034000635
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.288924565
Short name T1079
Test name
Test status
Simulation time 41521667 ps
CPU time 2.92 seconds
Started Jul 18 05:16:39 PM PDT 24
Finished Jul 18 05:16:46 PM PDT 24
Peak memory 218688 kb
Host smart-6ed3cf7f-6b22-48ef-8b43-8576bc02c756
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288924565 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.288924565
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4166746349
Short name T1148
Test name
Test status
Simulation time 132924161 ps
CPU time 0.78 seconds
Started Jul 18 05:16:30 PM PDT 24
Finished Jul 18 05:16:35 PM PDT 24
Peak memory 204420 kb
Host smart-b09f48ed-b672-4b48-8842-53fa5aead1f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166746349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4
166746349
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4071079506
Short name T1120
Test name
Test status
Simulation time 70889948 ps
CPU time 1.67 seconds
Started Jul 18 05:16:39 PM PDT 24
Finished Jul 18 05:16:45 PM PDT 24
Peak memory 215972 kb
Host smart-fc6ef073-2790-4102-b0de-6d659bd78b5a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071079506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4071079506
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2886821763
Short name T1134
Test name
Test status
Simulation time 10693671 ps
CPU time 0.66 seconds
Started Jul 18 05:16:40 PM PDT 24
Finished Jul 18 05:16:44 PM PDT 24
Peak memory 204272 kb
Host smart-85b7c17f-cd23-4244-a406-e5d00ca9d920
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886821763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2886821763
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1695244749
Short name T1068
Test name
Test status
Simulation time 817308362 ps
CPU time 4.53 seconds
Started Jul 18 05:16:40 PM PDT 24
Finished Jul 18 05:16:48 PM PDT 24
Peak memory 215972 kb
Host smart-f68a1013-caed-4477-a851-10ee6d49d4e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695244749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1695244749
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2073157108
Short name T1147
Test name
Test status
Simulation time 48144321 ps
CPU time 1.53 seconds
Started Jul 18 05:16:35 PM PDT 24
Finished Jul 18 05:16:42 PM PDT 24
Peak memory 216200 kb
Host smart-73f2a696-1edf-4b77-af4a-b8230863f291
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073157108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
073157108
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2537528857
Short name T164
Test name
Test status
Simulation time 6058646078 ps
CPU time 23.75 seconds
Started Jul 18 05:16:38 PM PDT 24
Finished Jul 18 05:17:07 PM PDT 24
Peak memory 216568 kb
Host smart-115a0b43-0d74-4804-a74b-0c2697827995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537528857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2537528857
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.702748478
Short name T1119
Test name
Test status
Simulation time 115190039 ps
CPU time 7.52 seconds
Started Jul 18 05:16:35 PM PDT 24
Finished Jul 18 05:16:48 PM PDT 24
Peak memory 207864 kb
Host smart-1906478f-42eb-4020-b2e7-1e465a38dda1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702748478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.702748478
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3044504222
Short name T1039
Test name
Test status
Simulation time 183864344 ps
CPU time 11.57 seconds
Started Jul 18 05:16:39 PM PDT 24
Finished Jul 18 05:16:54 PM PDT 24
Peak memory 215920 kb
Host smart-089425af-3d08-431d-8db5-ea8c4fd9ad04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044504222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3044504222
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3307308652
Short name T1105
Test name
Test status
Simulation time 95223298 ps
CPU time 2.94 seconds
Started Jul 18 05:16:39 PM PDT 24
Finished Jul 18 05:16:46 PM PDT 24
Peak memory 217212 kb
Host smart-0ce827b6-5384-4396-b4a8-ddccaadb6d8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307308652 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3307308652
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4172918968
Short name T1124
Test name
Test status
Simulation time 310771410 ps
CPU time 2.27 seconds
Started Jul 18 05:16:33 PM PDT 24
Finished Jul 18 05:16:41 PM PDT 24
Peak memory 216004 kb
Host smart-fac90c00-7782-49f9-8c08-b8becde2e0bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172918968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.4
172918968
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2422131697
Short name T1060
Test name
Test status
Simulation time 30035557 ps
CPU time 0.72 seconds
Started Jul 18 05:16:46 PM PDT 24
Finished Jul 18 05:16:48 PM PDT 24
Peak memory 204388 kb
Host smart-2f867cfb-9f72-455f-ae3e-4845f92578e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422131697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
422131697
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.305711120
Short name T124
Test name
Test status
Simulation time 26540204 ps
CPU time 2.05 seconds
Started Jul 18 05:16:39 PM PDT 24
Finished Jul 18 05:16:45 PM PDT 24
Peak memory 215908 kb
Host smart-a10e676c-7939-4db3-ade0-38d6ecba3342
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305711120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.305711120
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.907905393
Short name T1037
Test name
Test status
Simulation time 13916888 ps
CPU time 0.7 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:16:38 PM PDT 24
Peak memory 204632 kb
Host smart-f69f8616-e7c4-49ee-8cc9-006cabdb2844
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907905393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.907905393
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2763225770
Short name T1055
Test name
Test status
Simulation time 160497441 ps
CPU time 4.08 seconds
Started Jul 18 05:16:33 PM PDT 24
Finished Jul 18 05:16:43 PM PDT 24
Peak memory 216012 kb
Host smart-b02d2ab7-6c6b-42de-b215-97ba698f6495
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763225770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2763225770
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3398570223
Short name T1086
Test name
Test status
Simulation time 198655081 ps
CPU time 6.38 seconds
Started Jul 18 05:16:48 PM PDT 24
Finished Jul 18 05:16:56 PM PDT 24
Peak memory 217624 kb
Host smart-7ede2a5c-e2fb-4aaf-a048-98f6a5b55c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398570223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3398570223
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3493417159
Short name T120
Test name
Test status
Simulation time 42033157 ps
CPU time 2.99 seconds
Started Jul 18 05:16:57 PM PDT 24
Finished Jul 18 05:17:02 PM PDT 24
Peak memory 217636 kb
Host smart-ee4f2692-dd01-4c8c-ad37-ca2de741b553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493417159 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3493417159
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1042767697
Short name T133
Test name
Test status
Simulation time 20955508 ps
CPU time 1.29 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:16:59 PM PDT 24
Peak memory 207924 kb
Host smart-f9cd12f6-8708-4d12-a974-fdd68a9dc48f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042767697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1042767697
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1981107829
Short name T1150
Test name
Test status
Simulation time 13246637 ps
CPU time 0.74 seconds
Started Jul 18 05:16:49 PM PDT 24
Finished Jul 18 05:16:51 PM PDT 24
Peak memory 204424 kb
Host smart-79021fdb-f7d1-401f-b86b-598818183882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981107829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1981107829
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.338652134
Short name T150
Test name
Test status
Simulation time 248236131 ps
CPU time 3.08 seconds
Started Jul 18 05:16:52 PM PDT 24
Finished Jul 18 05:16:56 PM PDT 24
Peak memory 215976 kb
Host smart-f05768ee-376d-4496-a065-8cd17b2f7d0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338652134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.338652134
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3949167813
Short name T1132
Test name
Test status
Simulation time 607145278 ps
CPU time 4.16 seconds
Started Jul 18 05:16:50 PM PDT 24
Finished Jul 18 05:16:56 PM PDT 24
Peak memory 216208 kb
Host smart-a9c88360-8015-44e6-a046-1cdd54a49ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949167813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3949167813
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.11442663
Short name T122
Test name
Test status
Simulation time 367048902 ps
CPU time 8.13 seconds
Started Jul 18 05:16:53 PM PDT 24
Finished Jul 18 05:17:03 PM PDT 24
Peak memory 216132 kb
Host smart-fa57dbbb-8763-40ca-8ad8-f03e9507988a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11442663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_
tl_intg_err.11442663
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1628596704
Short name T1102
Test name
Test status
Simulation time 197230867 ps
CPU time 2.56 seconds
Started Jul 18 05:16:52 PM PDT 24
Finished Jul 18 05:16:56 PM PDT 24
Peak memory 217356 kb
Host smart-9a80b7b0-8f81-4502-a1a0-5fab569fb62c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628596704 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1628596704
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.45924519
Short name T129
Test name
Test status
Simulation time 221635363 ps
CPU time 2.62 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:17:01 PM PDT 24
Peak memory 207764 kb
Host smart-db9ce308-dd36-46bc-88b2-e6b66a06df7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45924519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.45924519
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2305707983
Short name T1064
Test name
Test status
Simulation time 23824756 ps
CPU time 0.71 seconds
Started Jul 18 05:16:49 PM PDT 24
Finished Jul 18 05:16:50 PM PDT 24
Peak memory 204728 kb
Host smart-da6a30be-840e-490e-8fa7-c8e76c914159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305707983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2305707983
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2702201
Short name T1080
Test name
Test status
Simulation time 64745630 ps
CPU time 2.78 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:17:00 PM PDT 24
Peak memory 216516 kb
Host smart-665aa91b-cc1d-4c04-a29e-904b1bd1e94b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi
_device_same_csr_outstanding.2702201
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3101109609
Short name T162
Test name
Test status
Simulation time 1782717715 ps
CPU time 11.79 seconds
Started Jul 18 05:16:57 PM PDT 24
Finished Jul 18 05:17:11 PM PDT 24
Peak memory 215932 kb
Host smart-5d122ab8-9c9a-48ba-8a81-83fd41173432
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101109609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3101109609
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2116125681
Short name T1066
Test name
Test status
Simulation time 344632751 ps
CPU time 2.68 seconds
Started Jul 18 05:16:52 PM PDT 24
Finished Jul 18 05:16:57 PM PDT 24
Peak memory 216976 kb
Host smart-46d64f51-21ba-4913-8c07-f8f6fac73a06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116125681 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2116125681
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1305591455
Short name T134
Test name
Test status
Simulation time 137190932 ps
CPU time 2.64 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:17:01 PM PDT 24
Peak memory 216048 kb
Host smart-4e7b2475-fda2-46b0-8d76-7e135135cb62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305591455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1305591455
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1612152149
Short name T1128
Test name
Test status
Simulation time 35561312 ps
CPU time 0.82 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:16:56 PM PDT 24
Peak memory 204792 kb
Host smart-0a8956ec-5c5b-45bc-8617-8d0ff1cf0fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612152149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1612152149
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2523157436
Short name T1074
Test name
Test status
Simulation time 62892661 ps
CPU time 4.42 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:17:03 PM PDT 24
Peak memory 216028 kb
Host smart-a3f08293-b281-4cb3-a557-ddc4978212f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523157436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2523157436
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3830079629
Short name T114
Test name
Test status
Simulation time 704460741 ps
CPU time 4.33 seconds
Started Jul 18 05:16:56 PM PDT 24
Finished Jul 18 05:17:03 PM PDT 24
Peak memory 216208 kb
Host smart-23fb2fc4-ca72-444a-b361-4cefd14c2452
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830079629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3830079629
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1104488872
Short name T157
Test name
Test status
Simulation time 54724514 ps
CPU time 1.64 seconds
Started Jul 18 05:17:05 PM PDT 24
Finished Jul 18 05:17:07 PM PDT 24
Peak memory 215888 kb
Host smart-3f90e3b8-40f9-42d1-83d2-edda9a269436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104488872 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1104488872
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.241745534
Short name T1114
Test name
Test status
Simulation time 37362152 ps
CPU time 1.45 seconds
Started Jul 18 05:17:04 PM PDT 24
Finished Jul 18 05:17:06 PM PDT 24
Peak memory 215968 kb
Host smart-b6e2066a-a0f2-4da2-8adb-91f36bbb82aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241745534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.241745534
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3390356497
Short name T1096
Test name
Test status
Simulation time 20170576 ps
CPU time 0.74 seconds
Started Jul 18 05:17:04 PM PDT 24
Finished Jul 18 05:17:06 PM PDT 24
Peak memory 204420 kb
Host smart-76c05eed-8e31-4b4d-a5ad-5e4e736d288e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390356497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3390356497
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1602728850
Short name T1117
Test name
Test status
Simulation time 54392747 ps
CPU time 1.74 seconds
Started Jul 18 05:17:05 PM PDT 24
Finished Jul 18 05:17:07 PM PDT 24
Peak memory 215944 kb
Host smart-3fb90961-a0d0-486e-a639-ae0292f4e1d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602728850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1602728850
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3102846660
Short name T115
Test name
Test status
Simulation time 199015877 ps
CPU time 2.81 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:17:00 PM PDT 24
Peak memory 216148 kb
Host smart-586c8db6-c53a-4eae-ae30-4ea6a958ffa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102846660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3102846660
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.625206124
Short name T105
Test name
Test status
Simulation time 380254255 ps
CPU time 12.38 seconds
Started Jul 18 05:17:05 PM PDT 24
Finished Jul 18 05:17:19 PM PDT 24
Peak memory 216028 kb
Host smart-3293d6be-1bbc-4da9-94eb-1e0ce18316c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625206124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.625206124
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1356545970
Short name T1069
Test name
Test status
Simulation time 162668501 ps
CPU time 1.66 seconds
Started Jul 18 05:16:53 PM PDT 24
Finished Jul 18 05:16:56 PM PDT 24
Peak memory 216124 kb
Host smart-0736ecfa-4807-4e28-ba6f-e7abd148cc02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356545970 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1356545970
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3631968794
Short name T1113
Test name
Test status
Simulation time 44371490 ps
CPU time 1.28 seconds
Started Jul 18 05:17:05 PM PDT 24
Finished Jul 18 05:17:07 PM PDT 24
Peak memory 207836 kb
Host smart-aa64a9a4-23be-4f4a-b26a-60c173645234
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631968794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3631968794
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1176663249
Short name T1032
Test name
Test status
Simulation time 58660338 ps
CPU time 0.78 seconds
Started Jul 18 05:16:51 PM PDT 24
Finished Jul 18 05:16:52 PM PDT 24
Peak memory 204652 kb
Host smart-c7ec24b8-d092-432c-ad1b-df825be8a54d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176663249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1176663249
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3907925604
Short name T1138
Test name
Test status
Simulation time 159246255 ps
CPU time 2.81 seconds
Started Jul 18 05:17:04 PM PDT 24
Finished Jul 18 05:17:07 PM PDT 24
Peak memory 215948 kb
Host smart-5a0f74f4-252a-4fbd-aac4-8297e1bb4e9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907925604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3907925604
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.613692157
Short name T111
Test name
Test status
Simulation time 74774516 ps
CPU time 3.23 seconds
Started Jul 18 05:17:03 PM PDT 24
Finished Jul 18 05:17:08 PM PDT 24
Peak memory 217152 kb
Host smart-4e5ae74e-c80d-4826-8174-3ef6fe4e9473
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613692157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.613692157
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2435634851
Short name T1107
Test name
Test status
Simulation time 6232492993 ps
CPU time 15.55 seconds
Started Jul 18 05:17:05 PM PDT 24
Finished Jul 18 05:17:21 PM PDT 24
Peak memory 216100 kb
Host smart-1aaebb5f-755c-46b2-95c0-1dd70f0ce30a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435634851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2435634851
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.349952729
Short name T1146
Test name
Test status
Simulation time 321995162 ps
CPU time 2.9 seconds
Started Jul 18 05:17:06 PM PDT 24
Finished Jul 18 05:17:11 PM PDT 24
Peak memory 218636 kb
Host smart-088a2bb9-18a4-475c-9043-bccfcd9fdd59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349952729 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.349952729
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.97002089
Short name T1048
Test name
Test status
Simulation time 53203180 ps
CPU time 1.59 seconds
Started Jul 18 05:17:01 PM PDT 24
Finished Jul 18 05:17:04 PM PDT 24
Peak memory 216016 kb
Host smart-7ab9b0c9-9905-48c1-bdd5-a37ab56edbdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97002089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.97002089
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1646603799
Short name T1144
Test name
Test status
Simulation time 13916799 ps
CPU time 0.78 seconds
Started Jul 18 05:17:00 PM PDT 24
Finished Jul 18 05:17:03 PM PDT 24
Peak memory 204476 kb
Host smart-0d7fbf17-2191-4c4b-83d0-53e49affb160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646603799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1646603799
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.179602170
Short name T1104
Test name
Test status
Simulation time 134056742 ps
CPU time 2.83 seconds
Started Jul 18 05:17:00 PM PDT 24
Finished Jul 18 05:17:04 PM PDT 24
Peak memory 216000 kb
Host smart-d58f82cc-18d0-43be-a051-cc4445722642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179602170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.179602170
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.67886657
Short name T1092
Test name
Test status
Simulation time 36697222 ps
CPU time 1.44 seconds
Started Jul 18 05:17:04 PM PDT 24
Finished Jul 18 05:17:06 PM PDT 24
Peak memory 216132 kb
Host smart-5958cd08-f0a3-4564-aac3-58462980aed4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67886657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.67886657
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1742908071
Short name T1083
Test name
Test status
Simulation time 592965905 ps
CPU time 8.06 seconds
Started Jul 18 05:17:00 PM PDT 24
Finished Jul 18 05:17:09 PM PDT 24
Peak memory 216080 kb
Host smart-c8cfe946-f2c7-4b8c-99d5-d47ddf798de3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742908071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1742908071
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.386789820
Short name T1046
Test name
Test status
Simulation time 97227412 ps
CPU time 1.76 seconds
Started Jul 18 05:17:01 PM PDT 24
Finished Jul 18 05:17:04 PM PDT 24
Peak memory 217244 kb
Host smart-9f5001c2-991e-4b9e-8be3-3aa0b69fb653
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386789820 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.386789820
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4241351055
Short name T130
Test name
Test status
Simulation time 32676700 ps
CPU time 1.93 seconds
Started Jul 18 05:17:01 PM PDT 24
Finished Jul 18 05:17:04 PM PDT 24
Peak memory 207816 kb
Host smart-b55b8141-b243-493c-9099-38f1c064575e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241351055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4241351055
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2595635121
Short name T1073
Test name
Test status
Simulation time 12761220 ps
CPU time 0.7 seconds
Started Jul 18 05:16:53 PM PDT 24
Finished Jul 18 05:16:56 PM PDT 24
Peak memory 204400 kb
Host smart-93866267-4d05-474c-b0ef-9d88524d5477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595635121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2595635121
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1692305161
Short name T1126
Test name
Test status
Simulation time 661277907 ps
CPU time 3.04 seconds
Started Jul 18 05:17:05 PM PDT 24
Finished Jul 18 05:17:09 PM PDT 24
Peak memory 216032 kb
Host smart-48188b79-761e-4430-a4d3-2e1b3159943b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692305161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1692305161
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.628177492
Short name T113
Test name
Test status
Simulation time 595883402 ps
CPU time 5.4 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:17:04 PM PDT 24
Peak memory 216188 kb
Host smart-f7be51f9-3811-4de1-ac6f-dea955b3ee59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628177492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.628177492
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3906030947
Short name T1081
Test name
Test status
Simulation time 199961966 ps
CPU time 12.93 seconds
Started Jul 18 05:17:06 PM PDT 24
Finished Jul 18 05:17:20 PM PDT 24
Peak memory 215940 kb
Host smart-b71b0e5e-1ffb-4183-bf59-060b20d31a88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906030947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3906030947
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.43699289
Short name T1063
Test name
Test status
Simulation time 252406104 ps
CPU time 3.49 seconds
Started Jul 18 05:26:06 PM PDT 24
Finished Jul 18 05:26:13 PM PDT 24
Peak memory 217856 kb
Host smart-7f14e22c-3091-45ac-82ad-6bc46c6fa634
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43699289 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.43699289
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2332779835
Short name T123
Test name
Test status
Simulation time 786404584 ps
CPU time 2.14 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:16:59 PM PDT 24
Peak memory 207776 kb
Host smart-58817527-ad01-4320-a218-eb7f86d204a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332779835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2332779835
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2020940980
Short name T1033
Test name
Test status
Simulation time 32173537 ps
CPU time 0.71 seconds
Started Jul 18 05:17:06 PM PDT 24
Finished Jul 18 05:17:07 PM PDT 24
Peak memory 204428 kb
Host smart-b155888a-d6f5-4317-a7ad-0be693ebbae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020940980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2020940980
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2561115639
Short name T1053
Test name
Test status
Simulation time 145279671 ps
CPU time 1.89 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:16:59 PM PDT 24
Peak memory 207784 kb
Host smart-2a0c3837-07c0-4c80-a162-17ce77ad1dfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561115639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2561115639
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.114738791
Short name T116
Test name
Test status
Simulation time 140143055 ps
CPU time 2.14 seconds
Started Jul 18 05:17:01 PM PDT 24
Finished Jul 18 05:17:05 PM PDT 24
Peak memory 216240 kb
Host smart-84c81841-6b5e-47a6-bc32-1c1a29c154ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114738791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.114738791
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1735768776
Short name T1059
Test name
Test status
Simulation time 456358226 ps
CPU time 6.95 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:17:04 PM PDT 24
Peak memory 215936 kb
Host smart-005cfe60-a760-44a6-998c-bbd5b2219ded
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735768776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1735768776
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2024823448
Short name T1067
Test name
Test status
Simulation time 304140393 ps
CPU time 1.86 seconds
Started Jul 18 05:17:10 PM PDT 24
Finished Jul 18 05:17:13 PM PDT 24
Peak memory 216000 kb
Host smart-e3032eee-7c2b-4370-9c25-0f5677fa0698
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024823448 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2024823448
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.921172809
Short name T1123
Test name
Test status
Simulation time 36204175 ps
CPU time 1.21 seconds
Started Jul 18 05:17:12 PM PDT 24
Finished Jul 18 05:17:17 PM PDT 24
Peak memory 216008 kb
Host smart-4da1c32e-5024-465d-a235-ae625fbafb81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921172809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.921172809
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.890263112
Short name T1112
Test name
Test status
Simulation time 24740832 ps
CPU time 0.74 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:16:57 PM PDT 24
Peak memory 204432 kb
Host smart-3c12fd9b-8b5a-4cc0-96e8-08bd743a3223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890263112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.890263112
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1968326872
Short name T1133
Test name
Test status
Simulation time 27649070 ps
CPU time 1.7 seconds
Started Jul 18 05:17:08 PM PDT 24
Finished Jul 18 05:17:11 PM PDT 24
Peak memory 215988 kb
Host smart-4e3ad8da-b8d3-413c-a6ec-e1bf76f8fc98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968326872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1968326872
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3461625364
Short name T1136
Test name
Test status
Simulation time 118458452 ps
CPU time 1.74 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:16:57 PM PDT 24
Peak memory 216252 kb
Host smart-c139285e-7516-4681-8a71-e095e527392b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461625364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3461625364
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2820728027
Short name T121
Test name
Test status
Simulation time 589910142 ps
CPU time 18.93 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:17:15 PM PDT 24
Peak memory 216032 kb
Host smart-fb00a5e3-05af-4541-bb06-75b8558e0285
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820728027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2820728027
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1101521159
Short name T106
Test name
Test status
Simulation time 46050558 ps
CPU time 1.71 seconds
Started Jul 18 05:17:22 PM PDT 24
Finished Jul 18 05:17:24 PM PDT 24
Peak memory 216048 kb
Host smart-f36e90cd-795f-4385-9994-0e3e41795a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101521159 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1101521159
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2240077151
Short name T131
Test name
Test status
Simulation time 98954639 ps
CPU time 1.89 seconds
Started Jul 18 05:17:11 PM PDT 24
Finished Jul 18 05:17:16 PM PDT 24
Peak memory 215944 kb
Host smart-480462ce-87ab-42d1-8e71-b7f0a65f09ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240077151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2240077151
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1955991715
Short name T1050
Test name
Test status
Simulation time 16673623 ps
CPU time 0.68 seconds
Started Jul 18 05:17:13 PM PDT 24
Finished Jul 18 05:17:17 PM PDT 24
Peak memory 204440 kb
Host smart-6b424fda-543e-4f72-8c1a-6d832cf2baa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955991715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1955991715
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.784576428
Short name T1045
Test name
Test status
Simulation time 353800724 ps
CPU time 2.01 seconds
Started Jul 18 05:17:11 PM PDT 24
Finished Jul 18 05:17:16 PM PDT 24
Peak memory 215972 kb
Host smart-416ca502-8f19-4933-8b39-f798320e28d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784576428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.784576428
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.582724054
Short name T1088
Test name
Test status
Simulation time 25968346 ps
CPU time 1.63 seconds
Started Jul 18 05:17:13 PM PDT 24
Finished Jul 18 05:17:18 PM PDT 24
Peak memory 216132 kb
Host smart-2055ac90-9112-41ab-bacd-f966627cd8c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582724054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.582724054
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.180796994
Short name T161
Test name
Test status
Simulation time 2381485253 ps
CPU time 12.25 seconds
Started Jul 18 05:17:12 PM PDT 24
Finished Jul 18 05:17:27 PM PDT 24
Peak memory 216504 kb
Host smart-16604aa3-75d7-49db-ad81-cccaf333fe40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180796994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.180796994
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3074745065
Short name T1094
Test name
Test status
Simulation time 1362534379 ps
CPU time 21.94 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:17:00 PM PDT 24
Peak memory 215916 kb
Host smart-85f71042-7675-4459-b976-aa6a729db842
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074745065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3074745065
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3575239233
Short name T1149
Test name
Test status
Simulation time 5577705023 ps
CPU time 24.5 seconds
Started Jul 18 05:16:34 PM PDT 24
Finished Jul 18 05:17:04 PM PDT 24
Peak memory 215912 kb
Host smart-05b6a688-b3d9-49de-afd5-684ff446c06e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575239233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3575239233
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2028865061
Short name T90
Test name
Test status
Simulation time 15010063 ps
CPU time 1 seconds
Started Jul 18 05:16:37 PM PDT 24
Finished Jul 18 05:16:43 PM PDT 24
Peak memory 207652 kb
Host smart-00866dda-acc9-4a80-99fe-d1c3119f96a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028865061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2028865061
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.82261711
Short name T1143
Test name
Test status
Simulation time 518648265 ps
CPU time 3.96 seconds
Started Jul 18 05:16:30 PM PDT 24
Finished Jul 18 05:16:38 PM PDT 24
Peak memory 219132 kb
Host smart-34e5ffd5-eb12-4549-b830-c0badacee35f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82261711 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.82261711
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.241597331
Short name T1135
Test name
Test status
Simulation time 28272540 ps
CPU time 1.83 seconds
Started Jul 18 05:16:33 PM PDT 24
Finished Jul 18 05:16:41 PM PDT 24
Peak memory 207780 kb
Host smart-8668f1b6-3dde-450a-8f51-59ced2f17104
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241597331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.241597331
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2126828466
Short name T1106
Test name
Test status
Simulation time 49070551 ps
CPU time 0.75 seconds
Started Jul 18 05:16:43 PM PDT 24
Finished Jul 18 05:16:46 PM PDT 24
Peak memory 204752 kb
Host smart-03e53bc8-27f6-4af8-8fba-c7a060258250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126828466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
126828466
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1257639551
Short name T132
Test name
Test status
Simulation time 66626516 ps
CPU time 2.16 seconds
Started Jul 18 05:16:34 PM PDT 24
Finished Jul 18 05:16:42 PM PDT 24
Peak memory 215988 kb
Host smart-36959d42-e396-416c-be24-9d303689146e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257639551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1257639551
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1495111079
Short name T1028
Test name
Test status
Simulation time 52174281 ps
CPU time 0.67 seconds
Started Jul 18 05:16:31 PM PDT 24
Finished Jul 18 05:16:35 PM PDT 24
Peak memory 204276 kb
Host smart-63384f97-b13b-4fc8-b1f6-20dde438bdce
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495111079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1495111079
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3882852286
Short name T149
Test name
Test status
Simulation time 509630769 ps
CPU time 2.99 seconds
Started Jul 18 05:16:29 PM PDT 24
Finished Jul 18 05:16:33 PM PDT 24
Peak memory 215976 kb
Host smart-01235f0d-e21e-49de-aa08-d1aa15600363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882852286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3882852286
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2957416475
Short name T1085
Test name
Test status
Simulation time 283478722 ps
CPU time 2.3 seconds
Started Jul 18 05:16:47 PM PDT 24
Finished Jul 18 05:16:51 PM PDT 24
Peak memory 216380 kb
Host smart-c57cc963-e282-4d82-9c20-b6605bbb6bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957416475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
957416475
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1859414988
Short name T119
Test name
Test status
Simulation time 1125293879 ps
CPU time 13.16 seconds
Started Jul 18 05:16:47 PM PDT 24
Finished Jul 18 05:17:01 PM PDT 24
Peak memory 216092 kb
Host smart-9ccc6ace-e447-4f78-944d-58c142559677
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859414988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1859414988
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.192176356
Short name T1058
Test name
Test status
Simulation time 45768153 ps
CPU time 0.74 seconds
Started Jul 18 05:17:10 PM PDT 24
Finished Jul 18 05:17:13 PM PDT 24
Peak memory 204480 kb
Host smart-9ff9197b-d718-4d48-8335-0192d5052b36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192176356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.192176356
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4263604130
Short name T1151
Test name
Test status
Simulation time 90133761 ps
CPU time 0.71 seconds
Started Jul 18 05:17:14 PM PDT 24
Finished Jul 18 05:17:18 PM PDT 24
Peak memory 204464 kb
Host smart-47c2fbce-5305-42b3-922b-993c6a049ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263604130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4263604130
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4038846161
Short name T1057
Test name
Test status
Simulation time 37902066 ps
CPU time 0.71 seconds
Started Jul 18 05:17:11 PM PDT 24
Finished Jul 18 05:17:15 PM PDT 24
Peak memory 204800 kb
Host smart-43538a24-714c-4262-b680-d1b97312d44b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038846161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4038846161
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2541796281
Short name T1103
Test name
Test status
Simulation time 16491842 ps
CPU time 0.72 seconds
Started Jul 18 05:17:08 PM PDT 24
Finished Jul 18 05:17:10 PM PDT 24
Peak memory 204752 kb
Host smart-ff6a85e2-36fd-42f7-a228-c1fac9842cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541796281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2541796281
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2441884119
Short name T1078
Test name
Test status
Simulation time 11248136 ps
CPU time 0.74 seconds
Started Jul 18 05:17:12 PM PDT 24
Finished Jul 18 05:17:17 PM PDT 24
Peak memory 204404 kb
Host smart-bbcf4553-2bef-411f-8534-35b6ee062c58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441884119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2441884119
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4224185120
Short name T1035
Test name
Test status
Simulation time 91362351 ps
CPU time 0.7 seconds
Started Jul 18 05:17:10 PM PDT 24
Finished Jul 18 05:17:13 PM PDT 24
Peak memory 204760 kb
Host smart-194821e5-118a-43f4-8207-ccc2e488aac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224185120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4224185120
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.164536318
Short name T1141
Test name
Test status
Simulation time 18978319 ps
CPU time 0.74 seconds
Started Jul 18 05:17:11 PM PDT 24
Finished Jul 18 05:17:15 PM PDT 24
Peak memory 204408 kb
Host smart-1a53b005-4612-49e0-adea-6b83d47cd3c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164536318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.164536318
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3711978622
Short name T1108
Test name
Test status
Simulation time 16853918 ps
CPU time 0.79 seconds
Started Jul 18 05:17:13 PM PDT 24
Finished Jul 18 05:17:17 PM PDT 24
Peak memory 204424 kb
Host smart-d62868ef-2c2f-41cb-85ed-13e1106a0eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711978622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3711978622
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.992139087
Short name T1030
Test name
Test status
Simulation time 12836233 ps
CPU time 0.76 seconds
Started Jul 18 05:17:08 PM PDT 24
Finished Jul 18 05:17:10 PM PDT 24
Peak memory 204476 kb
Host smart-636a85b5-fa5a-41fb-b7f0-ae75d47f1ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992139087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.992139087
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.891024969
Short name T1072
Test name
Test status
Simulation time 42716837 ps
CPU time 0.7 seconds
Started Jul 18 05:17:08 PM PDT 24
Finished Jul 18 05:17:09 PM PDT 24
Peak memory 204404 kb
Host smart-c3176885-781f-406e-8d0f-d4928eeee4f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891024969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.891024969
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3939341767
Short name T135
Test name
Test status
Simulation time 4489619607 ps
CPU time 22.96 seconds
Started Jul 18 05:16:44 PM PDT 24
Finished Jul 18 05:17:08 PM PDT 24
Peak memory 216016 kb
Host smart-42bc3853-fd53-4a04-893a-57308cf6eda9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939341767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3939341767
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.758448463
Short name T1125
Test name
Test status
Simulation time 1257261697 ps
CPU time 13.35 seconds
Started Jul 18 05:16:35 PM PDT 24
Finished Jul 18 05:16:55 PM PDT 24
Peak memory 207716 kb
Host smart-a904c50e-b1e1-40e5-9f25-09e9b33e6306
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758448463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.758448463
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3214354904
Short name T93
Test name
Test status
Simulation time 36605018 ps
CPU time 0.98 seconds
Started Jul 18 05:16:44 PM PDT 24
Finished Jul 18 05:16:47 PM PDT 24
Peak memory 207584 kb
Host smart-4b0c8b4d-6eb5-4718-8f74-adfc3db0572d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214354904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3214354904
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2910515399
Short name T104
Test name
Test status
Simulation time 435519150 ps
CPU time 2.93 seconds
Started Jul 18 05:16:44 PM PDT 24
Finished Jul 18 05:16:48 PM PDT 24
Peak memory 217124 kb
Host smart-505ca560-430d-4167-aeab-7bbdfbb7f9a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910515399 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2910515399
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2758524587
Short name T141
Test name
Test status
Simulation time 162501660 ps
CPU time 1.43 seconds
Started Jul 18 05:16:44 PM PDT 24
Finished Jul 18 05:16:47 PM PDT 24
Peak memory 216052 kb
Host smart-d85800f2-7344-4461-9588-6a4b9e87de66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758524587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
758524587
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1621537383
Short name T1100
Test name
Test status
Simulation time 21088660 ps
CPU time 0.69 seconds
Started Jul 18 05:16:35 PM PDT 24
Finished Jul 18 05:16:41 PM PDT 24
Peak memory 204512 kb
Host smart-8f62b43d-6418-48d8-b8ab-21dfe5af5df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621537383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
621537383
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3074606565
Short name T126
Test name
Test status
Simulation time 63109267 ps
CPU time 2.27 seconds
Started Jul 18 05:16:35 PM PDT 24
Finished Jul 18 05:16:43 PM PDT 24
Peak memory 215988 kb
Host smart-d667bdc7-69a8-4bc1-9345-9734d7d5dbab
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074606565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3074606565
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4127187277
Short name T1093
Test name
Test status
Simulation time 12377321 ps
CPU time 0.69 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:16:38 PM PDT 24
Peak memory 204332 kb
Host smart-40c65388-6cf1-4b61-b427-5b6c768d0be8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127187277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4127187277
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2253659285
Short name T1121
Test name
Test status
Simulation time 333155703 ps
CPU time 4.01 seconds
Started Jul 18 05:16:29 PM PDT 24
Finished Jul 18 05:16:35 PM PDT 24
Peak memory 216108 kb
Host smart-c9052257-a1c8-4137-a768-db4181bd0525
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253659285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2253659285
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1495835216
Short name T1089
Test name
Test status
Simulation time 247675298 ps
CPU time 1.88 seconds
Started Jul 18 05:16:35 PM PDT 24
Finished Jul 18 05:16:42 PM PDT 24
Peak memory 216300 kb
Host smart-dc2d2fa2-189b-45a2-b177-6f2e07c1d66d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495835216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
495835216
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1701360206
Short name T1076
Test name
Test status
Simulation time 1850641373 ps
CPU time 8.74 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:16:46 PM PDT 24
Peak memory 216528 kb
Host smart-5b15ff2d-323e-4ba6-8861-d51e26e20b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701360206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1701360206
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3763351193
Short name T1062
Test name
Test status
Simulation time 12075389 ps
CPU time 0.75 seconds
Started Jul 18 05:17:12 PM PDT 24
Finished Jul 18 05:17:16 PM PDT 24
Peak memory 204388 kb
Host smart-c3093d95-7194-4442-8297-768503233cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763351193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3763351193
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1501400419
Short name T1082
Test name
Test status
Simulation time 13018609 ps
CPU time 0.74 seconds
Started Jul 18 05:17:12 PM PDT 24
Finished Jul 18 05:17:17 PM PDT 24
Peak memory 204396 kb
Host smart-7acec7d6-9d07-4f20-8b68-3d512346ffda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501400419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1501400419
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.479204412
Short name T1099
Test name
Test status
Simulation time 26099361 ps
CPU time 0.77 seconds
Started Jul 18 05:17:09 PM PDT 24
Finished Jul 18 05:17:10 PM PDT 24
Peak memory 204448 kb
Host smart-c334e9d2-9010-4a97-a037-51137fd616c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479204412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.479204412
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3059681740
Short name T1029
Test name
Test status
Simulation time 16689455 ps
CPU time 0.79 seconds
Started Jul 18 05:17:12 PM PDT 24
Finished Jul 18 05:17:16 PM PDT 24
Peak memory 204408 kb
Host smart-a32af952-8d97-4493-acc4-4053a19d6e03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059681740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3059681740
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3265494352
Short name T1142
Test name
Test status
Simulation time 47214462 ps
CPU time 0.73 seconds
Started Jul 18 05:17:12 PM PDT 24
Finished Jul 18 05:17:16 PM PDT 24
Peak memory 204432 kb
Host smart-700c3ffd-9275-4a3d-a4f4-0a51ec43cba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265494352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3265494352
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2901098327
Short name T1127
Test name
Test status
Simulation time 35881528 ps
CPU time 0.69 seconds
Started Jul 18 05:17:12 PM PDT 24
Finished Jul 18 05:17:16 PM PDT 24
Peak memory 204412 kb
Host smart-9bc1ed42-4d93-4109-bebc-8bb7c32b21ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901098327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2901098327
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.762166259
Short name T1071
Test name
Test status
Simulation time 66431748 ps
CPU time 0.74 seconds
Started Jul 18 05:17:10 PM PDT 24
Finished Jul 18 05:17:12 PM PDT 24
Peak memory 204764 kb
Host smart-e79f58a3-82a7-43b7-92e9-49261a8b6bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762166259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.762166259
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2207277932
Short name T1090
Test name
Test status
Simulation time 43831901 ps
CPU time 0.76 seconds
Started Jul 18 05:17:13 PM PDT 24
Finished Jul 18 05:17:17 PM PDT 24
Peak memory 204404 kb
Host smart-538de939-2f16-4927-9396-a24fb3a76a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207277932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2207277932
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1841918241
Short name T1137
Test name
Test status
Simulation time 19809961 ps
CPU time 0.72 seconds
Started Jul 18 05:17:12 PM PDT 24
Finished Jul 18 05:17:16 PM PDT 24
Peak memory 204424 kb
Host smart-d6635f74-632a-4375-8729-9baa4dbe1e33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841918241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1841918241
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.821614626
Short name T1036
Test name
Test status
Simulation time 31766440 ps
CPU time 0.8 seconds
Started Jul 18 05:17:13 PM PDT 24
Finished Jul 18 05:17:17 PM PDT 24
Peak memory 204760 kb
Host smart-6d958e92-19d4-40d3-9b04-b14463556a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821614626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.821614626
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3889649075
Short name T1091
Test name
Test status
Simulation time 3462062021 ps
CPU time 17.01 seconds
Started Jul 18 05:16:38 PM PDT 24
Finished Jul 18 05:17:00 PM PDT 24
Peak memory 207856 kb
Host smart-b34fb81a-b88b-4654-b596-2f5e2a3fc592
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889649075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3889649075
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1358765643
Short name T1044
Test name
Test status
Simulation time 190815963 ps
CPU time 10.92 seconds
Started Jul 18 05:16:37 PM PDT 24
Finished Jul 18 05:16:53 PM PDT 24
Peak memory 207712 kb
Host smart-7fb7d16f-e7c7-46ae-9743-2eaded7318fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358765643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1358765643
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2397891502
Short name T92
Test name
Test status
Simulation time 66930033 ps
CPU time 0.96 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:16:38 PM PDT 24
Peak memory 207572 kb
Host smart-894fe36f-ba24-43b2-9a6d-7dde3de097a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397891502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2397891502
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3390681677
Short name T1061
Test name
Test status
Simulation time 124197451 ps
CPU time 2.34 seconds
Started Jul 18 05:16:39 PM PDT 24
Finished Jul 18 05:16:45 PM PDT 24
Peak memory 217600 kb
Host smart-2cbdf558-c4b5-4a5a-8967-083b39a16d10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390681677 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3390681677
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1265398905
Short name T1056
Test name
Test status
Simulation time 41007273 ps
CPU time 1.5 seconds
Started Jul 18 05:16:38 PM PDT 24
Finished Jul 18 05:16:44 PM PDT 24
Peak memory 216012 kb
Host smart-f86873cf-3350-4350-b16d-07934ef2b998
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265398905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
265398905
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2928484327
Short name T1051
Test name
Test status
Simulation time 20749421 ps
CPU time 0.69 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:16:38 PM PDT 24
Peak memory 204476 kb
Host smart-e6e92d6f-6a9e-4f03-83f0-1b4cb9c546b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928484327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
928484327
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.861210781
Short name T136
Test name
Test status
Simulation time 82418275 ps
CPU time 2.1 seconds
Started Jul 18 05:16:30 PM PDT 24
Finished Jul 18 05:16:36 PM PDT 24
Peak memory 216228 kb
Host smart-4d5fe7bc-a7b0-41f9-98c9-940b9ac5900c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861210781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.861210781
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4004287484
Short name T1038
Test name
Test status
Simulation time 40024368 ps
CPU time 0.69 seconds
Started Jul 18 05:16:33 PM PDT 24
Finished Jul 18 05:16:39 PM PDT 24
Peak memory 204324 kb
Host smart-711997eb-694d-44f2-bbb8-f4c0d43fb5d4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004287484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4004287484
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1000176027
Short name T1077
Test name
Test status
Simulation time 201152335 ps
CPU time 2.84 seconds
Started Jul 18 05:16:39 PM PDT 24
Finished Jul 18 05:16:46 PM PDT 24
Peak memory 215900 kb
Host smart-78f78706-704b-4ebc-bf7a-40deb99ca840
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000176027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1000176027
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.451231181
Short name T1054
Test name
Test status
Simulation time 1364643231 ps
CPU time 7.43 seconds
Started Jul 18 05:16:29 PM PDT 24
Finished Jul 18 05:16:38 PM PDT 24
Peak memory 216172 kb
Host smart-0bda422c-97ca-4b32-9c2e-b6e1c6ede335
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451231181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.451231181
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2587967980
Short name T1065
Test name
Test status
Simulation time 14696597 ps
CPU time 0.75 seconds
Started Jul 18 05:17:12 PM PDT 24
Finished Jul 18 05:17:16 PM PDT 24
Peak memory 204392 kb
Host smart-d891efdf-b71f-4b2a-920b-0bef07bf4df0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587967980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2587967980
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1150018221
Short name T1098
Test name
Test status
Simulation time 19560126 ps
CPU time 0.79 seconds
Started Jul 18 05:17:11 PM PDT 24
Finished Jul 18 05:17:15 PM PDT 24
Peak memory 204428 kb
Host smart-2e1bbee6-8127-4355-9d71-7c6ef073755f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150018221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1150018221
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3891658351
Short name T1111
Test name
Test status
Simulation time 13373667 ps
CPU time 0.73 seconds
Started Jul 18 05:17:09 PM PDT 24
Finished Jul 18 05:17:10 PM PDT 24
Peak memory 204396 kb
Host smart-b31af3f4-3db8-406e-afb2-f54b3923867d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891658351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3891658351
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2847964815
Short name T1084
Test name
Test status
Simulation time 15815774 ps
CPU time 0.74 seconds
Started Jul 18 05:17:12 PM PDT 24
Finished Jul 18 05:17:16 PM PDT 24
Peak memory 204764 kb
Host smart-e276a9e5-480c-4326-bcf1-8eb4863e505f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847964815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2847964815
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3084782556
Short name T1139
Test name
Test status
Simulation time 84010016 ps
CPU time 0.76 seconds
Started Jul 18 05:17:10 PM PDT 24
Finished Jul 18 05:17:13 PM PDT 24
Peak memory 204460 kb
Host smart-615934b2-7598-47fb-a74a-81abd1137a45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084782556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3084782556
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.762256377
Short name T1110
Test name
Test status
Simulation time 23457608 ps
CPU time 0.78 seconds
Started Jul 18 05:17:11 PM PDT 24
Finished Jul 18 05:17:14 PM PDT 24
Peak memory 204644 kb
Host smart-45273dbb-7508-4fcd-a5ff-188e6f239d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762256377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.762256377
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.647058521
Short name T1129
Test name
Test status
Simulation time 100899358 ps
CPU time 0.84 seconds
Started Jul 18 05:17:10 PM PDT 24
Finished Jul 18 05:17:13 PM PDT 24
Peak memory 204384 kb
Host smart-07a6d76e-5d4b-47e8-a457-41d0cceee344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647058521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.647058521
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2801176806
Short name T1087
Test name
Test status
Simulation time 55076739 ps
CPU time 0.75 seconds
Started Jul 18 05:17:14 PM PDT 24
Finished Jul 18 05:17:18 PM PDT 24
Peak memory 204444 kb
Host smart-dceb96cb-f644-4e4e-a637-2e8c56e0720a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801176806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2801176806
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3424070939
Short name T1031
Test name
Test status
Simulation time 18085581 ps
CPU time 0.76 seconds
Started Jul 18 05:17:11 PM PDT 24
Finished Jul 18 05:17:14 PM PDT 24
Peak memory 204792 kb
Host smart-2290f5fb-d654-4104-b809-ee6a23c1a1ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424070939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3424070939
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2959934836
Short name T1049
Test name
Test status
Simulation time 54284337 ps
CPU time 0.86 seconds
Started Jul 18 05:17:13 PM PDT 24
Finished Jul 18 05:17:17 PM PDT 24
Peak memory 204748 kb
Host smart-79a40f35-8815-43eb-9f7e-fa5163b26bf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959934836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2959934836
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1611576338
Short name T1047
Test name
Test status
Simulation time 105284554 ps
CPU time 1.89 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:16:59 PM PDT 24
Peak memory 216164 kb
Host smart-37530d0d-9040-4a77-8b90-079231a072d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611576338 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1611576338
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3606119705
Short name T1145
Test name
Test status
Simulation time 17671738 ps
CPU time 1.17 seconds
Started Jul 18 05:16:49 PM PDT 24
Finished Jul 18 05:16:51 PM PDT 24
Peak memory 207856 kb
Host smart-f6dc457d-b563-4add-a970-c7cc0bbe4e87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606119705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
606119705
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.209800834
Short name T1043
Test name
Test status
Simulation time 14103732 ps
CPU time 0.76 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:16:56 PM PDT 24
Peak memory 204720 kb
Host smart-f153d390-176a-407b-92fa-71e234d8f785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209800834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.209800834
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.127908476
Short name T1131
Test name
Test status
Simulation time 339325264 ps
CPU time 4.17 seconds
Started Jul 18 05:17:02 PM PDT 24
Finished Jul 18 05:17:07 PM PDT 24
Peak memory 215928 kb
Host smart-ae410d89-3dc9-4828-ad50-53d37d646a63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127908476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.127908476
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1654636132
Short name T110
Test name
Test status
Simulation time 65556160 ps
CPU time 4.43 seconds
Started Jul 18 05:16:38 PM PDT 24
Finished Jul 18 05:16:47 PM PDT 24
Peak memory 216116 kb
Host smart-16880377-db99-4c3e-b96a-6a2578f3bf4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654636132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
654636132
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.103471773
Short name T148
Test name
Test status
Simulation time 355161766 ps
CPU time 7.69 seconds
Started Jul 18 05:16:47 PM PDT 24
Finished Jul 18 05:16:56 PM PDT 24
Peak memory 223192 kb
Host smart-41b1c1e5-2b43-4c7e-bd1d-04e90924f940
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103471773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.103471773
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3507603854
Short name T1115
Test name
Test status
Simulation time 167021647 ps
CPU time 1.6 seconds
Started Jul 18 05:16:48 PM PDT 24
Finished Jul 18 05:16:51 PM PDT 24
Peak memory 215944 kb
Host smart-0d08d104-bdb2-4a26-b94b-8def43c6861c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507603854 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3507603854
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4055639596
Short name T127
Test name
Test status
Simulation time 514886303 ps
CPU time 2.76 seconds
Started Jul 18 05:16:53 PM PDT 24
Finished Jul 18 05:16:58 PM PDT 24
Peak memory 215980 kb
Host smart-e4aab664-53a6-444c-b75d-881f8fa4a3cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055639596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
055639596
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2845080926
Short name T1042
Test name
Test status
Simulation time 25844281 ps
CPU time 0.76 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:16:59 PM PDT 24
Peak memory 204352 kb
Host smart-2df776d2-0216-4e18-9dd3-e5f1bf92e4bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845080926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
845080926
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.973326013
Short name T1070
Test name
Test status
Simulation time 216958180 ps
CPU time 4.54 seconds
Started Jul 18 05:16:49 PM PDT 24
Finished Jul 18 05:16:55 PM PDT 24
Peak memory 217152 kb
Host smart-d67b48d1-d022-4e36-832d-43535f007c2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973326013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.973326013
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3546020623
Short name T158
Test name
Test status
Simulation time 303334123 ps
CPU time 4.71 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:17:00 PM PDT 24
Peak memory 217188 kb
Host smart-563736bd-5980-4c24-adec-7f1e559a95be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546020623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
546020623
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.984865883
Short name T1097
Test name
Test status
Simulation time 142746560 ps
CPU time 3.5 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:17:00 PM PDT 24
Peak memory 218124 kb
Host smart-b0f6c11e-8b9c-4329-9b42-16db3867a2f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984865883 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.984865883
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2517636866
Short name T125
Test name
Test status
Simulation time 47550954 ps
CPU time 1.42 seconds
Started Jul 18 05:16:48 PM PDT 24
Finished Jul 18 05:16:50 PM PDT 24
Peak memory 207808 kb
Host smart-3bec4aaf-be6f-486d-becf-310425fd073e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517636866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
517636866
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3963028224
Short name T1052
Test name
Test status
Simulation time 13160110 ps
CPU time 0.7 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:16:58 PM PDT 24
Peak memory 204760 kb
Host smart-c9f9496c-b488-481a-8207-125a9cc4d2ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963028224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
963028224
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1622148667
Short name T1041
Test name
Test status
Simulation time 222257458 ps
CPU time 1.8 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:16:58 PM PDT 24
Peak memory 215924 kb
Host smart-323bfbd6-85d0-4b01-95d0-8aa8cec1abf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622148667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1622148667
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3429445100
Short name T112
Test name
Test status
Simulation time 53478613 ps
CPU time 3.41 seconds
Started Jul 18 05:16:53 PM PDT 24
Finished Jul 18 05:16:58 PM PDT 24
Peak memory 216268 kb
Host smart-89b10039-ebe0-4b97-81ad-42fbfe4b7d52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429445100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
429445100
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1855027470
Short name T1101
Test name
Test status
Simulation time 100903121 ps
CPU time 2.08 seconds
Started Jul 18 05:16:50 PM PDT 24
Finished Jul 18 05:16:53 PM PDT 24
Peak memory 217024 kb
Host smart-652f2603-5e1f-46e8-b1be-07d6882a87a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855027470 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1855027470
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3349434520
Short name T1140
Test name
Test status
Simulation time 22284844 ps
CPU time 1.36 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:17:00 PM PDT 24
Peak memory 216036 kb
Host smart-bc91db5a-ceab-464f-a3ac-0bd87f526e9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349434520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
349434520
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3510247686
Short name T1040
Test name
Test status
Simulation time 23116459 ps
CPU time 0.72 seconds
Started Jul 18 05:16:57 PM PDT 24
Finished Jul 18 05:17:00 PM PDT 24
Peak memory 204408 kb
Host smart-d41c3c1c-2ada-4a9d-abe7-61bae1837c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510247686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
510247686
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2308332187
Short name T1116
Test name
Test status
Simulation time 1288955414 ps
CPU time 4.6 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:17:03 PM PDT 24
Peak memory 215936 kb
Host smart-2e6fd045-8fa7-4b91-8ff1-8cc4d90947c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308332187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2308332187
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1971395649
Short name T1122
Test name
Test status
Simulation time 116981411 ps
CPU time 3.09 seconds
Started Jul 18 05:16:51 PM PDT 24
Finished Jul 18 05:16:56 PM PDT 24
Peak memory 216196 kb
Host smart-cb7bfb39-6b5c-4cf5-8356-2aa3c21c38c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971395649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
971395649
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3872087412
Short name T107
Test name
Test status
Simulation time 3357335999 ps
CPU time 23.15 seconds
Started Jul 18 05:16:55 PM PDT 24
Finished Jul 18 05:17:21 PM PDT 24
Peak memory 216540 kb
Host smart-0fc0c49b-b65c-4320-a1c3-cd428793a365
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872087412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3872087412
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1703777977
Short name T1109
Test name
Test status
Simulation time 113889164 ps
CPU time 2.87 seconds
Started Jul 18 05:16:53 PM PDT 24
Finished Jul 18 05:16:58 PM PDT 24
Peak memory 216996 kb
Host smart-29b34e48-fd91-4b53-ade0-3af23e0bb920
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703777977 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1703777977
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3670115425
Short name T1095
Test name
Test status
Simulation time 37313114 ps
CPU time 1.37 seconds
Started Jul 18 05:16:52 PM PDT 24
Finished Jul 18 05:16:55 PM PDT 24
Peak memory 207680 kb
Host smart-592e6dab-09de-4720-ac1c-08f94feee3cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670115425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
670115425
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3038431188
Short name T1118
Test name
Test status
Simulation time 28444552 ps
CPU time 0.77 seconds
Started Jul 18 05:16:52 PM PDT 24
Finished Jul 18 05:16:54 PM PDT 24
Peak memory 204408 kb
Host smart-9231f1a2-4a5f-4320-8541-c78f54327175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038431188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
038431188
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3088842412
Short name T1034
Test name
Test status
Simulation time 71447894 ps
CPU time 1.82 seconds
Started Jul 18 05:17:06 PM PDT 24
Finished Jul 18 05:17:09 PM PDT 24
Peak memory 216008 kb
Host smart-3cb86ced-f983-4a6a-9735-1dc6075460a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088842412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3088842412
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2716484433
Short name T117
Test name
Test status
Simulation time 81874478 ps
CPU time 1.67 seconds
Started Jul 18 05:16:50 PM PDT 24
Finished Jul 18 05:16:53 PM PDT 24
Peak memory 216260 kb
Host smart-73ee0f71-a504-44ed-b3f7-21bb28304d73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716484433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
716484433
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3901116197
Short name T163
Test name
Test status
Simulation time 572375957 ps
CPU time 19.69 seconds
Started Jul 18 05:16:54 PM PDT 24
Finished Jul 18 05:17:16 PM PDT 24
Peak memory 216424 kb
Host smart-ebc56715-797a-4f0d-a431-a9d1844d931d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901116197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3901116197
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1050143085
Short name T447
Test name
Test status
Simulation time 32063058 ps
CPU time 0.71 seconds
Started Jul 18 05:18:52 PM PDT 24
Finished Jul 18 05:18:54 PM PDT 24
Peak memory 205136 kb
Host smart-8779c25a-3a0f-4ed0-b997-2d4094e6622d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050143085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
050143085
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1696547699
Short name T424
Test name
Test status
Simulation time 3659272370 ps
CPU time 9.8 seconds
Started Jul 18 05:18:50 PM PDT 24
Finished Jul 18 05:19:01 PM PDT 24
Peak memory 233156 kb
Host smart-660d6a59-35e7-4490-ad4b-802b590ab50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696547699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1696547699
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.4213806482
Short name T30
Test name
Test status
Simulation time 101560305 ps
CPU time 0.73 seconds
Started Jul 18 05:18:45 PM PDT 24
Finished Jul 18 05:18:48 PM PDT 24
Peak memory 207164 kb
Host smart-cadf989e-97a3-4bcd-bc34-e5b14aadb8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213806482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4213806482
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3634486912
Short name T1014
Test name
Test status
Simulation time 96302869099 ps
CPU time 170.15 seconds
Started Jul 18 05:18:49 PM PDT 24
Finished Jul 18 05:21:40 PM PDT 24
Peak memory 256688 kb
Host smart-a5ceb6f0-979b-4626-a75a-b4762bcf0c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634486912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3634486912
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2102846728
Short name T393
Test name
Test status
Simulation time 10322057198 ps
CPU time 79.14 seconds
Started Jul 18 05:18:51 PM PDT 24
Finished Jul 18 05:20:11 PM PDT 24
Peak memory 249620 kb
Host smart-713c0e74-df66-41d9-bff6-32189d636d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102846728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2102846728
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1392785811
Short name T827
Test name
Test status
Simulation time 18225088669 ps
CPU time 97.88 seconds
Started Jul 18 05:18:51 PM PDT 24
Finished Jul 18 05:20:30 PM PDT 24
Peak memory 249672 kb
Host smart-efcfa197-5c5a-47bb-81e3-ddf415e19036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392785811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1392785811
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.12825198
Short name T318
Test name
Test status
Simulation time 466568419 ps
CPU time 14.18 seconds
Started Jul 18 05:18:51 PM PDT 24
Finished Jul 18 05:19:06 PM PDT 24
Peak memory 241152 kb
Host smart-46473760-264b-465f-ba0e-3efc1aca0231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12825198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.12825198
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2383256744
Short name T70
Test name
Test status
Simulation time 71320726362 ps
CPU time 90.49 seconds
Started Jul 18 05:18:49 PM PDT 24
Finished Jul 18 05:20:21 PM PDT 24
Peak memory 249544 kb
Host smart-2d8e5c49-ceb2-482b-b3c0-0cf8ae57cf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383256744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2383256744
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1041275908
Short name T963
Test name
Test status
Simulation time 406491508 ps
CPU time 6.46 seconds
Started Jul 18 05:18:40 PM PDT 24
Finished Jul 18 05:18:49 PM PDT 24
Peak memory 233120 kb
Host smart-7511d455-feb1-4b9c-b7d2-3ddfaece9602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041275908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1041275908
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2881382433
Short name T211
Test name
Test status
Simulation time 45688850256 ps
CPU time 31.85 seconds
Started Jul 18 05:18:42 PM PDT 24
Finished Jul 18 05:19:16 PM PDT 24
Peak memory 224980 kb
Host smart-dced9d68-4ba2-4f70-b634-be8c000f1a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881382433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2881382433
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1422510141
Short name T186
Test name
Test status
Simulation time 335883707 ps
CPU time 4.63 seconds
Started Jul 18 05:18:36 PM PDT 24
Finished Jul 18 05:18:44 PM PDT 24
Peak memory 233024 kb
Host smart-25e0d13f-75b7-4466-abdc-cfe0078195b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422510141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1422510141
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1023985225
Short name T543
Test name
Test status
Simulation time 4075428411 ps
CPU time 5.25 seconds
Started Jul 18 05:18:45 PM PDT 24
Finished Jul 18 05:18:52 PM PDT 24
Peak memory 233196 kb
Host smart-c552eaa1-b596-47ba-bb87-b2016b116477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023985225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1023985225
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3664094291
Short name T763
Test name
Test status
Simulation time 4632911076 ps
CPU time 7.03 seconds
Started Jul 18 05:18:52 PM PDT 24
Finished Jul 18 05:19:00 PM PDT 24
Peak memory 223568 kb
Host smart-13d2217f-943f-460d-a05c-4a8533cd41b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3664094291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3664094291
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3371445864
Short name T153
Test name
Test status
Simulation time 7868493135 ps
CPU time 23.83 seconds
Started Jul 18 05:18:44 PM PDT 24
Finished Jul 18 05:19:10 PM PDT 24
Peak memory 234616 kb
Host smart-c1619da7-84dd-4810-adbe-3fdf54cf48c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371445864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3371445864
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1304021306
Short name T917
Test name
Test status
Simulation time 25135390699 ps
CPU time 12.28 seconds
Started Jul 18 05:18:38 PM PDT 24
Finished Jul 18 05:18:53 PM PDT 24
Peak memory 220212 kb
Host smart-9c807320-fddb-402d-9260-788b06dd1672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304021306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1304021306
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2883760720
Short name T611
Test name
Test status
Simulation time 3965680265 ps
CPU time 3.39 seconds
Started Jul 18 05:18:39 PM PDT 24
Finished Jul 18 05:18:45 PM PDT 24
Peak memory 208328 kb
Host smart-53aca710-6ba7-40ca-9be3-4ebfe4f48cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883760720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2883760720
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3193088128
Short name T922
Test name
Test status
Simulation time 29568916 ps
CPU time 0.97 seconds
Started Jul 18 05:18:45 PM PDT 24
Finished Jul 18 05:18:48 PM PDT 24
Peak memory 207432 kb
Host smart-5df2fed7-b2a6-40c8-bcd0-c35f4ab95013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193088128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3193088128
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1218568696
Short name T4
Test name
Test status
Simulation time 32578173 ps
CPU time 0.65 seconds
Started Jul 18 05:18:50 PM PDT 24
Finished Jul 18 05:18:51 PM PDT 24
Peak memory 205812 kb
Host smart-79f08587-490a-4de6-aabe-9661a82cfa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218568696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1218568696
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2911998116
Short name T894
Test name
Test status
Simulation time 6726542299 ps
CPU time 21.18 seconds
Started Jul 18 05:18:45 PM PDT 24
Finished Jul 18 05:19:08 PM PDT 24
Peak memory 233184 kb
Host smart-22320f36-07e6-428b-9b61-89fa93a8f1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911998116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2911998116
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2225868393
Short name T400
Test name
Test status
Simulation time 134204228 ps
CPU time 4.08 seconds
Started Jul 18 05:19:34 PM PDT 24
Finished Jul 18 05:19:42 PM PDT 24
Peak memory 224884 kb
Host smart-90d0ee11-f1e9-406c-99dc-d5d56b5f22a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225868393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2225868393
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1567245892
Short name T902
Test name
Test status
Simulation time 19544620 ps
CPU time 0.75 seconds
Started Jul 18 05:18:47 PM PDT 24
Finished Jul 18 05:18:49 PM PDT 24
Peak memory 205888 kb
Host smart-59d5b931-7561-4207-9482-fec565e7f440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567245892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1567245892
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1213684099
Short name T749
Test name
Test status
Simulation time 57768872530 ps
CPU time 113.62 seconds
Started Jul 18 05:19:33 PM PDT 24
Finished Jul 18 05:21:30 PM PDT 24
Peak memory 257776 kb
Host smart-2151b183-a7e9-4322-a912-a7c88529df81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213684099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1213684099
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2738705772
Short name T62
Test name
Test status
Simulation time 20688294759 ps
CPU time 83.78 seconds
Started Jul 18 05:19:30 PM PDT 24
Finished Jul 18 05:20:57 PM PDT 24
Peak memory 255452 kb
Host smart-83cffc9d-3645-49e4-b44c-6bbfe76cfcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738705772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2738705772
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.935540867
Short name T686
Test name
Test status
Simulation time 11152783078 ps
CPU time 25.96 seconds
Started Jul 18 05:19:36 PM PDT 24
Finished Jul 18 05:20:05 PM PDT 24
Peak memory 240400 kb
Host smart-2a66ea72-ea23-44b5-90eb-94bab6e98de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935540867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
935540867
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.805858694
Short name T665
Test name
Test status
Simulation time 474070941 ps
CPU time 3.65 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:19:47 PM PDT 24
Peak memory 224944 kb
Host smart-c3f0f500-e790-40ab-a6e0-fc321bde2634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805858694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.805858694
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2974905947
Short name T811
Test name
Test status
Simulation time 204525241 ps
CPU time 3.28 seconds
Started Jul 18 05:19:38 PM PDT 24
Finished Jul 18 05:19:43 PM PDT 24
Peak memory 224840 kb
Host smart-5d33ec2b-bf96-4d4f-af1f-6e5e2224acd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974905947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2974905947
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1369278427
Short name T604
Test name
Test status
Simulation time 1235152231 ps
CPU time 5.49 seconds
Started Jul 18 05:19:34 PM PDT 24
Finished Jul 18 05:19:43 PM PDT 24
Peak memory 233112 kb
Host smart-15b367db-0055-4a2a-80fb-a8481c252315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369278427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1369278427
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1247929958
Short name T437
Test name
Test status
Simulation time 14067574 ps
CPU time 0.98 seconds
Started Jul 18 05:18:44 PM PDT 24
Finished Jul 18 05:18:47 PM PDT 24
Peak memory 218404 kb
Host smart-62dd4339-db99-4c0c-9400-6f87e0321318
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247929958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1247929958
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2669597766
Short name T832
Test name
Test status
Simulation time 6123770488 ps
CPU time 11.83 seconds
Started Jul 18 05:19:33 PM PDT 24
Finished Jul 18 05:19:49 PM PDT 24
Peak memory 225060 kb
Host smart-70d07575-626f-46e2-a2bb-6a00c7934e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669597766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2669597766
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1906037955
Short name T624
Test name
Test status
Simulation time 5251545122 ps
CPU time 9.1 seconds
Started Jul 18 05:19:33 PM PDT 24
Finished Jul 18 05:19:46 PM PDT 24
Peak memory 220736 kb
Host smart-e51e046b-f59e-441f-b281-63ef605b4490
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1906037955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1906037955
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.687204258
Short name T76
Test name
Test status
Simulation time 400217878 ps
CPU time 1.05 seconds
Started Jul 18 05:19:34 PM PDT 24
Finished Jul 18 05:19:39 PM PDT 24
Peak memory 235788 kb
Host smart-33623b6b-5e6d-4499-8f7e-67925c399504
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687204258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.687204258
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3012358165
Short name T472
Test name
Test status
Simulation time 222734786 ps
CPU time 1.13 seconds
Started Jul 18 05:19:34 PM PDT 24
Finished Jul 18 05:19:39 PM PDT 24
Peak memory 207520 kb
Host smart-9ab3a6cb-f063-4e57-8160-d03fabdbc7b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012358165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3012358165
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3479204929
Short name T473
Test name
Test status
Simulation time 3742041087 ps
CPU time 5.26 seconds
Started Jul 18 05:18:51 PM PDT 24
Finished Jul 18 05:18:58 PM PDT 24
Peak memory 216756 kb
Host smart-1438ff66-052d-4dce-a0c0-737bedec3430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479204929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3479204929
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3550728053
Short name T1006
Test name
Test status
Simulation time 421852785 ps
CPU time 3.97 seconds
Started Jul 18 05:19:43 PM PDT 24
Finished Jul 18 05:19:50 PM PDT 24
Peak memory 216604 kb
Host smart-0f4b1cbc-d949-4058-83ac-d5bf00ae4bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550728053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3550728053
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.365425733
Short name T729
Test name
Test status
Simulation time 133978341 ps
CPU time 0.76 seconds
Started Jul 18 05:18:45 PM PDT 24
Finished Jul 18 05:18:48 PM PDT 24
Peak memory 206296 kb
Host smart-e51052c0-6737-4ddf-accc-0edbdde02d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365425733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.365425733
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2458383545
Short name T873
Test name
Test status
Simulation time 3727540715 ps
CPU time 10.88 seconds
Started Jul 18 05:19:39 PM PDT 24
Finished Jul 18 05:19:51 PM PDT 24
Peak memory 224992 kb
Host smart-e78241a9-f630-40a2-ade6-059bd1b51edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458383545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2458383545
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.867382639
Short name T990
Test name
Test status
Simulation time 23146122 ps
CPU time 0.74 seconds
Started Jul 18 05:21:25 PM PDT 24
Finished Jul 18 05:21:26 PM PDT 24
Peak memory 205176 kb
Host smart-4018e8be-8138-4d7a-8629-4a6a59d48621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867382639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.867382639
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.350916777
Short name T1016
Test name
Test status
Simulation time 245938008 ps
CPU time 5.57 seconds
Started Jul 18 05:21:32 PM PDT 24
Finished Jul 18 05:21:39 PM PDT 24
Peak memory 233088 kb
Host smart-44747362-b010-47bb-818d-b51804af780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350916777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.350916777
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3558672107
Short name T715
Test name
Test status
Simulation time 83581332 ps
CPU time 0.77 seconds
Started Jul 18 05:21:07 PM PDT 24
Finished Jul 18 05:21:09 PM PDT 24
Peak memory 205776 kb
Host smart-828ef0d1-35bf-4456-9a57-0bf069e90e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558672107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3558672107
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2873639753
Short name T983
Test name
Test status
Simulation time 1166951327 ps
CPU time 10.04 seconds
Started Jul 18 05:21:25 PM PDT 24
Finished Jul 18 05:21:35 PM PDT 24
Peak memory 249520 kb
Host smart-adb2f19a-8f11-4374-b52b-7d6ff6248e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873639753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2873639753
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3067963565
Short name T514
Test name
Test status
Simulation time 1437114396 ps
CPU time 18.14 seconds
Started Jul 18 05:21:29 PM PDT 24
Finished Jul 18 05:21:48 PM PDT 24
Peak memory 238024 kb
Host smart-2a55dba4-c258-4542-a57d-1b6f9ceec2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067963565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3067963565
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.4276544376
Short name T973
Test name
Test status
Simulation time 12784035419 ps
CPU time 96.36 seconds
Started Jul 18 05:21:26 PM PDT 24
Finished Jul 18 05:23:04 PM PDT 24
Peak memory 258140 kb
Host smart-d2090c09-e443-4964-804b-5d13d5bc257d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276544376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.4276544376
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3435051187
Short name T477
Test name
Test status
Simulation time 248552967 ps
CPU time 4.26 seconds
Started Jul 18 05:21:32 PM PDT 24
Finished Jul 18 05:21:37 PM PDT 24
Peak memory 234484 kb
Host smart-7dc19fb6-4abf-4036-beee-e679dd8031d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435051187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3435051187
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.4152004829
Short name T838
Test name
Test status
Simulation time 307887386208 ps
CPU time 523.07 seconds
Started Jul 18 05:21:25 PM PDT 24
Finished Jul 18 05:30:10 PM PDT 24
Peak memory 265316 kb
Host smart-d08c9590-825b-4fd5-aa61-f6d3ca72d97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152004829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.4152004829
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2290276392
Short name T471
Test name
Test status
Simulation time 879442467 ps
CPU time 5.54 seconds
Started Jul 18 05:21:28 PM PDT 24
Finished Jul 18 05:21:35 PM PDT 24
Peak memory 224880 kb
Host smart-5c84e76b-f18a-42f1-b2ea-08003d7ac3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290276392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2290276392
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1867300848
Short name T545
Test name
Test status
Simulation time 48057884898 ps
CPU time 63.92 seconds
Started Jul 18 05:21:27 PM PDT 24
Finished Jul 18 05:22:32 PM PDT 24
Peak memory 241376 kb
Host smart-52aa2496-f3de-4ca9-826a-b62ba888bac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867300848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1867300848
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2841209683
Short name T38
Test name
Test status
Simulation time 17226082 ps
CPU time 1.02 seconds
Started Jul 18 05:21:05 PM PDT 24
Finished Jul 18 05:21:07 PM PDT 24
Peak memory 217124 kb
Host smart-dce98ffa-61a0-4f9c-92be-bfd1260fddc4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841209683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2841209683
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1447022911
Short name T485
Test name
Test status
Simulation time 700805669 ps
CPU time 4.21 seconds
Started Jul 18 05:21:18 PM PDT 24
Finished Jul 18 05:21:23 PM PDT 24
Peak memory 224908 kb
Host smart-8ec608fd-6476-48eb-8d97-10f1c8f1551d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447022911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1447022911
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1365349360
Short name T986
Test name
Test status
Simulation time 742766463 ps
CPU time 3.39 seconds
Started Jul 18 05:21:25 PM PDT 24
Finished Jul 18 05:21:29 PM PDT 24
Peak memory 219324 kb
Host smart-b8a8d8cb-aed5-4fa9-a0f8-443bf9519dc7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1365349360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1365349360
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.249258441
Short name T887
Test name
Test status
Simulation time 11545299869 ps
CPU time 128.1 seconds
Started Jul 18 05:21:25 PM PDT 24
Finished Jul 18 05:23:34 PM PDT 24
Peak memory 239732 kb
Host smart-e6f8c694-e1fc-469a-9820-63669b54f3df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249258441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.249258441
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1600278573
Short name T389
Test name
Test status
Simulation time 3185052984 ps
CPU time 9.31 seconds
Started Jul 18 05:21:18 PM PDT 24
Finished Jul 18 05:21:28 PM PDT 24
Peak memory 216856 kb
Host smart-e3b3cbcf-c900-47a2-9d09-2c3ff50c095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600278573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1600278573
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3480511697
Short name T354
Test name
Test status
Simulation time 16576205958 ps
CPU time 11.66 seconds
Started Jul 18 05:21:18 PM PDT 24
Finished Jul 18 05:21:30 PM PDT 24
Peak memory 216544 kb
Host smart-cbd93f78-db51-4c7f-a53f-773f6195ef9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480511697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3480511697
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.4162201583
Short name T620
Test name
Test status
Simulation time 22485784 ps
CPU time 0.92 seconds
Started Jul 18 05:21:19 PM PDT 24
Finished Jul 18 05:21:21 PM PDT 24
Peak memory 207608 kb
Host smart-428e1ba6-ce0f-41b8-a464-40f7d29893f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162201583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4162201583
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3670028863
Short name T890
Test name
Test status
Simulation time 138897791 ps
CPU time 0.91 seconds
Started Jul 18 05:21:18 PM PDT 24
Finished Jul 18 05:21:19 PM PDT 24
Peak memory 207232 kb
Host smart-10d8f37f-fa93-4850-808b-3f2d77e30dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670028863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3670028863
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2470252095
Short name T755
Test name
Test status
Simulation time 10716714112 ps
CPU time 9.71 seconds
Started Jul 18 05:21:29 PM PDT 24
Finished Jul 18 05:21:39 PM PDT 24
Peak memory 233256 kb
Host smart-40214d39-9119-4004-b4ad-24dc801784d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470252095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2470252095
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1236713306
Short name T1003
Test name
Test status
Simulation time 36369653 ps
CPU time 0.73 seconds
Started Jul 18 05:21:28 PM PDT 24
Finished Jul 18 05:21:30 PM PDT 24
Peak memory 206040 kb
Host smart-3875fa29-a863-4166-873c-02e9ed14ad9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236713306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1236713306
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4021326094
Short name T631
Test name
Test status
Simulation time 29934435 ps
CPU time 2.18 seconds
Started Jul 18 05:21:26 PM PDT 24
Finished Jul 18 05:21:29 PM PDT 24
Peak memory 224532 kb
Host smart-a0b82ec3-2eb6-43c4-99c3-2e1d00911e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021326094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4021326094
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.552050817
Short name T874
Test name
Test status
Simulation time 98967814 ps
CPU time 0.77 seconds
Started Jul 18 05:21:31 PM PDT 24
Finished Jul 18 05:21:33 PM PDT 24
Peak memory 206868 kb
Host smart-ed62e9bc-b594-4faa-a127-1b382e5c3f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552050817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.552050817
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3390616601
Short name T521
Test name
Test status
Simulation time 132642684103 ps
CPU time 224.49 seconds
Started Jul 18 05:21:33 PM PDT 24
Finished Jul 18 05:25:18 PM PDT 24
Peak memory 251476 kb
Host smart-9c4926c3-76a8-48a3-bf4b-ae64502b44ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390616601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3390616601
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3444844780
Short name T784
Test name
Test status
Simulation time 72840798376 ps
CPU time 624.21 seconds
Started Jul 18 05:21:32 PM PDT 24
Finished Jul 18 05:31:57 PM PDT 24
Peak memory 257812 kb
Host smart-9b7d8c79-eafe-4edb-9cfe-683134df6778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444844780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3444844780
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3495998423
Short name T187
Test name
Test status
Simulation time 24226458561 ps
CPU time 61.66 seconds
Started Jul 18 05:21:23 PM PDT 24
Finished Jul 18 05:22:26 PM PDT 24
Peak memory 241452 kb
Host smart-51953bf9-9b13-49db-bd5a-f9d641719626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495998423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3495998423
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2409868919
Short name T987
Test name
Test status
Simulation time 7818320447 ps
CPU time 16.63 seconds
Started Jul 18 05:21:23 PM PDT 24
Finished Jul 18 05:21:41 PM PDT 24
Peak memory 234748 kb
Host smart-67c3c327-7613-410a-8b02-802d0128b8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409868919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2409868919
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2095478081
Short name T852
Test name
Test status
Simulation time 1477975795 ps
CPU time 32.64 seconds
Started Jul 18 05:21:29 PM PDT 24
Finished Jul 18 05:22:03 PM PDT 24
Peak memory 254620 kb
Host smart-8213bbb3-a7e9-45ae-9c53-5f8ec9b808d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095478081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2095478081
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2192711825
Short name T182
Test name
Test status
Simulation time 132408529 ps
CPU time 4.34 seconds
Started Jul 18 05:21:32 PM PDT 24
Finished Jul 18 05:21:37 PM PDT 24
Peak memory 224872 kb
Host smart-8f2f0ae8-d752-424d-9764-8bae172d8dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192711825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2192711825
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1573263059
Short name T273
Test name
Test status
Simulation time 1217066817 ps
CPU time 9.17 seconds
Started Jul 18 05:21:30 PM PDT 24
Finished Jul 18 05:21:40 PM PDT 24
Peak memory 224884 kb
Host smart-70ce1aeb-3635-46de-b6a9-d17df1f6a735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573263059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1573263059
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.355415051
Short name T792
Test name
Test status
Simulation time 23511844 ps
CPU time 1.02 seconds
Started Jul 18 05:21:28 PM PDT 24
Finished Jul 18 05:21:29 PM PDT 24
Peak memory 218288 kb
Host smart-74d48194-9c3e-4d06-934e-1a5c7d1dceee
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355415051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.355415051
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3900552997
Short name T956
Test name
Test status
Simulation time 5088446044 ps
CPU time 11.66 seconds
Started Jul 18 05:21:25 PM PDT 24
Finished Jul 18 05:21:38 PM PDT 24
Peak memory 249484 kb
Host smart-4110471c-5de0-4458-b2f2-44492f23e849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900552997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3900552997
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.55461047
Short name T281
Test name
Test status
Simulation time 10019214316 ps
CPU time 14.19 seconds
Started Jul 18 05:21:26 PM PDT 24
Finished Jul 18 05:21:41 PM PDT 24
Peak memory 233320 kb
Host smart-ed37ad4f-7f8f-4294-a005-64983dd4a8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55461047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.55461047
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1681323802
Short name T42
Test name
Test status
Simulation time 1146428239 ps
CPU time 6.58 seconds
Started Jul 18 05:21:26 PM PDT 24
Finished Jul 18 05:21:34 PM PDT 24
Peak memory 222568 kb
Host smart-8e4cb12e-a25f-4fc7-b134-74035e63758d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1681323802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1681323802
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4010098271
Short name T188
Test name
Test status
Simulation time 51638000357 ps
CPU time 439.59 seconds
Started Jul 18 05:21:29 PM PDT 24
Finished Jul 18 05:28:50 PM PDT 24
Peak memory 253332 kb
Host smart-4de8769f-60ad-468c-89b5-dc926fc4806d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010098271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4010098271
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.4285851058
Short name T361
Test name
Test status
Simulation time 912603078 ps
CPU time 4.98 seconds
Started Jul 18 05:21:29 PM PDT 24
Finished Jul 18 05:21:35 PM PDT 24
Peak memory 216700 kb
Host smart-22511e5c-0e28-4afb-8c48-ed0857b9c782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285851058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.4285851058
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.479925766
Short name T356
Test name
Test status
Simulation time 2340421940 ps
CPU time 6.83 seconds
Started Jul 18 05:21:26 PM PDT 24
Finished Jul 18 05:21:34 PM PDT 24
Peak memory 216664 kb
Host smart-68623e97-f963-4d5a-ab30-e1e7942c0ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479925766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.479925766
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2253634886
Short name T550
Test name
Test status
Simulation time 55780900 ps
CPU time 0.87 seconds
Started Jul 18 05:21:26 PM PDT 24
Finished Jul 18 05:21:28 PM PDT 24
Peak memory 206192 kb
Host smart-486fc2c0-aadf-49ce-9e9b-22dbfe34dffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253634886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2253634886
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3905757524
Short name T481
Test name
Test status
Simulation time 123417049 ps
CPU time 0.81 seconds
Started Jul 18 05:21:28 PM PDT 24
Finished Jul 18 05:21:30 PM PDT 24
Peak memory 206208 kb
Host smart-dbfa8648-ed4b-4e68-933b-5aa9ebf0dd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905757524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3905757524
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1786814695
Short name T552
Test name
Test status
Simulation time 39428726 ps
CPU time 0.74 seconds
Started Jul 18 05:21:51 PM PDT 24
Finished Jul 18 05:21:53 PM PDT 24
Peak memory 205112 kb
Host smart-a4d2673c-a16b-4074-ad47-4ed1cf6442d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786814695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1786814695
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3960096246
Short name T45
Test name
Test status
Simulation time 182149079 ps
CPU time 3.75 seconds
Started Jul 18 05:21:48 PM PDT 24
Finished Jul 18 05:21:54 PM PDT 24
Peak memory 233132 kb
Host smart-9e1e7dee-c36d-497e-a969-e60d58a021bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960096246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3960096246
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.293957492
Short name T802
Test name
Test status
Simulation time 15262907 ps
CPU time 0.77 seconds
Started Jul 18 05:21:51 PM PDT 24
Finished Jul 18 05:21:53 PM PDT 24
Peak memory 206828 kb
Host smart-a9f1aa8a-d6c0-4f24-af14-38c6aceb6972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293957492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.293957492
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1984905511
Short name T867
Test name
Test status
Simulation time 64605524566 ps
CPU time 282.26 seconds
Started Jul 18 05:21:48 PM PDT 24
Finished Jul 18 05:26:31 PM PDT 24
Peak memory 252788 kb
Host smart-ba26410d-c52b-4d05-abac-378e9d69e381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984905511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1984905511
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2590688972
Short name T822
Test name
Test status
Simulation time 3818022702 ps
CPU time 78.4 seconds
Started Jul 18 05:21:48 PM PDT 24
Finished Jul 18 05:23:08 PM PDT 24
Peak memory 257440 kb
Host smart-3ab64bce-e6a2-40e8-bd3a-e1345f82e5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590688972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2590688972
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1948529106
Short name T333
Test name
Test status
Simulation time 21952486851 ps
CPU time 57.34 seconds
Started Jul 18 05:21:51 PM PDT 24
Finished Jul 18 05:22:50 PM PDT 24
Peak memory 253648 kb
Host smart-9cc75ab1-f2f6-4d6f-85bc-aa4395908ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948529106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1948529106
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1455576910
Short name T835
Test name
Test status
Simulation time 165084202 ps
CPU time 8.87 seconds
Started Jul 18 05:21:50 PM PDT 24
Finished Jul 18 05:22:00 PM PDT 24
Peak memory 234136 kb
Host smart-614779f9-81b6-4ae0-8802-e9375ddbf7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455576910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1455576910
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2269926387
Short name T307
Test name
Test status
Simulation time 6139675849 ps
CPU time 87.43 seconds
Started Jul 18 05:21:45 PM PDT 24
Finished Jul 18 05:23:13 PM PDT 24
Peak memory 249612 kb
Host smart-2c646866-61dc-47ea-9306-dae8ff74e338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269926387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2269926387
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3812994300
Short name T529
Test name
Test status
Simulation time 536617334 ps
CPU time 3.59 seconds
Started Jul 18 05:21:45 PM PDT 24
Finished Jul 18 05:21:49 PM PDT 24
Peak memory 233120 kb
Host smart-f9d95c1f-d744-41d8-b0f1-5e4a02289747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812994300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3812994300
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4168924545
Short name T599
Test name
Test status
Simulation time 9310191563 ps
CPU time 50.96 seconds
Started Jul 18 05:21:51 PM PDT 24
Finished Jul 18 05:22:44 PM PDT 24
Peak memory 224948 kb
Host smart-887fe5f2-59d1-4f88-9c81-2e3aa3f59e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168924545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4168924545
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3385654812
Short name T777
Test name
Test status
Simulation time 87253852 ps
CPU time 1.1 seconds
Started Jul 18 05:21:46 PM PDT 24
Finished Jul 18 05:21:48 PM PDT 24
Peak memory 217056 kb
Host smart-3b151afa-fd5a-455d-a8f7-534f0a4dd5a8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385654812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3385654812
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4060242338
Short name T644
Test name
Test status
Simulation time 1183543853 ps
CPU time 4.39 seconds
Started Jul 18 05:21:50 PM PDT 24
Finished Jul 18 05:21:56 PM PDT 24
Peak memory 224928 kb
Host smart-7d9f3296-049e-47f0-911a-e84540576b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060242338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4060242338
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4247686415
Short name T851
Test name
Test status
Simulation time 689073988 ps
CPU time 4.42 seconds
Started Jul 18 05:21:50 PM PDT 24
Finished Jul 18 05:21:56 PM PDT 24
Peak memory 233128 kb
Host smart-2316144b-92e4-4c80-b646-5cd0f2fc3ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247686415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4247686415
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2069751378
Short name T564
Test name
Test status
Simulation time 1268259756 ps
CPU time 11.28 seconds
Started Jul 18 05:21:48 PM PDT 24
Finished Jul 18 05:22:01 PM PDT 24
Peak memory 219080 kb
Host smart-be3f877c-862b-4ffb-86b0-6232f7e0bb48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2069751378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2069751378
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2345712432
Short name T771
Test name
Test status
Simulation time 152395366 ps
CPU time 0.9 seconds
Started Jul 18 05:21:45 PM PDT 24
Finished Jul 18 05:21:47 PM PDT 24
Peak memory 206900 kb
Host smart-7bd1e164-01a0-4a25-84a8-eec07a0d6478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345712432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2345712432
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.642618246
Short name T681
Test name
Test status
Simulation time 8231342708 ps
CPU time 46.16 seconds
Started Jul 18 05:21:49 PM PDT 24
Finished Jul 18 05:22:36 PM PDT 24
Peak memory 218424 kb
Host smart-34d16cac-e7ec-46c0-8a14-7fc2f974fd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642618246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.642618246
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1489416505
Short name T339
Test name
Test status
Simulation time 36385677774 ps
CPU time 21.46 seconds
Started Jul 18 05:21:47 PM PDT 24
Finished Jul 18 05:22:10 PM PDT 24
Peak memory 216704 kb
Host smart-05df6489-1851-42b0-ae61-788d17e37549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489416505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1489416505
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.605799259
Short name T817
Test name
Test status
Simulation time 312671598 ps
CPU time 9.6 seconds
Started Jul 18 05:21:47 PM PDT 24
Finished Jul 18 05:21:58 PM PDT 24
Peak memory 216536 kb
Host smart-170d1736-a786-4511-8c97-f1655d1d1bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605799259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.605799259
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1538881433
Short name T343
Test name
Test status
Simulation time 262345273 ps
CPU time 0.75 seconds
Started Jul 18 05:21:51 PM PDT 24
Finished Jul 18 05:21:53 PM PDT 24
Peak memory 206308 kb
Host smart-61d13b20-2e51-4abe-b990-ada0e7b23df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538881433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1538881433
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2450628732
Short name T171
Test name
Test status
Simulation time 1355503780 ps
CPU time 7.93 seconds
Started Jul 18 05:21:51 PM PDT 24
Finished Jul 18 05:22:00 PM PDT 24
Peak memory 236488 kb
Host smart-38de71f5-1106-452b-8fa1-0e0773c64529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450628732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2450628732
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2953187383
Short name T369
Test name
Test status
Simulation time 43402258 ps
CPU time 0.79 seconds
Started Jul 18 05:22:35 PM PDT 24
Finished Jul 18 05:22:38 PM PDT 24
Peak memory 205728 kb
Host smart-24b918e3-45f8-42ad-adc2-ceb434813eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953187383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2953187383
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3378377344
Short name T237
Test name
Test status
Simulation time 2541242545 ps
CPU time 12.37 seconds
Started Jul 18 05:21:50 PM PDT 24
Finished Jul 18 05:22:04 PM PDT 24
Peak memory 225036 kb
Host smart-877e5ba2-a6f0-4334-b9ef-d2e48b73ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378377344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3378377344
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3666544544
Short name T856
Test name
Test status
Simulation time 31168447 ps
CPU time 0.82 seconds
Started Jul 18 05:22:13 PM PDT 24
Finished Jul 18 05:22:14 PM PDT 24
Peak memory 206852 kb
Host smart-9f9583f8-738f-4164-b99f-1571adf1342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666544544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3666544544
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.768756039
Short name T455
Test name
Test status
Simulation time 1211561432 ps
CPU time 15.4 seconds
Started Jul 18 05:21:51 PM PDT 24
Finished Jul 18 05:22:08 PM PDT 24
Peak memory 250088 kb
Host smart-0a04432d-927c-47bb-ad76-c60ffa7e971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768756039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.768756039
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4051852685
Short name T222
Test name
Test status
Simulation time 5937034971 ps
CPU time 79.04 seconds
Started Jul 18 05:21:53 PM PDT 24
Finished Jul 18 05:23:12 PM PDT 24
Peak memory 249736 kb
Host smart-bb06db09-3b69-4855-a619-cb502db5d75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051852685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4051852685
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1816544113
Short name T580
Test name
Test status
Simulation time 15154525203 ps
CPU time 32.7 seconds
Started Jul 18 05:21:50 PM PDT 24
Finished Jul 18 05:22:25 PM PDT 24
Peak memory 218096 kb
Host smart-d960724a-8b73-4bf1-b9fc-eed5754c6d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816544113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1816544113
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.715539718
Short name T1018
Test name
Test status
Simulation time 601299173 ps
CPU time 9.19 seconds
Started Jul 18 05:21:51 PM PDT 24
Finished Jul 18 05:22:01 PM PDT 24
Peak memory 224916 kb
Host smart-4b97bb35-d5a5-4989-a9d0-7b991992f357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715539718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.715539718
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3754692433
Short name T936
Test name
Test status
Simulation time 67367756218 ps
CPU time 119.58 seconds
Started Jul 18 05:21:51 PM PDT 24
Finished Jul 18 05:23:52 PM PDT 24
Peak memory 238868 kb
Host smart-73e9d462-afbf-4c69-87e1-f1edb8379d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754692433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3754692433
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.245675661
Short name T743
Test name
Test status
Simulation time 131007345 ps
CPU time 2.93 seconds
Started Jul 18 05:21:48 PM PDT 24
Finished Jul 18 05:21:52 PM PDT 24
Peak memory 224852 kb
Host smart-274d2b5a-73f4-4bbc-b0ec-aa44c03b0130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245675661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.245675661
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3946410011
Short name T735
Test name
Test status
Simulation time 3585806597 ps
CPU time 36.73 seconds
Started Jul 18 05:21:50 PM PDT 24
Finished Jul 18 05:22:29 PM PDT 24
Peak memory 233204 kb
Host smart-f7f6e5f9-a6d6-4ba6-81c7-b2532a272a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946410011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3946410011
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.977346715
Short name T39
Test name
Test status
Simulation time 31908218 ps
CPU time 1.04 seconds
Started Jul 18 05:21:51 PM PDT 24
Finished Jul 18 05:21:54 PM PDT 24
Peak memory 218284 kb
Host smart-8f440bf7-2f83-4255-a3f8-a817fa384738
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977346715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.977346715
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3175319210
Short name T265
Test name
Test status
Simulation time 1053381770 ps
CPU time 10.84 seconds
Started Jul 18 05:21:50 PM PDT 24
Finished Jul 18 05:22:02 PM PDT 24
Peak memory 239480 kb
Host smart-cd98004c-a24a-4bc3-9058-ddf2c7ead0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175319210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3175319210
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1775962467
Short name T12
Test name
Test status
Simulation time 10631457207 ps
CPU time 10.86 seconds
Started Jul 18 05:21:51 PM PDT 24
Finished Jul 18 05:22:03 PM PDT 24
Peak memory 233244 kb
Host smart-d78bb26c-c23a-4611-87d7-8579a867fdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775962467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1775962467
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2063027689
Short name T406
Test name
Test status
Simulation time 340846584 ps
CPU time 3.69 seconds
Started Jul 18 05:21:49 PM PDT 24
Finished Jul 18 05:21:54 PM PDT 24
Peak memory 219028 kb
Host smart-01aae5ee-aef6-4c5f-b2cc-92f457a1e0f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2063027689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2063027689
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2182899920
Short name T504
Test name
Test status
Simulation time 7990008111 ps
CPU time 20.85 seconds
Started Jul 18 05:21:47 PM PDT 24
Finished Jul 18 05:22:09 PM PDT 24
Peak memory 224904 kb
Host smart-a7e7e20c-0be0-4464-8491-ca48d0a4f8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182899920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2182899920
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2278771069
Short name T448
Test name
Test status
Simulation time 40870887995 ps
CPU time 22.45 seconds
Started Jul 18 05:21:51 PM PDT 24
Finished Jul 18 05:22:14 PM PDT 24
Peak memory 221068 kb
Host smart-da7b2e44-ec55-46ab-829f-91c36679f9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278771069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2278771069
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4132734675
Short name T519
Test name
Test status
Simulation time 2582244067 ps
CPU time 3.44 seconds
Started Jul 18 05:21:48 PM PDT 24
Finished Jul 18 05:21:53 PM PDT 24
Peak memory 216704 kb
Host smart-fc66499d-7cff-4403-b4fe-148ae40d19be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132734675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4132734675
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.417783758
Short name T436
Test name
Test status
Simulation time 40278258 ps
CPU time 0.93 seconds
Started Jul 18 05:21:49 PM PDT 24
Finished Jul 18 05:21:51 PM PDT 24
Peak memory 207040 kb
Host smart-44421a1d-42a6-45b6-ab08-6d92f1b1ae53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417783758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.417783758
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2019045845
Short name T479
Test name
Test status
Simulation time 47307219 ps
CPU time 0.86 seconds
Started Jul 18 05:21:49 PM PDT 24
Finished Jul 18 05:21:51 PM PDT 24
Peak memory 206248 kb
Host smart-b0dcf894-859d-413e-ad6f-41b0c07f49bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019045845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2019045845
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3376208122
Short name T189
Test name
Test status
Simulation time 478821090 ps
CPU time 5.24 seconds
Started Jul 18 05:21:50 PM PDT 24
Finished Jul 18 05:21:57 PM PDT 24
Peak memory 238744 kb
Host smart-7c989d8e-fea2-4e06-b0ab-77530c538c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376208122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3376208122
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3327752556
Short name T667
Test name
Test status
Simulation time 12340557 ps
CPU time 0.74 seconds
Started Jul 18 05:22:37 PM PDT 24
Finished Jul 18 05:22:39 PM PDT 24
Peak memory 205760 kb
Host smart-d6a2aab9-78d8-4a73-a606-4cc20bd43f67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327752556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3327752556
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1048593295
Short name T592
Test name
Test status
Simulation time 64378333 ps
CPU time 3.27 seconds
Started Jul 18 05:22:34 PM PDT 24
Finished Jul 18 05:22:39 PM PDT 24
Peak memory 224868 kb
Host smart-56e476d0-e2a4-43f0-ae5f-57aa7f953d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048593295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1048593295
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2897003664
Short name T460
Test name
Test status
Simulation time 34637342 ps
CPU time 0.78 seconds
Started Jul 18 05:22:34 PM PDT 24
Finished Jul 18 05:22:37 PM PDT 24
Peak memory 206876 kb
Host smart-163a9f97-6544-44fc-9efe-b8c2c9a540e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897003664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2897003664
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2277096175
Short name T914
Test name
Test status
Simulation time 12872741485 ps
CPU time 91.44 seconds
Started Jul 18 05:22:33 PM PDT 24
Finished Jul 18 05:24:05 PM PDT 24
Peak memory 263452 kb
Host smart-fcf98711-2c8b-4a01-aab8-0a7499f8b897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277096175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2277096175
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.4085582049
Short name T323
Test name
Test status
Simulation time 941506216 ps
CPU time 7.42 seconds
Started Jul 18 05:22:38 PM PDT 24
Finished Jul 18 05:22:46 PM PDT 24
Peak memory 219640 kb
Host smart-eac7763b-fbd0-446e-ab91-66cc842b6b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085582049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.4085582049
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3989918473
Short name T464
Test name
Test status
Simulation time 1672620031 ps
CPU time 6.05 seconds
Started Jul 18 05:22:38 PM PDT 24
Finished Jul 18 05:22:45 PM PDT 24
Peak memory 234728 kb
Host smart-914dee4b-4b17-4995-865e-52d5d0c3ab63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989918473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3989918473
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.334899727
Short name T101
Test name
Test status
Simulation time 4401180182 ps
CPU time 18.47 seconds
Started Jul 18 05:22:33 PM PDT 24
Finished Jul 18 05:22:52 PM PDT 24
Peak memory 237940 kb
Host smart-166fa50d-8bea-4f47-8b9b-3a2091f925ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334899727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.334899727
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1752720571
Short name T800
Test name
Test status
Simulation time 4936710848 ps
CPU time 47.63 seconds
Started Jul 18 05:22:31 PM PDT 24
Finished Jul 18 05:23:19 PM PDT 24
Peak memory 233336 kb
Host smart-cac294b3-c82c-4abf-806f-fc850ebd0d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752720571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1752720571
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3156587539
Short name T928
Test name
Test status
Simulation time 3903014352 ps
CPU time 45.42 seconds
Started Jul 18 05:22:35 PM PDT 24
Finished Jul 18 05:23:23 PM PDT 24
Peak memory 250940 kb
Host smart-2815f259-864b-412c-b8de-fc6b4bc8162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156587539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3156587539
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.372999984
Short name T445
Test name
Test status
Simulation time 31541335 ps
CPU time 1.05 seconds
Started Jul 18 05:22:34 PM PDT 24
Finished Jul 18 05:22:36 PM PDT 24
Peak memory 217076 kb
Host smart-b0f8848e-2166-424c-8edf-ce12e895f15c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372999984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.372999984
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3463666182
Short name T54
Test name
Test status
Simulation time 1590879874 ps
CPU time 6.77 seconds
Started Jul 18 05:22:36 PM PDT 24
Finished Jul 18 05:22:44 PM PDT 24
Peak memory 241352 kb
Host smart-8a681abc-3be4-4030-a8af-74e7240a4063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463666182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3463666182
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.240941076
Short name T227
Test name
Test status
Simulation time 571384017 ps
CPU time 5.01 seconds
Started Jul 18 05:22:34 PM PDT 24
Finished Jul 18 05:22:41 PM PDT 24
Peak memory 233068 kb
Host smart-e0f8cffa-9799-4176-8890-feb0e2dcc21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240941076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.240941076
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1188133709
Short name T501
Test name
Test status
Simulation time 468422362 ps
CPU time 4.44 seconds
Started Jul 18 05:22:31 PM PDT 24
Finished Jul 18 05:22:37 PM PDT 24
Peak memory 223276 kb
Host smart-293e8484-e281-4e47-8942-4c9bc8b087c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1188133709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1188133709
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1601866882
Short name T433
Test name
Test status
Simulation time 50623922198 ps
CPU time 130.97 seconds
Started Jul 18 05:22:38 PM PDT 24
Finished Jul 18 05:24:50 PM PDT 24
Peak memory 249676 kb
Host smart-6c4b8fcb-c500-43df-b6da-13b05cb7a95a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601866882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1601866882
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1270173225
Short name T368
Test name
Test status
Simulation time 3080150412 ps
CPU time 10.83 seconds
Started Jul 18 05:22:34 PM PDT 24
Finished Jul 18 05:22:47 PM PDT 24
Peak memory 216808 kb
Host smart-c2d82ccc-864c-4f42-8a3e-15685ecb8bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270173225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1270173225
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1967458174
Short name T591
Test name
Test status
Simulation time 1491105460 ps
CPU time 6.04 seconds
Started Jul 18 05:22:36 PM PDT 24
Finished Jul 18 05:22:44 PM PDT 24
Peak memory 216828 kb
Host smart-1717f56b-838f-4b53-9002-6088e8a53014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967458174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1967458174
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3191343577
Short name T582
Test name
Test status
Simulation time 33348917 ps
CPU time 0.9 seconds
Started Jul 18 05:22:36 PM PDT 24
Finished Jul 18 05:22:38 PM PDT 24
Peak memory 206864 kb
Host smart-3d365634-51fd-409d-a424-cb12d53f3dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191343577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3191343577
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4293855338
Short name T674
Test name
Test status
Simulation time 109652023 ps
CPU time 0.83 seconds
Started Jul 18 05:30:46 PM PDT 24
Finished Jul 18 05:30:51 PM PDT 24
Peak memory 207272 kb
Host smart-5e1433fe-57e8-4077-8538-3c13fa5c3afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293855338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4293855338
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.729843207
Short name T190
Test name
Test status
Simulation time 1221229299 ps
CPU time 10.53 seconds
Started Jul 18 05:22:36 PM PDT 24
Finished Jul 18 05:22:49 PM PDT 24
Peak memory 224872 kb
Host smart-ce9bf506-8c14-4463-83cd-d7a4182eabe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729843207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.729843207
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2594479279
Short name T342
Test name
Test status
Simulation time 25524137 ps
CPU time 0.7 seconds
Started Jul 18 05:22:33 PM PDT 24
Finished Jul 18 05:22:35 PM PDT 24
Peak memory 205724 kb
Host smart-b0179f7c-64c4-4459-8b9a-141bdb417354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594479279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2594479279
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3003959568
Short name T612
Test name
Test status
Simulation time 275394238 ps
CPU time 2.68 seconds
Started Jul 18 05:22:36 PM PDT 24
Finished Jul 18 05:22:40 PM PDT 24
Peak memory 224932 kb
Host smart-921ce9c7-34a9-4417-ad61-ed5a0d5ba423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003959568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3003959568
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3233551604
Short name T994
Test name
Test status
Simulation time 12088465 ps
CPU time 0.77 seconds
Started Jul 18 05:22:35 PM PDT 24
Finished Jul 18 05:22:38 PM PDT 24
Peak memory 205776 kb
Host smart-4d4dacd6-33ed-4d20-9c56-558026036ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233551604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3233551604
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.59840566
Short name T659
Test name
Test status
Simulation time 8025255743 ps
CPU time 70.68 seconds
Started Jul 18 05:22:37 PM PDT 24
Finished Jul 18 05:23:50 PM PDT 24
Peak memory 249612 kb
Host smart-23f46da6-e33d-4690-83d7-e69d36f5b029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59840566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.59840566
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3180616112
Short name T977
Test name
Test status
Simulation time 32437917864 ps
CPU time 362.52 seconds
Started Jul 18 05:22:36 PM PDT 24
Finished Jul 18 05:28:40 PM PDT 24
Peak memory 265844 kb
Host smart-0e30b72c-6634-426e-b435-4e7212442c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180616112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3180616112
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1978611550
Short name T56
Test name
Test status
Simulation time 40179587177 ps
CPU time 249.94 seconds
Started Jul 18 05:22:32 PM PDT 24
Finished Jul 18 05:26:43 PM PDT 24
Peak memory 266128 kb
Host smart-f3a042b5-1ead-43f4-be91-ef14616efdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978611550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1978611550
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.4072399070
Short name T860
Test name
Test status
Simulation time 3230250824 ps
CPU time 44.55 seconds
Started Jul 18 05:22:33 PM PDT 24
Finished Jul 18 05:23:19 PM PDT 24
Peak memory 225056 kb
Host smart-7ea890d1-49aa-4567-adaf-35b0ad823583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072399070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.4072399070
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.317362771
Short name T353
Test name
Test status
Simulation time 151752183 ps
CPU time 0.75 seconds
Started Jul 18 05:22:31 PM PDT 24
Finished Jul 18 05:22:33 PM PDT 24
Peak memory 216368 kb
Host smart-b97fff26-bb29-4270-8292-d0fba5a05a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317362771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.317362771
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.4253638767
Short name T810
Test name
Test status
Simulation time 55398170 ps
CPU time 2.15 seconds
Started Jul 18 05:22:36 PM PDT 24
Finished Jul 18 05:22:40 PM PDT 24
Peak memory 224424 kb
Host smart-9b460392-d867-4c97-a768-6836a8e4b8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253638767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4253638767
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3963856369
Short name T875
Test name
Test status
Simulation time 2309231729 ps
CPU time 13.4 seconds
Started Jul 18 05:22:32 PM PDT 24
Finished Jul 18 05:22:46 PM PDT 24
Peak memory 233216 kb
Host smart-79fad7b7-b254-4cf7-9236-ee280366716d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963856369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3963856369
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2861410342
Short name T713
Test name
Test status
Simulation time 18024509 ps
CPU time 1.07 seconds
Started Jul 18 05:22:34 PM PDT 24
Finished Jul 18 05:22:36 PM PDT 24
Peak memory 217164 kb
Host smart-5ae09459-be36-422c-9c46-bc45c80720dd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861410342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2861410342
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3169021283
Short name T559
Test name
Test status
Simulation time 183057811 ps
CPU time 3.09 seconds
Started Jul 18 05:22:34 PM PDT 24
Finished Jul 18 05:22:39 PM PDT 24
Peak memory 224944 kb
Host smart-35a1106c-c23e-4fc3-bde9-0fcc0197cbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169021283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3169021283
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.247280249
Short name T378
Test name
Test status
Simulation time 2867278567 ps
CPU time 4.36 seconds
Started Jul 18 05:22:33 PM PDT 24
Finished Jul 18 05:22:37 PM PDT 24
Peak memory 233128 kb
Host smart-0dc32355-cca6-46c3-9fc8-d63e2b1da883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247280249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.247280249
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.443118070
Short name T147
Test name
Test status
Simulation time 273979167 ps
CPU time 5.27 seconds
Started Jul 18 05:22:37 PM PDT 24
Finished Jul 18 05:22:44 PM PDT 24
Peak memory 220664 kb
Host smart-e422ec63-d41b-4e3f-b366-f4024444cb34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=443118070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.443118070
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2898538917
Short name T18
Test name
Test status
Simulation time 84171099878 ps
CPU time 431.48 seconds
Started Jul 18 05:22:33 PM PDT 24
Finished Jul 18 05:29:45 PM PDT 24
Peak memory 267140 kb
Host smart-8c34fbb1-80cd-409a-8366-e68066f0db1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898538917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2898538917
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1433883204
Short name T961
Test name
Test status
Simulation time 16036919721 ps
CPU time 19.65 seconds
Started Jul 18 05:22:30 PM PDT 24
Finished Jul 18 05:22:50 PM PDT 24
Peak memory 216788 kb
Host smart-ff5b7eae-8964-45b7-89ba-298c8d547744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433883204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1433883204
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1398391139
Short name T85
Test name
Test status
Simulation time 781371372 ps
CPU time 5.34 seconds
Started Jul 18 05:22:40 PM PDT 24
Finished Jul 18 05:22:46 PM PDT 24
Peak memory 216604 kb
Host smart-35d99a60-bf18-4756-953d-e00059c506a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398391139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1398391139
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.729253379
Short name T638
Test name
Test status
Simulation time 566520596 ps
CPU time 1.45 seconds
Started Jul 18 05:22:35 PM PDT 24
Finished Jul 18 05:22:38 PM PDT 24
Peak memory 208440 kb
Host smart-af71c8bb-57de-45db-ae00-5b32ff387292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729253379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.729253379
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3355719656
Short name T513
Test name
Test status
Simulation time 36850112 ps
CPU time 0.8 seconds
Started Jul 18 05:22:31 PM PDT 24
Finished Jul 18 05:22:32 PM PDT 24
Peak memory 206220 kb
Host smart-447be99b-0d02-47bb-bbec-7a9ae41c28c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355719656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3355719656
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1542714046
Short name T786
Test name
Test status
Simulation time 735264060 ps
CPU time 4.81 seconds
Started Jul 18 05:22:34 PM PDT 24
Finished Jul 18 05:22:40 PM PDT 24
Peak memory 233096 kb
Host smart-e1c6782e-150f-42fc-b412-8e63a64ddd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542714046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1542714046
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2582869161
Short name T1025
Test name
Test status
Simulation time 15763292 ps
CPU time 0.75 seconds
Started Jul 18 05:23:00 PM PDT 24
Finished Jul 18 05:23:02 PM PDT 24
Peak memory 206060 kb
Host smart-40fa14b6-52cb-403c-a72f-5b1cffc72dd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582869161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2582869161
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2429369588
Short name T687
Test name
Test status
Simulation time 4999781308 ps
CPU time 5.83 seconds
Started Jul 18 05:23:04 PM PDT 24
Finished Jul 18 05:23:12 PM PDT 24
Peak memory 233164 kb
Host smart-e8804542-bd41-402e-b2cf-1afd50247caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429369588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2429369588
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3543128354
Short name T355
Test name
Test status
Simulation time 44118660 ps
CPU time 0.76 seconds
Started Jul 18 05:22:40 PM PDT 24
Finished Jul 18 05:22:41 PM PDT 24
Peak memory 206228 kb
Host smart-88ffadfa-d81d-4748-9967-71eaacbb2134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543128354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3543128354
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2636441832
Short name T607
Test name
Test status
Simulation time 80827479941 ps
CPU time 168.95 seconds
Started Jul 18 05:22:59 PM PDT 24
Finished Jul 18 05:25:49 PM PDT 24
Peak memory 249632 kb
Host smart-fa28bbc1-218e-4967-aff3-094bdb2008ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636441832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2636441832
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3945733311
Short name T662
Test name
Test status
Simulation time 30540007649 ps
CPU time 141.98 seconds
Started Jul 18 05:23:01 PM PDT 24
Finished Jul 18 05:25:25 PM PDT 24
Peak memory 255752 kb
Host smart-207079db-2647-4012-baf1-edc54fd5daf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945733311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3945733311
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2965713851
Short name T989
Test name
Test status
Simulation time 5044405885 ps
CPU time 40.62 seconds
Started Jul 18 05:23:01 PM PDT 24
Finished Jul 18 05:23:43 PM PDT 24
Peak memory 233232 kb
Host smart-b97b2e79-7833-4bca-85c0-b2219063c4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965713851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2965713851
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3936205188
Short name T103
Test name
Test status
Simulation time 31141329999 ps
CPU time 135.75 seconds
Started Jul 18 05:23:01 PM PDT 24
Finished Jul 18 05:25:18 PM PDT 24
Peak memory 249668 kb
Host smart-93da59a0-683f-4bed-8ba7-fc503e5c1663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936205188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3936205188
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1731826167
Short name T645
Test name
Test status
Simulation time 1770384610 ps
CPU time 4.48 seconds
Started Jul 18 05:23:01 PM PDT 24
Finished Jul 18 05:23:07 PM PDT 24
Peak memory 224880 kb
Host smart-e7f7780d-fb42-4e54-9976-9f84aa1802c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731826167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1731826167
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3919068262
Short name T175
Test name
Test status
Simulation time 18190302721 ps
CPU time 90.4 seconds
Started Jul 18 05:23:06 PM PDT 24
Finished Jul 18 05:24:37 PM PDT 24
Peak memory 241360 kb
Host smart-945f247a-acec-49ab-80fe-c3f88b77bf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919068262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3919068262
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3350843099
Short name T598
Test name
Test status
Simulation time 45500213 ps
CPU time 1.1 seconds
Started Jul 18 05:22:34 PM PDT 24
Finished Jul 18 05:22:37 PM PDT 24
Peak memory 217120 kb
Host smart-7e45972d-4f55-47d2-befb-e3a8009dea0f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350843099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3350843099
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1622991848
Short name T968
Test name
Test status
Simulation time 1709456977 ps
CPU time 4.3 seconds
Started Jul 18 05:23:01 PM PDT 24
Finished Jul 18 05:23:06 PM PDT 24
Peak memory 224960 kb
Host smart-dac31319-d081-4771-8a84-dfa7f23087c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622991848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1622991848
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1822762413
Short name T69
Test name
Test status
Simulation time 161820354 ps
CPU time 2.73 seconds
Started Jul 18 05:23:02 PM PDT 24
Finished Jul 18 05:23:06 PM PDT 24
Peak memory 233128 kb
Host smart-4cf6bb8e-c92f-40ca-ab2f-d58f95d821a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822762413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1822762413
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2660461636
Short name T748
Test name
Test status
Simulation time 532158440 ps
CPU time 3.8 seconds
Started Jul 18 05:23:02 PM PDT 24
Finished Jul 18 05:23:07 PM PDT 24
Peak memory 220588 kb
Host smart-a8c64d12-fe08-4d08-88d9-ae4cfc423783
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2660461636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2660461636
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1200214084
Short name T140
Test name
Test status
Simulation time 60577637269 ps
CPU time 569.1 seconds
Started Jul 18 05:23:01 PM PDT 24
Finished Jul 18 05:32:31 PM PDT 24
Peak memory 273940 kb
Host smart-6ab1e8be-f2bf-4861-96d5-624dfd4ec987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200214084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1200214084
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2694923713
Short name T427
Test name
Test status
Simulation time 5262470664 ps
CPU time 22.12 seconds
Started Jul 18 05:22:34 PM PDT 24
Finished Jul 18 05:22:58 PM PDT 24
Peak memory 216884 kb
Host smart-982bef8a-047d-41b3-bd48-d822c8b811c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694923713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2694923713
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3039378774
Short name T938
Test name
Test status
Simulation time 72433664 ps
CPU time 1.31 seconds
Started Jul 18 05:22:35 PM PDT 24
Finished Jul 18 05:22:38 PM PDT 24
Peak memory 208048 kb
Host smart-e900119a-aae8-49c6-ac4c-e5fb7fd55d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039378774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3039378774
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2022155143
Short name T363
Test name
Test status
Simulation time 34105030 ps
CPU time 0.68 seconds
Started Jul 18 05:23:04 PM PDT 24
Finished Jul 18 05:23:06 PM PDT 24
Peak memory 205972 kb
Host smart-8b368036-3b57-43df-b6c4-0de9fc33843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022155143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2022155143
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4265958524
Short name T439
Test name
Test status
Simulation time 28752160 ps
CPU time 0.76 seconds
Started Jul 18 05:22:34 PM PDT 24
Finished Jul 18 05:22:36 PM PDT 24
Peak memory 206260 kb
Host smart-4d98d1be-8dd7-4fb4-a492-d1a88123f1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265958524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4265958524
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4253362254
Short name T235
Test name
Test status
Simulation time 4342377060 ps
CPU time 22.16 seconds
Started Jul 18 05:23:02 PM PDT 24
Finished Jul 18 05:23:26 PM PDT 24
Peak memory 238612 kb
Host smart-5d480356-d52a-4cdd-bf90-1eb9a3dd1459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253362254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4253362254
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.812804060
Short name T494
Test name
Test status
Simulation time 12268684 ps
CPU time 0.78 seconds
Started Jul 18 05:23:09 PM PDT 24
Finished Jul 18 05:23:10 PM PDT 24
Peak memory 206048 kb
Host smart-ee12d41e-3b78-4a2f-9ab1-1eaa0ec666cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812804060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.812804060
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1478185550
Short name T600
Test name
Test status
Simulation time 119582072 ps
CPU time 2.51 seconds
Started Jul 18 05:23:04 PM PDT 24
Finished Jul 18 05:23:08 PM PDT 24
Peak memory 233072 kb
Host smart-210a2369-c037-4b49-811c-2681a9ba5a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478185550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1478185550
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2439022731
Short name T394
Test name
Test status
Simulation time 13459967 ps
CPU time 0.84 seconds
Started Jul 18 05:23:02 PM PDT 24
Finished Jul 18 05:23:04 PM PDT 24
Peak memory 207092 kb
Host smart-6eccbea8-602b-418d-b975-19795e225d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439022731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2439022731
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.523385314
Short name T138
Test name
Test status
Simulation time 3497586263 ps
CPU time 59.14 seconds
Started Jul 18 05:23:04 PM PDT 24
Finished Jul 18 05:24:04 PM PDT 24
Peak memory 251036 kb
Host smart-a123ceb2-a4d0-431d-939c-79db45305a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523385314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.523385314
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3434847324
Short name T955
Test name
Test status
Simulation time 1543321737 ps
CPU time 3.78 seconds
Started Jul 18 05:23:03 PM PDT 24
Finished Jul 18 05:23:08 PM PDT 24
Peak memory 217804 kb
Host smart-fd1bb41d-7385-470a-bafb-c63edfa39d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434847324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3434847324
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2440934053
Short name T741
Test name
Test status
Simulation time 857124005 ps
CPU time 5.06 seconds
Started Jul 18 05:23:01 PM PDT 24
Finished Jul 18 05:23:07 PM PDT 24
Peak memory 233172 kb
Host smart-b37862a6-9031-41f3-a8a9-7129e4c0a09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440934053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2440934053
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1509688559
Short name T209
Test name
Test status
Simulation time 152439869602 ps
CPU time 233.19 seconds
Started Jul 18 05:23:02 PM PDT 24
Finished Jul 18 05:26:57 PM PDT 24
Peak memory 249636 kb
Host smart-41f05355-3775-4d66-9057-351bcfac5248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509688559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1509688559
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1501574440
Short name T207
Test name
Test status
Simulation time 213810875 ps
CPU time 5.13 seconds
Started Jul 18 05:23:06 PM PDT 24
Finished Jul 18 05:23:12 PM PDT 24
Peak memory 224940 kb
Host smart-23cee98e-5fd2-455d-a962-e380229b5e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501574440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1501574440
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3131700341
Short name T621
Test name
Test status
Simulation time 68159097 ps
CPU time 2.65 seconds
Started Jul 18 05:23:01 PM PDT 24
Finished Jul 18 05:23:05 PM PDT 24
Peak memory 232844 kb
Host smart-e3b69ebb-8615-41ab-863d-edec3ad16860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131700341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3131700341
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.519067528
Short name T446
Test name
Test status
Simulation time 67207839 ps
CPU time 1.19 seconds
Started Jul 18 05:23:00 PM PDT 24
Finished Jul 18 05:23:03 PM PDT 24
Peak memory 217064 kb
Host smart-e656367f-b107-47e0-843a-7b6e95945fc0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519067528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.519067528
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.768334507
Short name T268
Test name
Test status
Simulation time 250640737 ps
CPU time 5.14 seconds
Started Jul 18 05:23:05 PM PDT 24
Finished Jul 18 05:23:11 PM PDT 24
Peak memory 233148 kb
Host smart-d34be24d-5e89-4c47-9f12-43448971172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768334507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.768334507
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.912563534
Short name T855
Test name
Test status
Simulation time 23093123329 ps
CPU time 15.95 seconds
Started Jul 18 05:23:01 PM PDT 24
Finished Jul 18 05:23:19 PM PDT 24
Peak memory 233300 kb
Host smart-6a9fc152-ae3a-462c-a9b0-46e1e3976085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912563534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.912563534
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4241785176
Short name T920
Test name
Test status
Simulation time 659478687 ps
CPU time 3.88 seconds
Started Jul 18 05:23:03 PM PDT 24
Finished Jul 18 05:23:08 PM PDT 24
Peak memory 220624 kb
Host smart-7fa4a85e-f3af-4665-84bb-a6be933e0edd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4241785176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4241785176
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3799763073
Short name T16
Test name
Test status
Simulation time 23050403217 ps
CPU time 261.85 seconds
Started Jul 18 05:23:04 PM PDT 24
Finished Jul 18 05:27:27 PM PDT 24
Peak memory 256208 kb
Host smart-e25d36d3-e7f3-4e70-9216-56810b34597e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799763073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3799763073
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2216534264
Short name T539
Test name
Test status
Simulation time 2730439862 ps
CPU time 26.46 seconds
Started Jul 18 05:23:00 PM PDT 24
Finished Jul 18 05:23:28 PM PDT 24
Peak memory 216764 kb
Host smart-03626fcd-4671-4221-8992-acbc7cff95d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216534264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2216534264
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.593174969
Short name T976
Test name
Test status
Simulation time 1207625703 ps
CPU time 7.17 seconds
Started Jul 18 05:23:01 PM PDT 24
Finished Jul 18 05:23:10 PM PDT 24
Peak memory 216852 kb
Host smart-2fdaf1fc-3ea5-463c-ad5c-b600ef4e75ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593174969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.593174969
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3642762462
Short name T807
Test name
Test status
Simulation time 357551715 ps
CPU time 1.62 seconds
Started Jul 18 05:23:00 PM PDT 24
Finished Jul 18 05:23:03 PM PDT 24
Peak memory 216676 kb
Host smart-1e51dd12-dcac-42cd-8d45-4363484bd3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642762462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3642762462
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.257213121
Short name T773
Test name
Test status
Simulation time 303717509 ps
CPU time 0.97 seconds
Started Jul 18 05:22:59 PM PDT 24
Finished Jul 18 05:23:00 PM PDT 24
Peak memory 206188 kb
Host smart-99a41ed9-bde6-4492-ae7b-fe3f16c6252b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257213121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.257213121
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4162717922
Short name T243
Test name
Test status
Simulation time 2599840332 ps
CPU time 4.07 seconds
Started Jul 18 05:23:04 PM PDT 24
Finished Jul 18 05:23:09 PM PDT 24
Peak memory 233272 kb
Host smart-03ad13df-ffc1-46aa-a604-5b33f520ed4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162717922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4162717922
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2955678983
Short name T499
Test name
Test status
Simulation time 43295339 ps
CPU time 0.76 seconds
Started Jul 18 05:23:11 PM PDT 24
Finished Jul 18 05:23:12 PM PDT 24
Peak memory 205140 kb
Host smart-26a72f2b-e49e-438d-af47-f66d6e97be42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955678983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2955678983
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3748230158
Short name T893
Test name
Test status
Simulation time 510723462 ps
CPU time 4.35 seconds
Started Jul 18 05:23:10 PM PDT 24
Finished Jul 18 05:23:15 PM PDT 24
Peak memory 233072 kb
Host smart-daeb1ad9-3acc-4485-8bee-f49f9db0b356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748230158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3748230158
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2452269294
Short name T482
Test name
Test status
Simulation time 17234164 ps
CPU time 0.76 seconds
Started Jul 18 05:23:03 PM PDT 24
Finished Jul 18 05:23:05 PM PDT 24
Peak memory 207212 kb
Host smart-254cc42c-6348-4df0-adc4-d7bd285c2368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452269294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2452269294
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3126418092
Short name T221
Test name
Test status
Simulation time 3668654547 ps
CPU time 41.46 seconds
Started Jul 18 05:23:13 PM PDT 24
Finished Jul 18 05:23:55 PM PDT 24
Peak memory 249680 kb
Host smart-3219be31-18ee-4cdc-b9e2-8e6cdcab43df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126418092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3126418092
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.181927505
Short name T774
Test name
Test status
Simulation time 16692541839 ps
CPU time 70.72 seconds
Started Jul 18 05:23:12 PM PDT 24
Finished Jul 18 05:24:24 PM PDT 24
Peak memory 249676 kb
Host smart-b987725e-4b28-460f-8b20-d87fd8df1b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181927505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.181927505
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.824865068
Short name T144
Test name
Test status
Simulation time 8589701873 ps
CPU time 31.22 seconds
Started Jul 18 05:23:07 PM PDT 24
Finished Jul 18 05:23:39 PM PDT 24
Peak memory 238868 kb
Host smart-5de3ec29-d97d-4fd3-a4eb-f9279087cb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824865068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.824865068
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2315119516
Short name T463
Test name
Test status
Simulation time 6805470464 ps
CPU time 52.85 seconds
Started Jul 18 05:23:13 PM PDT 24
Finished Jul 18 05:24:06 PM PDT 24
Peak memory 240360 kb
Host smart-2af16842-2edf-472f-873c-1a3a869a3fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315119516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2315119516
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1388097288
Short name T739
Test name
Test status
Simulation time 8278694289 ps
CPU time 13.66 seconds
Started Jul 18 05:23:03 PM PDT 24
Finished Jul 18 05:23:18 PM PDT 24
Peak memory 233228 kb
Host smart-a9ecb657-57e1-4e03-b40b-03f6d6fe60bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388097288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1388097288
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3995746486
Short name T55
Test name
Test status
Simulation time 170807407 ps
CPU time 2.45 seconds
Started Jul 18 05:23:03 PM PDT 24
Finished Jul 18 05:23:06 PM PDT 24
Peak memory 233144 kb
Host smart-8c038ef7-8b31-4ada-afe0-db24da06fdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995746486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3995746486
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3365570107
Short name T414
Test name
Test status
Simulation time 34034477 ps
CPU time 1.2 seconds
Started Jul 18 05:23:03 PM PDT 24
Finished Jul 18 05:23:06 PM PDT 24
Peak memory 216972 kb
Host smart-d7c5ff6b-635b-428a-807f-2b9671aee8cf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365570107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3365570107
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3794128264
Short name T915
Test name
Test status
Simulation time 570588186 ps
CPU time 3.7 seconds
Started Jul 18 05:23:07 PM PDT 24
Finished Jul 18 05:23:12 PM PDT 24
Peak memory 233080 kb
Host smart-78265775-bfc9-4963-9b2f-395a6b15b1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794128264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3794128264
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1369112045
Short name T891
Test name
Test status
Simulation time 27935487744 ps
CPU time 18.56 seconds
Started Jul 18 05:23:05 PM PDT 24
Finished Jul 18 05:23:25 PM PDT 24
Peak memory 224860 kb
Host smart-3160c3f4-c8a2-4992-937d-be4917709620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369112045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1369112045
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.509819676
Short name T733
Test name
Test status
Simulation time 524312704 ps
CPU time 3.49 seconds
Started Jul 18 05:23:06 PM PDT 24
Finished Jul 18 05:23:11 PM PDT 24
Peak memory 221156 kb
Host smart-ea0cbf41-9f89-4070-80a7-d0c739fdc8ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=509819676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.509819676
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1615307648
Short name T156
Test name
Test status
Simulation time 118209837 ps
CPU time 1.15 seconds
Started Jul 18 05:23:11 PM PDT 24
Finished Jul 18 05:23:13 PM PDT 24
Peak memory 207348 kb
Host smart-95ad9b81-cb10-4765-bc7d-5e2eda4ac517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615307648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1615307648
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.864326740
Short name T680
Test name
Test status
Simulation time 16734983153 ps
CPU time 27.14 seconds
Started Jul 18 05:23:08 PM PDT 24
Finished Jul 18 05:23:36 PM PDT 24
Peak memory 220884 kb
Host smart-4e9b6aaa-c235-45fd-979e-8f92fa1b73aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864326740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.864326740
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.137761738
Short name T705
Test name
Test status
Simulation time 614548821 ps
CPU time 5.28 seconds
Started Jul 18 05:23:09 PM PDT 24
Finished Jul 18 05:23:15 PM PDT 24
Peak memory 216632 kb
Host smart-e4253a53-e026-49bc-9712-3cb03d77912c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137761738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.137761738
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2453851291
Short name T525
Test name
Test status
Simulation time 15463317 ps
CPU time 0.82 seconds
Started Jul 18 05:23:05 PM PDT 24
Finished Jul 18 05:23:07 PM PDT 24
Peak memory 205992 kb
Host smart-2f50182b-94ac-4ef8-8c22-44640cb0eae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453851291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2453851291
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.576290094
Short name T726
Test name
Test status
Simulation time 98334259 ps
CPU time 0.72 seconds
Started Jul 18 05:23:04 PM PDT 24
Finished Jul 18 05:23:06 PM PDT 24
Peak memory 206304 kb
Host smart-f7399989-c3b5-49a1-b6f7-562b59bd57b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576290094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.576290094
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2313504780
Short name T995
Test name
Test status
Simulation time 2777003215 ps
CPU time 12.89 seconds
Started Jul 18 05:23:08 PM PDT 24
Finished Jul 18 05:23:21 PM PDT 24
Peak memory 249316 kb
Host smart-0ce794d1-2ef8-4029-80da-afdddf788e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313504780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2313504780
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.910080991
Short name T745
Test name
Test status
Simulation time 11740688 ps
CPU time 0.75 seconds
Started Jul 18 05:23:29 PM PDT 24
Finished Jul 18 05:23:31 PM PDT 24
Peak memory 205200 kb
Host smart-2fa6febb-f9c0-4214-a91f-8b1c07f159d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910080991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.910080991
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1836401539
Short name T279
Test name
Test status
Simulation time 717383797 ps
CPU time 4.55 seconds
Started Jul 18 05:23:33 PM PDT 24
Finished Jul 18 05:23:38 PM PDT 24
Peak memory 233064 kb
Host smart-61aca010-9591-410f-8d45-4ea5c222378f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836401539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1836401539
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4065230323
Short name T789
Test name
Test status
Simulation time 34638659 ps
CPU time 0.83 seconds
Started Jul 18 05:23:01 PM PDT 24
Finished Jul 18 05:23:03 PM PDT 24
Peak memory 206828 kb
Host smart-c8c8aa8d-a175-4231-9398-0162dfaa8cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065230323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4065230323
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.306980326
Short name T613
Test name
Test status
Simulation time 173754324 ps
CPU time 3.28 seconds
Started Jul 18 05:23:29 PM PDT 24
Finished Jul 18 05:23:33 PM PDT 24
Peak memory 233096 kb
Host smart-1d1470f1-010e-4b7c-8171-bf5bec3da883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306980326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.306980326
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1486959029
Short name T551
Test name
Test status
Simulation time 352212700 ps
CPU time 5 seconds
Started Jul 18 05:23:28 PM PDT 24
Finished Jul 18 05:23:34 PM PDT 24
Peak memory 233108 kb
Host smart-02b9c675-666b-4535-9053-00984de1a068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486959029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1486959029
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.455048430
Short name T282
Test name
Test status
Simulation time 3925008720 ps
CPU time 37.49 seconds
Started Jul 18 05:23:33 PM PDT 24
Finished Jul 18 05:24:11 PM PDT 24
Peak memory 240944 kb
Host smart-4d88681a-4a86-4a46-ac33-ca216df7e41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455048430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.455048430
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2953174670
Short name T426
Test name
Test status
Simulation time 16720413 ps
CPU time 1.01 seconds
Started Jul 18 05:23:06 PM PDT 24
Finished Jul 18 05:23:08 PM PDT 24
Peak memory 218328 kb
Host smart-b8e41345-b8bf-4040-9daa-61926f2d57ce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953174670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2953174670
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4134112498
Short name T940
Test name
Test status
Simulation time 181227141 ps
CPU time 2.51 seconds
Started Jul 18 05:23:27 PM PDT 24
Finished Jul 18 05:23:31 PM PDT 24
Peak memory 233076 kb
Host smart-33a9a6de-2bed-4e7c-b2c2-59db2b68ede0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134112498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4134112498
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2386449648
Short name T754
Test name
Test status
Simulation time 6365296971 ps
CPU time 10.41 seconds
Started Jul 18 05:23:28 PM PDT 24
Finished Jul 18 05:23:39 PM PDT 24
Peak memory 233216 kb
Host smart-bb89aab3-587c-4b4f-b013-5cb4837911c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386449648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2386449648
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3786901166
Short name T44
Test name
Test status
Simulation time 129455693 ps
CPU time 5.02 seconds
Started Jul 18 05:23:30 PM PDT 24
Finished Jul 18 05:23:36 PM PDT 24
Peak memory 223400 kb
Host smart-525193aa-c618-4319-a35f-3fb429a44a5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3786901166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3786901166
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3433657430
Short name T208
Test name
Test status
Simulation time 40506965391 ps
CPU time 416.37 seconds
Started Jul 18 05:23:31 PM PDT 24
Finished Jul 18 05:30:28 PM PDT 24
Peak memory 257844 kb
Host smart-f4a6c398-7725-4d09-bd47-e182cdb7f5c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433657430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3433657430
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3389884970
Short name T727
Test name
Test status
Simulation time 5892126851 ps
CPU time 31.59 seconds
Started Jul 18 05:23:28 PM PDT 24
Finished Jul 18 05:24:01 PM PDT 24
Peak memory 216796 kb
Host smart-467e2d11-fbaa-43bf-958a-cff46ebd55a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389884970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3389884970
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3658403343
Short name T962
Test name
Test status
Simulation time 1549902902 ps
CPU time 6.4 seconds
Started Jul 18 05:23:26 PM PDT 24
Finished Jul 18 05:23:33 PM PDT 24
Peak memory 216796 kb
Host smart-7bbbc2f4-7b5c-43b9-9b57-f34d53ad0a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658403343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3658403343
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3332629072
Short name T520
Test name
Test status
Simulation time 142379524 ps
CPU time 0.99 seconds
Started Jul 18 05:23:27 PM PDT 24
Finished Jul 18 05:23:28 PM PDT 24
Peak memory 208136 kb
Host smart-49b9aa57-1416-4eba-a10e-d321e3797b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332629072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3332629072
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.716407555
Short name T553
Test name
Test status
Simulation time 80831493 ps
CPU time 0.8 seconds
Started Jul 18 05:23:27 PM PDT 24
Finished Jul 18 05:23:29 PM PDT 24
Peak memory 206272 kb
Host smart-f0364202-0905-4c74-b7d7-71ab8a92a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716407555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.716407555
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3447460904
Short name T663
Test name
Test status
Simulation time 244507151 ps
CPU time 2.56 seconds
Started Jul 18 05:23:29 PM PDT 24
Finished Jul 18 05:23:33 PM PDT 24
Peak memory 224972 kb
Host smart-2fad1019-6c9a-43db-a4a1-fe0b401c65a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447460904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3447460904
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2952064850
Short name T720
Test name
Test status
Simulation time 12190028 ps
CPU time 0.73 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:19:44 PM PDT 24
Peak memory 205668 kb
Host smart-385d4edc-851c-42b1-87f4-0359f3b39a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952064850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
952064850
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.232335612
Short name T362
Test name
Test status
Simulation time 129547104 ps
CPU time 2.09 seconds
Started Jul 18 05:19:40 PM PDT 24
Finished Jul 18 05:19:43 PM PDT 24
Peak memory 233156 kb
Host smart-f14dcb40-ba3f-42d7-b768-aa6ee64600f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232335612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.232335612
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2502424084
Short name T657
Test name
Test status
Simulation time 22448240 ps
CPU time 0.83 seconds
Started Jul 18 05:19:35 PM PDT 24
Finished Jul 18 05:19:39 PM PDT 24
Peak memory 206808 kb
Host smart-6886aa21-2b9b-4daa-8c92-77bad577ecec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502424084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2502424084
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2107502314
Short name T416
Test name
Test status
Simulation time 36525597922 ps
CPU time 44.25 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:20:27 PM PDT 24
Peak memory 250004 kb
Host smart-557fc3e9-db0c-4bd3-a38b-494ef6bd8a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107502314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2107502314
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3767697620
Short name T503
Test name
Test status
Simulation time 122502064407 ps
CPU time 78.6 seconds
Started Jul 18 05:19:43 PM PDT 24
Finished Jul 18 05:21:05 PM PDT 24
Peak memory 240804 kb
Host smart-5caceb12-5d97-4863-b1e5-4c3eb12cf724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767697620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3767697620
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1732752936
Short name T238
Test name
Test status
Simulation time 14401443527 ps
CPU time 149.87 seconds
Started Jul 18 05:19:39 PM PDT 24
Finished Jul 18 05:22:10 PM PDT 24
Peak memory 256440 kb
Host smart-d1099be1-2142-41b4-8875-fd15b8244b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732752936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1732752936
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3337107248
Short name T410
Test name
Test status
Simulation time 221317899 ps
CPU time 3.44 seconds
Started Jul 18 05:19:32 PM PDT 24
Finished Jul 18 05:19:38 PM PDT 24
Peak memory 224872 kb
Host smart-6b4bd99b-2ccb-4606-9896-d96fb081d0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337107248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3337107248
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1902735592
Short name T696
Test name
Test status
Simulation time 2242464869 ps
CPU time 47.21 seconds
Started Jul 18 05:19:34 PM PDT 24
Finished Jul 18 05:20:25 PM PDT 24
Peak memory 253460 kb
Host smart-9dd1ea57-7b07-4285-b058-6f8da3bbadbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902735592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1902735592
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1523023863
Short name T413
Test name
Test status
Simulation time 686260025 ps
CPU time 4.87 seconds
Started Jul 18 05:19:38 PM PDT 24
Finished Jul 18 05:19:45 PM PDT 24
Peak memory 224836 kb
Host smart-b048a9ff-64f4-465e-9c62-9e6214e9a7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523023863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1523023863
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.568829447
Short name T747
Test name
Test status
Simulation time 2837556647 ps
CPU time 29.57 seconds
Started Jul 18 05:19:31 PM PDT 24
Finished Jul 18 05:20:03 PM PDT 24
Peak memory 233184 kb
Host smart-586a569d-3a24-4c8c-830f-872694ae45bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568829447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.568829447
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3756080803
Short name T1026
Test name
Test status
Simulation time 42512145 ps
CPU time 1.12 seconds
Started Jul 18 05:19:33 PM PDT 24
Finished Jul 18 05:19:38 PM PDT 24
Peak memory 217076 kb
Host smart-6dca613c-0321-4303-aadf-ab648c8b10df
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756080803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3756080803
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.817803955
Short name T313
Test name
Test status
Simulation time 2072543812 ps
CPU time 6.94 seconds
Started Jul 18 05:19:36 PM PDT 24
Finished Jul 18 05:19:46 PM PDT 24
Peak memory 224880 kb
Host smart-ce1b0431-9f11-413b-b8f4-0126e1719c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817803955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
817803955
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.667139653
Short name T179
Test name
Test status
Simulation time 1070707886 ps
CPU time 2.87 seconds
Started Jul 18 05:19:43 PM PDT 24
Finished Jul 18 05:19:49 PM PDT 24
Peak memory 224712 kb
Host smart-dd514c23-825a-4a9d-ada2-6ba674090db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667139653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.667139653
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.174164512
Short name T717
Test name
Test status
Simulation time 221918700 ps
CPU time 5.78 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:19:49 PM PDT 24
Peak memory 223580 kb
Host smart-92519c31-732b-4940-862f-568fbd148d12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=174164512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.174164512
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.892705386
Short name T78
Test name
Test status
Simulation time 39169217 ps
CPU time 1 seconds
Started Jul 18 05:19:39 PM PDT 24
Finished Jul 18 05:19:41 PM PDT 24
Peak memory 235976 kb
Host smart-0b14f61f-1ff4-4db4-a2ef-7f864b7f1f62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892705386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.892705386
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2423299254
Short name T33
Test name
Test status
Simulation time 41326168514 ps
CPU time 383.52 seconds
Started Jul 18 05:19:43 PM PDT 24
Finished Jul 18 05:26:10 PM PDT 24
Peak memory 255876 kb
Host smart-2e50a8df-69b2-4dff-b684-143e18e396cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423299254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2423299254
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1282800269
Short name T533
Test name
Test status
Simulation time 16330349952 ps
CPU time 22.21 seconds
Started Jul 18 05:19:30 PM PDT 24
Finished Jul 18 05:19:55 PM PDT 24
Peak memory 216692 kb
Host smart-40617886-9924-4232-bcbb-98de39ad856d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282800269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1282800269
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1271143783
Short name T581
Test name
Test status
Simulation time 24535266 ps
CPU time 0.72 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:19:44 PM PDT 24
Peak memory 205988 kb
Host smart-5f62dfe0-e11a-4c7c-a724-e5aab21c6736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271143783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1271143783
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1599467386
Short name T809
Test name
Test status
Simulation time 118034033 ps
CPU time 1.64 seconds
Started Jul 18 05:19:43 PM PDT 24
Finished Jul 18 05:19:48 PM PDT 24
Peak memory 216500 kb
Host smart-66c33822-a49f-49a7-8663-c5c9407cc6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599467386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1599467386
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3697822161
Short name T360
Test name
Test status
Simulation time 310771892 ps
CPU time 0.9 seconds
Started Jul 18 05:19:39 PM PDT 24
Finished Jul 18 05:19:42 PM PDT 24
Peak memory 206224 kb
Host smart-c968f93f-bc70-4515-906f-de6982eb7c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697822161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3697822161
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2590987811
Short name T41
Test name
Test status
Simulation time 3307871668 ps
CPU time 8.21 seconds
Started Jul 18 05:19:34 PM PDT 24
Finished Jul 18 05:19:46 PM PDT 24
Peak memory 224960 kb
Host smart-d4ba14c8-4461-4e23-9358-4523e9dec968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590987811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2590987811
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3007389568
Short name T640
Test name
Test status
Simulation time 117348964 ps
CPU time 0.74 seconds
Started Jul 18 05:23:45 PM PDT 24
Finished Jul 18 05:23:47 PM PDT 24
Peak memory 205720 kb
Host smart-e956b339-34d6-45d4-82dd-27b6653c484e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007389568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3007389568
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3520545245
Short name T432
Test name
Test status
Simulation time 109853069 ps
CPU time 2.79 seconds
Started Jul 18 05:23:27 PM PDT 24
Finished Jul 18 05:23:31 PM PDT 24
Peak memory 233072 kb
Host smart-3bb7df12-b905-47db-bf59-41409ac8a315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520545245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3520545245
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.577876362
Short name T372
Test name
Test status
Simulation time 13842062 ps
CPU time 0.81 seconds
Started Jul 18 05:23:31 PM PDT 24
Finished Jul 18 05:23:33 PM PDT 24
Peak memory 206904 kb
Host smart-0b1595f9-89b1-4d14-a291-459126a1dd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577876362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.577876362
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.943066369
Short name T1017
Test name
Test status
Simulation time 11904738 ps
CPU time 0.74 seconds
Started Jul 18 05:23:48 PM PDT 24
Finished Jul 18 05:23:50 PM PDT 24
Peak memory 216208 kb
Host smart-4dca6ceb-d226-4b2f-9110-1a7d9139be6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943066369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.943066369
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.38818910
Short name T992
Test name
Test status
Simulation time 33368189950 ps
CPU time 78.41 seconds
Started Jul 18 05:23:47 PM PDT 24
Finished Jul 18 05:25:07 PM PDT 24
Peak memory 224644 kb
Host smart-a2b4f11e-08f2-4e45-b010-ed34ae9223af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38818910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.38818910
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2280438089
Short name T314
Test name
Test status
Simulation time 11468412917 ps
CPU time 158.06 seconds
Started Jul 18 05:23:44 PM PDT 24
Finished Jul 18 05:26:24 PM PDT 24
Peak memory 256196 kb
Host smart-8f39237f-ad88-48dc-b140-6a18ea55eea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280438089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2280438089
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2593280390
Short name T293
Test name
Test status
Simulation time 53373157880 ps
CPU time 392.59 seconds
Started Jul 18 05:23:43 PM PDT 24
Finished Jul 18 05:30:17 PM PDT 24
Peak memory 256592 kb
Host smart-d5bb3e26-de53-4627-9e1a-d5ae6fe63b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593280390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2593280390
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1633871531
Short name T758
Test name
Test status
Simulation time 1294121373 ps
CPU time 15.55 seconds
Started Jul 18 05:23:29 PM PDT 24
Finished Jul 18 05:23:46 PM PDT 24
Peak memory 224944 kb
Host smart-7fc8e5b5-b00a-47b2-a897-a0e890c3380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633871531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1633871531
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1224307539
Short name T698
Test name
Test status
Simulation time 20135204985 ps
CPU time 36.65 seconds
Started Jul 18 05:23:27 PM PDT 24
Finished Jul 18 05:24:04 PM PDT 24
Peak memory 233192 kb
Host smart-a8eab7f1-7955-4bdc-9b9f-dbfd34278954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224307539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1224307539
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.187504507
Short name T736
Test name
Test status
Simulation time 18249055626 ps
CPU time 20.35 seconds
Started Jul 18 05:23:33 PM PDT 24
Finished Jul 18 05:23:54 PM PDT 24
Peak memory 225000 kb
Host smart-5938347e-f3e1-47ae-a0b8-cdcc6f3aca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187504507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.187504507
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1794782854
Short name T49
Test name
Test status
Simulation time 296296841 ps
CPU time 2.42 seconds
Started Jul 18 05:23:28 PM PDT 24
Finished Jul 18 05:23:32 PM PDT 24
Peak memory 224828 kb
Host smart-61744583-a0df-40e0-8558-4d1bc6174c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794782854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1794782854
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1077650460
Short name T677
Test name
Test status
Simulation time 498613862 ps
CPU time 7.15 seconds
Started Jul 18 05:23:42 PM PDT 24
Finished Jul 18 05:23:50 PM PDT 24
Peak memory 222448 kb
Host smart-a5478dd1-2143-40cd-b352-121ab9bde861
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1077650460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1077650460
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2010326308
Short name T895
Test name
Test status
Simulation time 3850430325 ps
CPU time 18.22 seconds
Started Jul 18 05:23:44 PM PDT 24
Finished Jul 18 05:24:04 PM PDT 24
Peak memory 218052 kb
Host smart-55c47b95-62a2-4aa2-9997-35b0821e704f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010326308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2010326308
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3331766727
Short name T672
Test name
Test status
Simulation time 11134648810 ps
CPU time 25 seconds
Started Jul 18 05:24:02 PM PDT 24
Finished Jul 18 05:24:28 PM PDT 24
Peak memory 216772 kb
Host smart-9179ec33-68c1-4fe6-a7fe-0d0e060d043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331766727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3331766727
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3841434813
Short name T697
Test name
Test status
Simulation time 1709616122 ps
CPU time 7.41 seconds
Started Jul 18 05:23:27 PM PDT 24
Finished Jul 18 05:23:36 PM PDT 24
Peak memory 216584 kb
Host smart-3014e41d-957a-41f2-ae82-bc9fe47a8bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841434813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3841434813
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.170889481
Short name T868
Test name
Test status
Simulation time 574855095 ps
CPU time 1.21 seconds
Started Jul 18 05:23:28 PM PDT 24
Finished Jul 18 05:23:31 PM PDT 24
Peak memory 208436 kb
Host smart-a764951c-e771-49ac-9f84-309a60fb64c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170889481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.170889481
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3843945958
Short name T392
Test name
Test status
Simulation time 43168288 ps
CPU time 0.78 seconds
Started Jul 18 05:23:29 PM PDT 24
Finished Jul 18 05:23:31 PM PDT 24
Peak memory 206192 kb
Host smart-f2a36325-d290-4d21-a091-06b79b16ca53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843945958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3843945958
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2960558864
Short name T57
Test name
Test status
Simulation time 6091076762 ps
CPU time 3.66 seconds
Started Jul 18 05:23:30 PM PDT 24
Finished Jul 18 05:23:35 PM PDT 24
Peak memory 225008 kb
Host smart-247d4e8e-9f57-4921-a74c-0e8ee9a34fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960558864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2960558864
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3906011078
Short name T575
Test name
Test status
Simulation time 28461549 ps
CPU time 0.73 seconds
Started Jul 18 05:23:45 PM PDT 24
Finished Jul 18 05:23:47 PM PDT 24
Peak memory 205736 kb
Host smart-6c9284d6-37bc-44d1-ba9d-7d7d0c819b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906011078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3906011078
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2302522762
Short name T751
Test name
Test status
Simulation time 2264218608 ps
CPU time 5 seconds
Started Jul 18 05:23:45 PM PDT 24
Finished Jul 18 05:23:51 PM PDT 24
Peak memory 225052 kb
Host smart-022b1fce-aef0-49ee-9fc4-ff7d0290962b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302522762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2302522762
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2620826257
Short name T462
Test name
Test status
Simulation time 33658857 ps
CPU time 0.77 seconds
Started Jul 18 05:23:53 PM PDT 24
Finished Jul 18 05:23:55 PM PDT 24
Peak memory 205812 kb
Host smart-ee988996-7762-4f52-81a9-af5d76e098b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620826257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2620826257
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.611715363
Short name T954
Test name
Test status
Simulation time 267817065651 ps
CPU time 186.92 seconds
Started Jul 18 05:23:44 PM PDT 24
Finished Jul 18 05:26:52 PM PDT 24
Peak memory 250008 kb
Host smart-319ceb09-3648-44e9-b03e-23c92b7b83da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611715363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.611715363
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3528569268
Short name T590
Test name
Test status
Simulation time 2373741929 ps
CPU time 37.72 seconds
Started Jul 18 05:23:44 PM PDT 24
Finished Jul 18 05:24:22 PM PDT 24
Peak memory 234348 kb
Host smart-311fc896-70cc-4d4f-b5ed-cc69b8459566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528569268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3528569268
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.916963864
Short name T430
Test name
Test status
Simulation time 11662571095 ps
CPU time 42.3 seconds
Started Jul 18 05:23:52 PM PDT 24
Finished Jul 18 05:24:35 PM PDT 24
Peak memory 233196 kb
Host smart-893255a7-9341-4008-ba7f-078acd187ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916963864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.916963864
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2468129234
Short name T534
Test name
Test status
Simulation time 13735041411 ps
CPU time 91.18 seconds
Started Jul 18 05:23:43 PM PDT 24
Finished Jul 18 05:25:15 PM PDT 24
Peak memory 255568 kb
Host smart-a36c3b54-c48a-4afb-814c-a28493244d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468129234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2468129234
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2478978501
Short name T572
Test name
Test status
Simulation time 760414020 ps
CPU time 5.06 seconds
Started Jul 18 05:23:43 PM PDT 24
Finished Jul 18 05:23:49 PM PDT 24
Peak memory 233088 kb
Host smart-205fa0b3-64dc-4ffb-b186-dc7352a1c809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478978501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2478978501
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1469928242
Short name T278
Test name
Test status
Simulation time 320667019 ps
CPU time 3.64 seconds
Started Jul 18 05:23:45 PM PDT 24
Finished Jul 18 05:23:51 PM PDT 24
Peak memory 227556 kb
Host smart-232d365b-3552-40d1-a6d0-9a9286e7fded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469928242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1469928242
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3707511726
Short name T53
Test name
Test status
Simulation time 19595454044 ps
CPU time 15.95 seconds
Started Jul 18 05:23:50 PM PDT 24
Finished Jul 18 05:24:07 PM PDT 24
Peak memory 233204 kb
Host smart-2f0283f1-cce3-4f6f-bb8b-4f870eacaaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707511726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3707511726
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3418195245
Short name T1021
Test name
Test status
Simulation time 3944199689 ps
CPU time 13.25 seconds
Started Jul 18 05:23:43 PM PDT 24
Finished Jul 18 05:23:57 PM PDT 24
Peak memory 241436 kb
Host smart-09821102-6b35-47b8-92a2-c3aabd40bf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418195245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3418195245
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3426363477
Short name T850
Test name
Test status
Simulation time 182034117 ps
CPU time 4.59 seconds
Started Jul 18 05:23:47 PM PDT 24
Finished Jul 18 05:23:54 PM PDT 24
Peak memory 223388 kb
Host smart-60b2d326-529c-4345-8c14-e707f1ece269
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3426363477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3426363477
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2379399181
Short name T858
Test name
Test status
Simulation time 5523492773 ps
CPU time 11.55 seconds
Started Jul 18 05:23:48 PM PDT 24
Finished Jul 18 05:24:01 PM PDT 24
Peak memory 220300 kb
Host smart-4945c29a-eace-497f-bee9-6d283fbc0b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379399181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2379399181
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1648126267
Short name T892
Test name
Test status
Simulation time 17858291195 ps
CPU time 6.9 seconds
Started Jul 18 05:23:46 PM PDT 24
Finished Jul 18 05:23:55 PM PDT 24
Peak memory 216784 kb
Host smart-fdd39a64-bbbf-46d9-a3c4-659382113fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648126267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1648126267
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.14817283
Short name T768
Test name
Test status
Simulation time 24212085 ps
CPU time 0.79 seconds
Started Jul 18 05:23:58 PM PDT 24
Finished Jul 18 05:24:00 PM PDT 24
Peak memory 207268 kb
Host smart-a62d4821-4987-4938-b0cb-5f1d84995207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14817283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.14817283
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2199105776
Short name T399
Test name
Test status
Simulation time 118980860 ps
CPU time 0.86 seconds
Started Jul 18 05:23:45 PM PDT 24
Finished Jul 18 05:23:47 PM PDT 24
Peak memory 206588 kb
Host smart-e4e1a051-dbfa-4df0-98cf-98b031425273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199105776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2199105776
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3184898999
Short name T255
Test name
Test status
Simulation time 6233124828 ps
CPU time 7.78 seconds
Started Jul 18 05:23:43 PM PDT 24
Finished Jul 18 05:23:52 PM PDT 24
Peak memory 233236 kb
Host smart-92ff7931-e227-417f-8b7d-474928e6a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184898999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3184898999
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.16316555
Short name T364
Test name
Test status
Simulation time 93483684 ps
CPU time 0.71 seconds
Started Jul 18 05:23:54 PM PDT 24
Finished Jul 18 05:23:56 PM PDT 24
Peak memory 205720 kb
Host smart-71e1f7ab-ca69-46c1-a204-98bfb5e509e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16316555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.16316555
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2716784056
Short name T770
Test name
Test status
Simulation time 1639943477 ps
CPU time 10.79 seconds
Started Jul 18 05:23:48 PM PDT 24
Finished Jul 18 05:24:01 PM PDT 24
Peak memory 224848 kb
Host smart-c9f4db54-442b-4302-aa7a-e70ee752cc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716784056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2716784056
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.404247036
Short name T571
Test name
Test status
Simulation time 61667777 ps
CPU time 0.75 seconds
Started Jul 18 05:23:49 PM PDT 24
Finished Jul 18 05:23:51 PM PDT 24
Peak memory 206888 kb
Host smart-69f38a2e-1ff8-4bc4-af40-bce553c74513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404247036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.404247036
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1914347454
Short name T929
Test name
Test status
Simulation time 54320819671 ps
CPU time 129.5 seconds
Started Jul 18 05:23:47 PM PDT 24
Finished Jul 18 05:25:58 PM PDT 24
Peak memory 253052 kb
Host smart-2e0e75ca-eed5-4e61-9b50-7913e1acd93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914347454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1914347454
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1712235488
Short name T512
Test name
Test status
Simulation time 7607405244 ps
CPU time 26.15 seconds
Started Jul 18 05:23:48 PM PDT 24
Finished Jul 18 05:24:16 PM PDT 24
Peak memory 218164 kb
Host smart-12bf36ee-7a6b-43a6-ab87-464cec6ec7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712235488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1712235488
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3075764259
Short name T950
Test name
Test status
Simulation time 2441905847 ps
CPU time 24.63 seconds
Started Jul 18 05:23:46 PM PDT 24
Finished Jul 18 05:24:12 PM PDT 24
Peak memory 239516 kb
Host smart-ce1fe7a8-7550-473d-9b94-0f5703358e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075764259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3075764259
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1242336833
Short name T574
Test name
Test status
Simulation time 4129959051 ps
CPU time 58.26 seconds
Started Jul 18 05:23:45 PM PDT 24
Finished Jul 18 05:24:45 PM PDT 24
Peak memory 251468 kb
Host smart-e0020e0e-dfcd-4592-af97-85220d386d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242336833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1242336833
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2865915203
Short name T165
Test name
Test status
Simulation time 34846400088 ps
CPU time 70.53 seconds
Started Jul 18 05:23:45 PM PDT 24
Finished Jul 18 05:24:57 PM PDT 24
Peak memory 241672 kb
Host smart-a2e0117d-7114-48f3-be72-200fcda9d452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865915203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2865915203
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.724228197
Short name T927
Test name
Test status
Simulation time 351823162 ps
CPU time 6.42 seconds
Started Jul 18 05:23:58 PM PDT 24
Finished Jul 18 05:24:07 PM PDT 24
Peak memory 233112 kb
Host smart-296b8abc-6ec0-4c90-beb5-14fc4b6e0589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724228197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.724228197
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3593330681
Short name T767
Test name
Test status
Simulation time 1731240215 ps
CPU time 16.76 seconds
Started Jul 18 05:23:44 PM PDT 24
Finished Jul 18 05:24:03 PM PDT 24
Peak memory 224860 kb
Host smart-b2c68886-f97c-4246-9e32-7b82a6bd7d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593330681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3593330681
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2976966669
Short name T434
Test name
Test status
Simulation time 7734584788 ps
CPU time 15.42 seconds
Started Jul 18 05:23:47 PM PDT 24
Finished Jul 18 05:24:04 PM PDT 24
Peak memory 233200 kb
Host smart-c9ea0c58-b809-496a-8ad6-63cb792aff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976966669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2976966669
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2266808541
Short name T287
Test name
Test status
Simulation time 3801258302 ps
CPU time 17.92 seconds
Started Jul 18 05:23:46 PM PDT 24
Finished Jul 18 05:24:05 PM PDT 24
Peak memory 248856 kb
Host smart-f578493a-f3cc-4c52-a99d-b40b7354cd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266808541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2266808541
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2258859805
Short name T527
Test name
Test status
Simulation time 1099666562 ps
CPU time 8.59 seconds
Started Jul 18 05:23:47 PM PDT 24
Finished Jul 18 05:23:57 PM PDT 24
Peak memory 222408 kb
Host smart-091e745b-77e5-427f-a0fa-0157a89d8487
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2258859805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2258859805
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4269790960
Short name T695
Test name
Test status
Simulation time 42936030 ps
CPU time 0.74 seconds
Started Jul 18 05:23:45 PM PDT 24
Finished Jul 18 05:23:47 PM PDT 24
Peak memory 206228 kb
Host smart-f775ea73-395c-4647-8b82-60996629a09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269790960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4269790960
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.950151085
Short name T828
Test name
Test status
Simulation time 2001541404 ps
CPU time 10.03 seconds
Started Jul 18 05:23:55 PM PDT 24
Finished Jul 18 05:24:05 PM PDT 24
Peak memory 216664 kb
Host smart-d7f50c7a-7af7-4ab8-aa87-687868e40943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950151085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.950151085
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1565981832
Short name T569
Test name
Test status
Simulation time 397447347 ps
CPU time 2.13 seconds
Started Jul 18 05:24:28 PM PDT 24
Finished Jul 18 05:24:32 PM PDT 24
Peak memory 216572 kb
Host smart-69d61e1c-ff97-49f0-a81a-b6863234a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565981832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1565981832
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3913943864
Short name T981
Test name
Test status
Simulation time 38155244 ps
CPU time 0.71 seconds
Started Jul 18 05:23:47 PM PDT 24
Finished Jul 18 05:23:50 PM PDT 24
Peak memory 206252 kb
Host smart-96351f05-f7d4-40ef-ba84-4a1cad773893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913943864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3913943864
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.926036405
Short name T402
Test name
Test status
Simulation time 1941196542 ps
CPU time 8.61 seconds
Started Jul 18 05:23:48 PM PDT 24
Finished Jul 18 05:23:58 PM PDT 24
Peak memory 240952 kb
Host smart-019c3d7d-04cf-4d5b-bf72-d60300d6d151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926036405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.926036405
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2106869259
Short name T467
Test name
Test status
Simulation time 96269601 ps
CPU time 0.71 seconds
Started Jul 18 05:23:45 PM PDT 24
Finished Jul 18 05:23:48 PM PDT 24
Peak memory 205760 kb
Host smart-bbc7c40e-a15b-44fa-b090-50386b8112ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106869259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2106869259
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1142493333
Short name T823
Test name
Test status
Simulation time 777910910 ps
CPU time 3.14 seconds
Started Jul 18 05:23:53 PM PDT 24
Finished Jul 18 05:23:57 PM PDT 24
Peak memory 224824 kb
Host smart-a2028c2d-9239-4f1e-b8f8-e33bbbae19c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142493333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1142493333
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.235405781
Short name T351
Test name
Test status
Simulation time 81596650 ps
CPU time 0.77 seconds
Started Jul 18 05:23:46 PM PDT 24
Finished Jul 18 05:23:49 PM PDT 24
Peak memory 205832 kb
Host smart-0df9bb6e-d27f-4f90-920f-54a1a8f61d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235405781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.235405781
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2680235650
Short name T213
Test name
Test status
Simulation time 52007036119 ps
CPU time 194.73 seconds
Started Jul 18 05:23:58 PM PDT 24
Finished Jul 18 05:27:15 PM PDT 24
Peak memory 257124 kb
Host smart-267da849-a1ec-4668-a250-70ab4ac525d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680235650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2680235650
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.285620928
Short name T461
Test name
Test status
Simulation time 27855723751 ps
CPU time 55.57 seconds
Started Jul 18 05:23:45 PM PDT 24
Finished Jul 18 05:24:42 PM PDT 24
Peak memory 250104 kb
Host smart-b7c31986-a947-4aa8-b998-54b2d6e536e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285620928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.285620928
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.750347593
Short name T47
Test name
Test status
Simulation time 7341546236 ps
CPU time 73.75 seconds
Started Jul 18 05:23:53 PM PDT 24
Finished Jul 18 05:25:08 PM PDT 24
Peak memory 266064 kb
Host smart-3511e5cc-4b5a-441d-8c9a-7f8722427402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750347593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.750347593
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.87877433
Short name T322
Test name
Test status
Simulation time 9465890499 ps
CPU time 15.95 seconds
Started Jul 18 05:23:57 PM PDT 24
Finished Jul 18 05:24:15 PM PDT 24
Peak memory 249672 kb
Host smart-0f257b84-50ce-4b43-95af-ac49666ee64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87877433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.87877433
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3990889957
Short name T541
Test name
Test status
Simulation time 18816724 ps
CPU time 0.73 seconds
Started Jul 18 05:23:54 PM PDT 24
Finished Jul 18 05:23:56 PM PDT 24
Peak memory 216264 kb
Host smart-5d4e862b-021c-491d-b7a0-515ac6a4bc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990889957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3990889957
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1489279135
Short name T742
Test name
Test status
Simulation time 1294941641 ps
CPU time 6.16 seconds
Started Jul 18 05:23:58 PM PDT 24
Finished Jul 18 05:24:06 PM PDT 24
Peak memory 233144 kb
Host smart-0c2fac5a-b0f4-403b-97bd-2af153e775bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489279135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1489279135
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2521182521
Short name T252
Test name
Test status
Simulation time 1508566403 ps
CPU time 20.14 seconds
Started Jul 18 05:23:53 PM PDT 24
Finished Jul 18 05:24:14 PM PDT 24
Peak memory 250900 kb
Host smart-6652398e-912f-47fd-b31b-ea2db3b2e138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521182521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2521182521
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1299359281
Short name T280
Test name
Test status
Simulation time 19235297357 ps
CPU time 14.69 seconds
Started Jul 18 05:23:52 PM PDT 24
Finished Jul 18 05:24:07 PM PDT 24
Peak memory 233224 kb
Host smart-1b33ab9f-eed3-4389-8f5c-33ffa57d1e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299359281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1299359281
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4022952165
Short name T198
Test name
Test status
Simulation time 375254339 ps
CPU time 3.82 seconds
Started Jul 18 05:23:54 PM PDT 24
Finished Jul 18 05:23:59 PM PDT 24
Peak memory 233124 kb
Host smart-b0e9a162-52e3-4899-a0f9-0792ffaacb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022952165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4022952165
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4100904195
Short name T879
Test name
Test status
Simulation time 1314812709 ps
CPU time 11.79 seconds
Started Jul 18 05:23:58 PM PDT 24
Finished Jul 18 05:24:12 PM PDT 24
Peak memory 219816 kb
Host smart-acbc21c0-933c-482a-ad3e-3dff7e25ab6c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4100904195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4100904195
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1224604531
Short name T507
Test name
Test status
Simulation time 700850276203 ps
CPU time 350.25 seconds
Started Jul 18 05:23:57 PM PDT 24
Finished Jul 18 05:29:49 PM PDT 24
Peak memory 257904 kb
Host smart-acc515a7-612f-446c-bf95-26eaf6797207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224604531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1224604531
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2464105934
Short name T370
Test name
Test status
Simulation time 6050214049 ps
CPU time 28.7 seconds
Started Jul 18 05:23:57 PM PDT 24
Finished Jul 18 05:24:28 PM PDT 24
Peak memory 216732 kb
Host smart-80124894-1da4-4a8a-9b9d-58775c8628c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464105934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2464105934
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4276828530
Short name T487
Test name
Test status
Simulation time 1895634471 ps
CPU time 4.99 seconds
Started Jul 18 05:23:56 PM PDT 24
Finished Jul 18 05:24:02 PM PDT 24
Peak memory 216624 kb
Host smart-72517427-4e3a-41c5-ab20-ff2626cf6fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276828530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4276828530
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1755990351
Short name T594
Test name
Test status
Simulation time 27688724 ps
CPU time 0.84 seconds
Started Jul 18 05:23:46 PM PDT 24
Finished Jul 18 05:23:48 PM PDT 24
Peak memory 206280 kb
Host smart-352462e0-8de4-4fe3-bed2-66e753f558c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755990351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1755990351
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1437277328
Short name T841
Test name
Test status
Simulation time 326726085 ps
CPU time 0.99 seconds
Started Jul 18 05:28:36 PM PDT 24
Finished Jul 18 05:28:37 PM PDT 24
Peak memory 207288 kb
Host smart-5cb1b63c-7e0f-4bdc-8558-97411c1558b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437277328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1437277328
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1812205745
Short name T762
Test name
Test status
Simulation time 1722346830 ps
CPU time 3.27 seconds
Started Jul 18 05:23:46 PM PDT 24
Finished Jul 18 05:23:51 PM PDT 24
Peak memory 224620 kb
Host smart-f01fc754-aa73-4b16-9381-3d6ec5d68c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812205745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1812205745
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1394082437
Short name T884
Test name
Test status
Simulation time 34386583 ps
CPU time 0.74 seconds
Started Jul 18 05:23:56 PM PDT 24
Finished Jul 18 05:23:58 PM PDT 24
Peak memory 205696 kb
Host smart-d6ba6e01-fbe4-46c2-a0b5-baf7a5127a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394082437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1394082437
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.623545669
Short name T98
Test name
Test status
Simulation time 997022137 ps
CPU time 4.45 seconds
Started Jul 18 05:24:09 PM PDT 24
Finished Jul 18 05:24:14 PM PDT 24
Peak memory 224848 kb
Host smart-f6c689f5-ec25-41ef-be66-70184a8709d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623545669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.623545669
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1874267962
Short name T470
Test name
Test status
Simulation time 67236699 ps
CPU time 0.78 seconds
Started Jul 18 05:23:56 PM PDT 24
Finished Jul 18 05:23:57 PM PDT 24
Peak memory 205848 kb
Host smart-f399aeca-e699-4e74-8484-cf2b09a15b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874267962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1874267962
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2086948784
Short name T734
Test name
Test status
Simulation time 2778473908 ps
CPU time 37.41 seconds
Started Jul 18 05:23:57 PM PDT 24
Finished Jul 18 05:24:36 PM PDT 24
Peak memory 249880 kb
Host smart-a8f56107-4b0f-44da-8ec2-5a2958799ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086948784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2086948784
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2241017840
Short name T996
Test name
Test status
Simulation time 19376513537 ps
CPU time 79.76 seconds
Started Jul 18 05:23:58 PM PDT 24
Finished Jul 18 05:25:20 PM PDT 24
Peak memory 249652 kb
Host smart-310670e7-a029-412a-9c3b-03cf8d3d587f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241017840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2241017840
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2138294532
Short name T320
Test name
Test status
Simulation time 187352156 ps
CPU time 7.39 seconds
Started Jul 18 05:23:57 PM PDT 24
Finished Jul 18 05:24:06 PM PDT 24
Peak memory 224932 kb
Host smart-83be1622-7285-4194-a348-4e68b9e9103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138294532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2138294532
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1669834545
Short name T991
Test name
Test status
Simulation time 55087708899 ps
CPU time 66.62 seconds
Started Jul 18 05:24:02 PM PDT 24
Finished Jul 18 05:25:10 PM PDT 24
Peak memory 249596 kb
Host smart-b780bd5b-94b9-4bcb-8840-b617401a0e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669834545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1669834545
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2771738025
Short name T502
Test name
Test status
Simulation time 944725874 ps
CPU time 3.88 seconds
Started Jul 18 05:23:56 PM PDT 24
Finished Jul 18 05:24:00 PM PDT 24
Peak memory 225000 kb
Host smart-24643154-8e2f-481a-a028-fe26e4c6a0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771738025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2771738025
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.993453691
Short name T204
Test name
Test status
Simulation time 2270737580 ps
CPU time 33.52 seconds
Started Jul 18 05:24:03 PM PDT 24
Finished Jul 18 05:24:38 PM PDT 24
Peak memory 233208 kb
Host smart-262da590-13cb-4d93-874f-17ef7c9ca2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993453691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.993453691
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.223764883
Short name T1005
Test name
Test status
Simulation time 185724757 ps
CPU time 4.43 seconds
Started Jul 18 05:23:56 PM PDT 24
Finished Jul 18 05:24:02 PM PDT 24
Peak memory 233092 kb
Host smart-101205ae-f020-4570-aa4b-9eb16e8c4723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223764883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.223764883
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.4169905680
Short name T900
Test name
Test status
Simulation time 383569516 ps
CPU time 5.13 seconds
Started Jul 18 05:23:57 PM PDT 24
Finished Jul 18 05:24:03 PM PDT 24
Peak memory 233176 kb
Host smart-fc4103ff-4783-45aa-bbac-63cea91af5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169905680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4169905680
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3601609208
Short name T510
Test name
Test status
Simulation time 1091852045 ps
CPU time 5.5 seconds
Started Jul 18 05:23:59 PM PDT 24
Finished Jul 18 05:24:06 PM PDT 24
Peak memory 223512 kb
Host smart-8da180ce-84c2-4bf0-8e37-906fdec51425
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3601609208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3601609208
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4059021239
Short name T381
Test name
Test status
Simulation time 11933366 ps
CPU time 0.77 seconds
Started Jul 18 05:23:59 PM PDT 24
Finished Jul 18 05:24:02 PM PDT 24
Peak memory 206340 kb
Host smart-10351b38-60bc-4a24-86a8-51fe185f789c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059021239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4059021239
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1238071096
Short name T64
Test name
Test status
Simulation time 5430740402 ps
CPU time 11.88 seconds
Started Jul 18 05:24:00 PM PDT 24
Finished Jul 18 05:24:14 PM PDT 24
Peak memory 216788 kb
Host smart-14f48056-e7b6-4091-bd39-8c77d0723712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238071096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1238071096
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2035474397
Short name T349
Test name
Test status
Simulation time 13395382 ps
CPU time 0.69 seconds
Started Jul 18 05:23:56 PM PDT 24
Finished Jul 18 05:23:57 PM PDT 24
Peak memory 205956 kb
Host smart-bc344eb4-6ed9-463e-8168-a0fb61563279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035474397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2035474397
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2915523493
Short name T5
Test name
Test status
Simulation time 810484055 ps
CPU time 0.88 seconds
Started Jul 18 05:23:59 PM PDT 24
Finished Jul 18 05:24:02 PM PDT 24
Peak memory 205484 kb
Host smart-5a0d8621-faeb-442c-8c89-aff187e3db96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915523493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2915523493
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3702319360
Short name T374
Test name
Test status
Simulation time 677354970 ps
CPU time 3.21 seconds
Started Jul 18 05:24:02 PM PDT 24
Finished Jul 18 05:24:07 PM PDT 24
Peak memory 233028 kb
Host smart-4d01a658-19bd-4842-abe0-db3abd5ce9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702319360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3702319360
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2600933504
Short name T562
Test name
Test status
Simulation time 11397906 ps
CPU time 0.72 seconds
Started Jul 18 05:23:57 PM PDT 24
Finished Jul 18 05:24:00 PM PDT 24
Peak memory 205732 kb
Host smart-fca9015f-3f99-4e64-b74d-81a954dbb30e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600933504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2600933504
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.276517296
Short name T967
Test name
Test status
Simulation time 566903565 ps
CPU time 3.41 seconds
Started Jul 18 05:23:59 PM PDT 24
Finished Jul 18 05:24:04 PM PDT 24
Peak memory 225012 kb
Host smart-2a8b6768-1bb9-4702-822d-64d0e68f9c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276517296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.276517296
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4011073903
Short name T528
Test name
Test status
Simulation time 23283652 ps
CPU time 0.73 seconds
Started Jul 18 05:23:57 PM PDT 24
Finished Jul 18 05:23:59 PM PDT 24
Peak memory 206200 kb
Host smart-8a1285df-4f22-4b23-a213-f1fbad9a81a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011073903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4011073903
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2827875954
Short name T712
Test name
Test status
Simulation time 70157087818 ps
CPU time 252.04 seconds
Started Jul 18 05:23:56 PM PDT 24
Finished Jul 18 05:28:09 PM PDT 24
Peak memory 265336 kb
Host smart-be774411-2685-4cac-9043-8a2cfbe8cc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827875954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2827875954
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2835966653
Short name T650
Test name
Test status
Simulation time 13687303807 ps
CPU time 106.41 seconds
Started Jul 18 05:23:57 PM PDT 24
Finished Jul 18 05:25:45 PM PDT 24
Peak memory 249956 kb
Host smart-76df5a16-0c8e-48c5-aec7-8a00346eeec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835966653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2835966653
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2445645771
Short name T651
Test name
Test status
Simulation time 91452657769 ps
CPU time 164.23 seconds
Started Jul 18 05:23:57 PM PDT 24
Finished Jul 18 05:26:44 PM PDT 24
Peak memory 253760 kb
Host smart-1631a479-e2c4-4863-832c-12ecdf81289e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445645771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2445645771
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1453386278
Short name T535
Test name
Test status
Simulation time 749589501 ps
CPU time 15.84 seconds
Started Jul 18 05:23:57 PM PDT 24
Finished Jul 18 05:24:15 PM PDT 24
Peak memory 235508 kb
Host smart-e565e679-243d-4b70-9bdc-6e682d4f54ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453386278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1453386278
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2203482975
Short name T776
Test name
Test status
Simulation time 82699038299 ps
CPU time 64.12 seconds
Started Jul 18 05:23:57 PM PDT 24
Finished Jul 18 05:25:02 PM PDT 24
Peak memory 253404 kb
Host smart-ba8db967-03a3-4b60-8295-5b3e9e22d297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203482975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2203482975
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4256456966
Short name T357
Test name
Test status
Simulation time 1172711389 ps
CPU time 11.57 seconds
Started Jul 18 05:23:59 PM PDT 24
Finished Jul 18 05:24:12 PM PDT 24
Peak memory 233084 kb
Host smart-5bdce3b3-a789-4f75-a7f9-93bf885947d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256456966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4256456966
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2366796629
Short name T242
Test name
Test status
Simulation time 9212287484 ps
CPU time 33.95 seconds
Started Jul 18 05:23:58 PM PDT 24
Finished Jul 18 05:24:34 PM PDT 24
Peak memory 224980 kb
Host smart-08fd3c19-33cc-44c6-9435-fdbab1d17e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366796629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2366796629
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2776245546
Short name T267
Test name
Test status
Simulation time 426670573 ps
CPU time 4.56 seconds
Started Jul 18 05:23:59 PM PDT 24
Finished Jul 18 05:24:05 PM PDT 24
Peak memory 224900 kb
Host smart-95bd26b9-57cf-403e-a406-41294543a2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776245546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2776245546
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3767494582
Short name T614
Test name
Test status
Simulation time 1742685101 ps
CPU time 7.54 seconds
Started Jul 18 05:23:59 PM PDT 24
Finished Jul 18 05:24:09 PM PDT 24
Peak memory 232628 kb
Host smart-05ac78ac-9a57-4ab3-8e2e-8e306d896fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767494582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3767494582
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3052731870
Short name T709
Test name
Test status
Simulation time 3614518711 ps
CPU time 8.33 seconds
Started Jul 18 05:23:59 PM PDT 24
Finished Jul 18 05:24:09 PM PDT 24
Peak memory 223464 kb
Host smart-79939b1c-5fc7-4d27-a77e-e22c7ffad316
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3052731870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3052731870
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1783128444
Short name T982
Test name
Test status
Simulation time 5868506015 ps
CPU time 83.87 seconds
Started Jul 18 05:24:00 PM PDT 24
Finished Jul 18 05:25:25 PM PDT 24
Peak memory 257848 kb
Host smart-b2d9e5ef-b6a7-40eb-8e5a-8d12a8b207ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783128444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1783128444
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.579867257
Short name T926
Test name
Test status
Simulation time 1756889200 ps
CPU time 12.34 seconds
Started Jul 18 05:23:58 PM PDT 24
Finished Jul 18 05:24:13 PM PDT 24
Peak memory 219484 kb
Host smart-049e8f31-6bc0-4dfd-8bd0-478e858b9f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579867257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.579867257
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1294925123
Short name T350
Test name
Test status
Simulation time 20842015652 ps
CPU time 20.7 seconds
Started Jul 18 05:23:58 PM PDT 24
Finished Jul 18 05:24:21 PM PDT 24
Peak memory 216816 kb
Host smart-e5d732ca-6718-4c76-9b65-dff2dc9f17de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294925123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1294925123
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.845630645
Short name T585
Test name
Test status
Simulation time 26672859 ps
CPU time 1.13 seconds
Started Jul 18 05:24:02 PM PDT 24
Finished Jul 18 05:24:04 PM PDT 24
Peak memory 207360 kb
Host smart-f26ea231-2ef5-4477-a5c1-8f91a033bd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845630645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.845630645
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2658208435
Short name T988
Test name
Test status
Simulation time 239055912 ps
CPU time 0.79 seconds
Started Jul 18 05:23:55 PM PDT 24
Finished Jul 18 05:23:56 PM PDT 24
Peak memory 206264 kb
Host smart-12380583-86dc-4764-a304-93f52ad578bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658208435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2658208435
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3189636429
Short name T880
Test name
Test status
Simulation time 3773957950 ps
CPU time 14.37 seconds
Started Jul 18 05:24:03 PM PDT 24
Finished Jul 18 05:24:18 PM PDT 24
Peak memory 224940 kb
Host smart-6b521474-6acf-46df-97dc-a6093650381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189636429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3189636429
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4021333315
Short name T371
Test name
Test status
Simulation time 22242177 ps
CPU time 0.72 seconds
Started Jul 18 05:24:17 PM PDT 24
Finished Jul 18 05:24:19 PM PDT 24
Peak memory 205112 kb
Host smart-9e4b269a-d614-4ee7-ac17-a740563a90ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021333315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4021333315
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.256292712
Short name T825
Test name
Test status
Simulation time 4723817637 ps
CPU time 13.3 seconds
Started Jul 18 05:24:14 PM PDT 24
Finished Jul 18 05:24:29 PM PDT 24
Peak memory 233276 kb
Host smart-1496d37b-c256-424a-bcfc-cf1e0b325cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256292712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.256292712
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2619674657
Short name T731
Test name
Test status
Simulation time 15841742 ps
CPU time 0.82 seconds
Started Jul 18 05:23:58 PM PDT 24
Finished Jul 18 05:24:01 PM PDT 24
Peak memory 206884 kb
Host smart-4464d375-4399-464e-a27c-d2dba7a0d992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619674657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2619674657
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3804265083
Short name T925
Test name
Test status
Simulation time 14567641361 ps
CPU time 143.97 seconds
Started Jul 18 05:24:14 PM PDT 24
Finished Jul 18 05:26:39 PM PDT 24
Peak memory 250732 kb
Host smart-53473989-ae40-46c0-9895-adee6b895dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804265083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3804265083
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1342084026
Short name T508
Test name
Test status
Simulation time 8944802375 ps
CPU time 29.37 seconds
Started Jul 18 05:24:15 PM PDT 24
Finished Jul 18 05:24:46 PM PDT 24
Peak memory 249904 kb
Host smart-5c57955b-769b-4145-8e9b-7b25fd450ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342084026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1342084026
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4006374526
Short name T549
Test name
Test status
Simulation time 1887671376 ps
CPU time 8.18 seconds
Started Jul 18 05:24:13 PM PDT 24
Finished Jul 18 05:24:22 PM PDT 24
Peak memory 224928 kb
Host smart-72cf011e-f771-4132-b66d-079aa7f58109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006374526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4006374526
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4133765636
Short name T634
Test name
Test status
Simulation time 396761481 ps
CPU time 5.74 seconds
Started Jul 18 05:23:56 PM PDT 24
Finished Jul 18 05:24:03 PM PDT 24
Peak memory 233060 kb
Host smart-611efc04-d66a-49e7-ad11-c07b9ae2efed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133765636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4133765636
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.537017833
Short name T474
Test name
Test status
Simulation time 33417319 ps
CPU time 2.47 seconds
Started Jul 18 05:24:14 PM PDT 24
Finished Jul 18 05:24:17 PM PDT 24
Peak memory 232800 kb
Host smart-e159fa8a-9621-429f-b947-32721fbf015a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537017833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.537017833
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.927748176
Short name T260
Test name
Test status
Simulation time 1191366639 ps
CPU time 9.11 seconds
Started Jul 18 05:24:00 PM PDT 24
Finished Jul 18 05:24:11 PM PDT 24
Peak memory 240008 kb
Host smart-a5889779-451f-493f-af97-103e3865ac85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927748176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.927748176
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3135439512
Short name T854
Test name
Test status
Simulation time 9011444140 ps
CPU time 11.25 seconds
Started Jul 18 05:24:02 PM PDT 24
Finished Jul 18 05:24:14 PM PDT 24
Peak memory 220984 kb
Host smart-602c09e1-260c-46d2-b44e-52e79c31bb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135439512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3135439512
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2862837866
Short name T97
Test name
Test status
Simulation time 1891152247 ps
CPU time 6.8 seconds
Started Jul 18 05:24:15 PM PDT 24
Finished Jul 18 05:24:24 PM PDT 24
Peak memory 222416 kb
Host smart-02d1c376-478f-4488-b2d2-8da0174b589e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2862837866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2862837866
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1158815080
Short name T61
Test name
Test status
Simulation time 28639143915 ps
CPU time 315.46 seconds
Started Jul 18 05:24:12 PM PDT 24
Finished Jul 18 05:29:28 PM PDT 24
Peak memory 257908 kb
Host smart-9166b099-2ef8-4a1d-88c9-fa3c9dc6a9ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158815080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1158815080
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.234083934
Short name T834
Test name
Test status
Simulation time 474220238 ps
CPU time 7.82 seconds
Started Jul 18 05:23:58 PM PDT 24
Finished Jul 18 05:24:08 PM PDT 24
Peak memory 216668 kb
Host smart-b434a777-9bf6-4ae2-bdb0-143a157e7b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234083934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.234083934
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1340672697
Short name T820
Test name
Test status
Simulation time 98563009 ps
CPU time 1.15 seconds
Started Jul 18 05:24:02 PM PDT 24
Finished Jul 18 05:24:04 PM PDT 24
Peak memory 207976 kb
Host smart-72c330d4-9084-473c-98a9-a4192d4b0f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340672697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1340672697
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3813503061
Short name T861
Test name
Test status
Simulation time 151103278 ps
CPU time 1.42 seconds
Started Jul 18 05:24:01 PM PDT 24
Finished Jul 18 05:24:04 PM PDT 24
Peak memory 216576 kb
Host smart-883fd80c-8132-4c25-af51-2fb32d58bfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813503061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3813503061
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1086832297
Short name T797
Test name
Test status
Simulation time 33079770 ps
CPU time 0.85 seconds
Started Jul 18 05:23:59 PM PDT 24
Finished Jul 18 05:24:02 PM PDT 24
Peak memory 207216 kb
Host smart-b1144ba8-c75d-45af-afc0-b177ccffae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086832297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1086832297
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2716784772
Short name T88
Test name
Test status
Simulation time 1024171045 ps
CPU time 6.2 seconds
Started Jul 18 05:24:15 PM PDT 24
Finished Jul 18 05:24:22 PM PDT 24
Peak memory 224804 kb
Host smart-b3a8a6c4-a9f0-4be5-a002-a345ae8bbd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716784772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2716784772
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2256367962
Short name T690
Test name
Test status
Simulation time 23421059 ps
CPU time 0.7 seconds
Started Jul 18 05:24:16 PM PDT 24
Finished Jul 18 05:24:19 PM PDT 24
Peak memory 205168 kb
Host smart-65415f1e-33d7-4496-90e9-3f99b45c0013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256367962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2256367962
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.844469836
Short name T752
Test name
Test status
Simulation time 253148566 ps
CPU time 4.01 seconds
Started Jul 18 05:24:14 PM PDT 24
Finished Jul 18 05:24:19 PM PDT 24
Peak memory 224836 kb
Host smart-f8edfc41-1397-451e-950e-18e45c5ef285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844469836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.844469836
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1790694182
Short name T531
Test name
Test status
Simulation time 30536117 ps
CPU time 0.88 seconds
Started Jul 18 05:24:17 PM PDT 24
Finished Jul 18 05:24:19 PM PDT 24
Peak memory 206884 kb
Host smart-9c308e61-434c-497b-ab90-4f02feefa583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790694182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1790694182
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2077683589
Short name T398
Test name
Test status
Simulation time 2745048026 ps
CPU time 15.33 seconds
Started Jul 18 05:24:20 PM PDT 24
Finished Jul 18 05:24:36 PM PDT 24
Peak memory 235880 kb
Host smart-04c896d9-a2ec-492f-a97b-67637d530354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077683589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2077683589
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2182619853
Short name T95
Test name
Test status
Simulation time 4903250398 ps
CPU time 60.18 seconds
Started Jul 18 05:24:15 PM PDT 24
Finished Jul 18 05:25:17 PM PDT 24
Peak memory 249736 kb
Host smart-08834ab4-f14e-4538-a945-01cbc832beb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182619853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2182619853
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.4251154079
Short name T859
Test name
Test status
Simulation time 220968607 ps
CPU time 3.3 seconds
Started Jul 18 05:24:17 PM PDT 24
Finished Jul 18 05:24:22 PM PDT 24
Peak memory 233116 kb
Host smart-76702279-eceb-44c9-9a4c-6c5a1f373321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251154079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.4251154079
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3251151027
Short name T882
Test name
Test status
Simulation time 13472314 ps
CPU time 0.75 seconds
Started Jul 18 05:24:14 PM PDT 24
Finished Jul 18 05:24:16 PM PDT 24
Peak memory 216236 kb
Host smart-3c923827-3279-4244-8933-0890bf8251ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251151027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3251151027
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3944918965
Short name T199
Test name
Test status
Simulation time 1166560478 ps
CPU time 4.47 seconds
Started Jul 18 05:24:17 PM PDT 24
Finished Jul 18 05:24:23 PM PDT 24
Peak memory 233156 kb
Host smart-d9ed2113-299f-462d-9e27-6b649a7b3615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944918965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3944918965
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3167901900
Short name T999
Test name
Test status
Simulation time 1728191591 ps
CPU time 23.29 seconds
Started Jul 18 05:24:14 PM PDT 24
Finished Jul 18 05:24:38 PM PDT 24
Peak memory 249272 kb
Host smart-81075047-b150-4cfd-929a-6e818e90cc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167901900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3167901900
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2976005604
Short name T905
Test name
Test status
Simulation time 523985704 ps
CPU time 7.18 seconds
Started Jul 18 05:24:16 PM PDT 24
Finished Jul 18 05:24:25 PM PDT 24
Peak memory 233032 kb
Host smart-4f7d57ba-0f10-414a-b0dc-6c529fdc3e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976005604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2976005604
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3146248151
Short name T457
Test name
Test status
Simulation time 524629713 ps
CPU time 3.8 seconds
Started Jul 18 05:24:15 PM PDT 24
Finished Jul 18 05:24:20 PM PDT 24
Peak memory 223536 kb
Host smart-1081bb8e-6660-4431-b1cb-6b0b4580a8f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3146248151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3146248151
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2891463191
Short name T563
Test name
Test status
Simulation time 82339813635 ps
CPU time 784.25 seconds
Started Jul 18 05:24:17 PM PDT 24
Finished Jul 18 05:37:22 PM PDT 24
Peak memory 290796 kb
Host smart-3da63837-e260-4f84-a871-da76378ad8b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891463191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2891463191
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3663694256
Short name T328
Test name
Test status
Simulation time 1683337859 ps
CPU time 26.43 seconds
Started Jul 18 05:24:18 PM PDT 24
Finished Jul 18 05:24:46 PM PDT 24
Peak memory 217024 kb
Host smart-aed3a381-3cc3-408c-ab6a-de76e5cc0d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663694256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3663694256
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.427237846
Short name T998
Test name
Test status
Simulation time 4664350310 ps
CPU time 7.81 seconds
Started Jul 18 05:24:17 PM PDT 24
Finished Jul 18 05:24:26 PM PDT 24
Peak memory 216740 kb
Host smart-2135cfce-5869-459f-b67b-b10ee9945842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427237846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.427237846
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3127038430
Short name T972
Test name
Test status
Simulation time 58357151 ps
CPU time 1.12 seconds
Started Jul 18 05:24:15 PM PDT 24
Finished Jul 18 05:24:17 PM PDT 24
Peak memory 208212 kb
Host smart-44cddf0d-238d-4e18-9c17-297f67b09bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127038430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3127038430
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4150632118
Short name T1002
Test name
Test status
Simulation time 48007827 ps
CPU time 0.88 seconds
Started Jul 18 05:24:18 PM PDT 24
Finished Jul 18 05:24:20 PM PDT 24
Peak memory 206196 kb
Host smart-5418c18e-621b-4303-abeb-e0fc6d1e2044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150632118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4150632118
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.555979374
Short name T863
Test name
Test status
Simulation time 6083750165 ps
CPU time 21.31 seconds
Started Jul 18 05:24:13 PM PDT 24
Finished Jul 18 05:24:35 PM PDT 24
Peak memory 250436 kb
Host smart-a5947038-a1e7-4b66-9607-4f06b16c2f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555979374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.555979374
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3256194454
Short name T72
Test name
Test status
Simulation time 14765409 ps
CPU time 0.73 seconds
Started Jul 18 05:24:26 PM PDT 24
Finished Jul 18 05:24:28 PM PDT 24
Peak memory 206088 kb
Host smart-e2fcdc7b-10c0-44ff-903e-ed94dd18b5e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256194454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3256194454
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2458837648
Short name T286
Test name
Test status
Simulation time 503875631 ps
CPU time 6.99 seconds
Started Jul 18 05:24:29 PM PDT 24
Finished Jul 18 05:24:37 PM PDT 24
Peak memory 224976 kb
Host smart-54e76c00-5df9-4a7e-8e3a-200cf181774c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458837648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2458837648
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1939652566
Short name T341
Test name
Test status
Simulation time 17789729 ps
CPU time 0.78 seconds
Started Jul 18 05:24:13 PM PDT 24
Finished Jul 18 05:24:15 PM PDT 24
Peak memory 206160 kb
Host smart-4dc8595d-3b9e-4ff0-a8c4-253136d206f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939652566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1939652566
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1808104907
Short name T804
Test name
Test status
Simulation time 9955392243 ps
CPU time 41.5 seconds
Started Jul 18 05:24:30 PM PDT 24
Finished Jul 18 05:25:13 PM PDT 24
Peak memory 241512 kb
Host smart-96e00548-2e1e-4bc4-9b23-92a441821798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808104907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1808104907
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2745514725
Short name T971
Test name
Test status
Simulation time 28988000848 ps
CPU time 275.06 seconds
Started Jul 18 05:24:28 PM PDT 24
Finished Jul 18 05:29:05 PM PDT 24
Peak memory 249656 kb
Host smart-3e6c2b01-7b15-492d-b429-12ff56c6a109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745514725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2745514725
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1931766873
Short name T312
Test name
Test status
Simulation time 50274232796 ps
CPU time 86.25 seconds
Started Jul 18 05:24:27 PM PDT 24
Finished Jul 18 05:25:54 PM PDT 24
Peak memory 250068 kb
Host smart-e6348727-0613-4f0d-9d9c-357944702253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931766873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1931766873
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1982129111
Short name T876
Test name
Test status
Simulation time 928789397 ps
CPU time 9.49 seconds
Started Jul 18 05:24:28 PM PDT 24
Finished Jul 18 05:24:39 PM PDT 24
Peak memory 249540 kb
Host smart-a78bd9bf-73dd-4afb-9e76-7c2da366866f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982129111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1982129111
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2246464173
Short name T668
Test name
Test status
Simulation time 1442536479 ps
CPU time 8.22 seconds
Started Jul 18 05:24:27 PM PDT 24
Finished Jul 18 05:24:37 PM PDT 24
Peak memory 234848 kb
Host smart-6cd0736d-6f80-47c6-90d5-b86dc45a478a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246464173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2246464173
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1905049796
Short name T338
Test name
Test status
Simulation time 1031937869 ps
CPU time 5.14 seconds
Started Jul 18 05:24:15 PM PDT 24
Finished Jul 18 05:24:21 PM PDT 24
Peak memory 224876 kb
Host smart-b30af7fc-e5c7-4db6-80f7-f986c2d48a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905049796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1905049796
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3385534321
Short name T28
Test name
Test status
Simulation time 370638356 ps
CPU time 4.06 seconds
Started Jul 18 05:24:17 PM PDT 24
Finished Jul 18 05:24:23 PM PDT 24
Peak memory 233116 kb
Host smart-201e993c-acc7-448b-8a24-9ecc24fc2067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385534321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3385534321
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2035673938
Short name T943
Test name
Test status
Simulation time 5640533089 ps
CPU time 17.39 seconds
Started Jul 18 05:24:15 PM PDT 24
Finished Jul 18 05:24:34 PM PDT 24
Peak memory 241036 kb
Host smart-d1f157e5-c672-44ab-9347-8cf6768b412e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035673938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2035673938
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1618895693
Short name T566
Test name
Test status
Simulation time 830019166 ps
CPU time 2.44 seconds
Started Jul 18 05:24:32 PM PDT 24
Finished Jul 18 05:24:38 PM PDT 24
Peak memory 224916 kb
Host smart-74e66a1a-8b8a-421a-b585-adcca35d8e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618895693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1618895693
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1188034023
Short name T833
Test name
Test status
Simulation time 1042769229 ps
CPU time 7.6 seconds
Started Jul 18 05:24:24 PM PDT 24
Finished Jul 18 05:24:32 PM PDT 24
Peak memory 220608 kb
Host smart-24c2b56e-0932-4d1c-b358-c833a5a62004
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1188034023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1188034023
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1724465091
Short name T685
Test name
Test status
Simulation time 155677125 ps
CPU time 1.04 seconds
Started Jul 18 05:24:32 PM PDT 24
Finished Jul 18 05:24:36 PM PDT 24
Peak memory 207184 kb
Host smart-beb46a07-aa38-490c-8879-93baa5b47596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724465091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1724465091
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2444140202
Short name T836
Test name
Test status
Simulation time 36630025 ps
CPU time 0.71 seconds
Started Jul 18 05:24:16 PM PDT 24
Finished Jul 18 05:24:18 PM PDT 24
Peak memory 206008 kb
Host smart-2aba61ef-19f6-486b-8c46-63ccd4b10e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444140202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2444140202
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2454831464
Short name T584
Test name
Test status
Simulation time 8113145297 ps
CPU time 10.89 seconds
Started Jul 18 05:24:14 PM PDT 24
Finished Jul 18 05:24:26 PM PDT 24
Peak memory 216764 kb
Host smart-175a6f58-bf55-4237-b6dc-1286db1ca04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454831464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2454831464
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4035905340
Short name T853
Test name
Test status
Simulation time 115443842 ps
CPU time 2.64 seconds
Started Jul 18 05:24:14 PM PDT 24
Finished Jul 18 05:24:18 PM PDT 24
Peak memory 216608 kb
Host smart-fc68a0a1-e557-46dd-ba56-b2c906317428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035905340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4035905340
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1531410743
Short name T619
Test name
Test status
Simulation time 91085248 ps
CPU time 0.97 seconds
Started Jul 18 05:24:14 PM PDT 24
Finished Jul 18 05:24:17 PM PDT 24
Peak memory 206724 kb
Host smart-ea870ae4-1fd1-422d-804e-7d817a875211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531410743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1531410743
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3459281455
Short name T769
Test name
Test status
Simulation time 2634099104 ps
CPU time 4.56 seconds
Started Jul 18 05:24:16 PM PDT 24
Finished Jul 18 05:24:22 PM PDT 24
Peak memory 233212 kb
Host smart-7a15d67a-50c2-41cd-a6b9-acb5038e5c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459281455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3459281455
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1449887732
Short name T26
Test name
Test status
Simulation time 41136151 ps
CPU time 0.74 seconds
Started Jul 18 05:24:31 PM PDT 24
Finished Jul 18 05:24:35 PM PDT 24
Peak memory 205724 kb
Host smart-a7003de1-4d80-415c-b56d-a195833ec629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449887732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1449887732
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.745755211
Short name T629
Test name
Test status
Simulation time 117997345 ps
CPU time 2.21 seconds
Started Jul 18 05:24:27 PM PDT 24
Finished Jul 18 05:24:30 PM PDT 24
Peak memory 232796 kb
Host smart-e5054083-acd1-4f61-8c5b-1e1f817f589d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745755211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.745755211
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2131348441
Short name T862
Test name
Test status
Simulation time 20328563 ps
CPU time 0.78 seconds
Started Jul 18 05:24:27 PM PDT 24
Finished Jul 18 05:24:30 PM PDT 24
Peak memory 205876 kb
Host smart-279df9ff-33fc-4785-bdb9-2faa52afa998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131348441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2131348441
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2964522853
Short name T449
Test name
Test status
Simulation time 57193929 ps
CPU time 0.75 seconds
Started Jul 18 05:24:26 PM PDT 24
Finished Jul 18 05:24:27 PM PDT 24
Peak memory 216304 kb
Host smart-bf448343-25c7-421c-b79d-377cabe768aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964522853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2964522853
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2240748258
Short name T418
Test name
Test status
Simulation time 30955007923 ps
CPU time 24.58 seconds
Started Jul 18 05:24:32 PM PDT 24
Finished Jul 18 05:25:00 PM PDT 24
Peak memory 218096 kb
Host smart-9d72a1eb-1f5a-405f-b973-a1e2a80366c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240748258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2240748258
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3478080558
Short name T272
Test name
Test status
Simulation time 114533351655 ps
CPU time 273.42 seconds
Started Jul 18 05:24:34 PM PDT 24
Finished Jul 18 05:29:10 PM PDT 24
Peak memory 249716 kb
Host smart-87202faf-1122-4a60-8d04-56ee44a33f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478080558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3478080558
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.249504189
Short name T319
Test name
Test status
Simulation time 724344181 ps
CPU time 15.92 seconds
Started Jul 18 05:24:31 PM PDT 24
Finished Jul 18 05:24:49 PM PDT 24
Peak memory 235088 kb
Host smart-502a6347-e181-41af-b337-59ce82e238c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249504189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.249504189
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3990258301
Short name T428
Test name
Test status
Simulation time 31836581 ps
CPU time 2.21 seconds
Started Jul 18 05:24:29 PM PDT 24
Finished Jul 18 05:24:33 PM PDT 24
Peak memory 224928 kb
Host smart-85a61fec-b17a-4d73-891e-15d0e1aa1224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990258301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3990258301
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2047552793
Short name T497
Test name
Test status
Simulation time 2275716476 ps
CPU time 12.94 seconds
Started Jul 18 05:24:28 PM PDT 24
Finished Jul 18 05:24:43 PM PDT 24
Peak memory 249592 kb
Host smart-d3eb512c-1cdd-4bd3-9284-a0087eaa2e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047552793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2047552793
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4123012273
Short name T81
Test name
Test status
Simulation time 1159255962 ps
CPU time 5.69 seconds
Started Jul 18 05:24:33 PM PDT 24
Finished Jul 18 05:24:42 PM PDT 24
Peak memory 224892 kb
Host smart-52752c1a-7d73-4556-9129-41908770a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123012273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.4123012273
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1705136503
Short name T906
Test name
Test status
Simulation time 280960370 ps
CPU time 2.07 seconds
Started Jul 18 05:24:31 PM PDT 24
Finished Jul 18 05:24:36 PM PDT 24
Peak memory 224348 kb
Host smart-f255c8a4-640b-4367-8abb-533022200d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705136503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1705136503
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.809509428
Short name T918
Test name
Test status
Simulation time 1142013396 ps
CPU time 4.78 seconds
Started Jul 18 05:24:30 PM PDT 24
Finished Jul 18 05:24:37 PM PDT 24
Peak memory 221672 kb
Host smart-41503265-35ec-40d8-8013-9b6b3a1d8de7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=809509428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.809509428
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.876294313
Short name T303
Test name
Test status
Simulation time 33197387794 ps
CPU time 318.85 seconds
Started Jul 18 05:24:34 PM PDT 24
Finished Jul 18 05:29:56 PM PDT 24
Peak memory 255960 kb
Host smart-e46b21cd-a506-4e35-9bad-2fa90969a745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876294313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.876294313
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1373055246
Short name T693
Test name
Test status
Simulation time 730247054 ps
CPU time 10.67 seconds
Started Jul 18 05:24:27 PM PDT 24
Finished Jul 18 05:24:39 PM PDT 24
Peak memory 216676 kb
Host smart-9f8db7b2-8019-4d1c-bd5d-337145dd7132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373055246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1373055246
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1471995095
Short name T660
Test name
Test status
Simulation time 8543095900 ps
CPU time 7.68 seconds
Started Jul 18 05:24:32 PM PDT 24
Finished Jul 18 05:24:42 PM PDT 24
Peak memory 216732 kb
Host smart-44338ef1-9a89-4911-9512-a01d5c93f85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471995095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1471995095
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.958154145
Short name T738
Test name
Test status
Simulation time 142095475 ps
CPU time 3.88 seconds
Started Jul 18 05:24:28 PM PDT 24
Finished Jul 18 05:24:34 PM PDT 24
Peak memory 216680 kb
Host smart-e976489f-7af2-4745-be68-b1e6bd1c592a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958154145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.958154145
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.475956121
Short name T558
Test name
Test status
Simulation time 68851961 ps
CPU time 0.94 seconds
Started Jul 18 05:24:33 PM PDT 24
Finished Jul 18 05:24:37 PM PDT 24
Peak memory 206696 kb
Host smart-47ed3bb1-1d7b-4ec4-b654-fdf0a9293912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475956121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.475956121
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3653748847
Short name T174
Test name
Test status
Simulation time 4724054449 ps
CPU time 16.26 seconds
Started Jul 18 05:24:33 PM PDT 24
Finished Jul 18 05:24:52 PM PDT 24
Peak memory 225012 kb
Host smart-d74eda57-cd18-4e18-80ca-06799ccf2ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653748847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3653748847
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.694403295
Short name T635
Test name
Test status
Simulation time 152824923 ps
CPU time 0.72 seconds
Started Jul 18 05:19:30 PM PDT 24
Finished Jul 18 05:19:34 PM PDT 24
Peak memory 205288 kb
Host smart-2aafb939-7530-4728-a4ed-3228d4c0ac7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694403295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.694403295
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.775380510
Short name T658
Test name
Test status
Simulation time 3375710643 ps
CPU time 9.3 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:19:52 PM PDT 24
Peak memory 233208 kb
Host smart-e3d895fb-10a2-4e7a-8f1a-6e69bf101437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775380510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.775380510
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3518407705
Short name T491
Test name
Test status
Simulation time 41864347 ps
CPU time 0.81 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:19:44 PM PDT 24
Peak memory 205876 kb
Host smart-da53432e-4c03-449e-adcc-ae3dd33ce48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518407705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3518407705
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3883522096
Short name T212
Test name
Test status
Simulation time 53875860132 ps
CPU time 33.01 seconds
Started Jul 18 05:19:42 PM PDT 24
Finished Jul 18 05:20:18 PM PDT 24
Peak memory 249636 kb
Host smart-0e8bbbe1-3bd5-4e5f-be35-32b0ade34abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883522096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3883522096
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1756028923
Short name T730
Test name
Test status
Simulation time 6702414488 ps
CPU time 18.94 seconds
Started Jul 18 05:19:43 PM PDT 24
Finished Jul 18 05:20:05 PM PDT 24
Peak memory 222888 kb
Host smart-b0490f44-ee98-4978-b28b-1edd445e4395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756028923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1756028923
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1212735664
Short name T302
Test name
Test status
Simulation time 14807095435 ps
CPU time 113.95 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:21:37 PM PDT 24
Peak memory 255748 kb
Host smart-1463222d-b1fe-4d88-9fea-f736cb191ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212735664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1212735664
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3472798195
Short name T737
Test name
Test status
Simulation time 339518365 ps
CPU time 5.62 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:19:48 PM PDT 24
Peak memory 224976 kb
Host smart-9d07c191-1eeb-4fe5-be95-1851188211fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472798195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3472798195
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1528955567
Short name T169
Test name
Test status
Simulation time 3191286139 ps
CPU time 17.16 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:20:01 PM PDT 24
Peak memory 241436 kb
Host smart-7e81103e-9847-40b2-ae28-df834f292aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528955567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1528955567
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1860938621
Short name T908
Test name
Test status
Simulation time 677535999 ps
CPU time 3.34 seconds
Started Jul 18 05:19:40 PM PDT 24
Finished Jul 18 05:19:46 PM PDT 24
Peak memory 224884 kb
Host smart-e04b17a7-88e5-48b5-b89a-5bd546ddbf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860938621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1860938621
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.297451107
Short name T759
Test name
Test status
Simulation time 3446893800 ps
CPU time 13.29 seconds
Started Jul 18 05:19:38 PM PDT 24
Finished Jul 18 05:19:53 PM PDT 24
Peak memory 224940 kb
Host smart-5d64787b-4294-4b58-9248-7bf3453e3b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297451107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.297451107
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3394109496
Short name T493
Test name
Test status
Simulation time 178047387 ps
CPU time 1.08 seconds
Started Jul 18 05:19:39 PM PDT 24
Finished Jul 18 05:19:42 PM PDT 24
Peak memory 216880 kb
Host smart-123a76ae-cddb-4b1d-ab9c-2e3e14ee88f7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394109496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3394109496
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2131061344
Short name T919
Test name
Test status
Simulation time 1754947902 ps
CPU time 9.88 seconds
Started Jul 18 05:19:40 PM PDT 24
Finished Jul 18 05:19:53 PM PDT 24
Peak memory 241168 kb
Host smart-06613a92-4d1e-4b8b-9adc-451d18f26f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131061344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2131061344
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3154598548
Short name T336
Test name
Test status
Simulation time 95362445 ps
CPU time 2.18 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:19:46 PM PDT 24
Peak memory 224664 kb
Host smart-8027c597-dbea-47be-80eb-42acaa967ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154598548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3154598548
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1950526088
Short name T652
Test name
Test status
Simulation time 1432441253 ps
CPU time 9.83 seconds
Started Jul 18 05:19:42 PM PDT 24
Finished Jul 18 05:19:54 PM PDT 24
Peak memory 219508 kb
Host smart-ce00dc1a-aed5-449c-9baf-ba013af15635
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1950526088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1950526088
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1359389473
Short name T79
Test name
Test status
Simulation time 1104518040 ps
CPU time 1.11 seconds
Started Jul 18 05:19:40 PM PDT 24
Finished Jul 18 05:19:44 PM PDT 24
Peak memory 235748 kb
Host smart-fb864ece-1291-4438-94e4-28b88740115f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359389473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1359389473
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1800385615
Short name T509
Test name
Test status
Simulation time 203777069 ps
CPU time 1.07 seconds
Started Jul 18 05:19:42 PM PDT 24
Finished Jul 18 05:19:46 PM PDT 24
Peak memory 207364 kb
Host smart-17f9d587-088d-4882-ae29-71dfa766a7cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800385615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1800385615
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.853332988
Short name T384
Test name
Test status
Simulation time 9954480690 ps
CPU time 6.76 seconds
Started Jul 18 05:19:34 PM PDT 24
Finished Jul 18 05:19:45 PM PDT 24
Peak memory 216796 kb
Host smart-c8b54d3b-9dc5-49a2-9381-d954e24a3f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853332988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.853332988
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.432423397
Short name T484
Test name
Test status
Simulation time 2247439382 ps
CPU time 6.52 seconds
Started Jul 18 05:19:35 PM PDT 24
Finished Jul 18 05:19:45 PM PDT 24
Peak memory 216828 kb
Host smart-abed4f6c-a45e-42da-aea1-265a0943898f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432423397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.432423397
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3451636063
Short name T390
Test name
Test status
Simulation time 577283462 ps
CPU time 7.17 seconds
Started Jul 18 05:19:40 PM PDT 24
Finished Jul 18 05:19:49 PM PDT 24
Peak memory 216604 kb
Host smart-8fed135a-f673-4cce-a710-1c171df0b03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451636063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3451636063
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2372909766
Short name T775
Test name
Test status
Simulation time 158090097 ps
CPU time 1.21 seconds
Started Jul 18 05:19:32 PM PDT 24
Finished Jul 18 05:19:35 PM PDT 24
Peak memory 207248 kb
Host smart-c072e0de-f075-489d-ad85-6d90f952734b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372909766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2372909766
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2042584315
Short name T248
Test name
Test status
Simulation time 1809595279 ps
CPU time 6.63 seconds
Started Jul 18 05:19:36 PM PDT 24
Finished Jul 18 05:19:45 PM PDT 24
Peak memory 233144 kb
Host smart-c78babbc-b0a2-42f9-b33c-d2f580909b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042584315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2042584315
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1098377791
Short name T795
Test name
Test status
Simulation time 68204439 ps
CPU time 0.73 seconds
Started Jul 18 05:24:27 PM PDT 24
Finished Jul 18 05:24:30 PM PDT 24
Peak memory 205112 kb
Host smart-de9716a8-e911-42e4-9e93-6c318c2aa7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098377791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1098377791
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1657884563
Short name T172
Test name
Test status
Simulation time 43928174 ps
CPU time 2.37 seconds
Started Jul 18 05:24:30 PM PDT 24
Finished Jul 18 05:24:35 PM PDT 24
Peak memory 224884 kb
Host smart-88d01013-f45c-4925-9b6f-0d1e4bd11fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657884563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1657884563
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.594355552
Short name T911
Test name
Test status
Simulation time 25216213 ps
CPU time 0.78 seconds
Started Jul 18 05:24:29 PM PDT 24
Finished Jul 18 05:24:32 PM PDT 24
Peak memory 206176 kb
Host smart-773c477c-c018-406c-bb8b-2578f60f8754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594355552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.594355552
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2282925369
Short name T226
Test name
Test status
Simulation time 4969536612 ps
CPU time 51.94 seconds
Started Jul 18 05:24:34 PM PDT 24
Finished Jul 18 05:25:29 PM PDT 24
Peak memory 249620 kb
Host smart-d9159260-b4c7-491a-9789-cc77092d9234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282925369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2282925369
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3633437888
Short name T710
Test name
Test status
Simulation time 16197111151 ps
CPU time 24.08 seconds
Started Jul 18 05:24:31 PM PDT 24
Finished Jul 18 05:24:57 PM PDT 24
Peak memory 218280 kb
Host smart-7a8b2139-32c0-4ab0-84c2-f82f080c4b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633437888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3633437888
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1771618472
Short name T452
Test name
Test status
Simulation time 51664317 ps
CPU time 2.86 seconds
Started Jul 18 05:24:32 PM PDT 24
Finished Jul 18 05:24:38 PM PDT 24
Peak memory 224928 kb
Host smart-3e287af3-7447-4718-9b35-02b730e4a57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771618472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1771618472
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1461156320
Short name T263
Test name
Test status
Simulation time 95663403633 ps
CPU time 315.43 seconds
Started Jul 18 05:24:31 PM PDT 24
Finished Jul 18 05:29:49 PM PDT 24
Peak memory 255656 kb
Host smart-2f2df146-a26b-49d6-8a95-495603aad900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461156320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1461156320
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2768426987
Short name T723
Test name
Test status
Simulation time 588476366 ps
CPU time 2.98 seconds
Started Jul 18 05:24:27 PM PDT 24
Finished Jul 18 05:24:32 PM PDT 24
Peak memory 224856 kb
Host smart-b5bdfd99-c9fe-4c6e-aaa2-2fa25c006886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768426987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2768426987
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3924181439
Short name T375
Test name
Test status
Simulation time 53960403 ps
CPU time 2.5 seconds
Started Jul 18 05:24:33 PM PDT 24
Finished Jul 18 05:24:39 PM PDT 24
Peak memory 232884 kb
Host smart-aabd9854-98ba-455d-b163-d70336a60370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924181439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3924181439
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.298672537
Short name T2
Test name
Test status
Simulation time 8062625969 ps
CPU time 24.98 seconds
Started Jul 18 05:24:29 PM PDT 24
Finished Jul 18 05:24:56 PM PDT 24
Peak memory 233252 kb
Host smart-22466aca-2074-4a99-acc7-5cca45a28f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298672537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.298672537
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2101693948
Short name T217
Test name
Test status
Simulation time 1449126747 ps
CPU time 9.25 seconds
Started Jul 18 05:24:33 PM PDT 24
Finished Jul 18 05:24:45 PM PDT 24
Peak memory 224928 kb
Host smart-cde76b99-d539-40e1-a3a0-5085319329d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101693948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2101693948
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.833947147
Short name T706
Test name
Test status
Simulation time 377783067 ps
CPU time 3.95 seconds
Started Jul 18 05:24:27 PM PDT 24
Finished Jul 18 05:24:33 PM PDT 24
Peak memory 223844 kb
Host smart-f00eb1e8-37f6-448d-bdd5-eb6f578e3d4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=833947147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.833947147
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1500098324
Short name T848
Test name
Test status
Simulation time 182834368 ps
CPU time 1 seconds
Started Jul 18 05:24:25 PM PDT 24
Finished Jul 18 05:24:27 PM PDT 24
Peak memory 208028 kb
Host smart-f4cf1918-5d8a-491c-a190-43cb80ef3878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500098324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1500098324
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4121720458
Short name T441
Test name
Test status
Simulation time 16263418659 ps
CPU time 22.95 seconds
Started Jul 18 05:24:28 PM PDT 24
Finished Jul 18 05:24:53 PM PDT 24
Peak memory 216748 kb
Host smart-db1a27ad-4fe0-4b69-839a-82a740a1127a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121720458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4121720458
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.484679602
Short name T901
Test name
Test status
Simulation time 6776164570 ps
CPU time 18.25 seconds
Started Jul 18 05:24:31 PM PDT 24
Finished Jul 18 05:24:51 PM PDT 24
Peak memory 216796 kb
Host smart-8158b2b4-fbf9-4a17-bc72-ff04b05a6a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484679602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.484679602
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1447996904
Short name T332
Test name
Test status
Simulation time 333971158 ps
CPU time 3.49 seconds
Started Jul 18 05:24:34 PM PDT 24
Finished Jul 18 05:24:40 PM PDT 24
Peak memory 216652 kb
Host smart-75fb747b-2bf9-4431-8892-16453607249a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447996904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1447996904
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1995103156
Short name T565
Test name
Test status
Simulation time 28911244 ps
CPU time 0.82 seconds
Started Jul 18 05:24:28 PM PDT 24
Finished Jul 18 05:24:31 PM PDT 24
Peak memory 206240 kb
Host smart-f0cb8742-96f2-4812-9ee6-59eff7c10174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995103156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1995103156
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2559368566
Short name T6
Test name
Test status
Simulation time 39482579 ps
CPU time 2.69 seconds
Started Jul 18 05:24:26 PM PDT 24
Finished Jul 18 05:24:30 PM PDT 24
Peak memory 233084 kb
Host smart-28ea8a2f-794c-4e06-8fde-8b3ea9fcb812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559368566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2559368566
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.13033963
Short name T556
Test name
Test status
Simulation time 17118105 ps
CPU time 0.76 seconds
Started Jul 18 05:24:35 PM PDT 24
Finished Jul 18 05:24:38 PM PDT 24
Peak memory 206004 kb
Host smart-d1c2070f-f830-489e-8a3a-c7bcc0e17bce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13033963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.13033963
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2417042140
Short name T593
Test name
Test status
Simulation time 52605062 ps
CPU time 2.37 seconds
Started Jul 18 05:24:40 PM PDT 24
Finished Jul 18 05:24:43 PM PDT 24
Peak memory 224872 kb
Host smart-13f80739-8298-4fac-8ab7-2b1d19ccad12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417042140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2417042140
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2833075462
Short name T459
Test name
Test status
Simulation time 43759995 ps
CPU time 0.8 seconds
Started Jul 18 05:24:30 PM PDT 24
Finished Jul 18 05:24:33 PM PDT 24
Peak memory 207208 kb
Host smart-207abf43-d27e-4474-ae69-3d1d7fcdf00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833075462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2833075462
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1493920855
Short name T176
Test name
Test status
Simulation time 43402374505 ps
CPU time 66.57 seconds
Started Jul 18 05:24:34 PM PDT 24
Finished Jul 18 05:25:43 PM PDT 24
Peak memory 253116 kb
Host smart-602f7fa9-4df5-47f7-9fa2-5436784876dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493920855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1493920855
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2949709230
Short name T210
Test name
Test status
Simulation time 15428996154 ps
CPU time 127.13 seconds
Started Jul 18 05:24:35 PM PDT 24
Finished Jul 18 05:26:45 PM PDT 24
Peak memory 263992 kb
Host smart-95393bec-16fe-47b6-ad78-86f5fbdc1e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949709230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2949709230
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.631109152
Short name T236
Test name
Test status
Simulation time 109114824387 ps
CPU time 166.62 seconds
Started Jul 18 05:24:33 PM PDT 24
Finished Jul 18 05:27:23 PM PDT 24
Peak memory 257400 kb
Host smart-66a2fb72-16dd-4d01-ad53-f6a2cc3562a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631109152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.631109152
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1182116805
Short name T869
Test name
Test status
Simulation time 33602052655 ps
CPU time 126.5 seconds
Started Jul 18 05:24:28 PM PDT 24
Finished Jul 18 05:26:36 PM PDT 24
Peak memory 249652 kb
Host smart-edd3d80a-e507-4bd4-9310-58e0afd90ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182116805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1182116805
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2924039419
Short name T224
Test name
Test status
Simulation time 19075516531 ps
CPU time 17.09 seconds
Started Jul 18 05:24:32 PM PDT 24
Finished Jul 18 05:24:52 PM PDT 24
Peak memory 224972 kb
Host smart-f326f6bd-2764-4950-8ad2-28832eed20d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924039419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2924039419
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2313158658
Short name T845
Test name
Test status
Simulation time 19921148230 ps
CPU time 51.79 seconds
Started Jul 18 05:24:29 PM PDT 24
Finished Jul 18 05:25:23 PM PDT 24
Peak memory 225100 kb
Host smart-2342824b-cd0e-443e-ae3e-c9472eef6f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313158658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2313158658
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2632943302
Short name T821
Test name
Test status
Simulation time 361451520 ps
CPU time 3.06 seconds
Started Jul 18 05:24:35 PM PDT 24
Finished Jul 18 05:24:41 PM PDT 24
Peak memory 233084 kb
Host smart-5c4a60de-7fad-4f56-83a8-2afbac5b68fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632943302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2632943302
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.563616155
Short name T683
Test name
Test status
Simulation time 77172605 ps
CPU time 2.5 seconds
Started Jul 18 05:24:32 PM PDT 24
Finished Jul 18 05:24:38 PM PDT 24
Peak memory 223656 kb
Host smart-11415307-060a-4f6b-b019-017f88898889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563616155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.563616155
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2977904783
Short name T1013
Test name
Test status
Simulation time 1345471155 ps
CPU time 5.07 seconds
Started Jul 18 05:24:34 PM PDT 24
Finished Jul 18 05:24:42 PM PDT 24
Peak memory 219644 kb
Host smart-2c8860ed-5994-494f-9f8d-8b92c5c837a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2977904783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2977904783
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3040857470
Short name T740
Test name
Test status
Simulation time 3408484329 ps
CPU time 23.2 seconds
Started Jul 18 05:24:27 PM PDT 24
Finished Jul 18 05:24:52 PM PDT 24
Peak memory 216748 kb
Host smart-5881c745-7ef4-4342-bfac-f6da39bd76a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040857470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3040857470
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2023716758
Short name T345
Test name
Test status
Simulation time 2436665664 ps
CPU time 10.71 seconds
Started Jul 18 05:24:31 PM PDT 24
Finished Jul 18 05:24:44 PM PDT 24
Peak memory 216836 kb
Host smart-f039ee9a-882a-4c1f-a76d-fbefa19a11b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023716758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2023716758
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2690855935
Short name T997
Test name
Test status
Simulation time 170849247 ps
CPU time 3.31 seconds
Started Jul 18 05:24:29 PM PDT 24
Finished Jul 18 05:24:34 PM PDT 24
Peak memory 216652 kb
Host smart-ee575f96-b701-4214-a519-954a1bcab4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690855935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2690855935
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.143506504
Short name T746
Test name
Test status
Simulation time 41866441 ps
CPU time 0.94 seconds
Started Jul 18 05:24:35 PM PDT 24
Finished Jul 18 05:24:38 PM PDT 24
Peak memory 206116 kb
Host smart-5d4aa582-81da-4635-9f3f-d12c89cf5cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143506504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.143506504
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.832935526
Short name T259
Test name
Test status
Simulation time 575467434 ps
CPU time 8.38 seconds
Started Jul 18 05:24:32 PM PDT 24
Finished Jul 18 05:24:44 PM PDT 24
Peak memory 233088 kb
Host smart-380fe60c-5133-43dc-802e-7ca5465d79f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832935526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.832935526
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2301795200
Short name T966
Test name
Test status
Simulation time 16566920 ps
CPU time 0.73 seconds
Started Jul 18 05:24:37 PM PDT 24
Finished Jul 18 05:24:39 PM PDT 24
Peak memory 205720 kb
Host smart-42d88a51-9324-458d-99a1-5dd8213dec29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301795200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2301795200
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.170989922
Short name T34
Test name
Test status
Simulation time 144593241 ps
CPU time 3.45 seconds
Started Jul 18 05:24:28 PM PDT 24
Finished Jul 18 05:24:33 PM PDT 24
Peak memory 224928 kb
Host smart-6e6e7177-27bd-4c8e-a65e-9dad0bb7703f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170989922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.170989922
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3964017156
Short name T888
Test name
Test status
Simulation time 35850109 ps
CPU time 0.73 seconds
Started Jul 18 05:24:30 PM PDT 24
Finished Jul 18 05:24:33 PM PDT 24
Peak memory 206908 kb
Host smart-241ee139-8f67-40f7-98b1-9ebc275d641e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964017156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3964017156
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1618402924
Short name T296
Test name
Test status
Simulation time 14459085744 ps
CPU time 69.28 seconds
Started Jul 18 05:24:40 PM PDT 24
Finished Jul 18 05:25:50 PM PDT 24
Peak memory 257036 kb
Host smart-13c2b2f2-9224-4119-b517-2a401998d7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618402924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1618402924
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1824946837
Short name T488
Test name
Test status
Simulation time 180490834 ps
CPU time 2.53 seconds
Started Jul 18 05:24:26 PM PDT 24
Finished Jul 18 05:24:30 PM PDT 24
Peak memory 233092 kb
Host smart-edf0a410-cda6-4a57-b0c7-bf6b49776e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824946837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1824946837
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1047553511
Short name T818
Test name
Test status
Simulation time 70229668062 ps
CPU time 137.42 seconds
Started Jul 18 05:24:40 PM PDT 24
Finished Jul 18 05:26:58 PM PDT 24
Peak memory 254848 kb
Host smart-29159c26-49e0-4705-a6a6-acf971ddc5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047553511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1047553511
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1480943767
Short name T819
Test name
Test status
Simulation time 1421354840 ps
CPU time 8.34 seconds
Started Jul 18 05:24:35 PM PDT 24
Finished Jul 18 05:24:45 PM PDT 24
Peak memory 224840 kb
Host smart-bd7ef70a-da68-4717-9044-ef56c261de7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480943767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1480943767
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.947982064
Short name T275
Test name
Test status
Simulation time 147411090 ps
CPU time 2.43 seconds
Started Jul 18 05:24:40 PM PDT 24
Finished Jul 18 05:24:43 PM PDT 24
Peak memory 232908 kb
Host smart-9fdf4162-d281-4d22-92bf-fda44a739550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947982064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.947982064
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2010751175
Short name T261
Test name
Test status
Simulation time 3121879635 ps
CPU time 11.45 seconds
Started Jul 18 05:24:32 PM PDT 24
Finished Jul 18 05:24:47 PM PDT 24
Peak memory 241604 kb
Host smart-fc2852e0-fc1f-4bd7-be96-f4689b9d9064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010751175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2010751175
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.727916434
Short name T924
Test name
Test status
Simulation time 1016186255 ps
CPU time 3.97 seconds
Started Jul 18 05:24:31 PM PDT 24
Finished Jul 18 05:24:38 PM PDT 24
Peak memory 225108 kb
Host smart-85c6de74-f4e1-49b8-bee1-21f52a646799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727916434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.727916434
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.283846505
Short name T498
Test name
Test status
Simulation time 1397718978 ps
CPU time 4.16 seconds
Started Jul 18 05:24:40 PM PDT 24
Finished Jul 18 05:24:46 PM PDT 24
Peak memory 223544 kb
Host smart-029f87e4-061b-4ba4-bf40-b71d23af7526
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=283846505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.283846505
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3679770580
Short name T803
Test name
Test status
Simulation time 91821371 ps
CPU time 1.02 seconds
Started Jul 18 05:24:38 PM PDT 24
Finished Jul 18 05:24:40 PM PDT 24
Peak memory 207156 kb
Host smart-e3ca79a6-c5ce-454a-b2e6-2ad9d9955d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679770580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3679770580
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2536746279
Short name T544
Test name
Test status
Simulation time 2393487667 ps
CPU time 22.94 seconds
Started Jul 18 05:24:32 PM PDT 24
Finished Jul 18 05:24:58 PM PDT 24
Peak memory 217052 kb
Host smart-b8f54ec5-cd06-4d55-9148-cbbc55d10c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536746279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2536746279
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1756076469
Short name T548
Test name
Test status
Simulation time 1449696335 ps
CPU time 2.5 seconds
Started Jul 18 05:24:27 PM PDT 24
Finished Jul 18 05:24:30 PM PDT 24
Peak memory 216636 kb
Host smart-89f61759-2c0b-485c-afd5-7a1a46a2b8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756076469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1756076469
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4085835824
Short name T978
Test name
Test status
Simulation time 208610171 ps
CPU time 2.76 seconds
Started Jul 18 05:24:32 PM PDT 24
Finished Jul 18 05:24:37 PM PDT 24
Peak memory 216832 kb
Host smart-2adb39d2-5ad4-4e5e-9e75-e0decec6399c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085835824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4085835824
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3629078094
Short name T25
Test name
Test status
Simulation time 772434073 ps
CPU time 0.94 seconds
Started Jul 18 05:24:31 PM PDT 24
Finished Jul 18 05:24:35 PM PDT 24
Peak memory 206280 kb
Host smart-80649847-8d8f-4b11-8712-7b3a87bc7447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629078094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3629078094
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3724599368
Short name T787
Test name
Test status
Simulation time 2201845344 ps
CPU time 5.18 seconds
Started Jul 18 05:24:40 PM PDT 24
Finished Jul 18 05:24:46 PM PDT 24
Peak memory 233176 kb
Host smart-a535ada7-86e4-465d-8ba6-886452f628e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724599368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3724599368
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.252062926
Short name T377
Test name
Test status
Simulation time 20623936 ps
CPU time 0.75 seconds
Started Jul 18 05:24:44 PM PDT 24
Finished Jul 18 05:24:47 PM PDT 24
Peak memory 205176 kb
Host smart-ebc70a2d-93f9-43c3-8b34-075504561886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252062926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.252062926
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.305411577
Short name T655
Test name
Test status
Simulation time 3060149109 ps
CPU time 6.04 seconds
Started Jul 18 05:24:44 PM PDT 24
Finished Jul 18 05:24:51 PM PDT 24
Peak memory 233256 kb
Host smart-40de6abe-e49b-415c-8e4f-d07000895e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305411577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.305411577
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2728200291
Short name T732
Test name
Test status
Simulation time 19123129 ps
CPU time 0.78 seconds
Started Jul 18 05:24:37 PM PDT 24
Finished Jul 18 05:24:40 PM PDT 24
Peak memory 205868 kb
Host smart-33a0de00-ac99-41d4-a736-2052b64d483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728200291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2728200291
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.978808122
Short name T974
Test name
Test status
Simulation time 15315586114 ps
CPU time 80 seconds
Started Jul 18 05:24:50 PM PDT 24
Finished Jul 18 05:26:11 PM PDT 24
Peak memory 250512 kb
Host smart-7f9a6cb4-c3f9-42cc-b644-b441df3aec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978808122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.978808122
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.763601051
Short name T889
Test name
Test status
Simulation time 5277500175 ps
CPU time 74.59 seconds
Started Jul 18 05:24:49 PM PDT 24
Finished Jul 18 05:26:05 PM PDT 24
Peak memory 256752 kb
Host smart-180731af-d50d-48c3-886c-4bba3f1dd978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763601051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.763601051
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1029905904
Short name T218
Test name
Test status
Simulation time 61916626884 ps
CPU time 225.67 seconds
Started Jul 18 05:24:48 PM PDT 24
Finished Jul 18 05:28:36 PM PDT 24
Peak memory 268540 kb
Host smart-06016bfc-58fc-40ff-8ddd-c51f03c57537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029905904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1029905904
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.158293783
Short name T691
Test name
Test status
Simulation time 586032729 ps
CPU time 8.73 seconds
Started Jul 18 05:24:47 PM PDT 24
Finished Jul 18 05:24:58 PM PDT 24
Peak memory 224888 kb
Host smart-189846d4-f215-448d-bd60-1c3634c128e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158293783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.158293783
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.279071178
Short name T166
Test name
Test status
Simulation time 9292787326 ps
CPU time 58.25 seconds
Started Jul 18 05:24:50 PM PDT 24
Finished Jul 18 05:25:50 PM PDT 24
Peak memory 260768 kb
Host smart-ca3cd528-76c2-4334-a444-910ebb5b97c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279071178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.279071178
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2825303490
Short name T225
Test name
Test status
Simulation time 5962804036 ps
CPU time 22.86 seconds
Started Jul 18 05:24:46 PM PDT 24
Finished Jul 18 05:25:10 PM PDT 24
Peak memory 229808 kb
Host smart-5f8311dc-94b3-44c9-b8cc-fc776a7ed393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825303490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2825303490
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.256343051
Short name T274
Test name
Test status
Simulation time 64698068256 ps
CPU time 115.66 seconds
Started Jul 18 05:24:50 PM PDT 24
Finished Jul 18 05:26:48 PM PDT 24
Peak memory 233288 kb
Host smart-e78f0777-2cca-463f-8145-78fe3ef0f0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256343051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.256343051
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1675440926
Short name T661
Test name
Test status
Simulation time 2970107513 ps
CPU time 4.23 seconds
Started Jul 18 05:24:44 PM PDT 24
Finished Jul 18 05:24:50 PM PDT 24
Peak memory 224952 kb
Host smart-25a5e6b4-54f7-4432-9526-99af4765344d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675440926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1675440926
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.769037094
Short name T573
Test name
Test status
Simulation time 18674310397 ps
CPU time 8.52 seconds
Started Jul 18 05:24:53 PM PDT 24
Finished Jul 18 05:25:02 PM PDT 24
Peak memory 233268 kb
Host smart-66d34dae-9d2d-4843-8b65-8b3011da6dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769037094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.769037094
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.167495690
Short name T417
Test name
Test status
Simulation time 447802304 ps
CPU time 6.64 seconds
Started Jul 18 05:24:47 PM PDT 24
Finished Jul 18 05:24:55 PM PDT 24
Peak memory 222732 kb
Host smart-f1a07817-3c1d-4140-b829-2e7a97bf9e99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=167495690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.167495690
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1987009992
Short name T779
Test name
Test status
Simulation time 16231335899 ps
CPU time 22.9 seconds
Started Jul 18 05:24:31 PM PDT 24
Finished Jul 18 05:24:57 PM PDT 24
Peak memory 216824 kb
Host smart-d86d6c24-8b08-4ad8-9a8d-080ebdd46431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987009992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1987009992
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1701823460
Short name T808
Test name
Test status
Simulation time 2270998394 ps
CPU time 7.55 seconds
Started Jul 18 05:24:37 PM PDT 24
Finished Jul 18 05:24:46 PM PDT 24
Peak memory 216800 kb
Host smart-266fac3d-ba73-4c1a-8ab6-bdebc55e5bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701823460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1701823460
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2969017389
Short name T704
Test name
Test status
Simulation time 99679024 ps
CPU time 1.69 seconds
Started Jul 18 05:24:39 PM PDT 24
Finished Jul 18 05:24:41 PM PDT 24
Peak memory 216620 kb
Host smart-518430eb-e118-4929-b2e8-b2839ab7aa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969017389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2969017389
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3991010123
Short name T849
Test name
Test status
Simulation time 115714497 ps
CPU time 0.88 seconds
Started Jul 18 05:24:44 PM PDT 24
Finished Jul 18 05:24:46 PM PDT 24
Peak memory 207288 kb
Host smart-b68d8392-cebf-4400-991d-83ce45256db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991010123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3991010123
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3966311166
Short name T468
Test name
Test status
Simulation time 35935931337 ps
CPU time 25.97 seconds
Started Jul 18 05:24:44 PM PDT 24
Finished Jul 18 05:25:10 PM PDT 24
Peak memory 241408 kb
Host smart-6c6b244c-c216-4923-b350-2c55a89363ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966311166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3966311166
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3136363253
Short name T793
Test name
Test status
Simulation time 35270567 ps
CPU time 0.73 seconds
Started Jul 18 05:24:47 PM PDT 24
Finished Jul 18 05:24:49 PM PDT 24
Peak memory 205876 kb
Host smart-bad10bc0-c119-4514-af64-e01cbbbaa008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136363253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3136363253
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3168808562
Short name T586
Test name
Test status
Simulation time 2110538162 ps
CPU time 5.38 seconds
Started Jul 18 05:24:45 PM PDT 24
Finished Jul 18 05:24:53 PM PDT 24
Peak memory 224880 kb
Host smart-f899735c-4705-42eb-8abd-24a3d4b442cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168808562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3168808562
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.614222685
Short name T700
Test name
Test status
Simulation time 37350684 ps
CPU time 0.79 seconds
Started Jul 18 05:24:46 PM PDT 24
Finished Jul 18 05:24:48 PM PDT 24
Peak memory 206840 kb
Host smart-ca2c2434-2b99-4557-9d8a-82ebf5299ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614222685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.614222685
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1537308112
Short name T241
Test name
Test status
Simulation time 3175677727 ps
CPU time 39.45 seconds
Started Jul 18 05:24:45 PM PDT 24
Finished Jul 18 05:25:27 PM PDT 24
Peak memory 251636 kb
Host smart-bf4346e7-7dac-4e9b-bab6-67d710d9f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537308112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1537308112
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2375926980
Short name T139
Test name
Test status
Simulation time 55171849484 ps
CPU time 309.8 seconds
Started Jul 18 05:24:48 PM PDT 24
Finished Jul 18 05:30:00 PM PDT 24
Peak memory 266120 kb
Host smart-9bfda682-a687-4298-b5c0-025ae77db099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375926980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2375926980
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1758696517
Short name T523
Test name
Test status
Simulation time 45766913314 ps
CPU time 91.07 seconds
Started Jul 18 05:24:46 PM PDT 24
Finished Jul 18 05:26:19 PM PDT 24
Peak memory 252732 kb
Host smart-a6eede91-aa1e-4411-bba1-2c1c9477d8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758696517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1758696517
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1395780926
Short name T231
Test name
Test status
Simulation time 588979110 ps
CPU time 4.01 seconds
Started Jul 18 05:24:46 PM PDT 24
Finished Jul 18 05:24:52 PM PDT 24
Peak memory 233096 kb
Host smart-670f2ce2-c792-4122-9f88-bcfacddbfe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395780926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1395780926
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3750884909
Short name T177
Test name
Test status
Simulation time 23148963534 ps
CPU time 57.91 seconds
Started Jul 18 05:24:54 PM PDT 24
Finished Jul 18 05:25:52 PM PDT 24
Peak memory 237248 kb
Host smart-d4510063-275d-4372-886e-c76babdb6168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750884909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3750884909
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4150865295
Short name T288
Test name
Test status
Simulation time 6033015861 ps
CPU time 13.27 seconds
Started Jul 18 05:24:47 PM PDT 24
Finished Jul 18 05:25:02 PM PDT 24
Peak memory 233372 kb
Host smart-5c5f0a91-1eb1-432c-a95d-3b19bc261435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150865295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4150865295
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.164345259
Short name T718
Test name
Test status
Simulation time 19265907359 ps
CPU time 14.8 seconds
Started Jul 18 05:24:49 PM PDT 24
Finished Jul 18 05:25:06 PM PDT 24
Peak memory 233216 kb
Host smart-3a24b878-a710-4f07-ae88-117c81a9e92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164345259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.164345259
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4284439798
Short name T386
Test name
Test status
Simulation time 748639737 ps
CPU time 9.11 seconds
Started Jul 18 05:24:47 PM PDT 24
Finished Jul 18 05:24:59 PM PDT 24
Peak memory 222260 kb
Host smart-7790e80f-dbc8-43be-9c4b-6c141b72e932
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4284439798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4284439798
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2962122806
Short name T605
Test name
Test status
Simulation time 11130377594 ps
CPU time 65.91 seconds
Started Jul 18 05:24:47 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 249712 kb
Host smart-aac65417-8a93-431b-bad2-cf669e026823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962122806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2962122806
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2467612900
Short name T327
Test name
Test status
Simulation time 24200304814 ps
CPU time 32.91 seconds
Started Jul 18 05:24:47 PM PDT 24
Finished Jul 18 05:25:22 PM PDT 24
Peak memory 216820 kb
Host smart-825e32f2-5244-4549-95e1-f39102472b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467612900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2467612900
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1842638656
Short name T419
Test name
Test status
Simulation time 1646866323 ps
CPU time 3.3 seconds
Started Jul 18 05:24:46 PM PDT 24
Finished Jul 18 05:24:51 PM PDT 24
Peak memory 216808 kb
Host smart-ecd87a5c-36bb-49a9-a150-211371480268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842638656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1842638656
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.301609889
Short name T458
Test name
Test status
Simulation time 64677993 ps
CPU time 1.13 seconds
Started Jul 18 05:24:45 PM PDT 24
Finished Jul 18 05:24:48 PM PDT 24
Peak memory 207260 kb
Host smart-f92bf801-60ad-48f1-9131-0189847b7468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301609889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.301609889
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.950517009
Short name T965
Test name
Test status
Simulation time 12807877 ps
CPU time 0.73 seconds
Started Jul 18 05:24:45 PM PDT 24
Finished Jul 18 05:24:48 PM PDT 24
Peak memory 205896 kb
Host smart-e8e46060-5080-4ce0-b9fe-810492c6c609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950517009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.950517009
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.559099014
Short name T872
Test name
Test status
Simulation time 1129634959 ps
CPU time 6.22 seconds
Started Jul 18 05:24:48 PM PDT 24
Finished Jul 18 05:24:57 PM PDT 24
Peak memory 224912 kb
Host smart-ad87a296-ab68-493a-a97e-283e83a37ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559099014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.559099014
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3593437124
Short name T546
Test name
Test status
Simulation time 48228396 ps
CPU time 0.75 seconds
Started Jul 18 05:25:07 PM PDT 24
Finished Jul 18 05:25:09 PM PDT 24
Peak memory 206116 kb
Host smart-8fc43780-0234-4a6e-875f-4fc3762fbc4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593437124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3593437124
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3728128217
Short name T251
Test name
Test status
Simulation time 112221646 ps
CPU time 2.89 seconds
Started Jul 18 05:24:53 PM PDT 24
Finished Jul 18 05:24:57 PM PDT 24
Peak memory 233048 kb
Host smart-e09068d8-0db3-4a9b-b5ed-e2bcc6e3348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728128217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3728128217
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.4141167009
Short name T630
Test name
Test status
Simulation time 20202206 ps
CPU time 0.81 seconds
Started Jul 18 05:24:49 PM PDT 24
Finished Jul 18 05:24:52 PM PDT 24
Peak memory 206840 kb
Host smart-bb176775-6b69-409e-87db-fa3d00fdae0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141167009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4141167009
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4051165674
Short name T385
Test name
Test status
Simulation time 7407208712 ps
CPU time 33.63 seconds
Started Jul 18 05:25:10 PM PDT 24
Finished Jul 18 05:25:47 PM PDT 24
Peak memory 241396 kb
Host smart-11c07661-67ba-4227-9b7b-1c78e4767ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051165674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4051165674
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.4104586824
Short name T396
Test name
Test status
Simulation time 5302979904 ps
CPU time 14.68 seconds
Started Jul 18 05:25:11 PM PDT 24
Finished Jul 18 05:25:29 PM PDT 24
Peak memory 218024 kb
Host smart-88d06805-28b9-4e33-bd28-94641c95ecea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104586824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.4104586824
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2582853309
Short name T382
Test name
Test status
Simulation time 2034638502 ps
CPU time 46.2 seconds
Started Jul 18 05:25:09 PM PDT 24
Finished Jul 18 05:25:58 PM PDT 24
Peak memory 251112 kb
Host smart-9105b744-29b3-41fb-958c-6dc05b9bd722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582853309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2582853309
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3672752041
Short name T442
Test name
Test status
Simulation time 12324568422 ps
CPU time 42.52 seconds
Started Jul 18 05:24:50 PM PDT 24
Finished Jul 18 05:25:34 PM PDT 24
Peak memory 238552 kb
Host smart-5a1c0c25-19e9-4a5b-be00-f7a1ddd8fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672752041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3672752041
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3876212900
Short name T694
Test name
Test status
Simulation time 1797749670 ps
CPU time 7.29 seconds
Started Jul 18 05:24:49 PM PDT 24
Finished Jul 18 05:24:58 PM PDT 24
Peak memory 237244 kb
Host smart-9422c381-2cd1-4259-ad36-9b6e79783461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876212900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3876212900
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3488866288
Short name T205
Test name
Test status
Simulation time 1018329039 ps
CPU time 12.25 seconds
Started Jul 18 05:24:50 PM PDT 24
Finished Jul 18 05:25:04 PM PDT 24
Peak memory 224860 kb
Host smart-a45d172d-e71d-4db6-9e7a-dc9e67284bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488866288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3488866288
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.425559418
Short name T664
Test name
Test status
Simulation time 2159741081 ps
CPU time 6.05 seconds
Started Jul 18 05:24:48 PM PDT 24
Finished Jul 18 05:24:57 PM PDT 24
Peak memory 225008 kb
Host smart-8cbfbcbd-52f5-4342-a907-5c3d6c68af2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425559418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.425559418
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1896512192
Short name T490
Test name
Test status
Simulation time 53695489 ps
CPU time 2.77 seconds
Started Jul 18 05:24:48 PM PDT 24
Finished Jul 18 05:24:53 PM PDT 24
Peak memory 233136 kb
Host smart-0f70c7bb-7da5-428b-9bde-85e2ce2edf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896512192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1896512192
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2405433822
Short name T537
Test name
Test status
Simulation time 33668998 ps
CPU time 2.6 seconds
Started Jul 18 05:24:53 PM PDT 24
Finished Jul 18 05:24:57 PM PDT 24
Peak memory 232852 kb
Host smart-4e6cf088-8e44-44ea-ac53-c19d3a7503f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405433822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2405433822
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2666299968
Short name T407
Test name
Test status
Simulation time 280272077 ps
CPU time 5.37 seconds
Started Jul 18 05:24:53 PM PDT 24
Finished Jul 18 05:25:00 PM PDT 24
Peak memory 222092 kb
Host smart-af22c0e7-7d39-4e80-88c1-bde6fa69f97a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2666299968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2666299968
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3353109094
Short name T20
Test name
Test status
Simulation time 36388902809 ps
CPU time 123.36 seconds
Started Jul 18 05:25:07 PM PDT 24
Finished Jul 18 05:27:13 PM PDT 24
Peak memory 253580 kb
Host smart-de81121d-cd1c-43d0-a8ed-441ea2c65140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353109094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3353109094
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3460449487
Short name T707
Test name
Test status
Simulation time 1266664184 ps
CPU time 6.06 seconds
Started Jul 18 05:24:52 PM PDT 24
Finished Jul 18 05:24:59 PM PDT 24
Peak memory 216644 kb
Host smart-957ef991-d2ee-4035-80c1-b92780316b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460449487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3460449487
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2873955670
Short name T334
Test name
Test status
Simulation time 552583183 ps
CPU time 3.49 seconds
Started Jul 18 05:24:46 PM PDT 24
Finished Jul 18 05:24:51 PM PDT 24
Peak memory 216604 kb
Host smart-fc83e6dd-ef79-42fe-ab0e-c86072709de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873955670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2873955670
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2938512790
Short name T728
Test name
Test status
Simulation time 77515925 ps
CPU time 1.41 seconds
Started Jul 18 05:24:50 PM PDT 24
Finished Jul 18 05:24:53 PM PDT 24
Peak memory 216588 kb
Host smart-b63fe688-c214-4f51-a294-12e2ada17c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938512790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2938512790
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3249881845
Short name T415
Test name
Test status
Simulation time 92084007 ps
CPU time 0.77 seconds
Started Jul 18 05:24:49 PM PDT 24
Finished Jul 18 05:24:52 PM PDT 24
Peak memory 206192 kb
Host smart-5b04a658-8b7a-4852-b297-2bdd07b3b20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249881845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3249881845
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3352580111
Short name T764
Test name
Test status
Simulation time 654597266 ps
CPU time 3.1 seconds
Started Jul 18 05:24:54 PM PDT 24
Finished Jul 18 05:24:58 PM PDT 24
Peak memory 224936 kb
Host smart-6f2a8fd3-980a-4459-9755-707619645c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352580111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3352580111
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2744152871
Short name T937
Test name
Test status
Simulation time 37934315 ps
CPU time 0.77 seconds
Started Jul 18 05:25:31 PM PDT 24
Finished Jul 18 05:25:33 PM PDT 24
Peak memory 205136 kb
Host smart-601125ea-ad73-46a4-9379-9dac8143da07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744152871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2744152871
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.404656487
Short name T760
Test name
Test status
Simulation time 6886150848 ps
CPU time 18.37 seconds
Started Jul 18 05:25:07 PM PDT 24
Finished Jul 18 05:25:27 PM PDT 24
Peak memory 225096 kb
Host smart-2a22157b-99c8-4d98-b99a-3e3fcd5025af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404656487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.404656487
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.130091914
Short name T708
Test name
Test status
Simulation time 16549174 ps
CPU time 0.78 seconds
Started Jul 18 05:25:08 PM PDT 24
Finished Jul 18 05:25:11 PM PDT 24
Peak memory 206824 kb
Host smart-fa039d98-f055-41c3-9590-e9eae6eb1d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130091914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.130091914
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1442449978
Short name T791
Test name
Test status
Simulation time 6857836958 ps
CPU time 47.75 seconds
Started Jul 18 05:25:06 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 225092 kb
Host smart-77d6630e-9d1d-4343-a578-c8f410dcf7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442449978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1442449978
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3357684547
Short name T27
Test name
Test status
Simulation time 4147423657 ps
CPU time 23.67 seconds
Started Jul 18 05:25:09 PM PDT 24
Finished Jul 18 05:25:36 PM PDT 24
Peak memory 225120 kb
Host smart-cb571922-0a55-44d6-9fd4-8b54df786264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357684547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3357684547
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2393107032
Short name T297
Test name
Test status
Simulation time 9144966368 ps
CPU time 151.92 seconds
Started Jul 18 05:25:07 PM PDT 24
Finished Jul 18 05:27:41 PM PDT 24
Peak memory 268744 kb
Host smart-de0fe264-5121-4029-b907-2258e22cc3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393107032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2393107032
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.14329957
Short name T596
Test name
Test status
Simulation time 520439192 ps
CPU time 3.78 seconds
Started Jul 18 05:25:08 PM PDT 24
Finished Jul 18 05:25:15 PM PDT 24
Peak memory 224836 kb
Host smart-e76cb82e-f4a3-473d-bdbc-2100ac193642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14329957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.14329957
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1913243734
Short name T1019
Test name
Test status
Simulation time 101371036982 ps
CPU time 163.92 seconds
Started Jul 18 05:25:10 PM PDT 24
Finished Jul 18 05:27:58 PM PDT 24
Peak memory 249584 kb
Host smart-6467f598-32be-4f1f-897e-cbdec45cb40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913243734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1913243734
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2492772127
Short name T788
Test name
Test status
Simulation time 102892383 ps
CPU time 3.02 seconds
Started Jul 18 05:25:14 PM PDT 24
Finished Jul 18 05:25:20 PM PDT 24
Peak memory 233120 kb
Host smart-09ab0247-b205-44eb-99c1-07e750d638c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492772127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2492772127
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1537167378
Short name T271
Test name
Test status
Simulation time 18708338869 ps
CPU time 82.29 seconds
Started Jul 18 05:25:08 PM PDT 24
Finished Jul 18 05:26:32 PM PDT 24
Peak memory 240556 kb
Host smart-637adac4-52cf-472e-8da6-0920c3998a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537167378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1537167378
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1925563294
Short name T308
Test name
Test status
Simulation time 2673075666 ps
CPU time 5.12 seconds
Started Jul 18 05:25:08 PM PDT 24
Finished Jul 18 05:25:16 PM PDT 24
Peak memory 233216 kb
Host smart-e5fd98ed-2c78-4a29-b7ee-9eeaad2242e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925563294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1925563294
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.593588396
Short name T871
Test name
Test status
Simulation time 285464830 ps
CPU time 2.24 seconds
Started Jul 18 05:25:08 PM PDT 24
Finished Jul 18 05:25:13 PM PDT 24
Peak memory 223380 kb
Host smart-2c874e42-470c-48a8-9ca4-78dea852c945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593588396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.593588396
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2072371489
Short name T711
Test name
Test status
Simulation time 525964280 ps
CPU time 4.24 seconds
Started Jul 18 05:25:09 PM PDT 24
Finished Jul 18 05:25:16 PM PDT 24
Peak memory 223596 kb
Host smart-7760a090-db6d-4348-b951-03cdf0c7eb5e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2072371489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2072371489
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3966561577
Short name T476
Test name
Test status
Simulation time 1904552089 ps
CPU time 25.41 seconds
Started Jul 18 05:25:09 PM PDT 24
Finished Jul 18 05:25:37 PM PDT 24
Peak memory 216656 kb
Host smart-ca2b8da2-24f9-46ab-a3d5-3a634003bb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966561577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3966561577
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1631482292
Short name T84
Test name
Test status
Simulation time 3783993256 ps
CPU time 5.78 seconds
Started Jul 18 05:25:11 PM PDT 24
Finished Jul 18 05:25:20 PM PDT 24
Peak memory 216704 kb
Host smart-d991efdd-8c21-479d-b29f-eee07a34335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631482292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1631482292
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2833709935
Short name T632
Test name
Test status
Simulation time 15651784 ps
CPU time 0.84 seconds
Started Jul 18 05:25:05 PM PDT 24
Finished Jul 18 05:25:07 PM PDT 24
Peak memory 206460 kb
Host smart-19933fa1-9887-4dd2-b6e0-43ec489397e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833709935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2833709935
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3763149560
Short name T411
Test name
Test status
Simulation time 46255448 ps
CPU time 0.87 seconds
Started Jul 18 05:25:06 PM PDT 24
Finished Jul 18 05:25:07 PM PDT 24
Peak memory 206260 kb
Host smart-a29ea0a1-f4ae-4ad9-a688-68f27ac5c012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763149560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3763149560
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1609876007
Short name T903
Test name
Test status
Simulation time 551775909 ps
CPU time 6.69 seconds
Started Jul 18 05:25:10 PM PDT 24
Finished Jul 18 05:25:20 PM PDT 24
Peak memory 241264 kb
Host smart-7d7833b8-f82c-46fc-b5ee-8dde60b0bbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609876007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1609876007
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1312662831
Short name T540
Test name
Test status
Simulation time 48166437 ps
CPU time 0.72 seconds
Started Jul 18 05:25:10 PM PDT 24
Finished Jul 18 05:25:14 PM PDT 24
Peak memory 206044 kb
Host smart-833b6a24-7492-4902-abfa-153e5e9386af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312662831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1312662831
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1075861241
Short name T623
Test name
Test status
Simulation time 796066559 ps
CPU time 6.32 seconds
Started Jul 18 05:25:13 PM PDT 24
Finished Jul 18 05:25:22 PM PDT 24
Peak memory 232896 kb
Host smart-d1b43d4d-071f-4b58-8c9d-108a83fd42fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075861241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1075861241
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.868931943
Short name T567
Test name
Test status
Simulation time 204088123 ps
CPU time 0.78 seconds
Started Jul 18 05:25:13 PM PDT 24
Finished Jul 18 05:25:17 PM PDT 24
Peak memory 206884 kb
Host smart-d17f7669-b384-461d-aef4-7686ff39fd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868931943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.868931943
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3530831407
Short name T451
Test name
Test status
Simulation time 7832147464 ps
CPU time 16.36 seconds
Started Jul 18 05:25:06 PM PDT 24
Finished Jul 18 05:25:24 PM PDT 24
Peak memory 235580 kb
Host smart-4e9214e4-a74a-4cc3-9c99-dfe338811e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530831407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3530831407
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1382258952
Short name T601
Test name
Test status
Simulation time 1375167465 ps
CPU time 9.09 seconds
Started Jul 18 05:25:08 PM PDT 24
Finished Jul 18 05:25:19 PM PDT 24
Peak memory 233120 kb
Host smart-5cb70b0f-b2c0-45ad-b298-9adccb40e2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382258952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1382258952
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3787893589
Short name T137
Test name
Test status
Simulation time 45777218457 ps
CPU time 381.05 seconds
Started Jul 18 05:25:20 PM PDT 24
Finished Jul 18 05:31:42 PM PDT 24
Peak memory 257840 kb
Host smart-39136642-39bd-4435-b851-3756750aabfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787893589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3787893589
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.346006774
Short name T907
Test name
Test status
Simulation time 141978830 ps
CPU time 4.68 seconds
Started Jul 18 05:25:09 PM PDT 24
Finished Jul 18 05:25:17 PM PDT 24
Peak memory 224912 kb
Host smart-d7c13368-3551-4f1c-b65b-b5f674397836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346006774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.346006774
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1234839497
Short name T301
Test name
Test status
Simulation time 34543589436 ps
CPU time 109.92 seconds
Started Jul 18 05:25:10 PM PDT 24
Finished Jul 18 05:27:04 PM PDT 24
Peak memory 249540 kb
Host smart-d446830d-8872-4481-9235-41bd3720e0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234839497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1234839497
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.507082193
Short name T765
Test name
Test status
Simulation time 6859850679 ps
CPU time 19.25 seconds
Started Jul 18 05:25:16 PM PDT 24
Finished Jul 18 05:25:37 PM PDT 24
Peak memory 225000 kb
Host smart-f914ef2a-caab-4e26-bce7-c72bb406651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507082193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.507082193
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.348004119
Short name T216
Test name
Test status
Simulation time 5966025931 ps
CPU time 38.57 seconds
Started Jul 18 05:25:13 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 233204 kb
Host smart-2c2b49f7-f29e-4a58-9b94-f5c00ae4fd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348004119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.348004119
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4073651458
Short name T380
Test name
Test status
Simulation time 2118762905 ps
CPU time 9.57 seconds
Started Jul 18 05:25:12 PM PDT 24
Finished Jul 18 05:25:25 PM PDT 24
Peak memory 224832 kb
Host smart-bc1c6664-576c-4124-a394-8c8a898376ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073651458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4073651458
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.677875454
Short name T276
Test name
Test status
Simulation time 7362697372 ps
CPU time 13.47 seconds
Started Jul 18 05:25:07 PM PDT 24
Finished Jul 18 05:25:22 PM PDT 24
Peak memory 241416 kb
Host smart-15265760-00fd-4aa9-955f-97103294324f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677875454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.677875454
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2551593803
Short name T43
Test name
Test status
Simulation time 1893827958 ps
CPU time 20.16 seconds
Started Jul 18 05:25:10 PM PDT 24
Finished Jul 18 05:25:33 PM PDT 24
Peak memory 219212 kb
Host smart-d4921c91-f50e-42b6-8fa2-b122e73f0fe7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2551593803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2551593803
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.988584602
Short name T785
Test name
Test status
Simulation time 31790342 ps
CPU time 0.92 seconds
Started Jul 18 05:25:07 PM PDT 24
Finished Jul 18 05:25:09 PM PDT 24
Peak memory 207188 kb
Host smart-db5c65a5-baae-4ded-83b3-b84deca3a28e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988584602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.988584602
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3399205050
Short name T753
Test name
Test status
Simulation time 17432397267 ps
CPU time 22.58 seconds
Started Jul 18 05:25:13 PM PDT 24
Finished Jul 18 05:25:39 PM PDT 24
Peak memory 216992 kb
Host smart-4b80320d-4e94-47fc-bd90-699c9f8b1b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399205050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3399205050
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1698070162
Short name T603
Test name
Test status
Simulation time 1355749504 ps
CPU time 2.02 seconds
Started Jul 18 05:25:07 PM PDT 24
Finished Jul 18 05:25:11 PM PDT 24
Peak memory 216416 kb
Host smart-9e111ce8-256a-4f92-af39-eff082c6c7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698070162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1698070162
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.655675096
Short name T719
Test name
Test status
Simulation time 331135034 ps
CPU time 1.06 seconds
Started Jul 18 05:25:11 PM PDT 24
Finished Jul 18 05:25:15 PM PDT 24
Peak memory 207196 kb
Host smart-6fbaec83-a0df-4ed3-bc08-3058d59f861c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655675096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.655675096
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1058610028
Short name T346
Test name
Test status
Simulation time 84736461 ps
CPU time 0.81 seconds
Started Jul 18 05:25:08 PM PDT 24
Finished Jul 18 05:25:11 PM PDT 24
Peak memory 206244 kb
Host smart-5f2b4ff7-46b0-48c5-851d-e3283ea250ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058610028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1058610028
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1770170479
Short name T228
Test name
Test status
Simulation time 436553603 ps
CPU time 4.06 seconds
Started Jul 18 05:25:08 PM PDT 24
Finished Jul 18 05:25:15 PM PDT 24
Peak memory 224848 kb
Host smart-af30506d-a67f-40df-95e4-6d918886e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770170479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1770170479
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3793785927
Short name T951
Test name
Test status
Simulation time 85965035 ps
CPU time 0.74 seconds
Started Jul 18 05:25:10 PM PDT 24
Finished Jul 18 05:25:14 PM PDT 24
Peak memory 206036 kb
Host smart-f1a83d7e-eae4-4509-8ddc-5fcf3d5afd80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793785927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3793785927
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2396384791
Short name T517
Test name
Test status
Simulation time 297124645 ps
CPU time 3.14 seconds
Started Jul 18 05:25:14 PM PDT 24
Finished Jul 18 05:25:20 PM PDT 24
Peak memory 224936 kb
Host smart-3139efca-9e9e-469c-873f-34982b7bba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396384791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2396384791
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.942769913
Short name T500
Test name
Test status
Simulation time 16952473 ps
CPU time 0.79 seconds
Started Jul 18 05:25:12 PM PDT 24
Finished Jul 18 05:25:16 PM PDT 24
Peak memory 206864 kb
Host smart-9bfafa27-e912-4b91-917c-4ba76c5436e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942769913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.942769913
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1189921253
Short name T1001
Test name
Test status
Simulation time 15972800677 ps
CPU time 49.88 seconds
Started Jul 18 05:25:07 PM PDT 24
Finished Jul 18 05:25:58 PM PDT 24
Peak memory 249724 kb
Host smart-bf7b8464-e983-4912-b033-c0fb4109ded7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189921253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1189921253
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.72587644
Short name T518
Test name
Test status
Simulation time 3937215736 ps
CPU time 45.52 seconds
Started Jul 18 05:25:12 PM PDT 24
Finished Jul 18 05:26:01 PM PDT 24
Peak memory 237804 kb
Host smart-b1f33830-2b62-4890-9755-a586b1af09f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72587644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.72587644
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.369314315
Short name T330
Test name
Test status
Simulation time 10244720080 ps
CPU time 81.99 seconds
Started Jul 18 05:25:08 PM PDT 24
Finished Jul 18 05:26:33 PM PDT 24
Peak memory 225076 kb
Host smart-2a24664a-6f2b-4daa-bcda-d514042e7394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369314315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.369314315
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4280775500
Short name T542
Test name
Test status
Simulation time 951679109 ps
CPU time 7.55 seconds
Started Jul 18 05:25:15 PM PDT 24
Finished Jul 18 05:25:25 PM PDT 24
Peak memory 233096 kb
Host smart-5c4ae041-3791-4407-b3f1-389e5870eeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280775500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4280775500
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.948104241
Short name T102
Test name
Test status
Simulation time 2474550148 ps
CPU time 11.1 seconds
Started Jul 18 05:25:08 PM PDT 24
Finished Jul 18 05:25:21 PM PDT 24
Peak memory 238320 kb
Host smart-32a903fd-81df-42ee-983c-9597e1989e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948104241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.948104241
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3894642787
Short name T429
Test name
Test status
Simulation time 1472006546 ps
CPU time 5.41 seconds
Started Jul 18 05:25:15 PM PDT 24
Finished Jul 18 05:25:23 PM PDT 24
Peak memory 224908 kb
Host smart-ae10ec04-7309-4553-a85f-57c49b6748e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894642787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3894642787
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2162254453
Short name T780
Test name
Test status
Simulation time 786371853 ps
CPU time 16.16 seconds
Started Jul 18 05:25:14 PM PDT 24
Finished Jul 18 05:25:33 PM PDT 24
Peak memory 249420 kb
Host smart-b67455f7-3796-46d5-8026-3454dee9c953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162254453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2162254453
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4194546863
Short name T1004
Test name
Test status
Simulation time 2186682997 ps
CPU time 8.5 seconds
Started Jul 18 05:25:14 PM PDT 24
Finished Jul 18 05:25:25 PM PDT 24
Peak memory 233224 kb
Host smart-8d03166e-999d-46dc-8ce1-1f0f05eeaa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194546863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.4194546863
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1956779471
Short name T435
Test name
Test status
Simulation time 5375499454 ps
CPU time 11.86 seconds
Started Jul 18 05:25:11 PM PDT 24
Finished Jul 18 05:25:27 PM PDT 24
Peak memory 233136 kb
Host smart-6307ca1f-ba5b-403f-9ac0-b96b4d3932c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956779471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1956779471
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2708207968
Short name T847
Test name
Test status
Simulation time 332204558 ps
CPU time 5.61 seconds
Started Jul 18 05:25:11 PM PDT 24
Finished Jul 18 05:25:19 PM PDT 24
Peak memory 220884 kb
Host smart-3e651d47-2928-43ba-9b78-a362f3c2dbf8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2708207968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2708207968
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.483920576
Short name T511
Test name
Test status
Simulation time 300326313 ps
CPU time 0.94 seconds
Started Jul 18 05:25:11 PM PDT 24
Finished Jul 18 05:25:16 PM PDT 24
Peak memory 206972 kb
Host smart-63cfb7e1-7029-4fdc-bb35-985736737ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483920576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.483920576
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4268134042
Short name T94
Test name
Test status
Simulation time 5131844928 ps
CPU time 26.6 seconds
Started Jul 18 05:25:13 PM PDT 24
Finished Jul 18 05:25:43 PM PDT 24
Peak memory 216848 kb
Host smart-d4aeb9b4-3a81-4550-b904-488b2219511a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268134042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4268134042
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2205030130
Short name T946
Test name
Test status
Simulation time 223235477 ps
CPU time 1.54 seconds
Started Jul 18 05:25:14 PM PDT 24
Finished Jul 18 05:25:18 PM PDT 24
Peak memory 208192 kb
Host smart-27be9f26-2bde-461c-b41b-261300df4750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205030130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2205030130
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1550103299
Short name T616
Test name
Test status
Simulation time 190633779 ps
CPU time 8.46 seconds
Started Jul 18 05:25:07 PM PDT 24
Finished Jul 18 05:25:17 PM PDT 24
Peak memory 216580 kb
Host smart-d8b39edf-81af-4447-8d76-338a1e0ca385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550103299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1550103299
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1629816429
Short name T538
Test name
Test status
Simulation time 212370725 ps
CPU time 0.85 seconds
Started Jul 18 05:25:08 PM PDT 24
Finished Jul 18 05:25:11 PM PDT 24
Peak memory 206220 kb
Host smart-cacbfc4e-5cf1-41cb-86fc-c8cc033c5aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629816429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1629816429
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3430340837
Short name T250
Test name
Test status
Simulation time 381977413 ps
CPU time 5.35 seconds
Started Jul 18 05:25:09 PM PDT 24
Finished Jul 18 05:25:17 PM PDT 24
Peak memory 239112 kb
Host smart-5ba3b0fc-7556-450c-bc9d-f9c251744dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430340837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3430340837
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1046211189
Short name T842
Test name
Test status
Simulation time 17147873 ps
CPU time 0.7 seconds
Started Jul 18 05:25:09 PM PDT 24
Finished Jul 18 05:25:13 PM PDT 24
Peak memory 205044 kb
Host smart-0c8501c9-e697-4fe5-be52-001bb1d4f894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046211189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1046211189
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.109757009
Short name T283
Test name
Test status
Simulation time 1238536880 ps
CPU time 10.58 seconds
Started Jul 18 05:25:09 PM PDT 24
Finished Jul 18 05:25:22 PM PDT 24
Peak memory 233088 kb
Host smart-6847d160-4ef4-4ca5-87a6-9ca5c9c19a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109757009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.109757009
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2317868038
Short name T843
Test name
Test status
Simulation time 22290632 ps
CPU time 0.79 seconds
Started Jul 18 05:25:20 PM PDT 24
Finished Jul 18 05:25:22 PM PDT 24
Peak memory 207148 kb
Host smart-ddc6515e-a5b1-4754-bee6-688a10375c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317868038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2317868038
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2407506376
Short name T40
Test name
Test status
Simulation time 23979488640 ps
CPU time 166.79 seconds
Started Jul 18 05:25:15 PM PDT 24
Finished Jul 18 05:28:04 PM PDT 24
Peak memory 253940 kb
Host smart-9d3f322a-8b34-4447-9c29-7eb9caee3184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407506376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2407506376
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.161734608
Short name T408
Test name
Test status
Simulation time 27848841892 ps
CPU time 260.88 seconds
Started Jul 18 05:25:20 PM PDT 24
Finished Jul 18 05:29:42 PM PDT 24
Peak memory 249652 kb
Host smart-df795f4a-24f7-4e53-9dba-a42cdc4f5561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161734608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.161734608
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1750920657
Short name T864
Test name
Test status
Simulation time 453659133 ps
CPU time 10.55 seconds
Started Jul 18 05:25:12 PM PDT 24
Finished Jul 18 05:25:26 PM PDT 24
Peak memory 241364 kb
Host smart-e3900c75-28c4-4d7d-8748-a182445bdbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750920657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1750920657
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1299044129
Short name T947
Test name
Test status
Simulation time 134290526564 ps
CPU time 225.86 seconds
Started Jul 18 05:25:12 PM PDT 24
Finished Jul 18 05:29:01 PM PDT 24
Peak memory 256464 kb
Host smart-6648748d-f959-42ed-8110-59420416bde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299044129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1299044129
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.193830103
Short name T722
Test name
Test status
Simulation time 868046637 ps
CPU time 7.38 seconds
Started Jul 18 05:25:19 PM PDT 24
Finished Jul 18 05:25:27 PM PDT 24
Peak memory 233076 kb
Host smart-4ce05852-4a6c-4198-aae3-3403c7f65234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193830103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.193830103
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4273895502
Short name T725
Test name
Test status
Simulation time 240800818 ps
CPU time 3.98 seconds
Started Jul 18 05:25:12 PM PDT 24
Finished Jul 18 05:25:19 PM PDT 24
Peak memory 224880 kb
Host smart-840792e4-1fb7-4bf3-9521-106d90ecfbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273895502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4273895502
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3873102125
Short name T475
Test name
Test status
Simulation time 18727812283 ps
CPU time 16.43 seconds
Started Jul 18 05:25:15 PM PDT 24
Finished Jul 18 05:25:34 PM PDT 24
Peak memory 241044 kb
Host smart-ff889d16-46a5-42e7-9ac3-0c7649b2101a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873102125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3873102125
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2535851744
Short name T637
Test name
Test status
Simulation time 123564971 ps
CPU time 2.36 seconds
Started Jul 18 05:25:13 PM PDT 24
Finished Jul 18 05:25:18 PM PDT 24
Peak memory 232892 kb
Host smart-16a312a2-669f-472d-bd22-e1949aad1b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535851744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2535851744
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1629464883
Short name T721
Test name
Test status
Simulation time 474259293 ps
CPU time 7.46 seconds
Started Jul 18 05:25:12 PM PDT 24
Finished Jul 18 05:25:23 PM PDT 24
Peak memory 222720 kb
Host smart-9b465e14-e424-4fad-9801-8397d59d2e79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1629464883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1629464883
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1215222802
Short name T865
Test name
Test status
Simulation time 27011516042 ps
CPU time 130.98 seconds
Started Jul 18 05:25:16 PM PDT 24
Finished Jul 18 05:27:29 PM PDT 24
Peak memory 249708 kb
Host smart-c939cc52-9352-4b3a-ab54-b5455628a3cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215222802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1215222802
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2577861773
Short name T522
Test name
Test status
Simulation time 1663970438 ps
CPU time 25.35 seconds
Started Jul 18 05:25:09 PM PDT 24
Finished Jul 18 05:25:38 PM PDT 24
Peak memory 221780 kb
Host smart-a1587e92-6850-4faa-861d-f4cbfa1926d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577861773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2577861773
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1355932263
Short name T837
Test name
Test status
Simulation time 1243475940 ps
CPU time 5.47 seconds
Started Jul 18 05:25:13 PM PDT 24
Finished Jul 18 05:25:22 PM PDT 24
Peak memory 216676 kb
Host smart-d2417634-7935-4bf6-88ea-f377c234c517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355932263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1355932263
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.151047885
Short name T425
Test name
Test status
Simulation time 365801153 ps
CPU time 1.54 seconds
Started Jul 18 05:25:12 PM PDT 24
Finished Jul 18 05:25:17 PM PDT 24
Peak memory 216512 kb
Host smart-4dc30edb-19ff-4991-9281-a30761837943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151047885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.151047885
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.392928970
Short name T641
Test name
Test status
Simulation time 12329453 ps
CPU time 0.7 seconds
Started Jul 18 05:25:11 PM PDT 24
Finished Jul 18 05:25:15 PM PDT 24
Peak memory 206256 kb
Host smart-03012217-4a54-4236-8f79-e59f3ec47d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392928970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.392928970
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.519660338
Short name T647
Test name
Test status
Simulation time 5384251181 ps
CPU time 12.65 seconds
Started Jul 18 05:25:20 PM PDT 24
Finished Jul 18 05:25:33 PM PDT 24
Peak memory 241340 kb
Host smart-c8ea667b-a3b0-42e9-b861-6d7125123b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519660338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.519660338
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2550664519
Short name T678
Test name
Test status
Simulation time 11718273 ps
CPU time 0.72 seconds
Started Jul 18 05:20:06 PM PDT 24
Finished Jul 18 05:20:09 PM PDT 24
Peak memory 205720 kb
Host smart-b3e2e04b-ab2d-44e9-bec4-3d3f8f2bdeb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550664519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
550664519
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.274016944
Short name T881
Test name
Test status
Simulation time 140479796 ps
CPU time 2.63 seconds
Started Jul 18 05:19:42 PM PDT 24
Finished Jul 18 05:19:48 PM PDT 24
Peak memory 233092 kb
Host smart-0b685a03-4846-4a1f-b278-18f759e39865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274016944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.274016944
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3846778864
Short name T412
Test name
Test status
Simulation time 22919872 ps
CPU time 0.81 seconds
Started Jul 18 05:19:40 PM PDT 24
Finished Jul 18 05:19:43 PM PDT 24
Peak memory 206160 kb
Host smart-eac933b5-e8c3-44ef-93d1-2a33b59e9b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846778864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3846778864
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1831432733
Short name T757
Test name
Test status
Simulation time 13606669472 ps
CPU time 35.84 seconds
Started Jul 18 05:20:07 PM PDT 24
Finished Jul 18 05:20:45 PM PDT 24
Peak memory 225040 kb
Host smart-ac74ec60-8c87-4bf9-b0db-bb8668badc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831432733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1831432733
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.4229863052
Short name T831
Test name
Test status
Simulation time 44978187484 ps
CPU time 263.27 seconds
Started Jul 18 05:20:08 PM PDT 24
Finished Jul 18 05:24:33 PM PDT 24
Peak memory 261944 kb
Host smart-ee26b8ba-324b-4d4a-8735-836cc802ef98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229863052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4229863052
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.539960136
Short name T67
Test name
Test status
Simulation time 29447626733 ps
CPU time 143.61 seconds
Started Jul 18 05:20:08 PM PDT 24
Finished Jul 18 05:22:33 PM PDT 24
Peak memory 249952 kb
Host smart-e2dfb0c8-e272-41ea-aba4-9039eacd172e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539960136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
539960136
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.779917471
Short name T423
Test name
Test status
Simulation time 6855496792 ps
CPU time 20.63 seconds
Started Jul 18 05:19:43 PM PDT 24
Finished Jul 18 05:20:06 PM PDT 24
Peak memory 233204 kb
Host smart-b1c2f5f5-71d7-4d0b-9a29-63f17321ee84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779917471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.779917471
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2632772425
Short name T421
Test name
Test status
Simulation time 2001723668 ps
CPU time 5.96 seconds
Started Jul 18 05:19:43 PM PDT 24
Finished Jul 18 05:19:52 PM PDT 24
Peak memory 233744 kb
Host smart-3bf4f40b-2cd9-4137-80d3-2cb0db0bebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632772425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2632772425
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2843723343
Short name T100
Test name
Test status
Simulation time 174586422 ps
CPU time 5.61 seconds
Started Jul 18 05:19:41 PM PDT 24
Finished Jul 18 05:19:49 PM PDT 24
Peak memory 224928 kb
Host smart-d73b084b-6ade-43cc-a96f-06797013ec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843723343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2843723343
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3850664174
Short name T202
Test name
Test status
Simulation time 3989858587 ps
CPU time 16.71 seconds
Started Jul 18 05:19:43 PM PDT 24
Finished Jul 18 05:20:03 PM PDT 24
Peak memory 249156 kb
Host smart-1573df56-dc09-4496-a002-c6225294e78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850664174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3850664174
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3967618737
Short name T794
Test name
Test status
Simulation time 132294068 ps
CPU time 1.15 seconds
Started Jul 18 05:19:40 PM PDT 24
Finished Jul 18 05:19:44 PM PDT 24
Peak memory 218388 kb
Host smart-b96bcdea-95d3-4697-b25a-e00f1a007592
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967618737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3967618737
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3885593874
Short name T830
Test name
Test status
Simulation time 9735636669 ps
CPU time 18.26 seconds
Started Jul 18 05:19:43 PM PDT 24
Finished Jul 18 05:20:05 PM PDT 24
Peak memory 224956 kb
Host smart-414eb2e8-5aaf-46e8-aa35-b240ee0bf593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885593874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3885593874
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2030866246
Short name T939
Test name
Test status
Simulation time 2163634254 ps
CPU time 4.48 seconds
Started Jul 18 05:19:45 PM PDT 24
Finished Jul 18 05:19:52 PM PDT 24
Peak memory 225012 kb
Host smart-c2e64034-233b-4463-84d7-8889e77b9ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030866246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2030866246
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1396678095
Short name T142
Test name
Test status
Simulation time 938911434 ps
CPU time 12.44 seconds
Started Jul 18 05:20:13 PM PDT 24
Finished Jul 18 05:20:26 PM PDT 24
Peak memory 221092 kb
Host smart-cc2cc675-898f-4a5a-9943-5e4b8da4b050
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1396678095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1396678095
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.690296153
Short name T75
Test name
Test status
Simulation time 231719675 ps
CPU time 1.04 seconds
Started Jul 18 05:20:08 PM PDT 24
Finished Jul 18 05:20:11 PM PDT 24
Peak memory 235796 kb
Host smart-efb53c00-04c0-4064-a219-88a2135ad85c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690296153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.690296153
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2193604026
Short name T191
Test name
Test status
Simulation time 90913008937 ps
CPU time 83.87 seconds
Started Jul 18 05:20:05 PM PDT 24
Finished Jul 18 05:21:31 PM PDT 24
Peak memory 249768 kb
Host smart-d8c6a12e-5029-4626-9200-1cbba7748687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193604026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2193604026
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.951145743
Short name T934
Test name
Test status
Simulation time 1454125300 ps
CPU time 2.73 seconds
Started Jul 18 05:19:39 PM PDT 24
Finished Jul 18 05:19:43 PM PDT 24
Peak memory 216676 kb
Host smart-8d2558c9-1d41-4ca7-8d28-4e85160c917e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951145743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.951145743
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.329837244
Short name T1022
Test name
Test status
Simulation time 11953569612 ps
CPU time 10.86 seconds
Started Jul 18 05:19:45 PM PDT 24
Finished Jul 18 05:19:58 PM PDT 24
Peak memory 216684 kb
Host smart-12c84b43-e56a-4f55-823b-1e34b0042ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329837244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.329837244
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.587178132
Short name T560
Test name
Test status
Simulation time 69685684 ps
CPU time 1.05 seconds
Started Jul 18 05:19:39 PM PDT 24
Finished Jul 18 05:19:41 PM PDT 24
Peak memory 208276 kb
Host smart-d9282be6-31aa-4c5a-a210-31c2a2f31f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587178132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.587178132
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1196322001
Short name T58
Test name
Test status
Simulation time 103967541 ps
CPU time 0.83 seconds
Started Jul 18 05:19:43 PM PDT 24
Finished Jul 18 05:19:47 PM PDT 24
Peak memory 206216 kb
Host smart-a80a4873-47fd-403a-9663-05e17b1179a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196322001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1196322001
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1946785368
Short name T561
Test name
Test status
Simulation time 74925662429 ps
CPU time 30.25 seconds
Started Jul 18 05:19:43 PM PDT 24
Finished Jul 18 05:20:17 PM PDT 24
Peak memory 233196 kb
Host smart-fd55063a-ac56-4565-b21a-5d4937b8ca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946785368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1946785368
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3474007408
Short name T689
Test name
Test status
Simulation time 14425607 ps
CPU time 0.73 seconds
Started Jul 18 05:25:29 PM PDT 24
Finished Jul 18 05:25:31 PM PDT 24
Peak memory 205116 kb
Host smart-a17ff5f9-3b1c-40b8-a51e-36304ff082a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474007408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3474007408
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3847698947
Short name T245
Test name
Test status
Simulation time 39365718 ps
CPU time 2.67 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:25 PM PDT 24
Peak memory 233068 kb
Host smart-60b709a9-8c1e-4b5e-8ed9-38e2a8914371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847698947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3847698947
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3337503519
Short name T387
Test name
Test status
Simulation time 62892469 ps
CPU time 0.79 seconds
Started Jul 18 05:25:15 PM PDT 24
Finished Jul 18 05:25:18 PM PDT 24
Peak memory 206856 kb
Host smart-b6f1de23-4c69-4a23-beca-181ac37d644f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337503519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3337503519
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2430912524
Short name T295
Test name
Test status
Simulation time 50328401504 ps
CPU time 177.82 seconds
Started Jul 18 05:25:23 PM PDT 24
Finished Jul 18 05:28:24 PM PDT 24
Peak memory 267644 kb
Host smart-6b59e13e-4b6f-48ee-b027-8b730f8fd116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430912524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2430912524
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1491511719
Short name T673
Test name
Test status
Simulation time 1396968098 ps
CPU time 17.83 seconds
Started Jul 18 05:25:31 PM PDT 24
Finished Jul 18 05:25:50 PM PDT 24
Peak memory 217948 kb
Host smart-b682cb50-118d-434b-bfbf-f702016514b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491511719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1491511719
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.58445938
Short name T588
Test name
Test status
Simulation time 586364359 ps
CPU time 6.42 seconds
Started Jul 18 05:25:23 PM PDT 24
Finished Jul 18 05:25:33 PM PDT 24
Peak memory 233140 kb
Host smart-9d5692e0-bd83-4d9c-8cd9-2c994b398dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58445938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.58445938
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1939414825
Short name T643
Test name
Test status
Simulation time 135866423 ps
CPU time 0.75 seconds
Started Jul 18 05:25:22 PM PDT 24
Finished Jul 18 05:25:26 PM PDT 24
Peak memory 216260 kb
Host smart-e24bb5b9-3233-481a-8c96-7e2b7f8032d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939414825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1939414825
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2224603282
Short name T778
Test name
Test status
Simulation time 282390837 ps
CPU time 4.2 seconds
Started Jul 18 05:25:23 PM PDT 24
Finished Jul 18 05:25:30 PM PDT 24
Peak memory 224944 kb
Host smart-3cb02e38-4ba7-4de4-8f4e-00f884a50e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224603282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2224603282
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1096474913
Short name T579
Test name
Test status
Simulation time 3161525856 ps
CPU time 21.21 seconds
Started Jul 18 05:25:20 PM PDT 24
Finished Jul 18 05:25:42 PM PDT 24
Peak memory 225104 kb
Host smart-b7378c14-e16f-4220-9d3f-02e053ba3ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096474913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1096474913
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.512586029
Short name T577
Test name
Test status
Simulation time 1258558173 ps
CPU time 6.26 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:30 PM PDT 24
Peak memory 233184 kb
Host smart-20bd1feb-158a-4588-a863-b7be19cfa101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512586029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.512586029
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1693084847
Short name T975
Test name
Test status
Simulation time 4965416047 ps
CPU time 17.03 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:41 PM PDT 24
Peak memory 225044 kb
Host smart-e86721b4-c094-4f8b-8f8f-41c6d4c09635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693084847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1693084847
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3165229194
Short name T532
Test name
Test status
Simulation time 1427362847 ps
CPU time 10.12 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:34 PM PDT 24
Peak memory 223468 kb
Host smart-c23a34c7-82da-4d5d-a38d-a51f76a0fb09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3165229194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3165229194
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1544608881
Short name T22
Test name
Test status
Simulation time 62371957 ps
CPU time 1.02 seconds
Started Jul 18 05:25:22 PM PDT 24
Finished Jul 18 05:25:26 PM PDT 24
Peak memory 217600 kb
Host smart-2d6e85c6-6860-469c-aa4d-1418bda8f9bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544608881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1544608881
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.695150013
Short name T358
Test name
Test status
Simulation time 2802978029 ps
CPU time 16.28 seconds
Started Jul 18 05:25:09 PM PDT 24
Finished Jul 18 05:25:29 PM PDT 24
Peak memory 216856 kb
Host smart-b62f0141-f9c7-41c1-9250-1486a487b50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695150013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.695150013
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2113690092
Short name T443
Test name
Test status
Simulation time 5482037203 ps
CPU time 4.67 seconds
Started Jul 18 05:25:15 PM PDT 24
Finished Jul 18 05:25:22 PM PDT 24
Peak memory 216816 kb
Host smart-ba55e461-aabc-4694-9322-d5b1d8b3dd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113690092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2113690092
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.145075458
Short name T897
Test name
Test status
Simulation time 73337249 ps
CPU time 0.96 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:23 PM PDT 24
Peak memory 206280 kb
Host smart-ffc32477-7e2c-4ac5-bff4-1a590631b945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145075458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.145075458
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.789494184
Short name T931
Test name
Test status
Simulation time 64056479 ps
CPU time 0.84 seconds
Started Jul 18 05:25:18 PM PDT 24
Finished Jul 18 05:25:20 PM PDT 24
Peak memory 206264 kb
Host smart-57123710-4cf9-4bd4-8888-7976516c85ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789494184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.789494184
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3391016839
Short name T1012
Test name
Test status
Simulation time 3764387598 ps
CPU time 6.4 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:29 PM PDT 24
Peak memory 241036 kb
Host smart-5db59b98-f155-4094-bfcb-63e294e8ecb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391016839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3391016839
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3412210007
Short name T628
Test name
Test status
Simulation time 36348880 ps
CPU time 0.71 seconds
Started Jul 18 05:25:29 PM PDT 24
Finished Jul 18 05:25:31 PM PDT 24
Peak memory 205676 kb
Host smart-1ae6b475-58f1-45eb-b5af-b4f5610024a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412210007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3412210007
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.471774683
Short name T941
Test name
Test status
Simulation time 164143001 ps
CPU time 2.31 seconds
Started Jul 18 05:25:22 PM PDT 24
Finished Jul 18 05:25:27 PM PDT 24
Peak memory 232844 kb
Host smart-eda6932b-e9f7-41f4-997a-1cb8c6055ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471774683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.471774683
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2934476298
Short name T547
Test name
Test status
Simulation time 33934125 ps
CPU time 0.86 seconds
Started Jul 18 05:25:24 PM PDT 24
Finished Jul 18 05:25:28 PM PDT 24
Peak memory 207188 kb
Host smart-995171e7-d040-430a-8e4f-290dd8384eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934476298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2934476298
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4106837666
Short name T376
Test name
Test status
Simulation time 44513256050 ps
CPU time 307.08 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:30:31 PM PDT 24
Peak memory 256596 kb
Host smart-89a8e10e-1a93-4ce6-8508-7ec8a363fcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106837666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4106837666
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1122678884
Short name T840
Test name
Test status
Simulation time 5155164921 ps
CPU time 28.9 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:53 PM PDT 24
Peak memory 218056 kb
Host smart-0b101d73-d106-4f46-b919-7ce157b6e33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122678884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1122678884
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1736041000
Short name T1015
Test name
Test status
Simulation time 276508119 ps
CPU time 5.53 seconds
Started Jul 18 05:25:22 PM PDT 24
Finished Jul 18 05:25:32 PM PDT 24
Peak memory 224848 kb
Host smart-55d56e51-3813-41c9-b9aa-f833e4fee209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736041000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1736041000
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.235596079
Short name T422
Test name
Test status
Simulation time 408797779 ps
CPU time 0.97 seconds
Started Jul 18 05:25:23 PM PDT 24
Finished Jul 18 05:25:27 PM PDT 24
Peak memory 216444 kb
Host smart-5d42a70e-3851-46e1-b669-dd36417f7742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235596079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.235596079
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.591354346
Short name T675
Test name
Test status
Simulation time 13601358747 ps
CPU time 33.17 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:57 PM PDT 24
Peak memory 224964 kb
Host smart-bcceced1-fe15-436c-8990-a3a435e07839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591354346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.591354346
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3143244143
Short name T626
Test name
Test status
Simulation time 328224943 ps
CPU time 7.93 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:32 PM PDT 24
Peak memory 224936 kb
Host smart-0443e454-cda1-4eb9-a1f1-6eb960528cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143244143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3143244143
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.188467793
Short name T466
Test name
Test status
Simulation time 23792422769 ps
CPU time 19.82 seconds
Started Jul 18 05:25:19 PM PDT 24
Finished Jul 18 05:25:40 PM PDT 24
Peak memory 233272 kb
Host smart-8d3da04d-9718-4f22-b993-c845eccf2f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188467793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.188467793
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1806973516
Short name T181
Test name
Test status
Simulation time 3595247292 ps
CPU time 13.6 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:36 PM PDT 24
Peak memory 233300 kb
Host smart-094e54cb-cace-43df-8673-fc1bfa0dcd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806973516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1806973516
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1246678369
Short name T952
Test name
Test status
Simulation time 195989212 ps
CPU time 3.9 seconds
Started Jul 18 05:25:20 PM PDT 24
Finished Jul 18 05:25:25 PM PDT 24
Peak memory 223076 kb
Host smart-5fec8dd4-96c6-49b2-92d5-66bce40db074
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1246678369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1246678369
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3100277151
Short name T324
Test name
Test status
Simulation time 801602659 ps
CPU time 8.14 seconds
Started Jul 18 05:25:29 PM PDT 24
Finished Jul 18 05:25:38 PM PDT 24
Peak memory 216832 kb
Host smart-abf59490-8745-4982-ac52-f513a58b4b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100277151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3100277151
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1233532154
Short name T505
Test name
Test status
Simulation time 384453455 ps
CPU time 3.3 seconds
Started Jul 18 05:25:20 PM PDT 24
Finished Jul 18 05:25:25 PM PDT 24
Peak memory 216648 kb
Host smart-27f2f008-8f0b-4e39-977d-e145ba09939b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233532154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1233532154
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2684443643
Short name T750
Test name
Test status
Simulation time 486657137 ps
CPU time 3.39 seconds
Started Jul 18 05:25:22 PM PDT 24
Finished Jul 18 05:25:29 PM PDT 24
Peak memory 216692 kb
Host smart-ac49a5c6-75fe-40ed-9a01-2a1fc58f7c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684443643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2684443643
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.41676580
Short name T960
Test name
Test status
Simulation time 85796541 ps
CPU time 0.84 seconds
Started Jul 18 05:25:22 PM PDT 24
Finished Jul 18 05:25:25 PM PDT 24
Peak memory 206296 kb
Host smart-eb94fe20-69cc-425e-a98d-09dc20017578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41676580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.41676580
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.396033205
Short name T285
Test name
Test status
Simulation time 10876606657 ps
CPU time 11.34 seconds
Started Jul 18 05:25:23 PM PDT 24
Finished Jul 18 05:25:38 PM PDT 24
Peak memory 233296 kb
Host smart-451f0107-a11d-493e-93b0-49fd094df64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396033205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.396033205
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2563146501
Short name T23
Test name
Test status
Simulation time 37925192 ps
CPU time 0.73 seconds
Started Jul 18 05:25:23 PM PDT 24
Finished Jul 18 05:25:27 PM PDT 24
Peak memory 205696 kb
Host smart-775f7200-9972-4efe-80ff-347c407026b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563146501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2563146501
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.615675886
Short name T403
Test name
Test status
Simulation time 29994335 ps
CPU time 3.04 seconds
Started Jul 18 05:25:24 PM PDT 24
Finished Jul 18 05:25:30 PM PDT 24
Peak memory 233032 kb
Host smart-0d449a81-7af4-4c1e-af5f-4862a5622da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615675886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.615675886
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3654824049
Short name T483
Test name
Test status
Simulation time 71239016 ps
CPU time 0.81 seconds
Started Jul 18 05:25:18 PM PDT 24
Finished Jul 18 05:25:20 PM PDT 24
Peak memory 206832 kb
Host smart-c9d8fd24-fa4d-4bb3-9c1a-a26353a6bdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654824049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3654824049
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.494590641
Short name T898
Test name
Test status
Simulation time 836879367 ps
CPU time 16.86 seconds
Started Jul 18 05:25:23 PM PDT 24
Finished Jul 18 05:25:44 PM PDT 24
Peak memory 239820 kb
Host smart-24c9e9b7-cc19-42fd-97ac-5c6e4e41d6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494590641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.494590641
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.933614267
Short name T948
Test name
Test status
Simulation time 16414263248 ps
CPU time 73.06 seconds
Started Jul 18 05:25:20 PM PDT 24
Finished Jul 18 05:26:35 PM PDT 24
Peak memory 241300 kb
Host smart-3e7bed61-25e2-4c28-8e9f-f6edf22d3243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933614267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.933614267
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3198425982
Short name T206
Test name
Test status
Simulation time 40465356586 ps
CPU time 330.24 seconds
Started Jul 18 05:25:25 PM PDT 24
Finished Jul 18 05:30:58 PM PDT 24
Peak memory 256952 kb
Host smart-11283709-45d6-4a8e-b761-64713d7e3425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198425982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3198425982
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.633413291
Short name T321
Test name
Test status
Simulation time 15542354409 ps
CPU time 31.42 seconds
Started Jul 18 05:25:25 PM PDT 24
Finished Jul 18 05:25:59 PM PDT 24
Peak memory 237272 kb
Host smart-1a746a3a-e0f5-4e26-b854-fc8df296067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633413291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.633413291
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1099876209
Short name T11
Test name
Test status
Simulation time 1019518271 ps
CPU time 15.32 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:40 PM PDT 24
Peak memory 249504 kb
Host smart-e03f5cd2-4c6c-4bce-9484-f2432340faa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099876209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1099876209
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3452419491
Short name T65
Test name
Test status
Simulation time 319482429 ps
CPU time 4.74 seconds
Started Jul 18 05:25:24 PM PDT 24
Finished Jul 18 05:25:32 PM PDT 24
Peak memory 232560 kb
Host smart-ec2b30b1-9898-4dd2-98eb-a3b9a35e7949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452419491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3452419491
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2207992750
Short name T74
Test name
Test status
Simulation time 1379883897 ps
CPU time 11.88 seconds
Started Jul 18 05:25:24 PM PDT 24
Finished Jul 18 05:25:39 PM PDT 24
Peak memory 233112 kb
Host smart-0de5c031-1697-4a31-8b18-21491157c3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207992750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2207992750
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2937318597
Short name T932
Test name
Test status
Simulation time 7643248514 ps
CPU time 6.57 seconds
Started Jul 18 05:25:23 PM PDT 24
Finished Jul 18 05:25:34 PM PDT 24
Peak memory 225016 kb
Host smart-9f4d1bb2-597e-4a11-bce1-af34a9700ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937318597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2937318597
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4215297473
Short name T454
Test name
Test status
Simulation time 480640097 ps
CPU time 8.22 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:32 PM PDT 24
Peak memory 240964 kb
Host smart-54ebe7ca-118f-4cd6-b00d-5d304b415555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215297473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4215297473
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.209615879
Short name T639
Test name
Test status
Simulation time 113074824 ps
CPU time 4.6 seconds
Started Jul 18 05:25:24 PM PDT 24
Finished Jul 18 05:25:32 PM PDT 24
Peak memory 223484 kb
Host smart-161ab8d5-bbec-48b9-b0ba-5aada713c7ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=209615879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.209615879
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3814014391
Short name T583
Test name
Test status
Simulation time 998920478 ps
CPU time 8.22 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:32 PM PDT 24
Peak memory 218620 kb
Host smart-2749b111-4db6-45f2-a24e-649b10c50cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814014391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3814014391
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2346252391
Short name T87
Test name
Test status
Simulation time 15414086993 ps
CPU time 14.23 seconds
Started Jul 18 05:25:22 PM PDT 24
Finished Jul 18 05:25:40 PM PDT 24
Peak memory 216752 kb
Host smart-9243073a-6bf5-419b-bc23-9f8051876ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346252391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2346252391
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3174985336
Short name T440
Test name
Test status
Simulation time 615512578 ps
CPU time 10.22 seconds
Started Jul 18 05:25:23 PM PDT 24
Finished Jul 18 05:25:37 PM PDT 24
Peak memory 216676 kb
Host smart-3965177d-335f-4707-a068-72061cf5969b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174985336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3174985336
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.595971245
Short name T618
Test name
Test status
Simulation time 263398368 ps
CPU time 0.85 seconds
Started Jul 18 05:25:25 PM PDT 24
Finished Jul 18 05:25:29 PM PDT 24
Peak memory 206216 kb
Host smart-cfc64d70-4687-4bdd-aff5-13063314a8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595971245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.595971245
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.147708473
Short name T839
Test name
Test status
Simulation time 7529978993 ps
CPU time 27.87 seconds
Started Jul 18 05:25:24 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 241368 kb
Host smart-c9f26c08-407a-41ec-b72a-6a95696f3d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147708473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.147708473
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.394172656
Short name T878
Test name
Test status
Simulation time 104529119 ps
CPU time 0.72 seconds
Started Jul 18 05:25:23 PM PDT 24
Finished Jul 18 05:25:27 PM PDT 24
Peak memory 205744 kb
Host smart-0ff9d773-8241-464a-85a2-b0e470c3c61b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394172656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.394172656
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1681295277
Short name T257
Test name
Test status
Simulation time 444018912 ps
CPU time 3.9 seconds
Started Jul 18 05:25:22 PM PDT 24
Finished Jul 18 05:25:29 PM PDT 24
Peak memory 224872 kb
Host smart-e3b488f3-847f-4a46-8ec4-821160650b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681295277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1681295277
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2852650897
Short name T367
Test name
Test status
Simulation time 20005079 ps
CPU time 0.79 seconds
Started Jul 18 05:25:24 PM PDT 24
Finished Jul 18 05:25:28 PM PDT 24
Peak memory 206192 kb
Host smart-6fae459a-5a68-45e4-8be5-053322924065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852650897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2852650897
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2479324185
Short name T223
Test name
Test status
Simulation time 54956868730 ps
CPU time 193.65 seconds
Started Jul 18 05:25:22 PM PDT 24
Finished Jul 18 05:28:39 PM PDT 24
Peak memory 249572 kb
Host smart-38b64e16-308c-41ce-bf35-4272dc7ba724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479324185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2479324185
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1182068009
Short name T29
Test name
Test status
Simulation time 18783887308 ps
CPU time 178.86 seconds
Started Jul 18 05:25:27 PM PDT 24
Finished Jul 18 05:28:28 PM PDT 24
Peak memory 251148 kb
Host smart-c0f09527-3627-4682-bcfe-256f1b63734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182068009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1182068009
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3911827274
Short name T772
Test name
Test status
Simulation time 2514907932 ps
CPU time 28.47 seconds
Started Jul 18 05:25:23 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 222476 kb
Host smart-b8b945b8-00aa-410e-8a8b-433b45790254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911827274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3911827274
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4211177187
Short name T315
Test name
Test status
Simulation time 8137177642 ps
CPU time 67.84 seconds
Started Jul 18 05:25:24 PM PDT 24
Finished Jul 18 05:26:36 PM PDT 24
Peak memory 233512 kb
Host smart-d984b70c-6d33-49ae-a116-3265681332d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211177187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4211177187
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2055218985
Short name T253
Test name
Test status
Simulation time 88657171283 ps
CPU time 76.64 seconds
Started Jul 18 05:25:22 PM PDT 24
Finished Jul 18 05:26:42 PM PDT 24
Peak memory 241364 kb
Host smart-0e2deb31-02d9-4dc3-aef5-cc02fd76e579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055218985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2055218985
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2655928655
Short name T555
Test name
Test status
Simulation time 2521540365 ps
CPU time 11.91 seconds
Started Jul 18 05:25:25 PM PDT 24
Finished Jul 18 05:25:40 PM PDT 24
Peak memory 233204 kb
Host smart-483e1fe3-d6d1-4396-a243-085ffc24dc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655928655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2655928655
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1079798249
Short name T203
Test name
Test status
Simulation time 11553127944 ps
CPU time 25.94 seconds
Started Jul 18 05:25:29 PM PDT 24
Finished Jul 18 05:25:56 PM PDT 24
Peak memory 241204 kb
Host smart-fdcf3806-9a70-4e05-bf12-744ddfd6b702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079798249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1079798249
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1627402918
Short name T289
Test name
Test status
Simulation time 13871208949 ps
CPU time 10.55 seconds
Started Jul 18 05:25:30 PM PDT 24
Finished Jul 18 05:25:42 PM PDT 24
Peak memory 233168 kb
Host smart-808989ce-2bc9-4eb4-a212-7ca7230c92be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627402918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1627402918
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3302559072
Short name T183
Test name
Test status
Simulation time 6665916179 ps
CPU time 6.77 seconds
Started Jul 18 05:25:30 PM PDT 24
Finished Jul 18 05:25:38 PM PDT 24
Peak memory 233144 kb
Host smart-a78e83a8-8450-4e59-8b20-7e52debaa14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302559072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3302559072
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2850453026
Short name T933
Test name
Test status
Simulation time 117720944 ps
CPU time 4.15 seconds
Started Jul 18 05:25:22 PM PDT 24
Finished Jul 18 05:25:29 PM PDT 24
Peak memory 222968 kb
Host smart-929b49b9-7184-4fd2-a4c7-3c2970ee1bb2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2850453026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2850453026
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1502177728
Short name T684
Test name
Test status
Simulation time 185011870 ps
CPU time 0.88 seconds
Started Jul 18 05:25:29 PM PDT 24
Finished Jul 18 05:25:32 PM PDT 24
Peak memory 205892 kb
Host smart-8573a4ba-0047-415a-be81-2dec2f4c83fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502177728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1502177728
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.188575791
Short name T347
Test name
Test status
Simulation time 13925433 ps
CPU time 0.69 seconds
Started Jul 18 05:25:24 PM PDT 24
Finished Jul 18 05:25:28 PM PDT 24
Peak memory 206020 kb
Host smart-a901a18f-9585-40df-8548-9feb146095a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188575791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.188575791
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3061628917
Short name T8
Test name
Test status
Simulation time 577266731 ps
CPU time 3.83 seconds
Started Jul 18 05:25:21 PM PDT 24
Finished Jul 18 05:25:27 PM PDT 24
Peak memory 216660 kb
Host smart-716e1a78-4e59-4622-b1e7-64810f64d573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061628917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3061628917
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4237252738
Short name T59
Test name
Test status
Simulation time 392174593 ps
CPU time 2.73 seconds
Started Jul 18 05:25:30 PM PDT 24
Finished Jul 18 05:25:34 PM PDT 24
Peak memory 216632 kb
Host smart-4661c0a6-9756-47e9-9e3b-f25502715e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237252738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4237252738
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1380940839
Short name T1027
Test name
Test status
Simulation time 259350362 ps
CPU time 0.9 seconds
Started Jul 18 05:25:29 PM PDT 24
Finished Jul 18 05:25:31 PM PDT 24
Peak memory 206208 kb
Host smart-1e94265b-d7f5-488b-b75c-e4949bbff125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380940839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1380940839
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3607859446
Short name T798
Test name
Test status
Simulation time 20946159205 ps
CPU time 19.36 seconds
Started Jul 18 05:25:29 PM PDT 24
Finished Jul 18 05:25:50 PM PDT 24
Peak memory 233212 kb
Host smart-051c7144-72bd-4886-accc-494fcb873b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607859446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3607859446
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.647934557
Short name T813
Test name
Test status
Simulation time 13728221 ps
CPU time 0.7 seconds
Started Jul 18 05:25:48 PM PDT 24
Finished Jul 18 05:25:53 PM PDT 24
Peak memory 205124 kb
Host smart-efd4bf6b-1907-4d37-bed7-82593a3a79e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647934557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.647934557
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1249173502
Short name T870
Test name
Test status
Simulation time 493490842 ps
CPU time 5.06 seconds
Started Jul 18 05:25:43 PM PDT 24
Finished Jul 18 05:25:49 PM PDT 24
Peak memory 224848 kb
Host smart-f02fe348-1ebd-44dc-af6e-83ec2157a82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249173502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1249173502
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2682494407
Short name T969
Test name
Test status
Simulation time 54260369 ps
CPU time 0.78 seconds
Started Jul 18 05:25:43 PM PDT 24
Finished Jul 18 05:25:44 PM PDT 24
Peak memory 206808 kb
Host smart-eee64933-f8a5-422d-9127-b1d162bf0ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682494407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2682494407
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.161946476
Short name T232
Test name
Test status
Simulation time 3588045573 ps
CPU time 23.39 seconds
Started Jul 18 05:25:49 PM PDT 24
Finished Jul 18 05:26:16 PM PDT 24
Peak memory 251272 kb
Host smart-271d1bea-a2af-414c-aecd-94c543397b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161946476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.161946476
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2343078967
Short name T31
Test name
Test status
Simulation time 3237676247 ps
CPU time 50.38 seconds
Started Jul 18 05:25:45 PM PDT 24
Finished Jul 18 05:26:36 PM PDT 24
Peak memory 249684 kb
Host smart-a6abdb5a-31b1-458d-9ed5-94f5ab8c6626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343078967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2343078967
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2341743311
Short name T63
Test name
Test status
Simulation time 113512629488 ps
CPU time 259.43 seconds
Started Jul 18 05:25:45 PM PDT 24
Finished Jul 18 05:30:07 PM PDT 24
Peak memory 254584 kb
Host smart-d9c967f2-fafd-4b30-9c55-256697a69b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341743311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2341743311
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2949560957
Short name T699
Test name
Test status
Simulation time 2627840265 ps
CPU time 30.08 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:26:18 PM PDT 24
Peak memory 233308 kb
Host smart-0584ae7a-bca8-4bd0-adc9-028e6da49a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949560957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2949560957
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3626163388
Short name T993
Test name
Test status
Simulation time 1628677952 ps
CPU time 20.15 seconds
Started Jul 18 05:25:43 PM PDT 24
Finished Jul 18 05:26:05 PM PDT 24
Peak memory 238652 kb
Host smart-a31bfb27-d977-44fb-be8b-7a86e19eaa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626163388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3626163388
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.564284513
Short name T980
Test name
Test status
Simulation time 12301760844 ps
CPU time 28.2 seconds
Started Jul 18 05:25:42 PM PDT 24
Finished Jul 18 05:26:11 PM PDT 24
Peak memory 233224 kb
Host smart-6407da1a-759f-4d09-a9ed-fca863dbf3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564284513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.564284513
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.803653371
Short name T524
Test name
Test status
Simulation time 1424302068 ps
CPU time 19.48 seconds
Started Jul 18 05:25:43 PM PDT 24
Finished Jul 18 05:26:04 PM PDT 24
Peak memory 241304 kb
Host smart-fa5d6e3e-3bcf-425f-86da-ebcfce8211c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803653371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.803653371
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.4021575193
Short name T816
Test name
Test status
Simulation time 612014367 ps
CPU time 3.8 seconds
Started Jul 18 05:25:44 PM PDT 24
Finished Jul 18 05:25:49 PM PDT 24
Peak memory 224860 kb
Host smart-d7e4e8b1-5afd-42df-b47a-5a2fca6f9d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021575193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.4021575193
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.289773063
Short name T1020
Test name
Test status
Simulation time 417213404 ps
CPU time 2.47 seconds
Started Jul 18 05:25:44 PM PDT 24
Finished Jul 18 05:25:47 PM PDT 24
Peak memory 224936 kb
Host smart-87627542-8f87-4ed4-9569-36a3df0c8889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289773063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.289773063
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2915300119
Short name T409
Test name
Test status
Simulation time 291035213 ps
CPU time 3.8 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 220588 kb
Host smart-0068707a-1de0-4af7-a3f6-c27763431c3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2915300119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2915300119
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2128606844
Short name T155
Test name
Test status
Simulation time 3137578006 ps
CPU time 65.56 seconds
Started Jul 18 05:25:44 PM PDT 24
Finished Jul 18 05:26:50 PM PDT 24
Peak memory 252496 kb
Host smart-45669c2a-5cf9-402e-9f0d-705cb36da285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128606844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2128606844
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.825562127
Short name T469
Test name
Test status
Simulation time 28532145931 ps
CPU time 38.13 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:26:26 PM PDT 24
Peak memory 216752 kb
Host smart-e08eb864-2daf-46e6-99a1-a512f253e07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825562127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.825562127
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2240200376
Short name T597
Test name
Test status
Simulation time 11366545 ps
CPU time 0.75 seconds
Started Jul 18 05:25:43 PM PDT 24
Finished Jul 18 05:25:45 PM PDT 24
Peak memory 205912 kb
Host smart-162afc7d-426d-4384-98de-4fa599e2fcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240200376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2240200376
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2022309648
Short name T80
Test name
Test status
Simulation time 22406904 ps
CPU time 0.92 seconds
Started Jul 18 05:25:45 PM PDT 24
Finished Jul 18 05:25:48 PM PDT 24
Peak memory 207572 kb
Host smart-3eadfaa8-eadc-44d2-b4b2-dda7bc04b562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022309648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2022309648
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.703358544
Short name T984
Test name
Test status
Simulation time 398746803 ps
CPU time 0.83 seconds
Started Jul 18 05:25:42 PM PDT 24
Finished Jul 18 05:25:44 PM PDT 24
Peak memory 206484 kb
Host smart-8c7439c9-ed53-4426-8229-3382e6ec5506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703358544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.703358544
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2558802064
Short name T783
Test name
Test status
Simulation time 537907646 ps
CPU time 8.63 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:25:59 PM PDT 24
Peak memory 233168 kb
Host smart-55c1ddc2-0076-474f-96aa-31ca16dca835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558802064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2558802064
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3485840138
Short name T557
Test name
Test status
Simulation time 14019573 ps
CPU time 0.73 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:25:52 PM PDT 24
Peak memory 205168 kb
Host smart-fc802655-36e4-47fe-baf9-43fa02468e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485840138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3485840138
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3455185616
Short name T701
Test name
Test status
Simulation time 620218781 ps
CPU time 4.11 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:25:54 PM PDT 24
Peak memory 224924 kb
Host smart-ba5bbb73-a485-40a9-8fdc-513264eda86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455185616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3455185616
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.924927657
Short name T1007
Test name
Test status
Simulation time 16076235 ps
CPU time 0.78 seconds
Started Jul 18 05:25:44 PM PDT 24
Finished Jul 18 05:25:46 PM PDT 24
Peak memory 206136 kb
Host smart-acaf077c-bd28-4ca1-9cb0-7bb528fc87a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924927657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.924927657
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.102055560
Short name T805
Test name
Test status
Simulation time 43569653357 ps
CPU time 169.86 seconds
Started Jul 18 05:25:48 PM PDT 24
Finished Jul 18 05:28:41 PM PDT 24
Peak memory 257776 kb
Host smart-6f2a99ae-8087-474d-8500-f22b4789238d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102055560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.102055560
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1367135350
Short name T200
Test name
Test status
Simulation time 5808369576 ps
CPU time 88.71 seconds
Started Jul 18 05:25:48 PM PDT 24
Finished Jul 18 05:27:21 PM PDT 24
Peak memory 265180 kb
Host smart-a5aa623d-34cb-4729-b030-f7cff0a01445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367135350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1367135350
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3543639022
Short name T921
Test name
Test status
Simulation time 2383933385 ps
CPU time 17.49 seconds
Started Jul 18 05:25:48 PM PDT 24
Finished Jul 18 05:26:09 PM PDT 24
Peak memory 225148 kb
Host smart-b9703cb0-8d23-4f78-861f-9e95c3c112aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543639022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3543639022
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4045300117
Short name T576
Test name
Test status
Simulation time 1106152519 ps
CPU time 3.6 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 233132 kb
Host smart-981ba7bd-5b4b-43b7-b34d-efef130107e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045300117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4045300117
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1031941162
Short name T167
Test name
Test status
Simulation time 3711330331 ps
CPU time 49.21 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:26:40 PM PDT 24
Peak memory 251104 kb
Host smart-111f88ba-546d-45ca-81bb-b7ad036c5eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031941162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1031941162
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.684773209
Short name T258
Test name
Test status
Simulation time 5160047463 ps
CPU time 3.76 seconds
Started Jul 18 05:25:43 PM PDT 24
Finished Jul 18 05:25:47 PM PDT 24
Peak memory 224952 kb
Host smart-b9ca8df3-1f11-4d30-8f93-abbfd3cbeabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684773209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.684773209
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2487402463
Short name T782
Test name
Test status
Simulation time 2952328270 ps
CPU time 17.49 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:26:08 PM PDT 24
Peak memory 225008 kb
Host smart-76d3a93d-3359-4664-be42-67ac58d9076b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487402463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2487402463
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2579115711
Short name T595
Test name
Test status
Simulation time 673426908 ps
CPU time 3 seconds
Started Jul 18 05:25:50 PM PDT 24
Finished Jul 18 05:25:56 PM PDT 24
Peak memory 219276 kb
Host smart-d93e51f8-72c1-440c-ad81-7378ba3e281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579115711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2579115711
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2719063943
Short name T957
Test name
Test status
Simulation time 2626851644 ps
CPU time 10.11 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:26:00 PM PDT 24
Peak memory 220820 kb
Host smart-6b50765d-1765-42e1-875d-068004a027f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2719063943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2719063943
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3607269110
Short name T526
Test name
Test status
Simulation time 83805244 ps
CPU time 0.88 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:25:52 PM PDT 24
Peak memory 207200 kb
Host smart-4c25a4aa-c7be-466f-838e-7c1f9ca69187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607269110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3607269110
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2741251230
Short name T331
Test name
Test status
Simulation time 2364501004 ps
CPU time 14.96 seconds
Started Jul 18 05:25:45 PM PDT 24
Finished Jul 18 05:26:01 PM PDT 24
Peak memory 216752 kb
Host smart-cc8182f9-f0b8-415e-9f83-bd54a58d2857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741251230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2741251230
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3875420395
Short name T716
Test name
Test status
Simulation time 415119603 ps
CPU time 3.03 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 216584 kb
Host smart-616f31cf-84d4-4ae4-9b47-bb1efa6ce66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875420395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3875420395
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2873049523
Short name T24
Test name
Test status
Simulation time 368681891 ps
CPU time 1.17 seconds
Started Jul 18 05:25:43 PM PDT 24
Finished Jul 18 05:25:45 PM PDT 24
Peak memory 216724 kb
Host smart-b839d97f-65b1-458b-9d86-66393b47aecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873049523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2873049523
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3120640663
Short name T383
Test name
Test status
Simulation time 24972568 ps
CPU time 0.72 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:25:50 PM PDT 24
Peak memory 206248 kb
Host smart-e087031d-daee-4727-a67f-1454a3041a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120640663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3120640663
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2321267887
Short name T496
Test name
Test status
Simulation time 6234582395 ps
CPU time 16.4 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:26:07 PM PDT 24
Peak memory 232916 kb
Host smart-1855b741-3d26-4f50-a326-87c7e7fbb3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321267887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2321267887
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4091549236
Short name T649
Test name
Test status
Simulation time 85155380 ps
CPU time 0.71 seconds
Started Jul 18 05:25:50 PM PDT 24
Finished Jul 18 05:25:54 PM PDT 24
Peak memory 205140 kb
Host smart-2e24e5af-ff67-4df2-96c9-4e70172116e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091549236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4091549236
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3357490024
Short name T10
Test name
Test status
Simulation time 1985369568 ps
CPU time 4.4 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 224964 kb
Host smart-cd01c964-8a2d-44f5-a847-0d3c0b2a6fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357490024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3357490024
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3225983497
Short name T495
Test name
Test status
Simulation time 14127425 ps
CPU time 0.78 seconds
Started Jul 18 05:25:48 PM PDT 24
Finished Jul 18 05:25:52 PM PDT 24
Peak memory 206824 kb
Host smart-08fdf9f9-3d98-40d1-abb5-f0a07024cd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225983497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3225983497
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3855487208
Short name T866
Test name
Test status
Simulation time 799573087 ps
CPU time 5.16 seconds
Started Jul 18 05:25:50 PM PDT 24
Finished Jul 18 05:25:58 PM PDT 24
Peak memory 241324 kb
Host smart-9cf96ed6-5438-4093-a6b7-72ef0e86b529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855487208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3855487208
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3205534531
Short name T214
Test name
Test status
Simulation time 8289329328 ps
CPU time 95.86 seconds
Started Jul 18 05:25:49 PM PDT 24
Finished Jul 18 05:27:28 PM PDT 24
Peak memory 264548 kb
Host smart-75131793-2b66-4fd5-a590-2e2979aa65c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205534531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3205534531
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1968370613
Short name T220
Test name
Test status
Simulation time 95249636213 ps
CPU time 413.58 seconds
Started Jul 18 05:25:50 PM PDT 24
Finished Jul 18 05:32:47 PM PDT 24
Peak memory 263988 kb
Host smart-62965670-bc73-4879-bf7a-a5f8c79364a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968370613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1968370613
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2728853092
Short name T824
Test name
Test status
Simulation time 1345390554 ps
CPU time 18.56 seconds
Started Jul 18 05:25:45 PM PDT 24
Finished Jul 18 05:26:06 PM PDT 24
Peak memory 224932 kb
Host smart-cf750583-8819-48d8-8d22-54c06cd65551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728853092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2728853092
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1999512271
Short name T178
Test name
Test status
Simulation time 1374139328 ps
CPU time 26.32 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:26:16 PM PDT 24
Peak memory 233088 kb
Host smart-92aa999a-e142-4c54-b25b-f9931c67bc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999512271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1999512271
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2679340970
Short name T234
Test name
Test status
Simulation time 83399005 ps
CPU time 3.65 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 233168 kb
Host smart-c28d05ed-04cf-4c8f-a4e7-f470d23df7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679340970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2679340970
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4251613584
Short name T656
Test name
Test status
Simulation time 21452654480 ps
CPU time 19.31 seconds
Started Jul 18 05:25:48 PM PDT 24
Finished Jul 18 05:26:11 PM PDT 24
Peak memory 233224 kb
Host smart-935eda20-d08d-45ae-981c-14d8b91901d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251613584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4251613584
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2708062365
Short name T305
Test name
Test status
Simulation time 307589370 ps
CPU time 2.34 seconds
Started Jul 18 05:25:49 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 224880 kb
Host smart-ac1b0139-074c-4c73-97e4-02191b80edc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708062365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2708062365
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2958908992
Short name T337
Test name
Test status
Simulation time 30190847 ps
CPU time 1.97 seconds
Started Jul 18 05:25:48 PM PDT 24
Finished Jul 18 05:25:54 PM PDT 24
Peak memory 224556 kb
Host smart-29de37ef-f11f-482f-a366-4bf3efc021fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958908992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2958908992
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3681634061
Short name T979
Test name
Test status
Simulation time 2817339379 ps
CPU time 9.86 seconds
Started Jul 18 05:25:50 PM PDT 24
Finished Jul 18 05:26:03 PM PDT 24
Peak memory 223472 kb
Host smart-a258de8b-aa05-48ab-84bd-f9033b1e435a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3681634061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3681634061
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4202842159
Short name T311
Test name
Test status
Simulation time 18835145719 ps
CPU time 160.92 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:28:32 PM PDT 24
Peak memory 254832 kb
Host smart-a044e473-c94b-4805-8d8c-0fc62ab1989f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202842159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4202842159
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2254572681
Short name T578
Test name
Test status
Simulation time 3849680331 ps
CPU time 25.61 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:26:16 PM PDT 24
Peak memory 216764 kb
Host smart-a8ba612c-f32d-4242-908b-de6f33da3175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254572681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2254572681
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2166382648
Short name T814
Test name
Test status
Simulation time 726179447 ps
CPU time 5.95 seconds
Started Jul 18 05:25:49 PM PDT 24
Finished Jul 18 05:25:59 PM PDT 24
Peak memory 216532 kb
Host smart-d4045e36-72f9-4b95-830e-62bfbdf7c34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166382648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2166382648
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3254762722
Short name T32
Test name
Test status
Simulation time 515409634 ps
CPU time 1.11 seconds
Started Jul 18 05:25:49 PM PDT 24
Finished Jul 18 05:25:54 PM PDT 24
Peak memory 208252 kb
Host smart-d9216575-de2d-4da8-bc3d-0faf89928241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254762722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3254762722
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2457147669
Short name T379
Test name
Test status
Simulation time 11125391 ps
CPU time 0.69 seconds
Started Jul 18 05:25:48 PM PDT 24
Finished Jul 18 05:25:52 PM PDT 24
Peak memory 205940 kb
Host smart-45c6d8ab-354b-4b7c-ae55-e636bd7fb1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457147669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2457147669
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.124738388
Short name T958
Test name
Test status
Simulation time 24925716534 ps
CPU time 19.67 seconds
Started Jul 18 05:25:49 PM PDT 24
Finished Jul 18 05:26:12 PM PDT 24
Peak memory 224952 kb
Host smart-b1a9d542-53af-4d1a-ba10-3ae8b06a7010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124738388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.124738388
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3402603111
Short name T633
Test name
Test status
Simulation time 54079175 ps
CPU time 0.71 seconds
Started Jul 18 05:25:44 PM PDT 24
Finished Jul 18 05:25:46 PM PDT 24
Peak memory 205120 kb
Host smart-308dd01f-f363-4a5a-8e9f-08c7338204af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402603111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3402603111
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.834261689
Short name T249
Test name
Test status
Simulation time 284805357 ps
CPU time 6.3 seconds
Started Jul 18 05:25:45 PM PDT 24
Finished Jul 18 05:25:53 PM PDT 24
Peak memory 233340 kb
Host smart-5d2bf340-8584-4d6c-8b19-05a0265a9c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834261689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.834261689
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2989112448
Short name T627
Test name
Test status
Simulation time 19053187 ps
CPU time 0.79 seconds
Started Jul 18 05:25:49 PM PDT 24
Finished Jul 18 05:25:53 PM PDT 24
Peak memory 206608 kb
Host smart-07b20fd5-8c38-41b8-b985-3058e1c1416e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989112448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2989112448
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1022864084
Short name T1023
Test name
Test status
Simulation time 35556829036 ps
CPU time 61.34 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:26:50 PM PDT 24
Peak memory 241512 kb
Host smart-1921827b-7528-41a4-aaf6-f4738bfd5d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022864084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1022864084
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2872260680
Short name T702
Test name
Test status
Simulation time 1886603488 ps
CPU time 39.46 seconds
Started Jul 18 05:25:45 PM PDT 24
Finished Jul 18 05:26:26 PM PDT 24
Peak memory 241336 kb
Host smart-71e06b85-23b2-4f07-83fa-27a865eae8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872260680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2872260680
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3084624958
Short name T910
Test name
Test status
Simulation time 2852216991 ps
CPU time 51.22 seconds
Started Jul 18 05:25:45 PM PDT 24
Finished Jul 18 05:26:38 PM PDT 24
Peak memory 253816 kb
Host smart-f93e4f13-1889-4d11-9475-1613257047eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084624958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3084624958
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.613814541
Short name T744
Test name
Test status
Simulation time 1143818148 ps
CPU time 6.4 seconds
Started Jul 18 05:25:42 PM PDT 24
Finished Jul 18 05:25:50 PM PDT 24
Peak memory 241300 kb
Host smart-27ae0e29-7178-46fa-b668-01f91c22b157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613814541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.613814541
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1729209841
Short name T292
Test name
Test status
Simulation time 75094753045 ps
CPU time 259.19 seconds
Started Jul 18 05:25:45 PM PDT 24
Finished Jul 18 05:30:05 PM PDT 24
Peak memory 257756 kb
Host smart-beaec005-2062-44b7-8b74-6ce1428e88e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729209841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1729209841
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2590139536
Short name T492
Test name
Test status
Simulation time 835771831 ps
CPU time 7.67 seconds
Started Jul 18 05:25:50 PM PDT 24
Finished Jul 18 05:26:01 PM PDT 24
Peak memory 233100 kb
Host smart-7462509f-553e-4c05-b526-6ce04889e6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590139536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2590139536
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1309277956
Short name T254
Test name
Test status
Simulation time 49932132298 ps
CPU time 117.76 seconds
Started Jul 18 05:25:50 PM PDT 24
Finished Jul 18 05:27:51 PM PDT 24
Peak memory 253880 kb
Host smart-79498823-2791-47d9-bc8f-111eedf7ac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309277956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1309277956
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4253714502
Short name T304
Test name
Test status
Simulation time 619463246 ps
CPU time 6.04 seconds
Started Jul 18 05:25:50 PM PDT 24
Finished Jul 18 05:25:59 PM PDT 24
Peak memory 239824 kb
Host smart-9b957113-cf2b-40cd-8074-36deccc5c76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253714502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4253714502
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.831116219
Short name T46
Test name
Test status
Simulation time 10824400193 ps
CPU time 9.1 seconds
Started Jul 18 05:25:51 PM PDT 24
Finished Jul 18 05:26:03 PM PDT 24
Peak memory 233232 kb
Host smart-5dfc6eff-6607-4dc2-bd35-c8d9e746d17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831116219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.831116219
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1550879777
Short name T826
Test name
Test status
Simulation time 821708860 ps
CPU time 11.97 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:26:03 PM PDT 24
Peak memory 219508 kb
Host smart-abf3792b-7f83-4231-8511-21c14383c50c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1550879777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1550879777
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2205102696
Short name T420
Test name
Test status
Simulation time 2671549219 ps
CPU time 5.5 seconds
Started Jul 18 05:25:51 PM PDT 24
Finished Jul 18 05:25:59 PM PDT 24
Peak memory 216904 kb
Host smart-787afd38-281b-49fc-8fa7-cb4cf501c67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205102696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2205102696
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.577947585
Short name T761
Test name
Test status
Simulation time 1712616557 ps
CPU time 2.81 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:25:52 PM PDT 24
Peak memory 208200 kb
Host smart-545e8812-19ee-4d37-81c0-68eabb2113cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577947585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.577947585
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1018807840
Short name T602
Test name
Test status
Simulation time 22856814 ps
CPU time 0.8 seconds
Started Jul 18 05:25:50 PM PDT 24
Finished Jul 18 05:25:54 PM PDT 24
Peak memory 206372 kb
Host smart-b3867f05-04c5-49d0-a8c0-922599f35987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018807840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1018807840
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3429672786
Short name T806
Test name
Test status
Simulation time 35118055 ps
CPU time 0.88 seconds
Started Jul 18 05:25:50 PM PDT 24
Finished Jul 18 05:25:54 PM PDT 24
Peak memory 207388 kb
Host smart-34d77807-b759-4203-9795-bce1477cf2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429672786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3429672786
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.593981592
Short name T489
Test name
Test status
Simulation time 170228369335 ps
CPU time 47.52 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:26:37 PM PDT 24
Peak memory 241248 kb
Host smart-af5df253-9469-47db-a92f-7e1fe5467253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593981592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.593981592
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2040649848
Short name T366
Test name
Test status
Simulation time 11260953 ps
CPU time 0.7 seconds
Started Jul 18 05:26:00 PM PDT 24
Finished Jul 18 05:26:03 PM PDT 24
Peak memory 205640 kb
Host smart-9008c4cb-d895-4524-9e62-f6696e0dc384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040649848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2040649848
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2560573006
Short name T1024
Test name
Test status
Simulation time 228949669 ps
CPU time 3.64 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 233076 kb
Host smart-a15006c4-2646-41dd-b88a-5a17797a6655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560573006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2560573006
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2821342324
Short name T703
Test name
Test status
Simulation time 14072500 ps
CPU time 0.78 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:25:52 PM PDT 24
Peak memory 206876 kb
Host smart-6fcdef65-f263-45f8-8f7d-8758764bf4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821342324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2821342324
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.4096181568
Short name T964
Test name
Test status
Simulation time 9741061281 ps
CPU time 83.56 seconds
Started Jul 18 05:25:59 PM PDT 24
Finished Jul 18 05:27:24 PM PDT 24
Peak memory 249660 kb
Host smart-f855e4bc-6d67-4505-bb1f-9f3665392af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096181568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4096181568
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1196478734
Short name T904
Test name
Test status
Simulation time 42473180389 ps
CPU time 200.55 seconds
Started Jul 18 05:26:01 PM PDT 24
Finished Jul 18 05:29:23 PM PDT 24
Peak memory 264344 kb
Host smart-f0ac127b-9e87-436c-8b9a-8fe5c073830a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196478734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1196478734
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3214826101
Short name T193
Test name
Test status
Simulation time 40431798812 ps
CPU time 172.62 seconds
Started Jul 18 05:25:59 PM PDT 24
Finished Jul 18 05:28:53 PM PDT 24
Peak memory 252676 kb
Host smart-ea03b6eb-5d3d-4b36-bafd-c5a1b84ae78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214826101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3214826101
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.959665485
Short name T625
Test name
Test status
Simulation time 502048482 ps
CPU time 7.67 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:25:58 PM PDT 24
Peak memory 249552 kb
Host smart-410f5aa8-4a97-4fc9-a75b-0d23f8d37574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959665485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.959665485
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2785466846
Short name T373
Test name
Test status
Simulation time 5221696505 ps
CPU time 20.55 seconds
Started Jul 18 05:26:03 PM PDT 24
Finished Jul 18 05:26:27 PM PDT 24
Peak memory 225080 kb
Host smart-0464acca-75a1-4631-b17e-97e13ab5e11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785466846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2785466846
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2654738414
Short name T359
Test name
Test status
Simulation time 90649615 ps
CPU time 2.22 seconds
Started Jul 18 05:25:48 PM PDT 24
Finished Jul 18 05:25:54 PM PDT 24
Peak memory 224420 kb
Host smart-96fa8685-d27b-4156-8db1-7912cbd16351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654738414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2654738414
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1562579932
Short name T923
Test name
Test status
Simulation time 14236937408 ps
CPU time 56.32 seconds
Started Jul 18 05:25:48 PM PDT 24
Finished Jul 18 05:26:48 PM PDT 24
Peak memory 233152 kb
Host smart-1fa6c19c-7ce0-4765-b6bb-e89e1be16210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562579932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1562579932
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3596907807
Short name T530
Test name
Test status
Simulation time 630143846 ps
CPU time 5.32 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 224940 kb
Host smart-8d94f5ce-890d-4236-b306-ab0c40f5e9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596907807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3596907807
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1185023760
Short name T714
Test name
Test status
Simulation time 4993308878 ps
CPU time 13.22 seconds
Started Jul 18 05:25:45 PM PDT 24
Finished Jul 18 05:26:00 PM PDT 24
Peak memory 225208 kb
Host smart-6123d427-add7-43d7-a767-cc24f7990092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185023760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1185023760
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2408279252
Short name T949
Test name
Test status
Simulation time 419870210 ps
CPU time 4.18 seconds
Started Jul 18 05:26:03 PM PDT 24
Finished Jul 18 05:26:10 PM PDT 24
Peak memory 223392 kb
Host smart-4bc50548-335d-45d1-bc2a-4d75d3f6c241
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2408279252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2408279252
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1391592727
Short name T290
Test name
Test status
Simulation time 96218738239 ps
CPU time 411.41 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:32:56 PM PDT 24
Peak memory 264320 kb
Host smart-b9ec0a61-3d66-4043-b619-d6feadff4647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391592727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1391592727
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4106375458
Short name T930
Test name
Test status
Simulation time 17647013276 ps
CPU time 45.58 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:26:36 PM PDT 24
Peak memory 216776 kb
Host smart-aef9866d-4291-4dc7-aaec-4a5796f72888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106375458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4106375458
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.255745593
Short name T646
Test name
Test status
Simulation time 1869368469 ps
CPU time 9.38 seconds
Started Jul 18 05:25:47 PM PDT 24
Finished Jul 18 05:26:00 PM PDT 24
Peak memory 216300 kb
Host smart-4b99d296-df85-4080-96d0-3bdf61fd6008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255745593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.255745593
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2101335219
Short name T395
Test name
Test status
Simulation time 23276414 ps
CPU time 0.69 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:25:50 PM PDT 24
Peak memory 205912 kb
Host smart-01738830-a804-4e84-ae78-8f49abf5bb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101335219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2101335219
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3716436726
Short name T942
Test name
Test status
Simulation time 336057245 ps
CPU time 0.84 seconds
Started Jul 18 05:25:45 PM PDT 24
Finished Jul 18 05:25:47 PM PDT 24
Peak memory 206228 kb
Host smart-1b8392e5-ce38-4e91-bc2c-5f5207611893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716436726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3716436726
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1867564165
Short name T344
Test name
Test status
Simulation time 36920718 ps
CPU time 2.38 seconds
Started Jul 18 05:25:46 PM PDT 24
Finished Jul 18 05:25:50 PM PDT 24
Peak memory 224636 kb
Host smart-f3768b0f-0f3a-4cdc-ba78-87dd62d8309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867564165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1867564165
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3141514391
Short name T66
Test name
Test status
Simulation time 15405067 ps
CPU time 0.7 seconds
Started Jul 18 05:26:07 PM PDT 24
Finished Jul 18 05:26:11 PM PDT 24
Peak memory 205696 kb
Host smart-29ce5294-04d8-4c8d-9fbe-45d7a679a442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141514391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3141514391
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.4286796771
Short name T944
Test name
Test status
Simulation time 213491713 ps
CPU time 4.38 seconds
Started Jul 18 05:25:57 PM PDT 24
Finished Jul 18 05:26:02 PM PDT 24
Peak memory 233060 kb
Host smart-24bdf5f8-5c2f-4fff-a7fc-80c496e48e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286796771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4286796771
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.936125999
Short name T480
Test name
Test status
Simulation time 57285234 ps
CPU time 0.83 seconds
Started Jul 18 05:25:58 PM PDT 24
Finished Jul 18 05:26:00 PM PDT 24
Peak memory 207188 kb
Host smart-e72ec99c-81fb-4f06-8a62-97c0a90eb578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936125999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.936125999
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.4234528109
Short name T388
Test name
Test status
Simulation time 137412437351 ps
CPU time 175.47 seconds
Started Jul 18 05:25:58 PM PDT 24
Finished Jul 18 05:28:54 PM PDT 24
Peak memory 267076 kb
Host smart-f6521782-3cd1-4b58-b0df-ceeb80410a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234528109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.4234528109
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2082030276
Short name T340
Test name
Test status
Simulation time 93335655 ps
CPU time 0.86 seconds
Started Jul 18 05:25:59 PM PDT 24
Finished Jul 18 05:26:01 PM PDT 24
Peak memory 217588 kb
Host smart-f7181588-df2c-46ec-8ae1-0c395c568286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082030276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2082030276
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1192647677
Short name T1010
Test name
Test status
Simulation time 6299238728 ps
CPU time 63.13 seconds
Started Jul 18 05:25:58 PM PDT 24
Finished Jul 18 05:27:02 PM PDT 24
Peak memory 241440 kb
Host smart-0d0d0ab0-ee4f-4875-86c1-288869c22248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192647677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1192647677
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.4188127123
Short name T682
Test name
Test status
Simulation time 1074974975 ps
CPU time 16.35 seconds
Started Jul 18 05:25:59 PM PDT 24
Finished Jul 18 05:26:18 PM PDT 24
Peak memory 256412 kb
Host smart-7fbfa809-2a69-465c-976b-e45f6953944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188127123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.4188127123
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.937498423
Short name T168
Test name
Test status
Simulation time 22774554247 ps
CPU time 151.48 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:28:35 PM PDT 24
Peak memory 249784 kb
Host smart-705f73c1-8b69-41e1-8f7a-b301429636e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937498423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.937498423
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3853895726
Short name T48
Test name
Test status
Simulation time 2315427801 ps
CPU time 11.9 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:26:16 PM PDT 24
Peak memory 233280 kb
Host smart-3ea4b67a-593f-4b94-b3f7-de09b532e68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853895726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3853895726
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.919944060
Short name T506
Test name
Test status
Simulation time 124693384 ps
CPU time 2.36 seconds
Started Jul 18 05:26:05 PM PDT 24
Finished Jul 18 05:26:10 PM PDT 24
Peak memory 232848 kb
Host smart-e4487ca8-d527-4f76-b7ab-be4c4ca165fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919944060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.919944060
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2207205840
Short name T970
Test name
Test status
Simulation time 1199373211 ps
CPU time 2.9 seconds
Started Jul 18 05:26:00 PM PDT 24
Finished Jul 18 05:26:05 PM PDT 24
Peak memory 224876 kb
Host smart-d7f5a534-8351-42e6-8058-ec175dfb6276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207205840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2207205840
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4238526178
Short name T1011
Test name
Test status
Simulation time 13064475950 ps
CPU time 13.11 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:26:17 PM PDT 24
Peak memory 233308 kb
Host smart-d3bf1e68-4774-4859-a430-a09764abc68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238526178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4238526178
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.71743896
Short name T391
Test name
Test status
Simulation time 1455556583 ps
CPU time 4.62 seconds
Started Jul 18 05:26:00 PM PDT 24
Finished Jul 18 05:26:06 PM PDT 24
Peak memory 219128 kb
Host smart-b491a415-fc2c-4c78-aba8-7e1291445338
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=71743896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direc
t.71743896
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.962535653
Short name T196
Test name
Test status
Simulation time 7274573285 ps
CPU time 108.86 seconds
Started Jul 18 05:26:05 PM PDT 24
Finished Jul 18 05:27:57 PM PDT 24
Peak memory 257572 kb
Host smart-d984dcde-f7a7-4a5c-bca7-7f70a05776e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962535653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.962535653
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3628690166
Short name T326
Test name
Test status
Simulation time 17044875795 ps
CPU time 39.61 seconds
Started Jul 18 05:26:04 PM PDT 24
Finished Jul 18 05:26:47 PM PDT 24
Peak memory 216816 kb
Host smart-4768ffa0-4f2e-41d4-be1f-61bdeecb0970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628690166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3628690166
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.577541410
Short name T812
Test name
Test status
Simulation time 2993029613 ps
CPU time 4.44 seconds
Started Jul 18 05:26:04 PM PDT 24
Finished Jul 18 05:26:11 PM PDT 24
Peak memory 216708 kb
Host smart-5b64f050-5b98-4e1d-bcc1-2e9d68590931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577541410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.577541410
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1382277022
Short name T654
Test name
Test status
Simulation time 238363809 ps
CPU time 2.36 seconds
Started Jul 18 05:26:02 PM PDT 24
Finished Jul 18 05:26:07 PM PDT 24
Peak memory 216660 kb
Host smart-e1f1b3be-9631-4b94-ae9a-1a19ecf04085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382277022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1382277022
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2549041335
Short name T431
Test name
Test status
Simulation time 50327824 ps
CPU time 0.89 seconds
Started Jul 18 05:26:03 PM PDT 24
Finished Jul 18 05:26:07 PM PDT 24
Peak memory 206212 kb
Host smart-8dda8b55-d5df-4375-8544-ff1c0d5b1c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549041335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2549041335
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1137052068
Short name T450
Test name
Test status
Simulation time 684209487 ps
CPU time 4.42 seconds
Started Jul 18 05:26:00 PM PDT 24
Finished Jul 18 05:26:06 PM PDT 24
Peak memory 224940 kb
Host smart-d9aea647-8f84-46ad-9597-74ecfc550789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137052068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1137052068
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.4016621546
Short name T648
Test name
Test status
Simulation time 12081380 ps
CPU time 0.72 seconds
Started Jul 18 05:20:54 PM PDT 24
Finished Jul 18 05:20:56 PM PDT 24
Peak memory 205112 kb
Host smart-0638f266-70aa-4c4d-9387-ed959b832a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016621546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
016621546
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3322414622
Short name T815
Test name
Test status
Simulation time 68316484 ps
CPU time 0.8 seconds
Started Jul 18 05:20:10 PM PDT 24
Finished Jul 18 05:20:11 PM PDT 24
Peak memory 206852 kb
Host smart-6b8b3b73-3005-49aa-97d8-c05241913ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322414622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3322414622
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2302450474
Short name T653
Test name
Test status
Simulation time 1793014752 ps
CPU time 32.83 seconds
Started Jul 18 05:20:05 PM PDT 24
Finished Jul 18 05:20:38 PM PDT 24
Peak memory 255572 kb
Host smart-4fc338bf-59c4-4e56-9fb5-858072020a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302450474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2302450474
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.219625468
Short name T1008
Test name
Test status
Simulation time 11473355411 ps
CPU time 23.42 seconds
Started Jul 18 05:20:08 PM PDT 24
Finished Jul 18 05:20:33 PM PDT 24
Peak memory 218208 kb
Host smart-20c6753b-652a-46f4-ba0f-3f51f87f9bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219625468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.219625468
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2309914294
Short name T766
Test name
Test status
Simulation time 8105945455 ps
CPU time 70.16 seconds
Started Jul 18 05:20:47 PM PDT 24
Finished Jul 18 05:21:58 PM PDT 24
Peak memory 249848 kb
Host smart-c6a62f5f-e269-48d2-b52b-dc3527338235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309914294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2309914294
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3411233621
Short name T670
Test name
Test status
Simulation time 3106929934 ps
CPU time 58.58 seconds
Started Jul 18 05:20:09 PM PDT 24
Finished Jul 18 05:21:09 PM PDT 24
Peak memory 233252 kb
Host smart-a236dda5-617f-4ec6-a676-62d51e425b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411233621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3411233621
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1092050706
Short name T688
Test name
Test status
Simulation time 8430281226 ps
CPU time 59.29 seconds
Started Jul 18 05:20:06 PM PDT 24
Finished Jul 18 05:21:07 PM PDT 24
Peak memory 241416 kb
Host smart-0ebd3745-e543-47c0-b464-2500a6d18d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092050706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1092050706
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3504614198
Short name T796
Test name
Test status
Simulation time 1175472049 ps
CPU time 16.35 seconds
Started Jul 18 05:20:07 PM PDT 24
Finished Jul 18 05:20:26 PM PDT 24
Peak memory 219300 kb
Host smart-aae69531-71a3-4644-b02b-61c46662dc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504614198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3504614198
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.404445388
Short name T50
Test name
Test status
Simulation time 12223853458 ps
CPU time 56.17 seconds
Started Jul 18 05:20:07 PM PDT 24
Finished Jul 18 05:21:05 PM PDT 24
Peak memory 233300 kb
Host smart-71f109e4-5bf0-4692-ad2a-6ba2c56da712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404445388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.404445388
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.856009786
Short name T438
Test name
Test status
Simulation time 29950696 ps
CPU time 1.08 seconds
Started Jul 18 05:20:05 PM PDT 24
Finished Jul 18 05:20:08 PM PDT 24
Peak memory 218664 kb
Host smart-05b27a9e-9e20-43d5-8790-7de9c7c472a5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856009786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.856009786
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2506991967
Short name T617
Test name
Test status
Simulation time 54045647651 ps
CPU time 36.19 seconds
Started Jul 18 05:20:07 PM PDT 24
Finished Jul 18 05:20:45 PM PDT 24
Peak memory 233164 kb
Host smart-9d0f4853-e1d1-40c8-8212-12bccfcfdc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506991967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2506991967
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4210714258
Short name T781
Test name
Test status
Simulation time 23543107903 ps
CPU time 15.4 seconds
Started Jul 18 05:20:06 PM PDT 24
Finished Jul 18 05:20:23 PM PDT 24
Peak memory 237792 kb
Host smart-f9a03b19-2077-4468-80c9-9ea45507ef65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210714258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4210714258
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2657594974
Short name T143
Test name
Test status
Simulation time 523145867 ps
CPU time 3.86 seconds
Started Jul 18 05:20:07 PM PDT 24
Finished Jul 18 05:20:13 PM PDT 24
Peak memory 223480 kb
Host smart-8a8cc908-ec07-4ebc-b9ac-ce7bb0dc9acc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2657594974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2657594974
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1612490122
Short name T86
Test name
Test status
Simulation time 6090410280 ps
CPU time 119.76 seconds
Started Jul 18 05:20:57 PM PDT 24
Finished Jul 18 05:22:58 PM PDT 24
Peak memory 266660 kb
Host smart-304ecbfa-4357-4b9c-ba06-5879c16eaf13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612490122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1612490122
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.334801156
Short name T465
Test name
Test status
Simulation time 13109005 ps
CPU time 0.77 seconds
Started Jul 18 05:20:06 PM PDT 24
Finished Jul 18 05:20:09 PM PDT 24
Peak memory 205992 kb
Host smart-46bfbeb6-b914-4190-aec4-a9ff0fc5b5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334801156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.334801156
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3623333231
Short name T724
Test name
Test status
Simulation time 2056342093 ps
CPU time 3.99 seconds
Started Jul 18 05:20:07 PM PDT 24
Finished Jul 18 05:20:13 PM PDT 24
Peak memory 216772 kb
Host smart-020b09a4-725e-4dc4-b049-f406cbd9a98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623333231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3623333231
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2329881360
Short name T456
Test name
Test status
Simulation time 51501079 ps
CPU time 1.54 seconds
Started Jul 18 05:20:06 PM PDT 24
Finished Jul 18 05:20:09 PM PDT 24
Peak memory 216624 kb
Host smart-dd3d4bfe-2158-461c-a4c3-b925afeb294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329881360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2329881360
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2315483339
Short name T608
Test name
Test status
Simulation time 295322734 ps
CPU time 0.93 seconds
Started Jul 18 05:20:06 PM PDT 24
Finished Jul 18 05:20:08 PM PDT 24
Peak memory 207232 kb
Host smart-2827f201-82b6-4b54-bebf-7c7141f50bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315483339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2315483339
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.194223438
Short name T896
Test name
Test status
Simulation time 13048758305 ps
CPU time 16.11 seconds
Started Jul 18 05:20:06 PM PDT 24
Finished Jul 18 05:20:25 PM PDT 24
Peak memory 241388 kb
Host smart-d730e699-85e2-44cc-ac3c-aff6ff262b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194223438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.194223438
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2570922411
Short name T636
Test name
Test status
Simulation time 13212172 ps
CPU time 0.73 seconds
Started Jul 18 05:20:51 PM PDT 24
Finished Jul 18 05:20:54 PM PDT 24
Peak memory 205116 kb
Host smart-908c8058-45fd-4f03-b563-9dd5a83a9215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570922411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
570922411
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1403258790
Short name T256
Test name
Test status
Simulation time 747201987 ps
CPU time 5.64 seconds
Started Jul 18 05:20:59 PM PDT 24
Finished Jul 18 05:21:06 PM PDT 24
Peak memory 233144 kb
Host smart-c50253a3-8e87-4102-b1d6-f57793e6fd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403258790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1403258790
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3429485701
Short name T669
Test name
Test status
Simulation time 13858296 ps
CPU time 0.79 seconds
Started Jul 18 05:20:50 PM PDT 24
Finished Jul 18 05:20:51 PM PDT 24
Peak memory 206876 kb
Host smart-b4e6c508-6f4a-4125-95da-214f16ca291f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429485701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3429485701
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1924642553
Short name T885
Test name
Test status
Simulation time 25666203 ps
CPU time 0.75 seconds
Started Jul 18 05:20:57 PM PDT 24
Finished Jul 18 05:20:59 PM PDT 24
Peak memory 216232 kb
Host smart-41e415be-7d07-4318-ae52-2fe7cf37bc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924642553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1924642553
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2722352557
Short name T309
Test name
Test status
Simulation time 44858884950 ps
CPU time 147.4 seconds
Started Jul 18 05:20:53 PM PDT 24
Finished Jul 18 05:23:22 PM PDT 24
Peak memory 257152 kb
Host smart-378a437a-5da6-40bf-85cb-5f6da1c8cca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722352557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2722352557
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3236346179
Short name T554
Test name
Test status
Simulation time 23045299874 ps
CPU time 97.89 seconds
Started Jul 18 05:20:54 PM PDT 24
Finished Jul 18 05:22:33 PM PDT 24
Peak memory 238112 kb
Host smart-786d7c06-8e9f-47cb-8623-e8493f857369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236346179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3236346179
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.403679232
Short name T317
Test name
Test status
Simulation time 1828936341 ps
CPU time 17.45 seconds
Started Jul 18 05:20:57 PM PDT 24
Finished Jul 18 05:21:15 PM PDT 24
Peak memory 224932 kb
Host smart-f3ad61f1-42a4-477f-a412-6b3dca9932dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403679232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.403679232
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.770251535
Short name T83
Test name
Test status
Simulation time 24851227539 ps
CPU time 70.41 seconds
Started Jul 18 05:20:47 PM PDT 24
Finished Jul 18 05:21:58 PM PDT 24
Peak memory 255112 kb
Host smart-19db78e4-1a80-4472-b673-3de5be0a74c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770251535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
770251535
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2175112138
Short name T3
Test name
Test status
Simulation time 1272893349 ps
CPU time 5.32 seconds
Started Jul 18 05:20:50 PM PDT 24
Finished Jul 18 05:20:56 PM PDT 24
Peak memory 224860 kb
Host smart-37302e7c-3d46-43d4-a876-7560834cdb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175112138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2175112138
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1219104785
Short name T587
Test name
Test status
Simulation time 2972260481 ps
CPU time 7.81 seconds
Started Jul 18 05:20:51 PM PDT 24
Finished Jul 18 05:21:01 PM PDT 24
Peak memory 224944 kb
Host smart-cd24aa7d-6b48-4def-b088-b30921ec7e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219104785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1219104785
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1066442477
Short name T444
Test name
Test status
Simulation time 119673291 ps
CPU time 1.07 seconds
Started Jul 18 05:20:57 PM PDT 24
Finished Jul 18 05:20:59 PM PDT 24
Peak memory 217164 kb
Host smart-6cd73c78-3c82-4a61-b528-0e388ae38ede
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066442477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1066442477
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1578406962
Short name T666
Test name
Test status
Simulation time 1579140752 ps
CPU time 7.6 seconds
Started Jul 18 05:20:56 PM PDT 24
Finished Jul 18 05:21:05 PM PDT 24
Peak memory 224960 kb
Host smart-be63794e-c07d-4aa9-a4dd-6adf53e3d4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578406962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1578406962
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4060061052
Short name T244
Test name
Test status
Simulation time 22186813197 ps
CPU time 15.4 seconds
Started Jul 18 05:20:52 PM PDT 24
Finished Jul 18 05:21:10 PM PDT 24
Peak memory 233132 kb
Host smart-183e8b19-8c3b-4eec-baeb-adb4e3186d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060061052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4060061052
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.288678201
Short name T909
Test name
Test status
Simulation time 3253299163 ps
CPU time 12.02 seconds
Started Jul 18 05:20:53 PM PDT 24
Finished Jul 18 05:21:06 PM PDT 24
Peak memory 219736 kb
Host smart-7f454ba8-194d-4796-9f3c-25335195310f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=288678201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.288678201
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.965954641
Short name T615
Test name
Test status
Simulation time 39335116 ps
CPU time 0.93 seconds
Started Jul 18 05:20:56 PM PDT 24
Finished Jul 18 05:20:58 PM PDT 24
Peak memory 207700 kb
Host smart-77b6c7e5-36c7-4a5a-8117-a5e1ddefb771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965954641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.965954641
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.727167601
Short name T679
Test name
Test status
Simulation time 6635551061 ps
CPU time 40.1 seconds
Started Jul 18 05:20:51 PM PDT 24
Finished Jul 18 05:21:32 PM PDT 24
Peak memory 216824 kb
Host smart-116dd82e-fca6-41a4-b00f-c6f9c05195c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727167601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.727167601
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1003208931
Short name T515
Test name
Test status
Simulation time 5587001305 ps
CPU time 17.91 seconds
Started Jul 18 05:20:55 PM PDT 24
Finished Jul 18 05:21:14 PM PDT 24
Peak memory 216676 kb
Host smart-e22fbc53-fa2d-4fec-b93f-31cacc9fa4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003208931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1003208931
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1655692749
Short name T1009
Test name
Test status
Simulation time 746820147 ps
CPU time 7.92 seconds
Started Jul 18 05:20:52 PM PDT 24
Finished Jul 18 05:21:01 PM PDT 24
Peak memory 216708 kb
Host smart-8f5f8b48-672b-47d2-bdf7-7000ed1af31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655692749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1655692749
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3997235569
Short name T401
Test name
Test status
Simulation time 20210765 ps
CPU time 0.77 seconds
Started Jul 18 05:20:51 PM PDT 24
Finished Jul 18 05:20:54 PM PDT 24
Peak memory 206216 kb
Host smart-570872f9-dd29-4ae2-8697-f27176fb7c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997235569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3997235569
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.503513815
Short name T568
Test name
Test status
Simulation time 365769079 ps
CPU time 2.69 seconds
Started Jul 18 05:20:53 PM PDT 24
Finished Jul 18 05:20:57 PM PDT 24
Peak memory 233060 kb
Host smart-3307b5ab-881f-4a63-85e5-4cbc3fca742c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503513815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.503513815
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3792305740
Short name T453
Test name
Test status
Simulation time 18945063 ps
CPU time 0.7 seconds
Started Jul 18 05:20:54 PM PDT 24
Finished Jul 18 05:20:56 PM PDT 24
Peak memory 205668 kb
Host smart-56fa27cd-6701-4d17-b1f4-4bd64d803692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792305740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
792305740
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.121766447
Short name T1
Test name
Test status
Simulation time 1597110000 ps
CPU time 10.63 seconds
Started Jul 18 05:20:49 PM PDT 24
Finished Jul 18 05:21:01 PM PDT 24
Peak memory 224904 kb
Host smart-45051c98-d8d9-4c42-bf97-bf97486001dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121766447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.121766447
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3806551469
Short name T570
Test name
Test status
Simulation time 46926389 ps
CPU time 0.75 seconds
Started Jul 18 05:20:59 PM PDT 24
Finished Jul 18 05:21:00 PM PDT 24
Peak memory 205796 kb
Host smart-bbcab8b5-01da-4a0d-af42-ddea4a9bbcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806551469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3806551469
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1742369677
Short name T247
Test name
Test status
Simulation time 25539177641 ps
CPU time 36.29 seconds
Started Jul 18 05:20:55 PM PDT 24
Finished Jul 18 05:21:32 PM PDT 24
Peak memory 234220 kb
Host smart-8eab9037-1f24-4c26-b821-edc5bcc811ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742369677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1742369677
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3901029852
Short name T299
Test name
Test status
Simulation time 34067779866 ps
CPU time 54.09 seconds
Started Jul 18 05:20:52 PM PDT 24
Finished Jul 18 05:21:47 PM PDT 24
Peak memory 256936 kb
Host smart-3faec9e2-5767-4cd0-a156-9d5f202dceb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901029852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3901029852
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1685480487
Short name T291
Test name
Test status
Simulation time 65822390370 ps
CPU time 298.34 seconds
Started Jul 18 05:20:53 PM PDT 24
Finished Jul 18 05:25:53 PM PDT 24
Peak memory 257020 kb
Host smart-a3f3384c-d603-451b-84f8-89ba1f555906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685480487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1685480487
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1578577653
Short name T146
Test name
Test status
Simulation time 1769639950 ps
CPU time 25.38 seconds
Started Jul 18 05:20:50 PM PDT 24
Finished Jul 18 05:21:16 PM PDT 24
Peak memory 224836 kb
Host smart-6b0972bc-4f49-4cc4-8226-024efe1f96a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578577653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1578577653
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3339249294
Short name T829
Test name
Test status
Simulation time 231271836254 ps
CPU time 209.02 seconds
Started Jul 18 05:20:56 PM PDT 24
Finished Jul 18 05:24:26 PM PDT 24
Peak memory 249708 kb
Host smart-93f3cef9-914a-4f97-a4a5-d5ccb9759a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339249294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3339249294
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3171270894
Short name T953
Test name
Test status
Simulation time 1782624527 ps
CPU time 10 seconds
Started Jul 18 05:20:56 PM PDT 24
Finished Jul 18 05:21:07 PM PDT 24
Peak memory 229472 kb
Host smart-afba0bbb-66dc-4567-a753-b4ca95687222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171270894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3171270894
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2000906645
Short name T642
Test name
Test status
Simulation time 179444622 ps
CPU time 3.37 seconds
Started Jul 18 05:20:56 PM PDT 24
Finished Jul 18 05:21:00 PM PDT 24
Peak memory 224996 kb
Host smart-da42dd29-ef17-4b7d-b7b2-d73a4fb8beb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000906645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2000906645
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1309481653
Short name T610
Test name
Test status
Simulation time 129028717 ps
CPU time 1.09 seconds
Started Jul 18 05:20:57 PM PDT 24
Finished Jul 18 05:20:59 PM PDT 24
Peak memory 217132 kb
Host smart-af071e68-3a1b-43cf-9a4a-463fd1548b0c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309481653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1309481653
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.469835220
Short name T270
Test name
Test status
Simulation time 27167337002 ps
CPU time 20.74 seconds
Started Jul 18 05:20:53 PM PDT 24
Finished Jul 18 05:21:15 PM PDT 24
Peak memory 237736 kb
Host smart-6909b39a-c539-4251-a3ec-05f4c1933f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469835220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
469835220
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2350453853
Short name T916
Test name
Test status
Simulation time 11000402846 ps
CPU time 9.12 seconds
Started Jul 18 05:20:49 PM PDT 24
Finished Jul 18 05:20:58 PM PDT 24
Peak memory 225048 kb
Host smart-89b46240-81c2-42df-9bda-54f3a796685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350453853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2350453853
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1575211144
Short name T799
Test name
Test status
Simulation time 3681761568 ps
CPU time 12.6 seconds
Started Jul 18 05:20:51 PM PDT 24
Finished Jul 18 05:21:05 PM PDT 24
Peak memory 223472 kb
Host smart-7018dfcd-c0ae-4cfe-ac49-76b048be1e0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1575211144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1575211144
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3455884882
Short name T756
Test name
Test status
Simulation time 863986530 ps
CPU time 5.26 seconds
Started Jul 18 05:20:52 PM PDT 24
Finished Jul 18 05:20:59 PM PDT 24
Peak memory 216748 kb
Host smart-f43c0abe-4415-44bc-9173-a335f20816af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455884882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3455884882
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4216051647
Short name T959
Test name
Test status
Simulation time 831718108 ps
CPU time 6.56 seconds
Started Jul 18 05:21:01 PM PDT 24
Finished Jul 18 05:21:08 PM PDT 24
Peak memory 216696 kb
Host smart-ad186ef3-be4f-411c-b77a-9501d355369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216051647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4216051647
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4006733428
Short name T886
Test name
Test status
Simulation time 34639027 ps
CPU time 1.15 seconds
Started Jul 18 05:20:56 PM PDT 24
Finished Jul 18 05:20:58 PM PDT 24
Peak memory 208208 kb
Host smart-8c5f1529-a7d9-4408-8dcf-0d8f05bfa48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006733428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4006733428
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1737795396
Short name T1000
Test name
Test status
Simulation time 55491717 ps
CPU time 0.85 seconds
Started Jul 18 05:20:51 PM PDT 24
Finished Jul 18 05:20:53 PM PDT 24
Peak memory 206264 kb
Host smart-57268089-52e7-4500-9b05-0c3851b28c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737795396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1737795396
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1796266336
Short name T844
Test name
Test status
Simulation time 5397119846 ps
CPU time 10.67 seconds
Started Jul 18 05:20:57 PM PDT 24
Finished Jul 18 05:21:09 PM PDT 24
Peak memory 234316 kb
Host smart-6db61a1a-60ab-46b9-84f6-96b8d4210f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796266336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1796266336
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3659877190
Short name T692
Test name
Test status
Simulation time 13678902 ps
CPU time 0.74 seconds
Started Jul 18 05:21:05 PM PDT 24
Finished Jul 18 05:21:07 PM PDT 24
Peak memory 205752 kb
Host smart-ba107754-b564-4528-93e6-baa30b3a7d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659877190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
659877190
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2547673227
Short name T899
Test name
Test status
Simulation time 187825842 ps
CPU time 2.88 seconds
Started Jul 18 05:21:17 PM PDT 24
Finished Jul 18 05:21:21 PM PDT 24
Peak memory 224836 kb
Host smart-1b0de5c0-0010-4999-af1b-9cefd33bb92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547673227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2547673227
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1604392513
Short name T790
Test name
Test status
Simulation time 53404246 ps
CPU time 0.82 seconds
Started Jul 18 05:20:58 PM PDT 24
Finished Jul 18 05:21:00 PM PDT 24
Peak memory 206884 kb
Host smart-d089ac41-6c90-4f4f-942d-7e607d3c0257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604392513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1604392513
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1370679541
Short name T195
Test name
Test status
Simulation time 58016067933 ps
CPU time 416.07 seconds
Started Jul 18 05:21:03 PM PDT 24
Finished Jul 18 05:28:00 PM PDT 24
Peak memory 252976 kb
Host smart-2b05fb56-9a9c-4e17-9c1f-5e5a48b10fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370679541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1370679541
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2745718171
Short name T194
Test name
Test status
Simulation time 120988542701 ps
CPU time 223.19 seconds
Started Jul 18 05:21:17 PM PDT 24
Finished Jul 18 05:25:00 PM PDT 24
Peak memory 254220 kb
Host smart-23287c99-cdee-499a-8187-a41532e67c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745718171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2745718171
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2419285412
Short name T82
Test name
Test status
Simulation time 44385751700 ps
CPU time 79.09 seconds
Started Jul 18 05:21:15 PM PDT 24
Finished Jul 18 05:22:35 PM PDT 24
Peak memory 224812 kb
Host smart-ccf3cfa2-ec3f-4109-9010-465b24d64b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419285412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2419285412
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2454550191
Short name T316
Test name
Test status
Simulation time 7561334839 ps
CPU time 59.77 seconds
Started Jul 18 05:21:05 PM PDT 24
Finished Jul 18 05:22:06 PM PDT 24
Peak memory 233204 kb
Host smart-e889eebc-0d53-4b04-938e-6c3bdb8db3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454550191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2454550191
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2758379485
Short name T846
Test name
Test status
Simulation time 305809738 ps
CPU time 9.94 seconds
Started Jul 18 05:21:09 PM PDT 24
Finished Jul 18 05:21:19 PM PDT 24
Peak memory 239204 kb
Host smart-dff8496e-85bb-4d1d-b5d5-32d743a2891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758379485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2758379485
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3115361499
Short name T233
Test name
Test status
Simulation time 1767569096 ps
CPU time 19.16 seconds
Started Jul 18 05:21:05 PM PDT 24
Finished Jul 18 05:21:26 PM PDT 24
Peak memory 224936 kb
Host smart-8989059d-72cf-423b-930c-39b9d4798e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115361499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3115361499
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1483378467
Short name T68
Test name
Test status
Simulation time 462215797 ps
CPU time 8.47 seconds
Started Jul 18 05:21:08 PM PDT 24
Finished Jul 18 05:21:18 PM PDT 24
Peak memory 239628 kb
Host smart-46c81818-dad8-48bc-be0f-97424f1c561c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483378467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1483378467
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3287150149
Short name T877
Test name
Test status
Simulation time 27159332 ps
CPU time 1.03 seconds
Started Jul 18 05:20:52 PM PDT 24
Finished Jul 18 05:20:55 PM PDT 24
Peak memory 217120 kb
Host smart-d45774a3-46b7-4a99-be95-58a9b8012c1a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287150149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3287150149
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2657525725
Short name T264
Test name
Test status
Simulation time 316404161 ps
CPU time 3.18 seconds
Started Jul 18 05:21:05 PM PDT 24
Finished Jul 18 05:21:09 PM PDT 24
Peak memory 233084 kb
Host smart-b17eae93-b654-4b58-87cf-61e81028a669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657525725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2657525725
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3362968809
Short name T277
Test name
Test status
Simulation time 4301902913 ps
CPU time 13.47 seconds
Started Jul 18 05:21:20 PM PDT 24
Finished Jul 18 05:21:35 PM PDT 24
Peak memory 233256 kb
Host smart-41b83ff4-ba9d-46f4-a3d8-da6a2875377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362968809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3362968809
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.553055153
Short name T883
Test name
Test status
Simulation time 90561608 ps
CPU time 3.87 seconds
Started Jul 18 05:21:18 PM PDT 24
Finished Jul 18 05:21:22 PM PDT 24
Peak memory 222244 kb
Host smart-ebcf5f33-b681-43c5-b37a-aaa99263e931
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=553055153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.553055153
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2044982805
Short name T405
Test name
Test status
Simulation time 12078293 ps
CPU time 0.74 seconds
Started Jul 18 05:20:59 PM PDT 24
Finished Jul 18 05:21:01 PM PDT 24
Peak memory 206008 kb
Host smart-289923d9-ec05-402b-ba51-f1471c226ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044982805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2044982805
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.314295282
Short name T397
Test name
Test status
Simulation time 891032886 ps
CPU time 3.2 seconds
Started Jul 18 05:20:59 PM PDT 24
Finished Jul 18 05:21:03 PM PDT 24
Peak memory 216636 kb
Host smart-1b111449-b15f-4c74-a835-2f017797985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314295282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.314295282
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1178682572
Short name T589
Test name
Test status
Simulation time 106811857 ps
CPU time 1.91 seconds
Started Jul 18 05:21:18 PM PDT 24
Finished Jul 18 05:21:20 PM PDT 24
Peak memory 216240 kb
Host smart-153718cf-a754-4f83-91ae-a81f1065a912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178682572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1178682572
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3066816404
Short name T365
Test name
Test status
Simulation time 77082201 ps
CPU time 0.86 seconds
Started Jul 18 05:21:15 PM PDT 24
Finished Jul 18 05:21:17 PM PDT 24
Peak memory 206224 kb
Host smart-57d0b2ca-f209-4d02-94d6-ce0da1ec6762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066816404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3066816404
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2404559939
Short name T913
Test name
Test status
Simulation time 1847122592 ps
CPU time 4.57 seconds
Started Jul 18 05:21:17 PM PDT 24
Finished Jul 18 05:21:23 PM PDT 24
Peak memory 224940 kb
Host smart-5b2296d3-f441-4393-93d6-372d10a8e09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404559939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2404559939
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1710630096
Short name T71
Test name
Test status
Simulation time 47612588 ps
CPU time 0.72 seconds
Started Jul 18 05:21:18 PM PDT 24
Finished Jul 18 05:21:20 PM PDT 24
Peak memory 206048 kb
Host smart-d73a8721-63ec-464e-bc5f-016f302bd6a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710630096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
710630096
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3903347324
Short name T622
Test name
Test status
Simulation time 4888912891 ps
CPU time 11.79 seconds
Started Jul 18 05:21:08 PM PDT 24
Finished Jul 18 05:21:21 PM PDT 24
Peak memory 225064 kb
Host smart-3ec83da9-a66c-4fc1-9a95-ac484aedb678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903347324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3903347324
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.59441926
Short name T516
Test name
Test status
Simulation time 46934709 ps
CPU time 0.76 seconds
Started Jul 18 05:21:03 PM PDT 24
Finished Jul 18 05:21:04 PM PDT 24
Peak memory 206856 kb
Host smart-9b0b6e37-0313-4405-adc2-c1be78a7738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59441926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.59441926
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3928502244
Short name T676
Test name
Test status
Simulation time 4704225835 ps
CPU time 38.05 seconds
Started Jul 18 05:21:04 PM PDT 24
Finished Jul 18 05:21:42 PM PDT 24
Peak memory 249624 kb
Host smart-d6fedb7f-1000-4c0d-a5af-fdc0f77f1fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928502244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3928502244
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3892992593
Short name T486
Test name
Test status
Simulation time 43931745509 ps
CPU time 191.3 seconds
Started Jul 18 05:21:14 PM PDT 24
Finished Jul 18 05:24:26 PM PDT 24
Peak memory 251668 kb
Host smart-d5c6f6b9-01a0-4fce-aa47-35688d3d854f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892992593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3892992593
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.752949625
Short name T13
Test name
Test status
Simulation time 93527227 ps
CPU time 4.88 seconds
Started Jul 18 05:21:17 PM PDT 24
Finished Jul 18 05:21:23 PM PDT 24
Peak memory 233108 kb
Host smart-b3df1d4c-877d-4b19-8ee5-6f11d150e798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752949625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.752949625
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.80216685
Short name T246
Test name
Test status
Simulation time 1084305422 ps
CPU time 10.9 seconds
Started Jul 18 05:21:12 PM PDT 24
Finished Jul 18 05:21:23 PM PDT 24
Peak memory 224936 kb
Host smart-f51b734a-2963-4211-95b5-3827469ffb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80216685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.80216685
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.540420125
Short name T857
Test name
Test status
Simulation time 18566524283 ps
CPU time 53.29 seconds
Started Jul 18 05:21:15 PM PDT 24
Finished Jul 18 05:22:10 PM PDT 24
Peak memory 251292 kb
Host smart-ce3f9300-2279-4abe-925d-0e40f0b81828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540420125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.540420125
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2988401841
Short name T404
Test name
Test status
Simulation time 45701907 ps
CPU time 1.07 seconds
Started Jul 18 05:21:04 PM PDT 24
Finished Jul 18 05:21:06 PM PDT 24
Peak memory 217124 kb
Host smart-f5370ba2-445a-48de-a5c6-02b35fa1ab7a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988401841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2988401841
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3782635590
Short name T536
Test name
Test status
Simulation time 525476199 ps
CPU time 6.33 seconds
Started Jul 18 05:21:06 PM PDT 24
Finished Jul 18 05:21:13 PM PDT 24
Peak memory 238576 kb
Host smart-8ab9f735-8d24-4713-ac0d-3bbf4ff2e252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782635590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3782635590
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.327040474
Short name T801
Test name
Test status
Simulation time 108413775 ps
CPU time 3 seconds
Started Jul 18 05:21:19 PM PDT 24
Finished Jul 18 05:21:23 PM PDT 24
Peak memory 233120 kb
Host smart-5a71e7be-902e-4024-9d70-a2063f9cdb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327040474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.327040474
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2788132373
Short name T478
Test name
Test status
Simulation time 2918077490 ps
CPU time 14.48 seconds
Started Jul 18 05:21:04 PM PDT 24
Finished Jul 18 05:21:19 PM PDT 24
Peak memory 223560 kb
Host smart-c38527ac-4669-4900-8320-78583b3bb6b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2788132373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2788132373
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.881110673
Short name T173
Test name
Test status
Simulation time 110497511422 ps
CPU time 468.29 seconds
Started Jul 18 05:21:03 PM PDT 24
Finished Jul 18 05:28:52 PM PDT 24
Peak memory 274052 kb
Host smart-1f46a318-51de-4575-ab1d-1d710bd6434d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881110673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.881110673
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.657424987
Short name T985
Test name
Test status
Simulation time 1080046282 ps
CPU time 17.81 seconds
Started Jul 18 05:21:15 PM PDT 24
Finished Jul 18 05:21:34 PM PDT 24
Peak memory 220324 kb
Host smart-d4041f66-01f2-4b77-bc3f-7faa3584d8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657424987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.657424987
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3654595552
Short name T671
Test name
Test status
Simulation time 9809867221 ps
CPU time 14.18 seconds
Started Jul 18 05:21:18 PM PDT 24
Finished Jul 18 05:21:33 PM PDT 24
Peak memory 216532 kb
Host smart-1ec72f34-e759-49ee-8bc9-4b50dc276ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654595552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3654595552
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2306960473
Short name T935
Test name
Test status
Simulation time 25661963 ps
CPU time 1.46 seconds
Started Jul 18 05:21:16 PM PDT 24
Finished Jul 18 05:21:18 PM PDT 24
Peak memory 216644 kb
Host smart-8f863f39-0532-45fd-8864-d66bd8422410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306960473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2306960473
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1378815521
Short name T348
Test name
Test status
Simulation time 163418459 ps
CPU time 0.82 seconds
Started Jul 18 05:21:15 PM PDT 24
Finished Jul 18 05:21:17 PM PDT 24
Peak memory 206224 kb
Host smart-9d1128ef-2e56-4a29-bee3-8da3976f2130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378815521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1378815521
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4053020125
Short name T606
Test name
Test status
Simulation time 1041404606 ps
CPU time 5.27 seconds
Started Jul 18 05:21:17 PM PDT 24
Finished Jul 18 05:21:23 PM PDT 24
Peak memory 224928 kb
Host smart-d89afc94-72ee-48e2-9ac1-5470bb669650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053020125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4053020125
Directory /workspace/9.spi_device_upload/latest
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