Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2910648	1			T1	19884		T2	1		T3	401
all_values[1]	2910648	1			T1	19884		T2	1		T3	401
all_values[2]	2910648	1			T1	19884		T2	1		T3	401
all_values[3]	2910648	1			T1	19884		T2	1		T3	401
all_values[4]	2910648	1			T1	19884		T2	1		T3	401
all_values[5]	2910648	1			T1	19884		T2	1		T3	401
all_values[6]	2910648	1			T1	19884		T2	1		T3	401
all_values[7]	2910648	1			T1	19884		T2	1		T3	401

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22680906

1

T1

159072

T2

8

T3

3208

auto[1]

604278

1

T11

45

T13

869

T15

40

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23258001

1

T1

158990

T2

8

T3

3208

auto[1]

27183

1

T1

82

T9

256

T11

113

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2849606	1			T1	19827		T2	1		T3	401
all_values[0]	auto[0]	auto[1]	12489	1			T1	57		T9	128		T11	57
all_values[0]	auto[1]	auto[0]	47971	1			T11	6		T13	825		T15	1
all_values[0]	auto[1]	auto[1]	582	1			T11	1		T13	17		T15	2
all_values[1]	auto[0]	auto[0]	2764929	1			T1	19859		T2	1		T3	401
all_values[1]	auto[0]	auto[1]	8125	1			T1	25		T9	128		T11	18
all_values[1]	auto[1]	auto[0]	137103	1			T11	5		T13	2		T15	4
all_values[1]	auto[1]	auto[1]	491	1			T11	1		T15	4		T16	1
all_values[2]	auto[0]	auto[0]	2779432	1			T1	19884		T2	1		T3	401
all_values[2]	auto[0]	auto[1]	3226	1			T11	18		T13	2		T15	3
all_values[2]	auto[1]	auto[0]	127617	1			T11	6		T13	5		T16	3
all_values[2]	auto[1]	auto[1]	373	1			T11	1		T15	1		T16	4
all_values[3]	auto[0]	auto[0]	2877588	1			T1	19884		T2	1		T3	401
all_values[3]	auto[0]	auto[1]	201	1			T11	2		T13	1		T15	2
all_values[3]	auto[1]	auto[0]	32681	1			T11	3		T13	2		T15	2
all_values[3]	auto[1]	auto[1]	178	1			T13	2		T15	5		T16	4
all_values[4]	auto[0]	auto[0]	2824656	1			T1	19884		T2	1		T3	401
all_values[4]	auto[0]	auto[1]	182	1			T11	4		T13	3		T15	4
all_values[4]	auto[1]	auto[0]	85605	1			T13	1		T15	2		T16	2
all_values[4]	auto[1]	auto[1]	205	1			T11	2		T13	2		T15	4
all_values[5]	auto[0]	auto[0]	2881009	1			T1	19884		T2	1		T3	401
all_values[5]	auto[0]	auto[1]	180	1			T13	3		T15	2		T16	2
all_values[5]	auto[1]	auto[0]	29277	1			T11	5		T13	2		T15	4
all_values[5]	auto[1]	auto[1]	182	1			T13	3		T15	2		T16	2
all_values[6]	auto[0]	auto[0]	2836659	1			T1	19884		T2	1		T3	401
all_values[6]	auto[0]	auto[1]	183	1			T11	1		T13	3		T15	4
all_values[6]	auto[1]	auto[0]	73607	1			T11	5		T13	2		T15	1
all_values[6]	auto[1]	auto[1]	199	1			T11	4		T13	2		T15	3
all_values[7]	auto[0]	auto[0]	2842262	1			T1	19884		T2	1		T3	401
all_values[7]	auto[0]	auto[1]	179	1			T11	2		T13	4		T15	2
all_values[7]	auto[1]	auto[0]	67999	1			T11	4		T13	2		T15	2
all_values[7]	auto[1]	auto[1]	208	1			T11	2		T13	2		T15	3