Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33529	1			T1	120		T3	156		T9	280
auto[SpiFlashAddrCfg]	7812	1			T1	41		T3	8		T8	4
auto[SpiFlashAddr3b]	9379	1			T1	58		T2	1		T3	16
auto[SpiFlashAddr4b]	7726	1			T1	26		T2	1		T3	30

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32611

1

T1

135

T2

2

T3

71

auto[1]

25835

1

T1

110

T3

139

T9

103

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31505

1

T1

159

T2

1

T3

50

auto[1]

26941

1

T1

86

T2

1

T3

160

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38230	1			T1	119		T3	174		T9	298
values[1]	1067	1			T1	12		T3	2		T9	7
values[2]	1463	1			T1	3		T3	1		T4	1
values[3]	1464	1			T1	16		T2	1		T3	2
values[4]	1490	1			T1	10		T9	7		T10	2
values[5]	1610	1			T1	20		T3	2		T9	2
values[6]	1521	1			T1	11		T3	3		T9	4
values[7]	1424	1			T1	10		T2	1		T3	3
values[8]	10177	1			T1	44		T3	23		T4	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30349

1

T3

210

T8

10

T10

48

auto[1]

28097

1

T1

245

T2

2

T4

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55212

1

T1

234

T2

2

T3

194

write

3234

1

T1

11

T3

16

T9

24

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19703

1

T1

102

T2

2

T3

37

valids[0x1]

38743

1

T1

143

T3

173

T8

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1542	1			T1	7		T3	2		T9	7
internal_process_ops[0x5a]	1658	1			T1	12		T3	3		T9	8
internal_process_ops[0x05]	19507	1			T1	34		T3	132		T9	210
internal_process_ops[0x35]	1651	1			T1	6		T3	2		T9	5
internal_process_ops[0x15]	1580	1			T1	9		T3	2		T9	6
internal_process_ops[0x03]	1171	1			T1	2		T3	3		T4	1
internal_process_ops[0x0b]	1025	1			T1	1		T3	2		T9	1
internal_process_ops[0x3b]	1098	1			T1	5		T3	2		T4	2
internal_process_ops[0x6b]	1062	1			T1	5		T3	2		T8	2
internal_process_ops[0xbb]	1081	1			T1	3		T2	1		T3	4
internal_process_ops[0xeb]	1108	1			T1	2		T2	1		T3	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56862

1

T1

237

T2

2

T3

206

auto[1]

1584

1

T1

8

T3

4

T9

17

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56210

1

T1

237

T2

2

T3

201

auto[1]

2236

1

T1

8

T3

9

T9

16

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9771

1

T3

45

T10

42

T11

57

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6056

1

T3

111

T11

24

T13

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2168

1

T3

2

T8

4

T10

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1938

1

T3

6

T11

14

T13

5

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2562

1

T3

4

T8

4

T11

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2332

1

T3

7

T11

21

T13

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2042

1

T3

11

T8

2

T11

13

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1882

1

T3

8

T11

19

T13

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

103

1

T11

1

T13

1

T16

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

100

1

T174

1

T175

2

T176

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T11

2

T39

1

T16

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

103

1

T11

1

T38

1

T39

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

120

1

T10

4

T11

2

T12

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

72

1

T39

3

T44

1

T18

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

75

1

T11

2

T39

1

T16

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

111

1

T38

1

T40

2

T16

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

124

1

T3

3

T11

2

T12

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

99

1

T38

4

T39

1

T43

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

85

1

T38

2

T39

3

T44

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

86

1

T3

2

T39

3

T16

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

105

1

T3

6

T25

2

T38

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

117

1

T38

4

T39

2

T44

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

122

1

T3

3

T38

2

T16

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

87

1

T3

2

T11

1

T38

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9430

1

T1

69

T9

228

T24

33

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7448

1

T1

50

T9

43

T24

83

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1574

1

T1

25

T9

9

T24

6

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1371

1

T1

13

T9

7

T24

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1854

1

T1

21

T2

1

T4

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1836

1

T1

31

T9

21

T24

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1545

1

T1

13

T2

1

T9

11

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1403

1

T1

12

T9

14

T24

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

116

1

T1

1

T177

2

T178

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

105

1

T9

3

T94

1

T140

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

94

1

T9

1

T94

2

T35

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

114

1

T9

5

T24

4

T178

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

100

1

T9

1

T24

1

T177

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

82

1

T1

2

T177

2

T179

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

109

1

T24

1

T84

1

T180

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

92

1

T1

1

T9

4

T24

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

97

1

T1

1

T177

1

T179

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

122

1

T1

3

T177

2

T179

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

93

1

T9

1

T179

2

T181

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

89

1

T1

2

T9

3

T24

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

100

1

T177

2

T178

1

T179

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

103

1

T9

2

T179

2

T182

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

118

1

T1

1

T9

4

T177

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

102

1

T35

2

T181

8

T180

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3946	1			T3	16		T11	31		T12	2
auto[0]	values[0]	valids[0x1]	14827	1			T3	158		T10	46		T11	72
auto[0]	values[1]	valids[0x1]	562	1			T3	2		T11	7		T13	2
auto[0]	values[2]	valids[0x0]	551	1			T11	1		T38	7		T183	2
auto[0]	values[2]	valids[0x1]	265	1			T3	1		T11	3		T13	4
auto[0]	values[3]	valids[0x0]	545	1			T3	1		T8	2		T11	2
auto[0]	values[3]	valids[0x1]	330	1			T3	1		T11	2		T13	1
auto[0]	values[4]	valids[0x0]	576	1			T10	2		T11	8		T25	2
auto[0]	values[4]	valids[0x1]	322	1			T11	2		T13	1		T38	7
auto[0]	values[5]	valids[0x0]	580	1			T3	1		T11	3		T38	3
auto[0]	values[5]	valids[0x1]	314	1			T3	1		T11	3		T13	3
auto[0]	values[6]	valids[0x0]	566	1			T3	3		T11	8		T12	2
auto[0]	values[6]	valids[0x1]	335	1			T11	4		T38	5		T39	1
auto[0]	values[7]	valids[0x0]	570	1			T3	3		T11	5		T13	2
auto[0]	values[7]	valids[0x1]	302	1			T11	3		T38	1		T39	4
auto[0]	values[8]	valids[0x0]	3583	1			T3	13		T8	6		T11	30
auto[0]	values[8]	valids[0x1]	2175	1			T3	10		T8	2		T11	24
auto[1]	values[0]	valids[0x0]	3932	1			T1	40		T9	37		T24	25
auto[1]	values[0]	valids[0x1]	15525	1			T1	79		T9	261		T24	104
auto[1]	values[1]	valids[0x1]	505	1			T1	12		T9	7		T24	4
auto[1]	values[2]	valids[0x0]	376	1			T4	1		T9	3		T177	3
auto[1]	values[2]	valids[0x1]	271	1			T1	3		T9	3		T177	5
auto[1]	values[3]	valids[0x0]	349	1			T1	11		T2	1		T24	7
auto[1]	values[3]	valids[0x1]	240	1			T1	5		T9	2		T24	3
auto[1]	values[4]	valids[0x0]	354	1			T1	5		T9	3		T24	2
auto[1]	values[4]	valids[0x1]	238	1			T1	5		T9	4		T24	2
auto[1]	values[5]	valids[0x0]	440	1			T1	14		T24	7		T37	3
auto[1]	values[5]	valids[0x1]	276	1			T1	6		T9	2		T24	4
auto[1]	values[6]	valids[0x0]	382	1			T1	2		T9	2		T24	3
auto[1]	values[6]	valids[0x1]	238	1			T1	9		T9	2		T24	2
auto[1]	values[7]	valids[0x0]	351	1			T1	7		T2	1		T94	2
auto[1]	values[7]	valids[0x1]	201	1			T1	3		T9	1		T177	3
auto[1]	values[8]	valids[0x0]	2602	1			T1	23		T4	2		T9	21
auto[1]	values[8]	valids[0x1]	1817	1			T1	21		T9	15		T24	13