Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3409874

1

T1

5070

T2

49

T3

8291

auto[1]

27033

1

T1

25

T3

130

T9

203

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

845502

1

T1

56

T2

49

T3

35

auto[1]

2591405

1

T1

5039

T3

8386

T9

10868

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	661098	1			T1	20		T2	45		T3	3173
auto[524288:1048575]	351851	1			T1	1424		T4	556		T9	25
auto[1048576:1572863]	364172	1			T1	1884		T2	4		T3	20
auto[1572864:2097151]	399313	1			T1	23		T3	1874		T9	272
auto[2097152:2621439]	378691	1			T1	1184		T3	16		T4	2203
auto[2621440:3145727]	404367	1			T1	17		T3	264		T4	348
auto[3145728:3670015]	435275	1			T1	26		T3	2804		T4	3
auto[3670016:4194303]	442140	1			T1	517		T3	270		T4	7

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2625534

1

T1

5093

T2

7

T3

8416

auto[1]

811373

1

T1

2

T2

42

T3

5

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2926446

1

T1

4186

T2

49

T3

8420

auto[1]

510461

1

T1

909

T3

1

T9

3002

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	199502	1			T1	1		T2	45		T3	5
auto[0]	auto[0]	auto[0:524287]	auto[1]	358741	1			T1	19		T3	3143		T9	2751
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	83436	1			T1	9		T4	556		T9	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	201769	1			T1	1025		T9	22		T11	256
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	82673	1			T1	3		T2	4		T3	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	225813	1			T1	1368		T3	1		T9	387
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	82071	1			T1	10		T3	2		T9	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	246947	1			T1	9		T3	1818		T9	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	85800	1			T1	10		T3	1		T4	2203
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	242663	1			T1	1173		T3	1		T11	1494
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	77674	1			T1	6		T3	8		T4	348
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	272117	1			T1	5		T3	256		T9	132
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	114850	1			T1	3		T3	3		T4	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	258961	1			T1	11		T3	2788		T9	3496
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	108658	1			T1	2		T3	4		T4	7
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	262331	1			T1	515		T3	258		T9	904
auto[0]	auto[1]	auto[0:524287]	auto[0]	1021	1			T9	1		T38	10		T16	7
auto[0]	auto[1]	auto[0:524287]	auto[1]	98506	1			T38	7468		T16	4638		T177	1384
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	946	1			T9	1		T38	1		T16	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	62939	1			T1	384		T16	1655		T94	237
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2065	1			T1	1		T9	3		T38	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	50113	1			T1	512		T38	1		T39	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	702	1			T9	1		T24	2		T16	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	64468	1			T9	256		T16	1411		T84	256
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	502	1			T11	2		T27	4		T38	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	46859	1			T38	256		T39	106		T35	513
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	554	1			T9	1		T11	1		T39	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	51505	1			T9	512		T11	1297		T38	703
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	691	1			T1	3		T24	1		T38	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	57390	1			T1	1		T43	4		T178	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	692	1			T3	1		T9	4		T24	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	66915	1			T9	2219		T24	1		T16	4779
auto[1]	auto[0]	auto[0:524287]	auto[0]	473	1			T3	2		T9	2		T10	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	2030	1			T3	23		T9	57		T10	36
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	410	1			T1	1		T16	2		T43	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1988	1			T1	5		T16	3		T177	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	329	1			T3	1		T9	3		T24	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2443	1			T3	16		T9	15		T24	42
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	374	1			T1	4		T3	2		T9	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	4328	1			T3	52		T9	8		T38	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	356	1			T1	1		T3	1		T11	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2108	1			T3	13		T177	30		T178	10
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	290	1			T1	1		T9	4		T11	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1823	1			T1	5		T9	88		T13	127
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	404	1			T3	1		T9	1		T11	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2497	1			T3	12		T9	3		T11	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	358	1			T3	2		T9	3		T11	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2229	1			T3	5		T9	13		T38	94
auto[1]	auto[1]	auto[0:524287]	auto[0]	131	1			T38	3		T16	1		T94	8
auto[1]	auto[1]	auto[0:524287]	auto[1]	694	1			T38	115		T16	1		T179	12
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	87	1			T94	5		T140	1		T181	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	276	1			T181	2		T174	4		T237	5
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	86	1			T38	1		T39	1		T177	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	650	1			T38	10		T39	5		T177	7
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	56	1			T44	3		T18	2		T176	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	367	1			T176	5		T78	1		T79	9
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	59	1			T35	1		T18	1		T249	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	344	1			T35	5		T249	2		T29	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	66	1			T39	2		T21	1		T174	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	338	1			T39	17		T21	1		T176	22
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	75	1			T1	1		T178	3		T35	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	407	1			T1	7		T178	65		T35	23
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	111	1			T9	1		T24	1		T16	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	846	1			T9	3		T24	4		T16	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2095442	1			T1	4169		T2	7		T3	8286
auto[0]	auto[0]	auto[1]	808564	1			T2	42		T3	4		T4	3105
auto[0]	auto[1]	auto[0]	503602	1			T1	901		T3	1		T9	2997
auto[0]	auto[1]	auto[1]	2266	1			T9	1		T250	1		T178	1
auto[1]	auto[0]	auto[0]	22007	1			T1	16		T3	129		T9	196
auto[1]	auto[0]	auto[1]	433	1			T1	1		T3	1		T9	3
auto[1]	auto[1]	auto[0]	4483	1			T1	7		T9	4		T24	4
auto[1]	auto[1]	auto[1]	110	1			T1	1		T24	1		T39	2