Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2910648	1			T1	19884		T2	1		T3	401
all_pins[1]	2910648	1			T1	19884		T2	1		T3	401
all_pins[2]	2910648	1			T1	19884		T2	1		T3	401
all_pins[3]	2910648	1			T1	19884		T2	1		T3	401
all_pins[4]	2910648	1			T1	19884		T2	1		T3	401
all_pins[5]	2910648	1			T1	19884		T2	1		T3	401
all_pins[6]	2910648	1			T1	19884		T2	1		T3	401
all_pins[7]	2910648	1			T1	19884		T2	1		T3	401

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23208334	1			T1	159072		T2	8		T3	3208
values[0x1]	76850	1			T11	11		T13	33		T15	24
transitions[0x0=>0x1]	75525	1			T11	11		T13	30		T15	20
transitions[0x1=>0x0]	75541	1			T11	11		T13	30		T15	20

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2910018	1			T1	19884		T2	1		T3	401
all_pins[0]	values[0x1]	630	1			T11	1		T13	22		T15	2
all_pins[0]	transitions[0x0=>0x1]	421	1			T11	1		T13	22		T15	2
all_pins[0]	transitions[0x1=>0x0]	315	1			T11	1		T15	4		T17	1
all_pins[1]	values[0x0]	2910124	1			T1	19884		T2	1		T3	401
all_pins[1]	values[0x1]	524	1			T11	1		T15	4		T16	1
all_pins[1]	transitions[0x0=>0x1]	311	1			T11	1		T15	4		T16	1
all_pins[1]	transitions[0x1=>0x0]	183	1			T11	1		T15	1		T16	4
all_pins[2]	values[0x0]	2910252	1			T1	19884		T2	1		T3	401
all_pins[2]	values[0x1]	396	1			T11	1		T15	1		T16	4
all_pins[2]	transitions[0x0=>0x1]	352	1			T11	1		T15	1		T16	3
all_pins[2]	transitions[0x1=>0x0]	134	1			T13	2		T15	5		T16	3
all_pins[3]	values[0x0]	2910470	1			T1	19884		T2	1		T3	401
all_pins[3]	values[0x1]	178	1			T13	2		T15	5		T16	4
all_pins[3]	transitions[0x0=>0x1]	127	1			T13	2		T15	3		T16	4
all_pins[3]	transitions[0x1=>0x0]	154	1			T11	2		T13	2		T15	2
all_pins[4]	values[0x0]	2910443	1			T1	19884		T2	1		T3	401
all_pins[4]	values[0x1]	205	1			T11	2		T13	2		T15	4
all_pins[4]	transitions[0x0=>0x1]	164	1			T11	2		T13	1		T15	4
all_pins[4]	transitions[0x1=>0x0]	1280	1			T13	2		T15	2		T16	2
all_pins[5]	values[0x0]	2909327	1			T1	19884		T2	1		T3	401
all_pins[5]	values[0x1]	1321	1			T13	3		T15	2		T16	2
all_pins[5]	transitions[0x0=>0x1]	647	1			T13	2		T15	1		T16	1
all_pins[5]	transitions[0x1=>0x0]	72714	1			T11	4		T13	1		T15	2
all_pins[6]	values[0x0]	2837260	1			T1	19884		T2	1		T3	401
all_pins[6]	values[0x1]	73388	1			T11	4		T13	2		T15	3
all_pins[6]	transitions[0x0=>0x1]	73351	1			T11	4		T13	2		T15	3
all_pins[6]	transitions[0x1=>0x0]	171	1			T11	2		T13	2		T15	3
all_pins[7]	values[0x0]	2910440	1			T1	19884		T2	1		T3	401
all_pins[7]	values[0x1]	208	1			T11	2		T13	2		T15	3
all_pins[7]	transitions[0x0=>0x1]	152	1			T11	2		T13	1		T15	2
all_pins[7]	transitions[0x1=>0x0]	590	1			T11	1		T13	21		T15	1