Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17383

1

T3

71

T8

10

T10

48

auto[1]

12966

1

T3

139

T11

84

T13

27

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4164	1			T11	20		T27	6		T38	75
values[1]	4215	1			T8	10		T11	20		T12	31
values[2]	4180	1			T11	42		T38	82		T39	80
values[3]	3590	1			T11	43		T25	14		T38	34
values[4]	3584	1			T3	124		T13	24		T38	90
values[5]	3608	1			T3	33		T10	48		T11	41
values[6]	3386	1			T3	20		T11	42		T119	4
values[7]	3622	1			T3	33		T183	2		T117	14

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3873	1			T11	20		T12	31		T38	60
values[1]	3888	1			T3	33		T11	41		T38	70
values[2]	3940	1			T3	33		T11	42		T25	14
values[3]	3976	1			T16	123		T43	20		T44	60
values[4]	2976	1			T8	10		T10	48		T11	20
values[5]	3897	1			T3	20		T11	22		T13	150
values[6]	3564	1			T11	20		T117	14		T39	40
values[7]	4235	1			T3	124		T11	43		T13	24

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	173	1			T118	18		T16	14		T223	12
auto[0]	values[0]	values[1]	209	1			T38	13		T43	18		T21	10
auto[0]	values[0]	values[2]	321	1			T204	8		T213	15		T251	10
auto[0]	values[0]	values[3]	437	1			T16	12		T43	15		T174	9
auto[0]	values[0]	values[4]	365	1			T27	6		T39	19		T21	10
auto[0]	values[0]	values[5]	274	1			T38	42		T44	11		T234	12
auto[0]	values[0]	values[6]	220	1			T11	10		T39	9		T18	15
auto[0]	values[0]	values[7]	263	1			T16	11		T252	20		T234	12
auto[0]	values[1]	values[0]	554	1			T11	9		T12	31		T38	10
auto[0]	values[1]	values[1]	401	1			T216	8		T176	72		T233	37
auto[0]	values[1]	values[2]	258	1			T176	27		T253	18		T146	22
auto[0]	values[1]	values[3]	271	1			T44	10		T18	12		T88	6
auto[0]	values[1]	values[4]	167	1			T8	10		T44	13		T209	12
auto[0]	values[1]	values[5]	506	1			T13	139		T38	114		T201	8
auto[0]	values[1]	values[6]	289	1			T18	14		T208	13		T21	9
auto[0]	values[1]	values[7]	227	1			T38	11		T18	13		T208	10
auto[0]	values[2]	values[0]	268	1			T38	17		T39	8		T16	13
auto[0]	values[2]	values[1]	315	1			T39	6		T44	14		T199	13
auto[0]	values[2]	values[2]	341	1			T11	11		T38	52		T235	14
auto[0]	values[2]	values[3]	216	1			T16	25		T44	14		T18	14
auto[0]	values[2]	values[4]	214	1			T18	11		T254	8		T146	17
auto[0]	values[2]	values[5]	284	1			T11	13		T16	13		T208	12
auto[0]	values[2]	values[6]	332	1			T43	11		T44	11		T208	14
auto[0]	values[2]	values[7]	306	1			T175	10		T237	20		T212	18
auto[0]	values[3]	values[0]	164	1			T18	17		T197	8		T199	10
auto[0]	values[3]	values[1]	299	1			T255	4		T18	13		T137	20
auto[0]	values[3]	values[2]	406	1			T25	14		T90	18		T204	14
auto[0]	values[3]	values[3]	253	1			T16	14		T18	12		T196	4
auto[0]	values[3]	values[4]	118	1			T256	12		T168	13		T226	13
auto[0]	values[3]	values[5]	243	1			T257	4		T199	13		T234	12
auto[0]	values[3]	values[6]	228	1			T18	3		T174	12		T168	13
auto[0]	values[3]	values[7]	360	1			T11	28		T38	23		T39	16
auto[0]	values[4]	values[0]	341	1			T38	12		T175	16		T234	9
auto[0]	values[4]	values[1]	240	1			T38	42		T258	2		T18	15
auto[0]	values[4]	values[2]	234	1			T18	16		T21	24		T78	53
auto[0]	values[4]	values[3]	319	1			T44	14		T208	21		T174	13
auto[0]	values[4]	values[4]	219	1			T38	9		T39	16		T259	8
auto[0]	values[4]	values[5]	231	1			T260	12		T237	9		T261	4
auto[0]	values[4]	values[6]	198	1			T168	15		T78	11		T213	8
auto[0]	values[4]	values[7]	412	1			T3	13		T13	8		T21	10
auto[0]	values[5]	values[0]	376	1			T211	20		T201	9		T262	4
auto[0]	values[5]	values[1]	305	1			T3	20		T11	28		T263	8
auto[0]	values[5]	values[2]	354	1			T208	41		T21	8		T229	31
auto[0]	values[5]	values[3]	107	1			T16	9		T176	12		T226	14
auto[0]	values[5]	values[4]	352	1			T10	48		T38	74		T44	11
auto[0]	values[5]	values[5]	235	1			T16	13		T18	13		T78	29
auto[0]	values[5]	values[6]	153	1			T39	14		T201	9		T264	4
auto[0]	values[5]	values[7]	255	1			T38	11		T39	15		T199	7
auto[0]	values[6]	values[0]	153	1			T119	4		T228	8		T175	9
auto[0]	values[6]	values[1]	199	1			T208	11		T265	8		T237	14
auto[0]	values[6]	values[2]	220	1			T11	12		T18	10		T78	66
auto[0]	values[6]	values[3]	393	1			T266	4		T234	9		T146	20
auto[0]	values[6]	values[4]	79	1			T11	13		T267	2		T268	2
auto[0]	values[6]	values[5]	258	1			T3	14		T176	7		T199	9
auto[0]	values[6]	values[6]	223	1			T234	12		T204	6		T78	57
auto[0]	values[6]	values[7]	142	1			T18	5		T174	14		T175	11
auto[0]	values[7]	values[0]	262	1			T43	13		T18	16		T201	10
auto[0]	values[7]	values[1]	197	1			T217	6		T269	4		T215	8
auto[0]	values[7]	values[2]	355	1			T3	24		T16	12		T43	7
auto[0]	values[7]	values[3]	249	1			T16	9		T21	11		T176	10
auto[0]	values[7]	values[4]	285	1			T39	13		T18	16		T208	62
auto[0]	values[7]	values[5]	197	1			T18	21		T206	12		T168	9
auto[0]	values[7]	values[6]	361	1			T117	14		T18	17		T21	17
auto[0]	values[7]	values[7]	197	1			T183	2		T168	15		T237	10
auto[1]	values[0]	values[0]	152	1			T16	8		T41	22		T18	12
auto[1]	values[0]	values[1]	239	1			T38	7		T43	2		T139	12
auto[1]	values[0]	values[2]	230	1			T40	2		T204	16		T213	9
auto[1]	values[0]	values[3]	408	1			T16	8		T43	5		T174	20
auto[1]	values[0]	values[4]	298	1			T39	7		T21	11		T174	39
auto[1]	values[0]	values[5]	241	1			T38	13		T44	9		T270	10
auto[1]	values[0]	values[6]	138	1			T11	10		T39	11		T18	8
auto[1]	values[0]	values[7]	196	1			T16	9		T234	14		T229	7
auto[1]	values[1]	values[0]	297	1			T11	11		T38	10		T18	12
auto[1]	values[1]	values[1]	172	1			T176	10		T233	6		T226	7
auto[1]	values[1]	values[2]	128	1			T176	8		T146	21		T213	11
auto[1]	values[1]	values[3]	214	1			T44	10		T18	9		T208	7
auto[1]	values[1]	values[4]	74	1			T44	7		T168	8		T205	5
auto[1]	values[1]	values[5]	209	1			T13	11		T38	15		T201	12
auto[1]	values[1]	values[6]	230	1			T18	12		T208	7		T21	12
auto[1]	values[1]	values[7]	218	1			T38	20		T18	7		T208	10
auto[1]	values[2]	values[0]	212	1			T38	3		T39	34		T16	10
auto[1]	values[2]	values[1]	340	1			T39	32		T44	6		T199	29
auto[1]	values[2]	values[2]	163	1			T11	9		T38	10		T18	8
auto[1]	values[2]	values[3]	184	1			T16	15		T44	6		T18	6
auto[1]	values[2]	values[4]	187	1			T18	10		T146	11		T226	12
auto[1]	values[2]	values[5]	262	1			T11	9		T16	7		T208	8
auto[1]	values[2]	values[6]	319	1			T43	9		T44	9		T208	6
auto[1]	values[2]	values[7]	237	1			T175	10		T237	13		T204	9
auto[1]	values[3]	values[0]	134	1			T18	8		T199	10		T271	7
auto[1]	values[3]	values[1]	145	1			T18	8		T174	12		T272	16
auto[1]	values[3]	values[2]	280	1			T236	18		T204	8		T205	53
auto[1]	values[3]	values[3]	227	1			T16	6		T18	8		T214	7
auto[1]	values[3]	values[4]	121	1			T168	7		T273	20		T226	7
auto[1]	values[3]	values[5]	192	1			T199	16		T234	8		T170	6
auto[1]	values[3]	values[6]	219	1			T18	22		T174	8		T168	7
auto[1]	values[3]	values[7]	201	1			T11	15		T38	11		T39	6
auto[1]	values[4]	values[0]	128	1			T38	8		T175	8		T234	11
auto[1]	values[4]	values[1]	198	1			T38	8		T18	10		T234	6
auto[1]	values[4]	values[2]	82	1			T18	7		T21	19		T78	10
auto[1]	values[4]	values[3]	139	1			T44	6		T208	39		T174	8
auto[1]	values[4]	values[4]	109	1			T38	11		T39	13		T78	39
auto[1]	values[4]	values[5]	168	1			T237	11		T78	14		T226	14
auto[1]	values[4]	values[6]	142	1			T168	6		T210	6		T78	9
auto[1]	values[4]	values[7]	424	1			T3	111		T13	16		T21	16
auto[1]	values[5]	values[0]	274	1			T201	11		T146	5		T274	4
auto[1]	values[5]	values[1]	169	1			T3	13		T11	13		T195	10
auto[1]	values[5]	values[2]	181	1			T208	8		T21	12		T229	5
auto[1]	values[5]	values[3]	63	1			T16	11		T176	8		T226	6
auto[1]	values[5]	values[4]	181	1			T38	14		T44	9		T21	22
auto[1]	values[5]	values[5]	166	1			T16	9		T18	7		T78	9
auto[1]	values[5]	values[6]	99	1			T39	6		T201	11		T213	9
auto[1]	values[5]	values[7]	338	1			T38	9		T39	30		T42	6
auto[1]	values[6]	values[0]	210	1			T175	26		T176	7		T78	67
auto[1]	values[6]	values[1]	176	1			T275	10		T208	9		T237	6
auto[1]	values[6]	values[2]	271	1			T11	10		T247	20		T18	12
auto[1]	values[6]	values[3]	334	1			T234	11		T146	10		T276	7
auto[1]	values[6]	values[4]	51	1			T11	7		T277	9		T278	10
auto[1]	values[6]	values[5]	316	1			T3	6		T176	49		T199	11
auto[1]	values[6]	values[6]	180	1			T234	8		T204	14		T78	12
auto[1]	values[6]	values[7]	181	1			T18	15		T174	6		T175	9
auto[1]	values[7]	values[0]	175	1			T43	7		T18	7		T279	2
auto[1]	values[7]	values[1]	284	1			T214	7		T146	48		T271	11
auto[1]	values[7]	values[2]	116	1			T3	9		T16	13		T43	13
auto[1]	values[7]	values[3]	162	1			T16	14		T21	11		T176	16
auto[1]	values[7]	values[4]	156	1			T39	7		T18	4		T208	14
auto[1]	values[7]	values[5]	115	1			T18	25		T280	12		T168	12
auto[1]	values[7]	values[6]	233	1			T18	9		T21	5		T176	5
auto[1]	values[7]	values[7]	278	1			T168	26		T237	15		T78	92