Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	412	1			T3	1		T11	3		T38	4
auto[ReadAddrCrossIntoMailbox]	309	1			T3	1		T38	1		T39	3
auto[ReadAddrCrossOutOfMailbox]	313	1			T3	1		T11	5		T38	3
auto[ReadAddrCrossAllMailbox]	218	1			T3	1		T11	2		T38	3
auto[ReadAddrOutsideMailbox]	3718	1			T3	11		T8	4		T10	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2439

1

T3

8

T8

2

T10

1

auto[1]

2531

1

T3

7

T8

2

T10

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	908	1			T3	3		T11	7		T13	1
read_ops[0x0b]	802	1			T3	2		T11	10		T13	5
read_ops[0x3b]	826	1			T3	2		T11	6		T12	2
read_ops[0x6b]	790	1			T3	2		T8	2		T11	11
read_ops[0xbb]	819	1			T3	4		T8	2		T11	4
read_ops[0xeb]	825	1			T3	2		T10	2		T11	10

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T38	1		T18	1		T88	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T38	1		T16	1		T18	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T204	1		T78	2		T271	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T208	1		T21	2		T174	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T11	1		T118	1		T44	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T118	1		T174	1		T176	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T11	1		T235	1		T21	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T235	1		T208	1		T195	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	333	1			T3	2		T11	5		T38	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	362	1			T3	1		T13	1		T38	7
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T11	1		T39	1		T16	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T216	1		T175	1		T201	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T38	1		T18	1		T199	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T16	2		T21	2		T199	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T118	2		T208	1		T174	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T118	2		T16	1		T18	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T234	1		T204	1		T281	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T16	1		T208	1		T21	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T11	4		T13	4		T38	7
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T3	2		T11	5		T13	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T217	1		T235	1		T44	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	49	1			T16	2		T217	1		T235	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T174	1		T168	1		T144	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T39	1		T16	1		T208	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T11	1		T18	1		T168	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T11	1		T16	1		T208	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T18	1		T199	1		T78	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T78	1		T233	2		T146	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T3	1		T11	1		T12	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T3	1		T11	3		T12	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T38	1		T43	1		T18	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T38	1		T44	2		T174	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T43	2		T18	2		T21	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T16	1		T18	2		T21	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T43	2		T21	1		T199	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T11	1		T39	1		T174	3
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T3	1		T43	1		T21	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T11	1		T234	1		T271	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T8	1		T11	5		T13	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T3	1		T8	1		T11	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T3	1		T216	1		T18	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T43	1		T216	1		T18	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T260	1		T234	1		T229	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T16	1		T260	1		T168	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T3	1		T38	1		T235	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T11	1		T39	1		T43	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T18	1		T21	2		T260	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T260	1		T282	1		T274	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	305	1			T8	1		T25	2		T38	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T3	2		T8	1		T11	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T16	1		T216	1		T18	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T11	2		T16	1		T216	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T3	1		T18	1		T21	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T39	2		T16	1		T44	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T183	1		T176	1		T168	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T38	2		T183	1		T44	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	34	1			T38	1		T118	1		T235	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T38	2		T118	1		T235	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T3	1		T10	1		T11	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	304	1			T10	1		T11	4		T38	3