Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1761

1

T1

1

T5

8

T9

2

auto[1]

1894

1

T1

5

T5

17

T9

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2044

1

T1

6

T9

4

T11

9

auto[1]

1611

1

T5

25

T11

4

T22

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2885

1

T1

6

T5

25

T9

4

auto[1]

770

1

T11

7

T13

2

T23

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	754	1			T1	2		T5	7		T11	2
valid[1]	722	1			T1	1		T5	3		T11	3
valid[2]	770	1			T1	1		T5	3		T9	1
valid[3]	701	1			T1	1		T5	5		T9	3
valid[4]	708	1			T1	1		T5	7		T11	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	137	1			T84	2		T140	1		T181	2
auto[0]	auto[0]	valid[0]	auto[1]	173	1			T5	3		T11	1		T28	1
auto[0]	auto[0]	valid[1]	auto[0]	106	1			T16	2		T84	1		T18	1
auto[0]	auto[0]	valid[1]	auto[1]	155	1			T28	4		T86	2		T87	1
auto[0]	auto[0]	valid[2]	auto[0]	132	1			T9	1		T16	1		T84	1
auto[0]	auto[0]	valid[2]	auto[1]	157	1			T5	1		T11	1		T85	1
auto[0]	auto[0]	valid[3]	auto[0]	127	1			T1	1		T9	1		T11	1
auto[0]	auto[0]	valid[3]	auto[1]	148	1			T5	2		T11	1		T22	2
auto[0]	auto[0]	valid[4]	auto[0]	117	1			T18	1		T140	1		T180	3
auto[0]	auto[0]	valid[4]	auto[1]	141	1			T5	2		T22	1		T28	3
auto[0]	auto[1]	valid[0]	auto[0]	131	1			T1	2		T11	1		T16	1
auto[0]	auto[1]	valid[0]	auto[1]	168	1			T5	4		T22	1		T28	1
auto[0]	auto[1]	valid[1]	auto[0]	133	1			T1	1		T16	1		T84	1
auto[0]	auto[1]	valid[1]	auto[1]	161	1			T5	3		T11	1		T22	1
auto[0]	auto[1]	valid[2]	auto[0]	141	1			T1	1		T18	1		T140	2
auto[0]	auto[1]	valid[2]	auto[1]	179	1			T5	2		T28	6		T86	1
auto[0]	auto[1]	valid[3]	auto[0]	111	1			T9	2		T18	4		T181	1
auto[0]	auto[1]	valid[3]	auto[1]	170	1			T5	3		T22	1		T28	1
auto[0]	auto[1]	valid[4]	auto[0]	139	1			T1	1		T13	1		T84	1
auto[0]	auto[1]	valid[4]	auto[1]	159	1			T5	5		T22	3		T28	2
auto[1]	auto[0]	valid[0]	auto[0]	65	1			T16	1		T18	1		T181	1
auto[1]	auto[0]	valid[1]	auto[0]	79	1			T18	2		T180	1		T175	1
auto[1]	auto[0]	valid[2]	auto[0]	78	1			T11	1		T18	1		T174	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T11	3		T23	1		T16	1
auto[1]	auto[0]	valid[4]	auto[0]	72	1			T13	1		T84	2		T18	1
auto[1]	auto[1]	valid[0]	auto[0]	80	1			T13	1		T23	1		T18	1
auto[1]	auto[1]	valid[1]	auto[0]	88	1			T11	2		T18	1		T180	1
auto[1]	auto[1]	valid[2]	auto[0]	83	1			T16	1		T18	2		T181	1
auto[1]	auto[1]	valid[3]	auto[0]	71	1			T140	1		T181	1		T21	1
auto[1]	auto[1]	valid[4]	auto[0]	80	1			T11	1		T18	1		T181	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal