Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51442

1

T1

150

T6

9

T7

7

auto[1]

16794

1

T5

411

T11

84

T22

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49402

1

T1

94

T5

411

T6

4

auto[1]

18834

1

T1

56

T6

5

T7

2

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35200	1			T1	74		T5	203		T6	6
others[1]	5725	1			T1	9		T5	33		T7	1
others[2]	5723	1			T1	8		T5	30		T6	3
others[3]	6463	1			T1	19		T5	45		T7	1
interest[1]	3781	1			T1	9		T5	19		T9	6
interest[4]	22835	1			T1	52		T5	127		T6	2
interest[64]	11344	1			T1	31		T5	81		T7	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16684	1			T1	43		T6	3		T7	3
auto[0]	auto[0]	others[1]	2767	1			T1	5		T9	7		T11	16
auto[0]	auto[0]	others[2]	2754	1			T1	6		T6	1		T9	9
auto[0]	auto[0]	others[3]	3131	1			T1	13		T7	1		T9	17
auto[0]	auto[0]	interest[1]	1801	1			T1	5		T9	4		T11	12
auto[0]	auto[0]	interest[4]	10759	1			T1	30		T6	2		T7	2
auto[0]	auto[0]	interest[64]	5471	1			T1	22		T7	1		T9	22
auto[0]	auto[1]	others[0]	8876	1			T5	203		T11	39		T22	9
auto[0]	auto[1]	others[1]	1391	1			T5	33		T11	10		T28	32
auto[0]	auto[1]	others[2]	1392	1			T5	30		T11	12		T28	26
auto[0]	auto[1]	others[3]	1537	1			T5	45		T11	8		T28	39
auto[0]	auto[1]	interest[1]	905	1			T5	19		T11	2		T28	18
auto[0]	auto[1]	interest[4]	5866	1			T5	127		T11	26		T22	9
auto[0]	auto[1]	interest[64]	2693	1			T5	81		T11	13		T28	52
auto[1]	auto[0]	others[0]	9640	1			T1	31		T6	3		T7	1
auto[1]	auto[0]	others[1]	1567	1			T1	4		T7	1		T9	7
auto[1]	auto[0]	others[2]	1577	1			T1	2		T6	2		T9	2
auto[1]	auto[0]	others[3]	1795	1			T1	6		T9	4		T11	17
auto[1]	auto[0]	interest[1]	1075	1			T1	4		T9	2		T11	13
auto[1]	auto[0]	interest[4]	6210	1			T1	22		T7	1		T9	14
auto[1]	auto[0]	interest[64]	3180	1			T1	9		T9	16		T11	23

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal