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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T1042 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4164483543 Jul 19 04:34:10 PM PDT 24 Jul 19 04:34:23 PM PDT 24 12224061 ps
T102 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1891643389 Jul 19 04:34:07 PM PDT 24 Jul 19 04:34:22 PM PDT 24 172551457 ps
T114 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1861394855 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:29 PM PDT 24 553929263 ps
T103 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.536247612 Jul 19 04:34:02 PM PDT 24 Jul 19 04:34:12 PM PDT 24 146020534 ps
T1043 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1247837539 Jul 19 04:34:03 PM PDT 24 Jul 19 04:34:11 PM PDT 24 36749281 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.609193083 Jul 19 04:33:59 PM PDT 24 Jul 19 04:34:06 PM PDT 24 11097735 ps
T1045 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2327906689 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:17 PM PDT 24 27267112 ps
T1046 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2032669009 Jul 19 04:34:17 PM PDT 24 Jul 19 04:34:30 PM PDT 24 13649266 ps
T109 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2834893048 Jul 19 04:34:07 PM PDT 24 Jul 19 04:34:21 PM PDT 24 56261332 ps
T1047 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4123564214 Jul 19 04:34:13 PM PDT 24 Jul 19 04:34:29 PM PDT 24 108685831 ps
T115 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3689309830 Jul 19 04:34:19 PM PDT 24 Jul 19 04:34:34 PM PDT 24 398617305 ps
T116 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3248399949 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:41 PM PDT 24 320550578 ps
T1048 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3846509694 Jul 19 04:34:24 PM PDT 24 Jul 19 04:34:36 PM PDT 24 57144722 ps
T1049 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.494340851 Jul 19 04:34:09 PM PDT 24 Jul 19 04:34:22 PM PDT 24 379292194 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2699156009 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:17 PM PDT 24 27927568 ps
T1051 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3248446748 Jul 19 04:35:44 PM PDT 24 Jul 19 04:35:51 PM PDT 24 33370956 ps
T104 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1777047462 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:19 PM PDT 24 812434158 ps
T186 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3264979962 Jul 19 04:34:03 PM PDT 24 Jul 19 04:34:18 PM PDT 24 1096844078 ps
T1052 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.117445799 Jul 19 04:34:08 PM PDT 24 Jul 19 04:34:21 PM PDT 24 111154414 ps
T126 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.994555886 Jul 19 04:34:05 PM PDT 24 Jul 19 04:34:15 PM PDT 24 180540323 ps
T127 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2781665125 Jul 19 04:34:07 PM PDT 24 Jul 19 04:34:20 PM PDT 24 35349403 ps
T128 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4125985034 Jul 19 04:34:15 PM PDT 24 Jul 19 04:34:31 PM PDT 24 36127874 ps
T1053 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.547618857 Jul 19 04:34:07 PM PDT 24 Jul 19 04:34:25 PM PDT 24 520741614 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2879789270 Jul 19 04:34:01 PM PDT 24 Jul 19 04:34:08 PM PDT 24 33454876 ps
T105 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1070766218 Jul 19 04:34:09 PM PDT 24 Jul 19 04:34:24 PM PDT 24 311387024 ps
T1055 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.547265610 Jul 19 04:34:15 PM PDT 24 Jul 19 04:34:32 PM PDT 24 521252132 ps
T1056 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.337424102 Jul 19 04:34:17 PM PDT 24 Jul 19 04:34:30 PM PDT 24 46910756 ps
T106 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.928210282 Jul 19 04:34:08 PM PDT 24 Jul 19 04:34:24 PM PDT 24 775292576 ps
T110 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1122343166 Jul 19 04:34:24 PM PDT 24 Jul 19 04:34:37 PM PDT 24 481792795 ps
T129 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3789546732 Jul 19 04:34:35 PM PDT 24 Jul 19 04:34:43 PM PDT 24 36562799 ps
T1057 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3095054523 Jul 19 04:34:16 PM PDT 24 Jul 19 04:34:29 PM PDT 24 15591686 ps
T1058 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1457916728 Jul 19 04:34:18 PM PDT 24 Jul 19 04:34:31 PM PDT 24 14730011 ps
T1059 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.893880157 Jul 19 04:34:03 PM PDT 24 Jul 19 04:34:12 PM PDT 24 55098972 ps
T130 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1186144889 Jul 19 04:33:59 PM PDT 24 Jul 19 04:34:06 PM PDT 24 358302102 ps
T133 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3582143626 Jul 19 04:34:05 PM PDT 24 Jul 19 04:34:15 PM PDT 24 49259229 ps
T1060 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2514556092 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:26 PM PDT 24 247064841 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3659513566 Jul 19 04:34:07 PM PDT 24 Jul 19 04:34:19 PM PDT 24 39804741 ps
T1062 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3302324573 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:25 PM PDT 24 36164946 ps
T131 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1590296673 Jul 19 04:34:05 PM PDT 24 Jul 19 04:34:15 PM PDT 24 86643847 ps
T107 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1971478793 Jul 19 04:34:04 PM PDT 24 Jul 19 04:34:16 PM PDT 24 57720565 ps
T1063 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2528819210 Jul 19 04:34:31 PM PDT 24 Jul 19 04:34:41 PM PDT 24 23722956 ps
T187 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1330572140 Jul 19 04:34:02 PM PDT 24 Jul 19 04:34:16 PM PDT 24 4508724490 ps
T1064 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2436853998 Jul 19 04:34:32 PM PDT 24 Jul 19 04:34:41 PM PDT 24 46124921 ps
T108 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3036267882 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:27 PM PDT 24 763937726 ps
T161 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2234858447 Jul 19 04:34:01 PM PDT 24 Jul 19 04:34:12 PM PDT 24 217297914 ps
T1065 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2764087088 Jul 19 04:34:03 PM PDT 24 Jul 19 04:34:12 PM PDT 24 593009031 ps
T166 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2637686985 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:21 PM PDT 24 165998103 ps
T1066 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1030656738 Jul 19 04:34:01 PM PDT 24 Jul 19 04:34:10 PM PDT 24 50918887 ps
T111 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.666047083 Jul 19 04:34:14 PM PDT 24 Jul 19 04:34:30 PM PDT 24 130652123 ps
T1067 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1545808268 Jul 19 04:34:19 PM PDT 24 Jul 19 04:34:32 PM PDT 24 16469593 ps
T162 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4104585922 Jul 19 04:34:17 PM PDT 24 Jul 19 04:34:33 PM PDT 24 297605191 ps
T1068 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3492842745 Jul 19 04:34:15 PM PDT 24 Jul 19 04:34:28 PM PDT 24 52239547 ps
T184 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3657842914 Jul 19 04:34:13 PM PDT 24 Jul 19 04:34:31 PM PDT 24 190648367 ps
T132 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3878335172 Jul 19 04:34:04 PM PDT 24 Jul 19 04:34:34 PM PDT 24 926220469 ps
T134 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1653995186 Jul 19 04:34:01 PM PDT 24 Jul 19 04:34:31 PM PDT 24 1146326640 ps
T1069 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2303483468 Jul 19 04:34:02 PM PDT 24 Jul 19 04:34:09 PM PDT 24 23443657 ps
T1070 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2389602150 Jul 19 04:34:14 PM PDT 24 Jul 19 04:34:27 PM PDT 24 45586480 ps
T1071 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1253400680 Jul 19 04:34:10 PM PDT 24 Jul 19 04:34:25 PM PDT 24 60671805 ps
T1072 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2573517857 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:15 PM PDT 24 40293722 ps
T1073 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.721646413 Jul 19 04:34:31 PM PDT 24 Jul 19 04:34:41 PM PDT 24 45706462 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2008325533 Jul 19 04:34:05 PM PDT 24 Jul 19 04:34:14 PM PDT 24 10853474 ps
T1075 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2477497227 Jul 19 04:33:59 PM PDT 24 Jul 19 04:34:09 PM PDT 24 118826983 ps
T191 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1249977717 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:41 PM PDT 24 1242849537 ps
T1076 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1375416400 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:48 PM PDT 24 2173171310 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3862785788 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:26 PM PDT 24 30928814 ps
T1078 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3797032342 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:25 PM PDT 24 19795354 ps
T163 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.903115645 Jul 19 04:34:13 PM PDT 24 Jul 19 04:34:30 PM PDT 24 147135369 ps
T1079 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.945667550 Jul 19 04:34:12 PM PDT 24 Jul 19 04:34:25 PM PDT 24 48095732 ps
T1080 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3333542057 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:27 PM PDT 24 103005879 ps
T164 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2774729335 Jul 19 04:34:13 PM PDT 24 Jul 19 04:34:28 PM PDT 24 135517491 ps
T165 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3029450074 Jul 19 04:34:09 PM PDT 24 Jul 19 04:34:22 PM PDT 24 76759915 ps
T167 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3510768338 Jul 19 04:34:03 PM PDT 24 Jul 19 04:34:17 PM PDT 24 1316364936 ps
T1081 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1796057026 Jul 19 04:34:14 PM PDT 24 Jul 19 04:34:27 PM PDT 24 85768040 ps
T1082 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1026879628 Jul 19 04:34:16 PM PDT 24 Jul 19 04:34:30 PM PDT 24 12600294 ps
T1083 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3110257510 Jul 19 04:34:13 PM PDT 24 Jul 19 04:34:26 PM PDT 24 25765686 ps
T1084 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1860537340 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:17 PM PDT 24 30179225 ps
T1085 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4077690674 Jul 19 04:34:00 PM PDT 24 Jul 19 04:34:06 PM PDT 24 15228268 ps
T173 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1731063547 Jul 19 04:34:07 PM PDT 24 Jul 19 04:34:19 PM PDT 24 130199043 ps
T188 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2335233173 Jul 19 04:34:01 PM PDT 24 Jul 19 04:34:31 PM PDT 24 4170705828 ps
T189 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3729076973 Jul 19 04:34:15 PM PDT 24 Jul 19 04:34:40 PM PDT 24 947605510 ps
T1086 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1099384424 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:21 PM PDT 24 386578191 ps
T1087 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.597009419 Jul 19 04:34:30 PM PDT 24 Jul 19 04:34:40 PM PDT 24 14671796 ps
T1088 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2645963937 Jul 19 04:34:13 PM PDT 24 Jul 19 04:34:29 PM PDT 24 406120907 ps
T1089 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4040666244 Jul 19 04:34:03 PM PDT 24 Jul 19 04:34:13 PM PDT 24 55415183 ps
T1090 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3240236434 Jul 19 04:34:09 PM PDT 24 Jul 19 04:34:22 PM PDT 24 53115758 ps
T1091 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2277034399 Jul 19 04:34:07 PM PDT 24 Jul 19 04:34:21 PM PDT 24 736386132 ps
T1092 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.825806700 Jul 19 04:34:04 PM PDT 24 Jul 19 04:34:16 PM PDT 24 193018772 ps
T1093 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1266123844 Jul 19 04:34:08 PM PDT 24 Jul 19 04:34:28 PM PDT 24 377886274 ps
T1094 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2458687237 Jul 19 04:34:08 PM PDT 24 Jul 19 04:34:38 PM PDT 24 1015137713 ps
T1095 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4238054375 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:40 PM PDT 24 5453911127 ps
T1096 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.726017513 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:30 PM PDT 24 1577177636 ps
T1097 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2863085169 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:24 PM PDT 24 18297546 ps
T1098 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.397320617 Jul 19 04:34:17 PM PDT 24 Jul 19 04:34:32 PM PDT 24 67123062 ps
T1099 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1095631831 Jul 19 04:34:00 PM PDT 24 Jul 19 04:34:08 PM PDT 24 372240255 ps
T1100 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3047826563 Jul 19 04:34:08 PM PDT 24 Jul 19 04:34:21 PM PDT 24 54256835 ps
T1101 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.87754878 Jul 19 04:34:19 PM PDT 24 Jul 19 04:34:32 PM PDT 24 57049056 ps
T1102 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1995309348 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:17 PM PDT 24 231147798 ps
T1103 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2861322381 Jul 19 04:34:08 PM PDT 24 Jul 19 04:34:20 PM PDT 24 11849189 ps
T1104 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4015472387 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:28 PM PDT 24 160670667 ps
T1105 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1280719900 Jul 19 04:34:07 PM PDT 24 Jul 19 04:34:21 PM PDT 24 127319520 ps
T1106 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4115966800 Jul 19 04:34:10 PM PDT 24 Jul 19 04:34:23 PM PDT 24 50581964 ps
T1107 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3739309490 Jul 19 04:34:31 PM PDT 24 Jul 19 04:34:40 PM PDT 24 50784167 ps
T1108 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2119890290 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:17 PM PDT 24 88401467 ps
T1109 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2665533990 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:19 PM PDT 24 143350699 ps
T1110 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1374508589 Jul 19 04:33:58 PM PDT 24 Jul 19 04:34:04 PM PDT 24 18699504 ps
T1111 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3414364156 Jul 19 04:34:07 PM PDT 24 Jul 19 04:34:20 PM PDT 24 19853460 ps
T1112 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3198344920 Jul 19 04:34:19 PM PDT 24 Jul 19 04:34:36 PM PDT 24 154367531 ps
T1113 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.112322890 Jul 19 04:34:09 PM PDT 24 Jul 19 04:34:23 PM PDT 24 52911138 ps
T1114 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1772381117 Jul 19 04:34:16 PM PDT 24 Jul 19 04:34:30 PM PDT 24 51748580 ps
T1115 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3918893775 Jul 19 04:34:24 PM PDT 24 Jul 19 04:34:36 PM PDT 24 12533914 ps
T1116 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2988206808 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:25 PM PDT 24 140837591 ps
T1117 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2333751714 Jul 19 04:34:07 PM PDT 24 Jul 19 04:34:18 PM PDT 24 70089862 ps
T1118 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1973232079 Jul 19 04:34:24 PM PDT 24 Jul 19 04:34:36 PM PDT 24 26168225 ps
T82 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3350878276 Jul 19 04:33:58 PM PDT 24 Jul 19 04:34:04 PM PDT 24 40176638 ps
T83 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2018184011 Jul 19 04:34:13 PM PDT 24 Jul 19 04:34:27 PM PDT 24 366985083 ps
T1119 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1324782017 Jul 19 04:34:32 PM PDT 24 Jul 19 04:34:42 PM PDT 24 226403076 ps
T1120 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1524148077 Jul 19 04:34:00 PM PDT 24 Jul 19 04:34:07 PM PDT 24 30320758 ps
T1121 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1672261130 Jul 19 04:34:01 PM PDT 24 Jul 19 04:34:08 PM PDT 24 154319254 ps
T1122 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3068165951 Jul 19 04:34:09 PM PDT 24 Jul 19 04:34:21 PM PDT 24 11737642 ps
T1123 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4284288514 Jul 19 04:34:04 PM PDT 24 Jul 19 04:34:13 PM PDT 24 23736676 ps
T1124 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3541632931 Jul 19 04:34:29 PM PDT 24 Jul 19 04:34:39 PM PDT 24 34901361 ps
T1125 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3082624526 Jul 19 04:34:02 PM PDT 24 Jul 19 04:34:11 PM PDT 24 211645197 ps
T1126 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1406841372 Jul 19 04:34:23 PM PDT 24 Jul 19 04:34:36 PM PDT 24 79411745 ps
T1127 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3294772673 Jul 19 04:34:08 PM PDT 24 Jul 19 04:34:22 PM PDT 24 205034036 ps
T1128 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1842383938 Jul 19 04:34:05 PM PDT 24 Jul 19 04:34:16 PM PDT 24 65237765 ps
T1129 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1604913129 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:27 PM PDT 24 223900714 ps
T185 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3100755065 Jul 19 04:34:01 PM PDT 24 Jul 19 04:34:10 PM PDT 24 44910771 ps
T1130 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.562417323 Jul 19 04:34:08 PM PDT 24 Jul 19 04:34:34 PM PDT 24 3761101013 ps
T1131 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1399868485 Jul 19 04:34:08 PM PDT 24 Jul 19 04:34:19 PM PDT 24 30968496 ps
T1132 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.128462809 Jul 19 04:33:57 PM PDT 24 Jul 19 04:34:09 PM PDT 24 1328345765 ps
T1133 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1678433084 Jul 19 04:34:07 PM PDT 24 Jul 19 04:34:18 PM PDT 24 13462220 ps
T1134 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1318854711 Jul 19 04:34:17 PM PDT 24 Jul 19 04:34:33 PM PDT 24 86720397 ps
T1135 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1406884001 Jul 19 04:34:09 PM PDT 24 Jul 19 04:34:21 PM PDT 24 16041713 ps
T1136 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3116477484 Jul 19 04:33:54 PM PDT 24 Jul 19 04:34:00 PM PDT 24 27942190 ps
T1137 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3751115956 Jul 19 04:34:00 PM PDT 24 Jul 19 04:34:07 PM PDT 24 18711561 ps
T1138 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4201144339 Jul 19 04:34:23 PM PDT 24 Jul 19 04:34:35 PM PDT 24 19070704 ps
T1139 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3178098388 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:20 PM PDT 24 1437537992 ps
T1140 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1293311424 Jul 19 04:34:06 PM PDT 24 Jul 19 04:34:16 PM PDT 24 74670715 ps
T1141 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1798552447 Jul 19 04:34:13 PM PDT 24 Jul 19 04:34:27 PM PDT 24 49297964 ps
T1142 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.58587931 Jul 19 04:34:07 PM PDT 24 Jul 19 04:34:22 PM PDT 24 74878087 ps
T192 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2619876299 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:36 PM PDT 24 791691359 ps
T1143 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2425909233 Jul 19 04:34:13 PM PDT 24 Jul 19 04:34:28 PM PDT 24 150252675 ps
T190 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4154044658 Jul 19 04:34:03 PM PDT 24 Jul 19 04:34:30 PM PDT 24 3478445747 ps
T1144 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1761005218 Jul 19 04:34:00 PM PDT 24 Jul 19 04:34:27 PM PDT 24 1196921208 ps
T1145 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2790691785 Jul 19 04:34:18 PM PDT 24 Jul 19 04:34:31 PM PDT 24 15286856 ps
T1146 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1281754309 Jul 19 04:34:31 PM PDT 24 Jul 19 04:34:41 PM PDT 24 31851393 ps
T1147 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1363946044 Jul 19 04:34:18 PM PDT 24 Jul 19 04:34:31 PM PDT 24 14774896 ps
T1148 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2185625085 Jul 19 04:33:59 PM PDT 24 Jul 19 04:34:16 PM PDT 24 671483131 ps
T1149 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1408974575 Jul 19 04:34:11 PM PDT 24 Jul 19 04:34:38 PM PDT 24 553724943 ps
T1150 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.407128393 Jul 19 04:34:20 PM PDT 24 Jul 19 04:34:35 PM PDT 24 115728706 ps
T1151 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.831180956 Jul 19 04:34:10 PM PDT 24 Jul 19 04:34:23 PM PDT 24 23351481 ps

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3888965371
Short name T9
Test name
Test status
Simulation time 2986289779 ps
CPU time 58.05 seconds
Started Jul 19 05:40:35 PM PDT 24
Finished Jul 19 05:41:34 PM PDT 24
Peak memory 254208 kb
Host smart-6860a82e-287f-453f-bdda-03ab0245afb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888965371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3888965371
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2503279971
Short name T11
Test name
Test status
Simulation time 70075756869 ps
CPU time 366.34 seconds
Started Jul 19 05:35:04 PM PDT 24
Finished Jul 19 05:42:11 PM PDT 24
Peak memory 249708 kb
Host smart-618f0dff-11a0-4be1-a53f-baa86e84af91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503279971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2503279971
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4224862755
Short name T18
Test name
Test status
Simulation time 114652565358 ps
CPU time 1270.95 seconds
Started Jul 19 05:37:05 PM PDT 24
Finished Jul 19 05:58:18 PM PDT 24
Peak memory 282460 kb
Host smart-f56da2be-ac5d-43e0-b604-cfdf21958aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224862755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4224862755
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3689309830
Short name T115
Test name
Test status
Simulation time 398617305 ps
CPU time 2.5 seconds
Started Jul 19 04:34:19 PM PDT 24
Finished Jul 19 04:34:34 PM PDT 24
Peak memory 217748 kb
Host smart-03d23529-e99f-4d84-a6e5-2834ab94e667
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689309830 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3689309830
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1513915557
Short name T78
Test name
Test status
Simulation time 105014385817 ps
CPU time 580.41 seconds
Started Jul 19 05:35:13 PM PDT 24
Finished Jul 19 05:45:57 PM PDT 24
Peak memory 296520 kb
Host smart-f1c07aef-0efb-4e58-bf48-9a222c09e255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513915557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1513915557
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2987807410
Short name T63
Test name
Test status
Simulation time 25693707 ps
CPU time 0.73 seconds
Started Jul 19 05:34:36 PM PDT 24
Finished Jul 19 05:34:44 PM PDT 24
Peak memory 216416 kb
Host smart-7c28869d-f9b1-4eb2-b2b2-3edb54ff6ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987807410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2987807410
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4205473559
Short name T204
Test name
Test status
Simulation time 172267523694 ps
CPU time 578.63 seconds
Started Jul 19 05:36:24 PM PDT 24
Finished Jul 19 05:46:23 PM PDT 24
Peak memory 268160 kb
Host smart-27c6d440-cfa8-4044-9935-538fb97f8fd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205473559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4205473559
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4127565298
Short name T97
Test name
Test status
Simulation time 296817553 ps
CPU time 16.93 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:31 PM PDT 24
Peak memory 215836 kb
Host smart-6eb6aeca-1233-4b7c-adaf-a758e1ca4850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127565298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4127565298
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4063431261
Short name T21
Test name
Test status
Simulation time 89221586966 ps
CPU time 850.3 seconds
Started Jul 19 05:35:52 PM PDT 24
Finished Jul 19 05:50:43 PM PDT 24
Peak memory 273680 kb
Host smart-56f12aa3-99d7-48ab-9f78-e7aae0324bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063431261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4063431261
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3009734858
Short name T271
Test name
Test status
Simulation time 5914989745 ps
CPU time 146.26 seconds
Started Jul 19 05:39:33 PM PDT 24
Finished Jul 19 05:42:04 PM PDT 24
Peak memory 266144 kb
Host smart-2421ee2f-92f6-46dd-86d9-6a45b5fbdd02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009734858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3009734858
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3645767842
Short name T124
Test name
Test status
Simulation time 40539227 ps
CPU time 1.41 seconds
Started Jul 19 04:34:03 PM PDT 24
Finished Jul 19 04:34:11 PM PDT 24
Peak memory 207696 kb
Host smart-97ce3006-689a-46ee-bca7-a267b5c8128b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645767842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
645767842
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.492906045
Short name T37
Test name
Test status
Simulation time 11255113703 ps
CPU time 38.29 seconds
Started Jul 19 05:34:48 PM PDT 24
Finished Jul 19 05:36:20 PM PDT 24
Peak memory 225136 kb
Host smart-49ff2f7c-83f7-430c-9779-9429a0ac61ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492906045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.492906045
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.466796438
Short name T16
Test name
Test status
Simulation time 749114119380 ps
CPU time 613.5 seconds
Started Jul 19 05:39:52 PM PDT 24
Finished Jul 19 05:50:12 PM PDT 24
Peak memory 273804 kb
Host smart-24eddfc4-1859-4c03-a49e-bcf61ce18575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466796438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.466796438
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1226057109
Short name T389
Test name
Test status
Simulation time 22306832 ps
CPU time 0.74 seconds
Started Jul 19 05:37:09 PM PDT 24
Finished Jul 19 05:37:11 PM PDT 24
Peak memory 205720 kb
Host smart-2ed3842a-7325-4f1a-863e-1724e60b23f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226057109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1226057109
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.876544954
Short name T243
Test name
Test status
Simulation time 309306304166 ps
CPU time 751.05 seconds
Started Jul 19 05:39:17 PM PDT 24
Finished Jul 19 05:51:50 PM PDT 24
Peak memory 281320 kb
Host smart-d5cd8211-7c31-4810-bfdc-9a8cc22889c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876544954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.876544954
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1971478793
Short name T107
Test name
Test status
Simulation time 57720565 ps
CPU time 3.44 seconds
Started Jul 19 04:34:04 PM PDT 24
Finished Jul 19 04:34:16 PM PDT 24
Peak memory 217204 kb
Host smart-08fca1e7-35fd-469f-9e99-2f97ed52d561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971478793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
971478793
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2762190552
Short name T226
Test name
Test status
Simulation time 51872659621 ps
CPU time 372.67 seconds
Started Jul 19 05:36:58 PM PDT 24
Finished Jul 19 05:43:12 PM PDT 24
Peak memory 250012 kb
Host smart-e11ee0a8-8e66-4930-aeba-198459e5afc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762190552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2762190552
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.727112203
Short name T168
Test name
Test status
Simulation time 68427920822 ps
CPU time 675.64 seconds
Started Jul 19 05:37:22 PM PDT 24
Finished Jul 19 05:48:39 PM PDT 24
Peak memory 269276 kb
Host smart-d0d3be28-4c66-4f16-b180-b964a01f47f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727112203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.727112203
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2582702335
Short name T32
Test name
Test status
Simulation time 46985998 ps
CPU time 1.03 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:34:52 PM PDT 24
Peak memory 218448 kb
Host smart-32554287-1c07-4865-ac1e-caef894cead9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582702335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2582702335
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2300626736
Short name T1
Test name
Test status
Simulation time 52465750900 ps
CPU time 236.61 seconds
Started Jul 19 05:40:36 PM PDT 24
Finished Jul 19 05:44:36 PM PDT 24
Peak memory 249832 kb
Host smart-78cf8922-8eb2-4b64-bc34-5b3454a83938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300626736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2300626736
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1728144213
Short name T67
Test name
Test status
Simulation time 86647162 ps
CPU time 1.2 seconds
Started Jul 19 05:34:36 PM PDT 24
Finished Jul 19 05:34:45 PM PDT 24
Peak memory 236200 kb
Host smart-54863116-9eb7-45cb-851c-ec73036e3323
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728144213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1728144213
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.4223728172
Short name T175
Test name
Test status
Simulation time 4540442416 ps
CPU time 77.37 seconds
Started Jul 19 05:38:02 PM PDT 24
Finished Jul 19 05:39:21 PM PDT 24
Peak memory 252444 kb
Host smart-c26f0707-1d92-4ee7-b762-dd4818d9b84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223728172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4223728172
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3840570374
Short name T39
Test name
Test status
Simulation time 54308904991 ps
CPU time 362.58 seconds
Started Jul 19 05:40:21 PM PDT 24
Finished Jul 19 05:46:28 PM PDT 24
Peak memory 252984 kb
Host smart-621a2e03-0a17-4a61-ac47-4990e930aed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840570374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3840570374
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2898136522
Short name T194
Test name
Test status
Simulation time 62117261469 ps
CPU time 122.58 seconds
Started Jul 19 05:39:07 PM PDT 24
Finished Jul 19 05:41:10 PM PDT 24
Peak memory 250692 kb
Host smart-ca8a2934-f6d1-42a9-a65f-6fbe706c2e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898136522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2898136522
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2981396891
Short name T84
Test name
Test status
Simulation time 3310111021 ps
CPU time 43.25 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:37:38 PM PDT 24
Peak memory 225284 kb
Host smart-77a4496a-a473-44e5-b1ed-74b2cb7b97bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981396891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2981396891
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2353434299
Short name T246
Test name
Test status
Simulation time 6535317830 ps
CPU time 92.3 seconds
Started Jul 19 05:40:10 PM PDT 24
Finished Jul 19 05:41:51 PM PDT 24
Peak memory 254420 kb
Host smart-5ba9686e-6f10-408d-a473-23798b946259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353434299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2353434299
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.277329624
Short name T150
Test name
Test status
Simulation time 412309264745 ps
CPU time 1134.63 seconds
Started Jul 19 05:40:30 PM PDT 24
Finished Jul 19 05:59:26 PM PDT 24
Peak memory 319544 kb
Host smart-4fb9f4e7-85e0-4b86-ad08-c1f64c1d2f60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277329624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.277329624
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1960178053
Short name T238
Test name
Test status
Simulation time 5363951225 ps
CPU time 130.36 seconds
Started Jul 19 05:40:20 PM PDT 24
Finished Jul 19 05:42:35 PM PDT 24
Peak memory 266164 kb
Host smart-08c755c5-666a-44dc-810c-322dfcd10162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960178053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1960178053
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2016866685
Short name T48
Test name
Test status
Simulation time 3507963980 ps
CPU time 93.65 seconds
Started Jul 19 05:37:52 PM PDT 24
Finished Jul 19 05:39:26 PM PDT 24
Peak memory 265036 kb
Host smart-81a7544c-fcdf-484b-a1c9-7b7810f8d13a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016866685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2016866685
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.928210282
Short name T106
Test name
Test status
Simulation time 775292576 ps
CPU time 4.05 seconds
Started Jul 19 04:34:08 PM PDT 24
Finished Jul 19 04:34:24 PM PDT 24
Peak memory 216144 kb
Host smart-6eb14ad1-e4fb-4de5-9334-54654d140106
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928210282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.928210282
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2727423300
Short name T205
Test name
Test status
Simulation time 36791622840 ps
CPU time 287.27 seconds
Started Jul 19 05:36:30 PM PDT 24
Finished Jul 19 05:41:33 PM PDT 24
Peak memory 265944 kb
Host smart-e7d36cdf-0a0d-4068-acdc-f48ec4bf8200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727423300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2727423300
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.118146692
Short name T202
Test name
Test status
Simulation time 31147447277 ps
CPU time 71.08 seconds
Started Jul 19 05:34:55 PM PDT 24
Finished Jul 19 05:37:07 PM PDT 24
Peak memory 256908 kb
Host smart-f71ecf38-7d8f-457b-be4d-8c9be8f19ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118146692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.118146692
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3248399949
Short name T116
Test name
Test status
Simulation time 320550578 ps
CPU time 17.03 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:41 PM PDT 24
Peak memory 215932 kb
Host smart-66e606df-4a1e-4ec8-94af-0057fdc08747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248399949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3248399949
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2226317526
Short name T298
Test name
Test status
Simulation time 47035291595 ps
CPU time 453.41 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:44:28 PM PDT 24
Peak memory 252748 kb
Host smart-8190c467-85c0-4e13-be96-203fec5e3825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226317526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2226317526
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1800696251
Short name T207
Test name
Test status
Simulation time 248983414406 ps
CPU time 474.42 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:45:28 PM PDT 24
Peak memory 257096 kb
Host smart-7e7a3e2e-d004-4d00-8a36-553290bbf819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800696251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1800696251
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.157439468
Short name T79
Test name
Test status
Simulation time 6869226432 ps
CPU time 79.15 seconds
Started Jul 19 05:37:53 PM PDT 24
Finished Jul 19 05:39:14 PM PDT 24
Peak memory 268536 kb
Host smart-7fb7aac1-80c2-48e9-8ce4-a0786ca3f84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157439468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.157439468
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.566272606
Short name T323
Test name
Test status
Simulation time 155744813 ps
CPU time 5.28 seconds
Started Jul 19 05:38:30 PM PDT 24
Finished Jul 19 05:38:37 PM PDT 24
Peak memory 233372 kb
Host smart-82bd7052-7f12-4738-8b73-5c8104273927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566272606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.566272606
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2915584271
Short name T4
Test name
Test status
Simulation time 1582617879 ps
CPU time 13.05 seconds
Started Jul 19 05:40:08 PM PDT 24
Finished Jul 19 05:40:27 PM PDT 24
Peak memory 224920 kb
Host smart-67f105c9-a635-4a5f-bdb4-069c3e563b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915584271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2915584271
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2945619533
Short name T261
Test name
Test status
Simulation time 1114081956 ps
CPU time 11.58 seconds
Started Jul 19 05:37:16 PM PDT 24
Finished Jul 19 05:37:29 PM PDT 24
Peak memory 224912 kb
Host smart-48886d53-b302-4041-9f2c-2746fe667107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945619533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2945619533
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2335233173
Short name T188
Test name
Test status
Simulation time 4170705828 ps
CPU time 22.81 seconds
Started Jul 19 04:34:01 PM PDT 24
Finished Jul 19 04:34:31 PM PDT 24
Peak memory 216048 kb
Host smart-507042df-2afb-4f80-a54d-88119234f86c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335233173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2335233173
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.639885493
Short name T288
Test name
Test status
Simulation time 189588322 ps
CPU time 4.28 seconds
Started Jul 19 05:37:22 PM PDT 24
Finished Jul 19 05:37:27 PM PDT 24
Peak memory 233168 kb
Host smart-fd469dbd-118d-4e1a-859a-226f18c4eed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639885493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.639885493
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.138399961
Short name T295
Test name
Test status
Simulation time 22845087208 ps
CPU time 206.39 seconds
Started Jul 19 05:37:38 PM PDT 24
Finished Jul 19 05:41:05 PM PDT 24
Peak memory 251508 kb
Host smart-58209bb1-cfb8-4d58-ab98-79025a2aaceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138399961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.138399961
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.4063132627
Short name T93
Test name
Test status
Simulation time 150543991 ps
CPU time 4.08 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:37:38 PM PDT 24
Peak memory 221088 kb
Host smart-8b34d334-a7e9-47a9-91f9-a0a92359fba5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4063132627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.4063132627
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.384326295
Short name T42
Test name
Test status
Simulation time 140273946 ps
CPU time 3.18 seconds
Started Jul 19 05:36:32 PM PDT 24
Finished Jul 19 05:36:50 PM PDT 24
Peak memory 228980 kb
Host smart-34e50922-a6a2-41b5-bfa8-ba38cee74c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384326295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.384326295
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3657842914
Short name T184
Test name
Test status
Simulation time 190648367 ps
CPU time 5.02 seconds
Started Jul 19 04:34:13 PM PDT 24
Finished Jul 19 04:34:31 PM PDT 24
Peak memory 216244 kb
Host smart-76d4b4c9-2bcf-4af0-87d0-60f8fd68a038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657842914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
657842914
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3350878276
Short name T82
Test name
Test status
Simulation time 40176638 ps
CPU time 0.95 seconds
Started Jul 19 04:33:58 PM PDT 24
Finished Jul 19 04:34:04 PM PDT 24
Peak memory 207532 kb
Host smart-ca3643d7-7949-4f9e-b1cf-05e98382ad83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350878276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3350878276
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1653995186
Short name T134
Test name
Test status
Simulation time 1146326640 ps
CPU time 23.88 seconds
Started Jul 19 04:34:01 PM PDT 24
Finished Jul 19 04:34:31 PM PDT 24
Peak memory 215920 kb
Host smart-83e064c0-9a00-4d2e-a2ce-c8c3bb25bb74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653995186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1653995186
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1375416400
Short name T1076
Test name
Test status
Simulation time 2173171310 ps
CPU time 32.9 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:48 PM PDT 24
Peak memory 207776 kb
Host smart-3a56c023-9605-47ae-becf-8618d6c7ab50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375416400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1375416400
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1798552447
Short name T1141
Test name
Test status
Simulation time 49297964 ps
CPU time 1.14 seconds
Started Jul 19 04:34:13 PM PDT 24
Finished Jul 19 04:34:27 PM PDT 24
Peak memory 207668 kb
Host smart-3d3b3bc7-dccf-485b-b48d-b7fe5300245f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798552447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1798552447
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2119890290
Short name T1108
Test name
Test status
Simulation time 88401467 ps
CPU time 2.44 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:17 PM PDT 24
Peak memory 217144 kb
Host smart-273a28d4-7505-4494-9e64-f075b6e7a001
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119890290 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2119890290
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.152086815
Short name T1039
Test name
Test status
Simulation time 332009241 ps
CPU time 1.29 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:16 PM PDT 24
Peak memory 215932 kb
Host smart-ba33a754-b2e2-4235-a7b4-62e477bc4813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152086815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.152086815
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2879789270
Short name T1054
Test name
Test status
Simulation time 33454876 ps
CPU time 0.75 seconds
Started Jul 19 04:34:01 PM PDT 24
Finished Jul 19 04:34:08 PM PDT 24
Peak memory 204408 kb
Host smart-19bfe0b7-7001-4102-977f-9f567595c369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879789270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
879789270
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4284288514
Short name T1123
Test name
Test status
Simulation time 23736676 ps
CPU time 1.58 seconds
Started Jul 19 04:34:04 PM PDT 24
Finished Jul 19 04:34:13 PM PDT 24
Peak memory 215876 kb
Host smart-9320c72b-5397-405c-b77c-7656fd5ecd57
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284288514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4284288514
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3110257510
Short name T1083
Test name
Test status
Simulation time 25765686 ps
CPU time 0.65 seconds
Started Jul 19 04:34:13 PM PDT 24
Finished Jul 19 04:34:26 PM PDT 24
Peak memory 204256 kb
Host smart-1a56f5bd-9105-4e58-bb9c-41daf92f0551
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110257510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3110257510
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1293311424
Short name T1140
Test name
Test status
Simulation time 74670715 ps
CPU time 1.88 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:16 PM PDT 24
Peak memory 207708 kb
Host smart-ca7d8fdc-4861-44b2-9be9-6d516046a614
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293311424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1293311424
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.726017513
Short name T1096
Test name
Test status
Simulation time 1577177636 ps
CPU time 14.61 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:30 PM PDT 24
Peak memory 207756 kb
Host smart-c202f833-ac01-4139-b3c5-3f90a5543b37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726017513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.726017513
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.630385784
Short name T159
Test name
Test status
Simulation time 2294310551 ps
CPU time 26.98 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:50 PM PDT 24
Peak memory 207852 kb
Host smart-3dd948ab-3692-4ffd-a108-96feec4272fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630385784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.630385784
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1247837539
Short name T1043
Test name
Test status
Simulation time 36749281 ps
CPU time 0.95 seconds
Started Jul 19 04:34:03 PM PDT 24
Finished Jul 19 04:34:11 PM PDT 24
Peak memory 207436 kb
Host smart-faecb166-3890-4e0d-b940-fced91219265
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247837539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1247837539
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3659513566
Short name T1061
Test name
Test status
Simulation time 39804741 ps
CPU time 2.55 seconds
Started Jul 19 04:34:07 PM PDT 24
Finished Jul 19 04:34:19 PM PDT 24
Peak memory 217452 kb
Host smart-a0d04e82-023e-44d2-9487-4a05ba34c393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659513566 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3659513566
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3046665807
Short name T125
Test name
Test status
Simulation time 131917322 ps
CPU time 2.11 seconds
Started Jul 19 04:34:03 PM PDT 24
Finished Jul 19 04:34:12 PM PDT 24
Peak memory 215836 kb
Host smart-c733f5ed-3b88-4982-a30b-c609fbb0c817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046665807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
046665807
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.386179570
Short name T1040
Test name
Test status
Simulation time 21333761 ps
CPU time 0.74 seconds
Started Jul 19 04:34:02 PM PDT 24
Finished Jul 19 04:34:10 PM PDT 24
Peak memory 204740 kb
Host smart-c63f773c-6939-4e77-9afc-50a190b9fc83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386179570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.386179570
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3152520227
Short name T122
Test name
Test status
Simulation time 22102474 ps
CPU time 1.62 seconds
Started Jul 19 04:33:59 PM PDT 24
Finished Jul 19 04:34:07 PM PDT 24
Peak memory 215904 kb
Host smart-7744279b-25a8-4175-b4f5-d107cd846da1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152520227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3152520227
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2008325533
Short name T1074
Test name
Test status
Simulation time 10853474 ps
CPU time 0.65 seconds
Started Jul 19 04:34:05 PM PDT 24
Finished Jul 19 04:34:14 PM PDT 24
Peak memory 204272 kb
Host smart-b9385aba-ab89-405c-9071-1b9866fdd89c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008325533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2008325533
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1731063547
Short name T173
Test name
Test status
Simulation time 130199043 ps
CPU time 1.71 seconds
Started Jul 19 04:34:07 PM PDT 24
Finished Jul 19 04:34:19 PM PDT 24
Peak memory 207720 kb
Host smart-2795d79c-f096-4952-9029-883a7c717d92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731063547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1731063547
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1099384424
Short name T1086
Test name
Test status
Simulation time 386578191 ps
CPU time 4.55 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:21 PM PDT 24
Peak memory 216172 kb
Host smart-320f1b1c-7da1-483b-a94d-ca32ac75d437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099384424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
099384424
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1330572140
Short name T187
Test name
Test status
Simulation time 4508724490 ps
CPU time 7.04 seconds
Started Jul 19 04:34:02 PM PDT 24
Finished Jul 19 04:34:16 PM PDT 24
Peak memory 216092 kb
Host smart-8bd84f9c-13aa-4fdc-9566-cb8d23762360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330572140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1330572140
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1406841372
Short name T1126
Test name
Test status
Simulation time 79411745 ps
CPU time 2.41 seconds
Started Jul 19 04:34:23 PM PDT 24
Finished Jul 19 04:34:36 PM PDT 24
Peak memory 216972 kb
Host smart-122af49f-15b2-492e-9f2e-1655fbeeeaca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406841372 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1406841372
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2665533990
Short name T1109
Test name
Test status
Simulation time 143350699 ps
CPU time 2.77 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:19 PM PDT 24
Peak memory 215848 kb
Host smart-9d170b05-bb83-4365-b82e-49bfcdd581be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665533990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2665533990
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3414364156
Short name T1111
Test name
Test status
Simulation time 19853460 ps
CPU time 0.68 seconds
Started Jul 19 04:34:07 PM PDT 24
Finished Jul 19 04:34:20 PM PDT 24
Peak memory 204712 kb
Host smart-bab342df-0aa4-4693-bbdc-a85630f94d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414364156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3414364156
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1318854711
Short name T1134
Test name
Test status
Simulation time 86720397 ps
CPU time 2.89 seconds
Started Jul 19 04:34:17 PM PDT 24
Finished Jul 19 04:34:33 PM PDT 24
Peak memory 215968 kb
Host smart-d8f7a23a-b369-4264-9f0a-245c53b49e8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318854711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1318854711
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2637686985
Short name T166
Test name
Test status
Simulation time 165998103 ps
CPU time 3.99 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:21 PM PDT 24
Peak memory 216456 kb
Host smart-44c52659-ab6c-40ab-a9b7-44b437c6a9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637686985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2637686985
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4158897964
Short name T98
Test name
Test status
Simulation time 534483596 ps
CPU time 14.49 seconds
Started Jul 19 04:34:19 PM PDT 24
Finished Jul 19 04:34:46 PM PDT 24
Peak memory 216016 kb
Host smart-e3d2cb26-569b-4155-adad-44e4e9f11711
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158897964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4158897964
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3561336914
Short name T100
Test name
Test status
Simulation time 219995753 ps
CPU time 1.64 seconds
Started Jul 19 04:34:34 PM PDT 24
Finished Jul 19 04:34:43 PM PDT 24
Peak memory 215988 kb
Host smart-19931d82-67e3-4342-8106-7c61a395610a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561336914 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3561336914
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3240236434
Short name T1090
Test name
Test status
Simulation time 53115758 ps
CPU time 1.19 seconds
Started Jul 19 04:34:09 PM PDT 24
Finished Jul 19 04:34:22 PM PDT 24
Peak memory 207700 kb
Host smart-74821d70-e080-4ce5-b67c-747e6f17e311
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240236434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3240236434
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.87754878
Short name T1101
Test name
Test status
Simulation time 57049056 ps
CPU time 0.73 seconds
Started Jul 19 04:34:19 PM PDT 24
Finished Jul 19 04:34:32 PM PDT 24
Peak memory 204360 kb
Host smart-3b00311e-47d4-4000-b0d5-11613cbaf150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87754878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.87754878
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3333542057
Short name T1080
Test name
Test status
Simulation time 103005879 ps
CPU time 2.7 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:27 PM PDT 24
Peak memory 215976 kb
Host smart-839a91fd-19de-4563-b760-fba456e480e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333542057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3333542057
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1530086487
Short name T101
Test name
Test status
Simulation time 56914585 ps
CPU time 3.03 seconds
Started Jul 19 04:34:08 PM PDT 24
Finished Jul 19 04:34:23 PM PDT 24
Peak memory 216116 kb
Host smart-20986a08-c176-429a-9e3b-d340aca387a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530086487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1530086487
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1861394855
Short name T114
Test name
Test status
Simulation time 553929263 ps
CPU time 13.99 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:29 PM PDT 24
Peak memory 215964 kb
Host smart-a1ac8f4a-6d0e-45b0-a360-a101a3065660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861394855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1861394855
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2425909233
Short name T1143
Test name
Test status
Simulation time 150252675 ps
CPU time 2.26 seconds
Started Jul 19 04:34:13 PM PDT 24
Finished Jul 19 04:34:28 PM PDT 24
Peak memory 218012 kb
Host smart-23a27a3d-3a79-420c-b01d-7bc9a62488fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425909233 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2425909233
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3789546732
Short name T129
Test name
Test status
Simulation time 36562799 ps
CPU time 1.2 seconds
Started Jul 19 04:34:35 PM PDT 24
Finished Jul 19 04:34:43 PM PDT 24
Peak memory 207652 kb
Host smart-f1aedd77-9d19-4f9f-b590-9ad63ba4b83e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789546732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3789546732
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1363946044
Short name T1147
Test name
Test status
Simulation time 14774896 ps
CPU time 0.77 seconds
Started Jul 19 04:34:18 PM PDT 24
Finished Jul 19 04:34:31 PM PDT 24
Peak memory 204924 kb
Host smart-09e82ab4-9589-4120-963e-85532c9c98ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363946044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1363946044
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1253400680
Short name T1071
Test name
Test status
Simulation time 60671805 ps
CPU time 3.55 seconds
Started Jul 19 04:34:10 PM PDT 24
Finished Jul 19 04:34:25 PM PDT 24
Peak memory 216012 kb
Host smart-2f9fa5ba-501f-4a72-992c-b82da54014a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253400680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1253400680
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1070766218
Short name T105
Test name
Test status
Simulation time 311387024 ps
CPU time 2.57 seconds
Started Jul 19 04:34:09 PM PDT 24
Finished Jul 19 04:34:24 PM PDT 24
Peak memory 217328 kb
Host smart-49b3c5da-0434-4aa9-a318-9d2477499d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070766218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1070766218
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3729076973
Short name T189
Test name
Test status
Simulation time 947605510 ps
CPU time 12.84 seconds
Started Jul 19 04:34:15 PM PDT 24
Finished Jul 19 04:34:40 PM PDT 24
Peak memory 216004 kb
Host smart-21c82949-f732-4afe-927b-7ec576fe7655
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729076973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3729076973
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.903115645
Short name T163
Test name
Test status
Simulation time 147135369 ps
CPU time 3.59 seconds
Started Jul 19 04:34:13 PM PDT 24
Finished Jul 19 04:34:30 PM PDT 24
Peak memory 217688 kb
Host smart-47a6c45b-2a46-49a4-b551-0fcfd43fc698
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903115645 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.903115645
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.117445799
Short name T1052
Test name
Test status
Simulation time 111154414 ps
CPU time 1.16 seconds
Started Jul 19 04:34:08 PM PDT 24
Finished Jul 19 04:34:21 PM PDT 24
Peak memory 215980 kb
Host smart-a9c7b2af-6f0e-44e3-96e6-e4d619416083
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117445799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.117445799
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3492842745
Short name T1068
Test name
Test status
Simulation time 52239547 ps
CPU time 0.75 seconds
Started Jul 19 04:34:15 PM PDT 24
Finished Jul 19 04:34:28 PM PDT 24
Peak memory 204396 kb
Host smart-8cdbdb3c-2968-4ca1-a139-488e2b80de48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492842745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3492842745
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2514556092
Short name T1060
Test name
Test status
Simulation time 247064841 ps
CPU time 1.69 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:26 PM PDT 24
Peak memory 207692 kb
Host smart-d91c63ea-d02b-4297-a4b5-996e484e9ca4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514556092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2514556092
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3036267882
Short name T108
Test name
Test status
Simulation time 763937726 ps
CPU time 3.34 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:27 PM PDT 24
Peak memory 216152 kb
Host smart-495cef0a-1a0e-47a9-8dc8-12b3cb014af1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036267882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3036267882
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2619876299
Short name T192
Test name
Test status
Simulation time 791691359 ps
CPU time 12.05 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:36 PM PDT 24
Peak memory 216236 kb
Host smart-27e09ac2-cfe4-4960-a8a3-8099f019d2c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619876299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2619876299
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1122343166
Short name T110
Test name
Test status
Simulation time 481792795 ps
CPU time 2.28 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:34:37 PM PDT 24
Peak memory 217124 kb
Host smart-0aa7f01b-7c96-4c24-bd01-ea3dabe730ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122343166 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1122343166
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2333751714
Short name T1117
Test name
Test status
Simulation time 70089862 ps
CPU time 1.29 seconds
Started Jul 19 04:34:07 PM PDT 24
Finished Jul 19 04:34:18 PM PDT 24
Peak memory 215984 kb
Host smart-b68838c2-569a-4f78-88ee-e6cd9827fc89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333751714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2333751714
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2863085169
Short name T1097
Test name
Test status
Simulation time 18297546 ps
CPU time 0.72 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:24 PM PDT 24
Peak memory 204700 kb
Host smart-182010d7-e6e1-41af-99ff-f883c1cb23d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863085169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2863085169
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2277034399
Short name T1091
Test name
Test status
Simulation time 736386132 ps
CPU time 4.1 seconds
Started Jul 19 04:34:07 PM PDT 24
Finished Jul 19 04:34:21 PM PDT 24
Peak memory 215692 kb
Host smart-5ffcc2f2-0d65-43de-9d12-0e66921fd628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277034399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2277034399
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.58587931
Short name T1142
Test name
Test status
Simulation time 74878087 ps
CPU time 4.67 seconds
Started Jul 19 04:34:07 PM PDT 24
Finished Jul 19 04:34:22 PM PDT 24
Peak memory 216260 kb
Host smart-ddd6600d-1d81-4023-8041-4eef3a1d937f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58587931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.58587931
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3998836046
Short name T95
Test name
Test status
Simulation time 110250955 ps
CPU time 6.15 seconds
Started Jul 19 04:34:21 PM PDT 24
Finished Jul 19 04:34:39 PM PDT 24
Peak memory 215868 kb
Host smart-51c2fea8-5904-4a39-b33a-9c65d73b0e32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998836046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3998836046
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3294772673
Short name T1127
Test name
Test status
Simulation time 205034036 ps
CPU time 3.54 seconds
Started Jul 19 04:34:08 PM PDT 24
Finished Jul 19 04:34:22 PM PDT 24
Peak memory 219032 kb
Host smart-d26f4b59-73ca-44f4-8706-b3c3ba0956da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294772673 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3294772673
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4125985034
Short name T128
Test name
Test status
Simulation time 36127874 ps
CPU time 2.58 seconds
Started Jul 19 04:34:15 PM PDT 24
Finished Jul 19 04:34:31 PM PDT 24
Peak memory 215896 kb
Host smart-16bf4c3d-e316-4068-82ff-c772e06fc8c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125985034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4125985034
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.721646413
Short name T1073
Test name
Test status
Simulation time 45706462 ps
CPU time 0.76 seconds
Started Jul 19 04:34:31 PM PDT 24
Finished Jul 19 04:34:41 PM PDT 24
Peak memory 204672 kb
Host smart-cbb6b4ac-ad03-4fcd-9979-356057205817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721646413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.721646413
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4123564214
Short name T1047
Test name
Test status
Simulation time 108685831 ps
CPU time 2.81 seconds
Started Jul 19 04:34:13 PM PDT 24
Finished Jul 19 04:34:29 PM PDT 24
Peak memory 215868 kb
Host smart-bc3062b4-1c01-4b11-aeaa-23392baa0158
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123564214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4123564214
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1891643389
Short name T102
Test name
Test status
Simulation time 172551457 ps
CPU time 3.62 seconds
Started Jul 19 04:34:07 PM PDT 24
Finished Jul 19 04:34:22 PM PDT 24
Peak memory 216056 kb
Host smart-2124d056-915f-4286-a46d-5c65e5cd7069
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891643389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1891643389
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2458687237
Short name T1094
Test name
Test status
Simulation time 1015137713 ps
CPU time 18.46 seconds
Started Jul 19 04:34:08 PM PDT 24
Finished Jul 19 04:34:38 PM PDT 24
Peak memory 215956 kb
Host smart-fc08c098-8211-48a2-a5a2-53849105a850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458687237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2458687237
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1280719900
Short name T1105
Test name
Test status
Simulation time 127319520 ps
CPU time 3.58 seconds
Started Jul 19 04:34:07 PM PDT 24
Finished Jul 19 04:34:21 PM PDT 24
Peak memory 217580 kb
Host smart-4552066e-3ff5-4298-a555-937f9ecbaba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280719900 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1280719900
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4121004604
Short name T120
Test name
Test status
Simulation time 222166477 ps
CPU time 2.06 seconds
Started Jul 19 04:34:31 PM PDT 24
Finished Jul 19 04:34:46 PM PDT 24
Peak memory 215696 kb
Host smart-616b6853-3220-4e1a-8802-cd1431e1a42d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121004604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4121004604
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4115966800
Short name T1106
Test name
Test status
Simulation time 50581964 ps
CPU time 0.72 seconds
Started Jul 19 04:34:10 PM PDT 24
Finished Jul 19 04:34:23 PM PDT 24
Peak memory 204424 kb
Host smart-4c9c669e-53fd-4bbc-b317-1387824f6b3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115966800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4115966800
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.407128393
Short name T1150
Test name
Test status
Simulation time 115728706 ps
CPU time 3.08 seconds
Started Jul 19 04:34:20 PM PDT 24
Finished Jul 19 04:34:35 PM PDT 24
Peak memory 215984 kb
Host smart-8e5825dd-7c2f-4799-8385-5f9878398ff5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407128393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.407128393
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4015472387
Short name T1104
Test name
Test status
Simulation time 160670667 ps
CPU time 3.66 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:28 PM PDT 24
Peak memory 216152 kb
Host smart-fff0e801-224f-44f1-80b4-3de2e6107a3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015472387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4015472387
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1266123844
Short name T1093
Test name
Test status
Simulation time 377886274 ps
CPU time 8.75 seconds
Started Jul 19 04:34:08 PM PDT 24
Finished Jul 19 04:34:28 PM PDT 24
Peak memory 215960 kb
Host smart-a26eba78-f482-4c2f-a8b0-19bd7d587b62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266123844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1266123844
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.547265610
Short name T1055
Test name
Test status
Simulation time 521252132 ps
CPU time 3.84 seconds
Started Jul 19 04:34:15 PM PDT 24
Finished Jul 19 04:34:32 PM PDT 24
Peak memory 218092 kb
Host smart-8c2997f8-0992-429a-b4c5-e643639f2754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547265610 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.547265610
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3198344920
Short name T1112
Test name
Test status
Simulation time 154367531 ps
CPU time 1.21 seconds
Started Jul 19 04:34:19 PM PDT 24
Finished Jul 19 04:34:36 PM PDT 24
Peak memory 207728 kb
Host smart-9a673fc0-2b68-403f-9a92-7d5b4cb40095
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198344920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3198344920
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1457916728
Short name T1058
Test name
Test status
Simulation time 14730011 ps
CPU time 0.7 seconds
Started Jul 19 04:34:18 PM PDT 24
Finished Jul 19 04:34:31 PM PDT 24
Peak memory 204676 kb
Host smart-e29a9060-5c53-4544-a517-8a48c3a567ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457916728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1457916728
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1604913129
Short name T1129
Test name
Test status
Simulation time 223900714 ps
CPU time 3.14 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:27 PM PDT 24
Peak memory 215936 kb
Host smart-7003cd8a-5305-4866-b2f9-f0eb2e9c590b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604913129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1604913129
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.666047083
Short name T111
Test name
Test status
Simulation time 130652123 ps
CPU time 3.28 seconds
Started Jul 19 04:34:14 PM PDT 24
Finished Jul 19 04:34:30 PM PDT 24
Peak memory 216372 kb
Host smart-64bdbdc4-fed2-4e16-a8e5-058a22dd4667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666047083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.666047083
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1249977717
Short name T191
Test name
Test status
Simulation time 1242849537 ps
CPU time 17.27 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:41 PM PDT 24
Peak memory 222132 kb
Host smart-07b28013-8908-41b1-b16c-4944690ec728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249977717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1249977717
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3029450074
Short name T165
Test name
Test status
Simulation time 76759915 ps
CPU time 1.94 seconds
Started Jul 19 04:34:09 PM PDT 24
Finished Jul 19 04:34:22 PM PDT 24
Peak memory 215832 kb
Host smart-86ddec28-14b5-49f1-82c5-a272eb1aa56a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029450074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3029450074
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1678433084
Short name T1133
Test name
Test status
Simulation time 13462220 ps
CPU time 0.72 seconds
Started Jul 19 04:34:07 PM PDT 24
Finished Jul 19 04:34:18 PM PDT 24
Peak memory 204420 kb
Host smart-079c9369-32ef-4026-a792-dbe24540a782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678433084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1678433084
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4104585922
Short name T162
Test name
Test status
Simulation time 297605191 ps
CPU time 3.05 seconds
Started Jul 19 04:34:17 PM PDT 24
Finished Jul 19 04:34:33 PM PDT 24
Peak memory 215892 kb
Host smart-724e6b2e-d3fc-498e-85e2-81217d25f536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104585922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4104585922
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3862785788
Short name T1077
Test name
Test status
Simulation time 30928814 ps
CPU time 2.02 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:26 PM PDT 24
Peak memory 216108 kb
Host smart-7b0ec04b-5260-41aa-966d-947b84df8a4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862785788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3862785788
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2774729335
Short name T164
Test name
Test status
Simulation time 135517491 ps
CPU time 1.8 seconds
Started Jul 19 04:34:13 PM PDT 24
Finished Jul 19 04:34:28 PM PDT 24
Peak memory 216036 kb
Host smart-1ca9445e-e9fc-4058-93bf-1b06abd0256b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774729335 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2774729335
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2645963937
Short name T1088
Test name
Test status
Simulation time 406120907 ps
CPU time 2.49 seconds
Started Jul 19 04:34:13 PM PDT 24
Finished Jul 19 04:34:29 PM PDT 24
Peak memory 215832 kb
Host smart-cfce38a4-1437-488b-9f72-6654e05490df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645963937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2645963937
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4164483543
Short name T1042
Test name
Test status
Simulation time 12224061 ps
CPU time 0.71 seconds
Started Jul 19 04:34:10 PM PDT 24
Finished Jul 19 04:34:23 PM PDT 24
Peak memory 204316 kb
Host smart-af8a9aad-f438-41d9-9a56-93c384eabba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164483543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4164483543
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4083692117
Short name T160
Test name
Test status
Simulation time 559544220 ps
CPU time 3.17 seconds
Started Jul 19 04:34:19 PM PDT 24
Finished Jul 19 04:34:34 PM PDT 24
Peak memory 215984 kb
Host smart-3b5d085b-8429-4791-a4a9-592c08c7c06e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083692117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4083692117
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1860537340
Short name T1084
Test name
Test status
Simulation time 30179225 ps
CPU time 1.59 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:17 PM PDT 24
Peak memory 216124 kb
Host smart-89c778f1-ee1d-49ed-bf16-282e1f141446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860537340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1860537340
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1408974575
Short name T1149
Test name
Test status
Simulation time 553724943 ps
CPU time 13.84 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:38 PM PDT 24
Peak memory 217088 kb
Host smart-d6044c84-f93c-4af8-841e-1ad8a0a16781
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408974575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1408974575
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2139057168
Short name T121
Test name
Test status
Simulation time 507431109 ps
CPU time 8.09 seconds
Started Jul 19 04:34:04 PM PDT 24
Finished Jul 19 04:34:20 PM PDT 24
Peak memory 215912 kb
Host smart-a27249bc-ce9e-47f7-8bc0-731acb01e474
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139057168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2139057168
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2185625085
Short name T1148
Test name
Test status
Simulation time 671483131 ps
CPU time 11.06 seconds
Started Jul 19 04:33:59 PM PDT 24
Finished Jul 19 04:34:16 PM PDT 24
Peak memory 215800 kb
Host smart-10f11822-fa4e-4ff6-897d-d7a6c950196d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185625085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2185625085
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2477497227
Short name T1075
Test name
Test status
Simulation time 118826983 ps
CPU time 3.46 seconds
Started Jul 19 04:33:59 PM PDT 24
Finished Jul 19 04:34:09 PM PDT 24
Peak memory 218436 kb
Host smart-e3a7d61e-a3c0-469c-9005-f9fbb1bdce40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477497227 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2477497227
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1995309348
Short name T1102
Test name
Test status
Simulation time 231147798 ps
CPU time 1.84 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:17 PM PDT 24
Peak memory 207700 kb
Host smart-d1ea58a9-71aa-449e-b418-827afc867fda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995309348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
995309348
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1374508589
Short name T1110
Test name
Test status
Simulation time 18699504 ps
CPU time 0.75 seconds
Started Jul 19 04:33:58 PM PDT 24
Finished Jul 19 04:34:04 PM PDT 24
Peak memory 204388 kb
Host smart-a11454dc-6797-4bd9-bd68-d273d5ed74ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374508589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
374508589
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.994555886
Short name T126
Test name
Test status
Simulation time 180540323 ps
CPU time 1.63 seconds
Started Jul 19 04:34:05 PM PDT 24
Finished Jul 19 04:34:15 PM PDT 24
Peak memory 215948 kb
Host smart-17ea060a-eb74-427f-bfad-6c090299cb47
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994555886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.994555886
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.789991559
Short name T1036
Test name
Test status
Simulation time 21212472 ps
CPU time 0.67 seconds
Started Jul 19 04:34:00 PM PDT 24
Finished Jul 19 04:34:06 PM PDT 24
Peak memory 204664 kb
Host smart-9734032d-1f7d-4f2f-b548-d65d25a94f96
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789991559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.789991559
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.825806700
Short name T1092
Test name
Test status
Simulation time 193018772 ps
CPU time 4 seconds
Started Jul 19 04:34:04 PM PDT 24
Finished Jul 19 04:34:16 PM PDT 24
Peak memory 215840 kb
Host smart-9a44b7c7-7f86-4de1-952a-7ce26bec7e44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825806700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.825806700
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1777047462
Short name T104
Test name
Test status
Simulation time 812434158 ps
CPU time 4.8 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:19 PM PDT 24
Peak memory 215484 kb
Host smart-0ba1322e-07b9-4e8f-a3ed-c29f50329cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777047462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
777047462
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1383464858
Short name T96
Test name
Test status
Simulation time 808798173 ps
CPU time 6.85 seconds
Started Jul 19 04:34:01 PM PDT 24
Finished Jul 19 04:34:15 PM PDT 24
Peak memory 215944 kb
Host smart-6d22fc29-7ca9-412a-90b2-0aafb944d5a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383464858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1383464858
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.831180956
Short name T1151
Test name
Test status
Simulation time 23351481 ps
CPU time 0.69 seconds
Started Jul 19 04:34:10 PM PDT 24
Finished Jul 19 04:34:23 PM PDT 24
Peak memory 204364 kb
Host smart-5db4dbe2-a030-4819-bbe2-7f050b0ad7ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831180956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.831180956
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1026879628
Short name T1082
Test name
Test status
Simulation time 12600294 ps
CPU time 0.78 seconds
Started Jul 19 04:34:16 PM PDT 24
Finished Jul 19 04:34:30 PM PDT 24
Peak memory 204408 kb
Host smart-7445a1c5-860c-46af-99fa-1575a35297f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026879628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1026879628
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3720284316
Short name T1041
Test name
Test status
Simulation time 20849230 ps
CPU time 0.69 seconds
Started Jul 19 04:34:15 PM PDT 24
Finished Jul 19 04:34:29 PM PDT 24
Peak memory 204364 kb
Host smart-bb0cb99d-0c03-482c-b620-1874bc251a53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720284316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3720284316
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1772381117
Short name T1114
Test name
Test status
Simulation time 51748580 ps
CPU time 0.74 seconds
Started Jul 19 04:34:16 PM PDT 24
Finished Jul 19 04:34:30 PM PDT 24
Peak memory 204712 kb
Host smart-bd1ed144-800a-4bbf-a43c-eee0cc75048b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772381117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1772381117
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1399868485
Short name T1131
Test name
Test status
Simulation time 30968496 ps
CPU time 0.73 seconds
Started Jul 19 04:34:08 PM PDT 24
Finished Jul 19 04:34:19 PM PDT 24
Peak memory 204444 kb
Host smart-ab676d1c-b5f0-46d8-acee-a444ef72124e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399868485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1399868485
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4201144339
Short name T1138
Test name
Test status
Simulation time 19070704 ps
CPU time 0.68 seconds
Started Jul 19 04:34:23 PM PDT 24
Finished Jul 19 04:34:35 PM PDT 24
Peak memory 204620 kb
Host smart-cf66b4ee-7267-4a0e-a9cd-d568eadd7197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201144339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4201144339
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3739309490
Short name T1107
Test name
Test status
Simulation time 50784167 ps
CPU time 0.71 seconds
Started Jul 19 04:34:31 PM PDT 24
Finished Jul 19 04:34:40 PM PDT 24
Peak memory 204352 kb
Host smart-d5ce4c43-8ae7-4bac-83bd-7060c09b7f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739309490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3739309490
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3541632931
Short name T1124
Test name
Test status
Simulation time 34901361 ps
CPU time 0.71 seconds
Started Jul 19 04:34:29 PM PDT 24
Finished Jul 19 04:34:39 PM PDT 24
Peak memory 204352 kb
Host smart-13759aa2-73c9-4207-8bb0-0a54bff6a7c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541632931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3541632931
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.945667550
Short name T1079
Test name
Test status
Simulation time 48095732 ps
CPU time 0.71 seconds
Started Jul 19 04:34:12 PM PDT 24
Finished Jul 19 04:34:25 PM PDT 24
Peak memory 204380 kb
Host smart-d982da0a-81ac-4696-b25d-778b56117bdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945667550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.945667550
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3797032342
Short name T1078
Test name
Test status
Simulation time 19795354 ps
CPU time 0.73 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:25 PM PDT 24
Peak memory 204680 kb
Host smart-8ee1d077-e506-40a8-ae66-a623a8980dff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797032342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3797032342
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1761005218
Short name T1144
Test name
Test status
Simulation time 1196921208 ps
CPU time 21.25 seconds
Started Jul 19 04:34:00 PM PDT 24
Finished Jul 19 04:34:27 PM PDT 24
Peak memory 217160 kb
Host smart-6d37035a-a15e-4798-b9dd-ae5102f7937f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761005218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1761005218
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4238054375
Short name T1095
Test name
Test status
Simulation time 5453911127 ps
CPU time 23.02 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:40 PM PDT 24
Peak memory 215868 kb
Host smart-95cbfa70-2416-43be-8180-93659c3aa237
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238054375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.4238054375
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.912230535
Short name T81
Test name
Test status
Simulation time 29573021 ps
CPU time 1 seconds
Started Jul 19 04:34:08 PM PDT 24
Finished Jul 19 04:34:20 PM PDT 24
Peak memory 207528 kb
Host smart-d3d2871f-a0d3-4c53-a478-953e019d998f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912230535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.912230535
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2988206808
Short name T1116
Test name
Test status
Simulation time 140837591 ps
CPU time 1.61 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:25 PM PDT 24
Peak memory 216040 kb
Host smart-e682807f-b3e1-4186-8261-686d85437165
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988206808 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2988206808
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1186144889
Short name T130
Test name
Test status
Simulation time 358302102 ps
CPU time 2.51 seconds
Started Jul 19 04:33:59 PM PDT 24
Finished Jul 19 04:34:06 PM PDT 24
Peak memory 215900 kb
Host smart-89c8f61e-1ace-4880-96cb-e229531fe61f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186144889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
186144889
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2699156009
Short name T1050
Test name
Test status
Simulation time 27927568 ps
CPU time 0.7 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:17 PM PDT 24
Peak memory 204408 kb
Host smart-2ba4d8f3-7331-41e1-adb2-4d7c60e81bae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699156009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
699156009
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.606010881
Short name T123
Test name
Test status
Simulation time 40285214 ps
CPU time 1.63 seconds
Started Jul 19 04:34:01 PM PDT 24
Finished Jul 19 04:34:08 PM PDT 24
Peak memory 215988 kb
Host smart-87e59aec-3ef5-44c0-b9e4-a12681c112b4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606010881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.606010881
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1524148077
Short name T1120
Test name
Test status
Simulation time 30320758 ps
CPU time 0.64 seconds
Started Jul 19 04:34:00 PM PDT 24
Finished Jul 19 04:34:07 PM PDT 24
Peak memory 204320 kb
Host smart-682b9450-1a6d-4769-9544-758d4f55ec2b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524148077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1524148077
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.893880157
Short name T1059
Test name
Test status
Simulation time 55098972 ps
CPU time 1.76 seconds
Started Jul 19 04:34:03 PM PDT 24
Finished Jul 19 04:34:12 PM PDT 24
Peak memory 215912 kb
Host smart-85b8ffc1-e28e-400e-90fc-8f80db84159b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893880157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.893880157
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.536247612
Short name T103
Test name
Test status
Simulation time 146020534 ps
CPU time 3.61 seconds
Started Jul 19 04:34:02 PM PDT 24
Finished Jul 19 04:34:12 PM PDT 24
Peak memory 216220 kb
Host smart-394a1066-2a78-46cf-9a22-c6c9167f4691
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536247612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.536247612
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3510768338
Short name T167
Test name
Test status
Simulation time 1316364936 ps
CPU time 7.44 seconds
Started Jul 19 04:34:03 PM PDT 24
Finished Jul 19 04:34:17 PM PDT 24
Peak memory 215908 kb
Host smart-9e68b5ae-1655-4eee-881b-7957faec0b24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510768338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3510768338
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.597009419
Short name T1087
Test name
Test status
Simulation time 14671796 ps
CPU time 0.71 seconds
Started Jul 19 04:34:30 PM PDT 24
Finished Jul 19 04:34:40 PM PDT 24
Peak memory 204336 kb
Host smart-627eccf3-c1ad-4f53-9909-5517d8e746a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597009419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.597009419
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2528819210
Short name T1063
Test name
Test status
Simulation time 23722956 ps
CPU time 0.71 seconds
Started Jul 19 04:34:31 PM PDT 24
Finished Jul 19 04:34:41 PM PDT 24
Peak memory 204176 kb
Host smart-372d2731-a5b4-4dc5-924d-67faf06ef3c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528819210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2528819210
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2327906689
Short name T1045
Test name
Test status
Simulation time 27267112 ps
CPU time 0.73 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:17 PM PDT 24
Peak memory 204468 kb
Host smart-1473962a-2a8b-49cf-a5d4-1d94d7af8a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327906689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2327906689
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.337424102
Short name T1056
Test name
Test status
Simulation time 46910756 ps
CPU time 0.71 seconds
Started Jul 19 04:34:17 PM PDT 24
Finished Jul 19 04:34:30 PM PDT 24
Peak memory 204684 kb
Host smart-fb8d7881-637f-47a4-8d5a-a44a62e01018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337424102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.337424102
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1406884001
Short name T1135
Test name
Test status
Simulation time 16041713 ps
CPU time 0.68 seconds
Started Jul 19 04:34:09 PM PDT 24
Finished Jul 19 04:34:21 PM PDT 24
Peak memory 204284 kb
Host smart-a6ace8fd-23ff-40cd-bbc3-ee1b946e9812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406884001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1406884001
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3068165951
Short name T1122
Test name
Test status
Simulation time 11737642 ps
CPU time 0.7 seconds
Started Jul 19 04:34:09 PM PDT 24
Finished Jul 19 04:34:21 PM PDT 24
Peak memory 204404 kb
Host smart-87f44b66-a5c1-4735-8bcf-4ecfc092eae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068165951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3068165951
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1281754309
Short name T1146
Test name
Test status
Simulation time 31851393 ps
CPU time 0.69 seconds
Started Jul 19 04:34:31 PM PDT 24
Finished Jul 19 04:34:41 PM PDT 24
Peak memory 204364 kb
Host smart-c87cf8d0-4287-4cbc-8bf5-1d902e679c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281754309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1281754309
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3846509694
Short name T1048
Test name
Test status
Simulation time 57144722 ps
CPU time 0.7 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:34:36 PM PDT 24
Peak memory 204336 kb
Host smart-54ef2452-42b6-4330-89ac-5624f29cabbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846509694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3846509694
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2436853998
Short name T1064
Test name
Test status
Simulation time 46124921 ps
CPU time 0.74 seconds
Started Jul 19 04:34:32 PM PDT 24
Finished Jul 19 04:34:41 PM PDT 24
Peak memory 204664 kb
Host smart-791a3538-cf51-415c-8bdc-c071923c942a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436853998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2436853998
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3302324573
Short name T1062
Test name
Test status
Simulation time 36164946 ps
CPU time 0.74 seconds
Started Jul 19 04:34:11 PM PDT 24
Finished Jul 19 04:34:25 PM PDT 24
Peak memory 204452 kb
Host smart-d343bbb7-49ac-40e2-a512-0124440f6352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302324573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3302324573
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3878335172
Short name T132
Test name
Test status
Simulation time 926220469 ps
CPU time 22.04 seconds
Started Jul 19 04:34:04 PM PDT 24
Finished Jul 19 04:34:34 PM PDT 24
Peak memory 215916 kb
Host smart-4ecd49d6-8cd0-4a1e-bb3d-934f1f1bce34
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878335172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3878335172
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.562417323
Short name T1130
Test name
Test status
Simulation time 3761101013 ps
CPU time 13.7 seconds
Started Jul 19 04:34:08 PM PDT 24
Finished Jul 19 04:34:34 PM PDT 24
Peak memory 207708 kb
Host smart-f00b2451-1b72-42ba-a60a-007ce7d60204
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562417323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.562417323
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2018184011
Short name T83
Test name
Test status
Simulation time 366985083 ps
CPU time 1.43 seconds
Started Jul 19 04:34:13 PM PDT 24
Finished Jul 19 04:34:27 PM PDT 24
Peak memory 207712 kb
Host smart-30ab0cd8-6d63-4067-9b3b-18583982b0c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018184011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2018184011
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2834893048
Short name T109
Test name
Test status
Simulation time 56261332 ps
CPU time 3.92 seconds
Started Jul 19 04:34:07 PM PDT 24
Finished Jul 19 04:34:21 PM PDT 24
Peak memory 218504 kb
Host smart-b5c1d421-2a8f-45b2-96ec-0707907dfcdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834893048 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2834893048
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2781665125
Short name T127
Test name
Test status
Simulation time 35349403 ps
CPU time 2.2 seconds
Started Jul 19 04:34:07 PM PDT 24
Finished Jul 19 04:34:20 PM PDT 24
Peak memory 215904 kb
Host smart-4d250e90-1dfd-4063-b253-6138272cc602
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781665125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
781665125
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4077690674
Short name T1085
Test name
Test status
Simulation time 15228268 ps
CPU time 0.77 seconds
Started Jul 19 04:34:00 PM PDT 24
Finished Jul 19 04:34:06 PM PDT 24
Peak memory 204436 kb
Host smart-0429201e-bd5f-47a4-bd10-d5b6412ce1d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077690674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
077690674
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3582143626
Short name T133
Test name
Test status
Simulation time 49259229 ps
CPU time 2.07 seconds
Started Jul 19 04:34:05 PM PDT 24
Finished Jul 19 04:34:15 PM PDT 24
Peak memory 215908 kb
Host smart-1c6421ca-a30b-475d-8539-bff4e23a9137
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582143626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3582143626
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.609193083
Short name T1044
Test name
Test status
Simulation time 11097735 ps
CPU time 0.66 seconds
Started Jul 19 04:33:59 PM PDT 24
Finished Jul 19 04:34:06 PM PDT 24
Peak memory 204652 kb
Host smart-86b537d0-0ec7-409f-b48b-b8b371730423
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609193083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.609193083
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2764087088
Short name T1065
Test name
Test status
Simulation time 593009031 ps
CPU time 2.95 seconds
Started Jul 19 04:34:03 PM PDT 24
Finished Jul 19 04:34:12 PM PDT 24
Peak memory 215892 kb
Host smart-dd0c6e8a-0746-4bf3-a6a9-e9c0f58869cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764087088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2764087088
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3178098388
Short name T1139
Test name
Test status
Simulation time 1437537992 ps
CPU time 3.65 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:20 PM PDT 24
Peak memory 216144 kb
Host smart-f88d3de0-d360-4c60-97cc-7ee6b8ab9ddd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178098388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
178098388
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.128462809
Short name T1132
Test name
Test status
Simulation time 1328345765 ps
CPU time 7.9 seconds
Started Jul 19 04:33:57 PM PDT 24
Finished Jul 19 04:34:09 PM PDT 24
Peak memory 216448 kb
Host smart-d43cc2d1-2f6c-4994-a42a-27adb0fa9641
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128462809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.128462809
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2861322381
Short name T1103
Test name
Test status
Simulation time 11849189 ps
CPU time 0.76 seconds
Started Jul 19 04:34:08 PM PDT 24
Finished Jul 19 04:34:20 PM PDT 24
Peak memory 204920 kb
Host smart-803131cb-794f-4384-9d45-663b915fd22a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861322381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2861322381
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3918893775
Short name T1115
Test name
Test status
Simulation time 12533914 ps
CPU time 0.72 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:34:36 PM PDT 24
Peak memory 204392 kb
Host smart-f327a027-61c5-4bd9-aa3b-e147db3ff761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918893775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3918893775
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1796057026
Short name T1081
Test name
Test status
Simulation time 85768040 ps
CPU time 0.71 seconds
Started Jul 19 04:34:14 PM PDT 24
Finished Jul 19 04:34:27 PM PDT 24
Peak memory 204416 kb
Host smart-0a19863a-1d9e-4cec-99a6-5ca39f41682f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796057026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1796057026
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3248446748
Short name T1051
Test name
Test status
Simulation time 33370956 ps
CPU time 0.73 seconds
Started Jul 19 04:35:44 PM PDT 24
Finished Jul 19 04:35:51 PM PDT 24
Peak memory 204368 kb
Host smart-d3876ab6-6fb5-49f2-ad85-8c509af6f646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248446748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3248446748
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1545808268
Short name T1067
Test name
Test status
Simulation time 16469593 ps
CPU time 0.76 seconds
Started Jul 19 04:34:19 PM PDT 24
Finished Jul 19 04:34:32 PM PDT 24
Peak memory 204340 kb
Host smart-4530ac04-07f1-4e5c-a464-832ada788d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545808268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1545808268
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3095054523
Short name T1057
Test name
Test status
Simulation time 15591686 ps
CPU time 0.66 seconds
Started Jul 19 04:34:16 PM PDT 24
Finished Jul 19 04:34:29 PM PDT 24
Peak memory 204412 kb
Host smart-3be1c1de-1b87-404d-ae5d-a18de1aaadc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095054523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3095054523
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2790691785
Short name T1145
Test name
Test status
Simulation time 15286856 ps
CPU time 0.74 seconds
Started Jul 19 04:34:18 PM PDT 24
Finished Jul 19 04:34:31 PM PDT 24
Peak memory 204728 kb
Host smart-dbf2ae11-1d3f-4ce1-8e5d-10edfccc1808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790691785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2790691785
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1973232079
Short name T1118
Test name
Test status
Simulation time 26168225 ps
CPU time 0.72 seconds
Started Jul 19 04:34:24 PM PDT 24
Finished Jul 19 04:34:36 PM PDT 24
Peak memory 204692 kb
Host smart-80f931f5-0039-492d-b276-085e7bd5e078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973232079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1973232079
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2032669009
Short name T1046
Test name
Test status
Simulation time 13649266 ps
CPU time 0.7 seconds
Started Jul 19 04:34:17 PM PDT 24
Finished Jul 19 04:34:30 PM PDT 24
Peak memory 204724 kb
Host smart-fd30e36e-0210-420d-bc96-60c74ec87702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032669009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2032669009
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2389602150
Short name T1070
Test name
Test status
Simulation time 45586480 ps
CPU time 0.68 seconds
Started Jul 19 04:34:14 PM PDT 24
Finished Jul 19 04:34:27 PM PDT 24
Peak memory 204384 kb
Host smart-62380c40-be32-4024-9c66-0ec7cb576f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389602150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2389602150
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3082624526
Short name T1125
Test name
Test status
Simulation time 211645197 ps
CPU time 1.64 seconds
Started Jul 19 04:34:02 PM PDT 24
Finished Jul 19 04:34:11 PM PDT 24
Peak memory 216116 kb
Host smart-85b1d908-90b8-4741-849f-a349e7231ff0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082624526 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3082624526
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.702242419
Short name T1038
Test name
Test status
Simulation time 369974037 ps
CPU time 2.56 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:17 PM PDT 24
Peak memory 215904 kb
Host smart-7cb10228-cb52-47b0-b5ee-8b6a36452aee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702242419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.702242419
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2573517857
Short name T1072
Test name
Test status
Simulation time 40293722 ps
CPU time 0.76 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:15 PM PDT 24
Peak memory 203616 kb
Host smart-1abfbd8c-c57a-4be3-8f99-2c054628ba90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573517857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
573517857
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2234858447
Short name T161
Test name
Test status
Simulation time 217297914 ps
CPU time 4.41 seconds
Started Jul 19 04:34:01 PM PDT 24
Finished Jul 19 04:34:12 PM PDT 24
Peak memory 215912 kb
Host smart-a6275023-abb7-4f02-8414-bcc677b1f957
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234858447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2234858447
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4154044658
Short name T190
Test name
Test status
Simulation time 3478445747 ps
CPU time 19.3 seconds
Started Jul 19 04:34:03 PM PDT 24
Finished Jul 19 04:34:30 PM PDT 24
Peak memory 216612 kb
Host smart-d5472f84-ae10-4f35-9fd3-ac4f463184b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154044658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4154044658
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1095631831
Short name T1099
Test name
Test status
Simulation time 372240255 ps
CPU time 2.66 seconds
Started Jul 19 04:34:00 PM PDT 24
Finished Jul 19 04:34:08 PM PDT 24
Peak memory 218408 kb
Host smart-0a8900ed-0cd5-4b57-a044-0f11b6c3fc28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095631831 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1095631831
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3751115956
Short name T1137
Test name
Test status
Simulation time 18711561 ps
CPU time 0.78 seconds
Started Jul 19 04:34:00 PM PDT 24
Finished Jul 19 04:34:07 PM PDT 24
Peak memory 204708 kb
Host smart-404202ff-a57b-4c47-b528-b2f60418db37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751115956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
751115956
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1885112422
Short name T1037
Test name
Test status
Simulation time 341028622 ps
CPU time 4.13 seconds
Started Jul 19 04:34:02 PM PDT 24
Finished Jul 19 04:34:13 PM PDT 24
Peak memory 215828 kb
Host smart-7049ee39-c3d2-4185-bd06-1409f76e27cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885112422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1885112422
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3100755065
Short name T185
Test name
Test status
Simulation time 44910771 ps
CPU time 2.52 seconds
Started Jul 19 04:34:01 PM PDT 24
Finished Jul 19 04:34:10 PM PDT 24
Peak memory 216376 kb
Host smart-aec1745c-c3be-4073-b917-a0b4183f508c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100755065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
100755065
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3264979962
Short name T186
Test name
Test status
Simulation time 1096844078 ps
CPU time 7.55 seconds
Started Jul 19 04:34:03 PM PDT 24
Finished Jul 19 04:34:18 PM PDT 24
Peak memory 216480 kb
Host smart-bff1d913-d1d8-430a-805c-5b2ef46629db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264979962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3264979962
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1246914626
Short name T113
Test name
Test status
Simulation time 100556893 ps
CPU time 1.6 seconds
Started Jul 19 04:34:05 PM PDT 24
Finished Jul 19 04:34:15 PM PDT 24
Peak memory 215964 kb
Host smart-3fad7cb9-bc90-4b66-8bda-d01914b9ba7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246914626 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1246914626
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1590296673
Short name T131
Test name
Test status
Simulation time 86643847 ps
CPU time 1.29 seconds
Started Jul 19 04:34:05 PM PDT 24
Finished Jul 19 04:34:15 PM PDT 24
Peak memory 207724 kb
Host smart-e532fb32-f593-48f5-b61b-346b676ddfdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590296673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
590296673
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1672261130
Short name T1121
Test name
Test status
Simulation time 154319254 ps
CPU time 0.75 seconds
Started Jul 19 04:34:01 PM PDT 24
Finished Jul 19 04:34:08 PM PDT 24
Peak memory 204596 kb
Host smart-45638296-0eb7-4d18-b14e-a9937cfaa87b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672261130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
672261130
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3047826563
Short name T1100
Test name
Test status
Simulation time 54256835 ps
CPU time 2.51 seconds
Started Jul 19 04:34:08 PM PDT 24
Finished Jul 19 04:34:21 PM PDT 24
Peak memory 215860 kb
Host smart-c7e6952f-0847-4dd2-acf7-852ab0e9d2e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047826563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3047826563
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2200229885
Short name T99
Test name
Test status
Simulation time 57158159 ps
CPU time 1.8 seconds
Started Jul 19 04:34:08 PM PDT 24
Finished Jul 19 04:34:22 PM PDT 24
Peak memory 216116 kb
Host smart-db4b2a70-cc47-4142-93b4-4a0739da118e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200229885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
200229885
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.18623143
Short name T112
Test name
Test status
Simulation time 2200571181 ps
CPU time 7.34 seconds
Started Jul 19 04:34:06 PM PDT 24
Finished Jul 19 04:34:22 PM PDT 24
Peak memory 217756 kb
Host smart-dc43f977-368e-4785-bab1-857603c1f9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18623143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_t
l_intg_err.18623143
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.494340851
Short name T1049
Test name
Test status
Simulation time 379292194 ps
CPU time 1.65 seconds
Started Jul 19 04:34:09 PM PDT 24
Finished Jul 19 04:34:22 PM PDT 24
Peak memory 215912 kb
Host smart-0679cf5f-18f4-413c-85f0-4920ee40186e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494340851 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.494340851
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1842383938
Short name T1128
Test name
Test status
Simulation time 65237765 ps
CPU time 1.63 seconds
Started Jul 19 04:34:05 PM PDT 24
Finished Jul 19 04:34:16 PM PDT 24
Peak memory 207824 kb
Host smart-906bab76-6ee4-4625-b2ab-3f1fbd8f4d82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842383938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
842383938
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2303483468
Short name T1069
Test name
Test status
Simulation time 23443657 ps
CPU time 0.68 seconds
Started Jul 19 04:34:02 PM PDT 24
Finished Jul 19 04:34:09 PM PDT 24
Peak memory 204396 kb
Host smart-fec41a7a-d432-4b37-bc95-1dc82490949b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303483468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
303483468
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1030656738
Short name T1066
Test name
Test status
Simulation time 50918887 ps
CPU time 1.76 seconds
Started Jul 19 04:34:01 PM PDT 24
Finished Jul 19 04:34:10 PM PDT 24
Peak memory 215900 kb
Host smart-761e73e7-e9f0-4937-825c-753dfd12d6a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030656738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1030656738
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.112322890
Short name T1113
Test name
Test status
Simulation time 52911138 ps
CPU time 1.76 seconds
Started Jul 19 04:34:09 PM PDT 24
Finished Jul 19 04:34:23 PM PDT 24
Peak memory 215968 kb
Host smart-406944cc-a957-4920-b6e0-13ae0b067662
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112322890 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.112322890
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.397320617
Short name T1098
Test name
Test status
Simulation time 67123062 ps
CPU time 1.93 seconds
Started Jul 19 04:34:17 PM PDT 24
Finished Jul 19 04:34:32 PM PDT 24
Peak memory 215848 kb
Host smart-837c38fd-dc74-4974-b4a1-78f41a004ab2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397320617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.397320617
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3116477484
Short name T1136
Test name
Test status
Simulation time 27942190 ps
CPU time 0.75 seconds
Started Jul 19 04:33:54 PM PDT 24
Finished Jul 19 04:34:00 PM PDT 24
Peak memory 204512 kb
Host smart-f83bacbd-01d6-4716-a9da-43c526b6e149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116477484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
116477484
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1324782017
Short name T1119
Test name
Test status
Simulation time 226403076 ps
CPU time 1.72 seconds
Started Jul 19 04:34:32 PM PDT 24
Finished Jul 19 04:34:42 PM PDT 24
Peak memory 215968 kb
Host smart-03b52a0c-b0b5-40ee-8582-2ad369011f64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324782017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1324782017
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4040666244
Short name T1089
Test name
Test status
Simulation time 55415183 ps
CPU time 1.69 seconds
Started Jul 19 04:34:03 PM PDT 24
Finished Jul 19 04:34:13 PM PDT 24
Peak memory 215992 kb
Host smart-e6ab7a2a-849c-4f41-8850-a377ad0f67f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040666244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
040666244
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.547618857
Short name T1053
Test name
Test status
Simulation time 520741614 ps
CPU time 7 seconds
Started Jul 19 04:34:07 PM PDT 24
Finished Jul 19 04:34:25 PM PDT 24
Peak memory 223468 kb
Host smart-11484c83-8566-47bd-b55a-f7308a79b76a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547618857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.547618857
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1420934814
Short name T511
Test name
Test status
Simulation time 112150239 ps
CPU time 0.72 seconds
Started Jul 19 05:34:35 PM PDT 24
Finished Jul 19 05:34:40 PM PDT 24
Peak memory 205164 kb
Host smart-7637a1fe-e703-4689-950f-3ad3955dc2d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420934814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
420934814
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.806309600
Short name T197
Test name
Test status
Simulation time 11454129160 ps
CPU time 24.87 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:35:17 PM PDT 24
Peak memory 233176 kb
Host smart-d99b33b9-1479-4812-a8c8-5efc2044dab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806309600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.806309600
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3905090859
Short name T531
Test name
Test status
Simulation time 61476331 ps
CPU time 0.79 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:34:54 PM PDT 24
Peak memory 206856 kb
Host smart-5a8f1ed5-0dba-487c-a344-759c4cd8d59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905090859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3905090859
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3701685832
Short name T294
Test name
Test status
Simulation time 16241131637 ps
CPU time 88.41 seconds
Started Jul 19 05:34:36 PM PDT 24
Finished Jul 19 05:36:13 PM PDT 24
Peak memory 257872 kb
Host smart-bafc04fe-cd46-452e-8d88-4afbc4a2176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701685832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3701685832
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.769965684
Short name T306
Test name
Test status
Simulation time 2678548396 ps
CPU time 61.07 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:35:54 PM PDT 24
Peak memory 257120 kb
Host smart-a94825bf-94d8-47e7-ab2f-ca51ccec9c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769965684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.769965684
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1285257698
Short name T790
Test name
Test status
Simulation time 4944894481 ps
CPU time 36.6 seconds
Started Jul 19 05:34:39 PM PDT 24
Finished Jul 19 05:35:46 PM PDT 24
Peak memory 238568 kb
Host smart-e1ed5dd7-fd46-4403-96c4-ba3f51f5c16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285257698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1285257698
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.537603027
Short name T329
Test name
Test status
Simulation time 948994013 ps
CPU time 5.83 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:34:59 PM PDT 24
Peak memory 233132 kb
Host smart-067954f8-0019-4ab3-8974-c290fef513c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537603027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.537603027
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3001662462
Short name T510
Test name
Test status
Simulation time 71006496794 ps
CPU time 148.7 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:37:24 PM PDT 24
Peak memory 266084 kb
Host smart-868224bb-ef8c-4297-8b2f-2efb8e968253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001662462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3001662462
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3091051385
Short name T436
Test name
Test status
Simulation time 442565603 ps
CPU time 4.16 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:35:00 PM PDT 24
Peak memory 233144 kb
Host smart-8a323f0d-e96b-4f09-9af6-d4f0b1ae9e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091051385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3091051385
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2796065217
Short name T495
Test name
Test status
Simulation time 601384757 ps
CPU time 10.32 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:35:04 PM PDT 24
Peak memory 240884 kb
Host smart-89e50c1c-e807-4abf-b20e-fdcdaa14334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796065217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2796065217
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3827432854
Short name T467
Test name
Test status
Simulation time 746293655 ps
CPU time 6.62 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:35:02 PM PDT 24
Peak memory 240348 kb
Host smart-8d6d4527-515e-4881-8ecb-4cc3327ba009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827432854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3827432854
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1444168509
Short name T982
Test name
Test status
Simulation time 70299369 ps
CPU time 2.52 seconds
Started Jul 19 05:34:38 PM PDT 24
Finished Jul 19 05:35:09 PM PDT 24
Peak memory 233056 kb
Host smart-80969316-3764-46f4-b317-c270b88cac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444168509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1444168509
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2028796994
Short name T518
Test name
Test status
Simulation time 13005064362 ps
CPU time 15.92 seconds
Started Jul 19 05:34:35 PM PDT 24
Finished Jul 19 05:34:54 PM PDT 24
Peak memory 222024 kb
Host smart-1f7d2f7d-7287-4443-8ab6-54bffa9fd008
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2028796994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2028796994
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1853353239
Short name T748
Test name
Test status
Simulation time 155354499 ps
CPU time 1.24 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:34:54 PM PDT 24
Peak memory 207500 kb
Host smart-5f9e0458-291e-4fa2-9618-94c309324253
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853353239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1853353239
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.777722737
Short name T69
Test name
Test status
Simulation time 1402534675 ps
CPU time 5.2 seconds
Started Jul 19 05:34:40 PM PDT 24
Finished Jul 19 05:35:18 PM PDT 24
Peak memory 217092 kb
Host smart-e45ed164-676d-41f1-8107-279452f85f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777722737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.777722737
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1376885356
Short name T85
Test name
Test status
Simulation time 1107368244 ps
CPU time 3.83 seconds
Started Jul 19 05:34:35 PM PDT 24
Finished Jul 19 05:34:45 PM PDT 24
Peak memory 216660 kb
Host smart-61e9c0cf-4845-45fa-a4b2-4dcbf31e3bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376885356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1376885356
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2939300450
Short name T343
Test name
Test status
Simulation time 205736334 ps
CPU time 1.44 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:34:54 PM PDT 24
Peak memory 216728 kb
Host smart-c32a4b0f-4cf5-4c9a-87a4-bca899fc62d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939300450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2939300450
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1442727455
Short name T508
Test name
Test status
Simulation time 83355670 ps
CPU time 0.95 seconds
Started Jul 19 05:34:39 PM PDT 24
Finished Jul 19 05:35:11 PM PDT 24
Peak memory 206320 kb
Host smart-027fc263-3015-4e10-a75e-91b1b14ecdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442727455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1442727455
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3779722552
Short name T345
Test name
Test status
Simulation time 627321199 ps
CPU time 2.91 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:34:58 PM PDT 24
Peak memory 233128 kb
Host smart-25628537-c189-4fc3-84d4-a1cc2e314160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779722552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3779722552
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.189142832
Short name T978
Test name
Test status
Simulation time 12458537 ps
CPU time 0.71 seconds
Started Jul 19 05:34:54 PM PDT 24
Finished Jul 19 05:35:57 PM PDT 24
Peak memory 206208 kb
Host smart-78f1d7be-3a96-4c34-a2b8-ae8c54011fca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189142832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.189142832
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3101762756
Short name T455
Test name
Test status
Simulation time 370867170 ps
CPU time 2.32 seconds
Started Jul 19 05:34:48 PM PDT 24
Finished Jul 19 05:35:44 PM PDT 24
Peak memory 233232 kb
Host smart-19313867-eb11-4ef4-bf0c-be8e78673abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101762756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3101762756
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3675863811
Short name T932
Test name
Test status
Simulation time 21184598 ps
CPU time 0.83 seconds
Started Jul 19 05:34:49 PM PDT 24
Finished Jul 19 05:35:44 PM PDT 24
Peak memory 207212 kb
Host smart-bade9680-da4b-4d4e-a0bc-ab0a516e3569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675863811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3675863811
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2995392812
Short name T541
Test name
Test status
Simulation time 10905077328 ps
CPU time 23.04 seconds
Started Jul 19 05:34:49 PM PDT 24
Finished Jul 19 05:36:09 PM PDT 24
Peak memory 235880 kb
Host smart-62924460-34ff-45bb-b88d-4a3a7c10ea91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995392812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2995392812
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3215529413
Short name T277
Test name
Test status
Simulation time 25750951054 ps
CPU time 96.28 seconds
Started Jul 19 05:34:48 PM PDT 24
Finished Jul 19 05:37:18 PM PDT 24
Peak memory 250996 kb
Host smart-5988ce4d-b67f-420f-bf1f-05109c82a38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215529413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3215529413
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3051488808
Short name T705
Test name
Test status
Simulation time 12860068958 ps
CPU time 124.47 seconds
Started Jul 19 05:34:46 PM PDT 24
Finished Jul 19 05:37:40 PM PDT 24
Peak memory 249736 kb
Host smart-ec44c4c5-8100-4614-ba04-2348205603aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051488808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3051488808
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3293525711
Short name T734
Test name
Test status
Simulation time 67964115 ps
CPU time 2.86 seconds
Started Jul 19 05:34:54 PM PDT 24
Finished Jul 19 05:35:59 PM PDT 24
Peak memory 233280 kb
Host smart-2ac39102-78dc-47f5-ab15-a0ef57bad777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293525711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3293525711
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.4017770146
Short name T622
Test name
Test status
Simulation time 1520035886 ps
CPU time 21.63 seconds
Started Jul 19 05:34:48 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 241376 kb
Host smart-561aad1b-4038-4d87-834c-879b9e61f9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017770146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.4017770146
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.687936873
Short name T892
Test name
Test status
Simulation time 1055649981 ps
CPU time 2.72 seconds
Started Jul 19 05:34:46 PM PDT 24
Finished Jul 19 05:35:38 PM PDT 24
Peak memory 224836 kb
Host smart-ab48b55a-ea9c-481c-9ea0-4015910f2abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687936873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.687936873
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2527667904
Short name T359
Test name
Test status
Simulation time 13057365688 ps
CPU time 33.17 seconds
Started Jul 19 05:34:48 PM PDT 24
Finished Jul 19 05:36:15 PM PDT 24
Peak memory 233244 kb
Host smart-6c60aaf9-45eb-489e-8370-515f1bdcb483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527667904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2527667904
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2236021591
Short name T903
Test name
Test status
Simulation time 358541470 ps
CPU time 1.11 seconds
Started Jul 19 05:34:45 PM PDT 24
Finished Jul 19 05:35:36 PM PDT 24
Peak memory 217136 kb
Host smart-5f5506be-749e-4e78-af42-20e5331b4e8c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236021591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2236021591
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1939282882
Short name T273
Test name
Test status
Simulation time 33347628056 ps
CPU time 27.16 seconds
Started Jul 19 05:34:53 PM PDT 24
Finished Jul 19 05:36:21 PM PDT 24
Peak memory 237360 kb
Host smart-be213864-3b40-484f-aeb7-59c0aa0992c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939282882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1939282882
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3858201610
Short name T758
Test name
Test status
Simulation time 5396329159 ps
CPU time 3.8 seconds
Started Jul 19 05:34:53 PM PDT 24
Finished Jul 19 05:35:58 PM PDT 24
Peak memory 225176 kb
Host smart-b6666f2f-8318-4c55-b3e0-e23e48c2e69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858201610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3858201610
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4085675632
Short name T797
Test name
Test status
Simulation time 13974925089 ps
CPU time 9.33 seconds
Started Jul 19 05:34:47 PM PDT 24
Finished Jul 19 05:35:48 PM PDT 24
Peak memory 219172 kb
Host smart-1671c3b5-7454-4e27-965a-02c97966bc3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4085675632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4085675632
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3855607310
Short name T65
Test name
Test status
Simulation time 171791129 ps
CPU time 1.21 seconds
Started Jul 19 05:34:47 PM PDT 24
Finished Jul 19 05:35:40 PM PDT 24
Peak memory 236264 kb
Host smart-8e7f6729-9e49-4805-8f94-d2314ce178ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855607310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3855607310
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1675131863
Short name T172
Test name
Test status
Simulation time 11525131276 ps
CPU time 81.2 seconds
Started Jul 19 05:34:57 PM PDT 24
Finished Jul 19 05:37:20 PM PDT 24
Peak memory 250308 kb
Host smart-34329aed-f1ba-4886-b42a-65e180e857c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675131863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1675131863
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4180892071
Short name T332
Test name
Test status
Simulation time 6022469036 ps
CPU time 32.43 seconds
Started Jul 19 05:34:47 PM PDT 24
Finished Jul 19 05:36:11 PM PDT 24
Peak memory 217036 kb
Host smart-0dc42f9e-ddb7-448c-8e2a-23a3fe66b0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180892071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4180892071
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2135185755
Short name T594
Test name
Test status
Simulation time 9271390324 ps
CPU time 5.29 seconds
Started Jul 19 05:34:49 PM PDT 24
Finished Jul 19 05:35:49 PM PDT 24
Peak memory 216768 kb
Host smart-d27dea08-088f-4f7a-ab8f-3deb2544726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135185755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2135185755
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3073185485
Short name T646
Test name
Test status
Simulation time 143663969 ps
CPU time 1.37 seconds
Started Jul 19 05:34:46 PM PDT 24
Finished Jul 19 05:35:36 PM PDT 24
Peak memory 207828 kb
Host smart-1750ff26-69af-4f05-8623-fd723b567122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073185485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3073185485
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.948106528
Short name T445
Test name
Test status
Simulation time 42977918 ps
CPU time 0.87 seconds
Started Jul 19 05:34:48 PM PDT 24
Finished Jul 19 05:35:43 PM PDT 24
Peak memory 207308 kb
Host smart-ebb404c4-9c88-42a7-b557-fb9915d7b209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948106528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.948106528
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3129054345
Short name T665
Test name
Test status
Simulation time 151659264 ps
CPU time 2.9 seconds
Started Jul 19 05:34:47 PM PDT 24
Finished Jul 19 05:35:42 PM PDT 24
Peak memory 224880 kb
Host smart-282171f2-6d92-4dc8-ba69-dd31eb81b622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129054345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3129054345
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2419982328
Short name T477
Test name
Test status
Simulation time 217507552 ps
CPU time 4.69 seconds
Started Jul 19 05:36:33 PM PDT 24
Finished Jul 19 05:36:51 PM PDT 24
Peak memory 224944 kb
Host smart-b6cb0e16-1079-4d4f-8497-880378e5c4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419982328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2419982328
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2900091169
Short name T706
Test name
Test status
Simulation time 19874509 ps
CPU time 0.77 seconds
Started Jul 19 05:36:27 PM PDT 24
Finished Jul 19 05:36:46 PM PDT 24
Peak memory 205888 kb
Host smart-5f0343d1-306e-4236-870d-43e5f09491f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900091169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2900091169
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2929924589
Short name T485
Test name
Test status
Simulation time 4074975312 ps
CPU time 24.81 seconds
Started Jul 19 05:37:00 PM PDT 24
Finished Jul 19 05:37:26 PM PDT 24
Peak memory 254392 kb
Host smart-d1b07a50-3c9c-4b49-acb8-6d18c04579a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929924589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2929924589
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2449733926
Short name T933
Test name
Test status
Simulation time 8441397354 ps
CPU time 41.29 seconds
Started Jul 19 05:36:41 PM PDT 24
Finished Jul 19 05:37:30 PM PDT 24
Peak memory 238820 kb
Host smart-3aade8bc-e9e8-4b60-8cd7-cdae49111403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449733926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2449733926
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.4157964373
Short name T712
Test name
Test status
Simulation time 3584251754 ps
CPU time 11.46 seconds
Started Jul 19 05:36:31 PM PDT 24
Finished Jul 19 05:36:58 PM PDT 24
Peak memory 233388 kb
Host smart-313b917f-5e4e-4bd1-9770-93b8e223e45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157964373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4157964373
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.4282422410
Short name T649
Test name
Test status
Simulation time 22329711982 ps
CPU time 163.9 seconds
Started Jul 19 05:36:32 PM PDT 24
Finished Jul 19 05:39:30 PM PDT 24
Peak memory 253940 kb
Host smart-e63fcbac-823f-4c70-b169-8c1f4ea3d3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282422410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.4282422410
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1977377222
Short name T230
Test name
Test status
Simulation time 2211050211 ps
CPU time 13.54 seconds
Started Jul 19 05:36:33 PM PDT 24
Finished Jul 19 05:37:00 PM PDT 24
Peak memory 233344 kb
Host smart-1db29000-f6e8-493e-a3d8-e2b10c340933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977377222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1977377222
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3078849083
Short name T484
Test name
Test status
Simulation time 941434527 ps
CPU time 9.79 seconds
Started Jul 19 05:36:31 PM PDT 24
Finished Jul 19 05:36:56 PM PDT 24
Peak memory 233096 kb
Host smart-b5faa8b9-4206-4b69-8f42-6eb43e17a8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078849083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3078849083
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2246169486
Short name T423
Test name
Test status
Simulation time 65315501 ps
CPU time 1.09 seconds
Started Jul 19 05:36:23 PM PDT 24
Finished Jul 19 05:36:45 PM PDT 24
Peak memory 217152 kb
Host smart-f1eaee5f-41ce-42d6-a5d0-320d5a1a0858
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246169486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2246169486
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.728305001
Short name T884
Test name
Test status
Simulation time 5465263371 ps
CPU time 5.25 seconds
Started Jul 19 05:36:22 PM PDT 24
Finished Jul 19 05:36:49 PM PDT 24
Peak memory 233280 kb
Host smart-018ad8af-bc21-47aa-a8a1-a085578524f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728305001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.728305001
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1086565934
Short name T730
Test name
Test status
Simulation time 1136996020 ps
CPU time 5.37 seconds
Started Jul 19 05:36:31 PM PDT 24
Finished Jul 19 05:36:52 PM PDT 24
Peak memory 219692 kb
Host smart-34208a11-99c1-4716-bbf1-86f69b7a4ec0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1086565934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1086565934
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2191970814
Short name T251
Test name
Test status
Simulation time 23888548789 ps
CPU time 135.93 seconds
Started Jul 19 05:36:40 PM PDT 24
Finished Jul 19 05:39:05 PM PDT 24
Peak memory 267008 kb
Host smart-3a6ee1a4-ac47-4418-800e-5ffc8483ae67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191970814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2191970814
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2015003100
Short name T814
Test name
Test status
Simulation time 2058339838 ps
CPU time 21.65 seconds
Started Jul 19 05:36:24 PM PDT 24
Finished Jul 19 05:37:06 PM PDT 24
Peak memory 216632 kb
Host smart-e34fcefc-2415-42af-a92c-393a15121116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015003100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2015003100
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2226756442
Short name T415
Test name
Test status
Simulation time 3530659250 ps
CPU time 4.26 seconds
Started Jul 19 05:36:25 PM PDT 24
Finished Jul 19 05:36:49 PM PDT 24
Peak memory 216720 kb
Host smart-414c976e-e565-4295-ae5c-5671136ad036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226756442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2226756442
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2360936334
Short name T450
Test name
Test status
Simulation time 204235226 ps
CPU time 1.19 seconds
Started Jul 19 05:36:23 PM PDT 24
Finished Jul 19 05:36:45 PM PDT 24
Peak memory 207736 kb
Host smart-3e449ce7-d6f7-4950-b4c2-d6fa2294e638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360936334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2360936334
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.626386415
Short name T830
Test name
Test status
Simulation time 223300948 ps
CPU time 0.92 seconds
Started Jul 19 05:36:23 PM PDT 24
Finished Jul 19 05:36:45 PM PDT 24
Peak memory 206784 kb
Host smart-a8d70ad2-46a0-4ad0-ae72-f0ab091ac530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626386415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.626386415
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2091666082
Short name T762
Test name
Test status
Simulation time 5620030111 ps
CPU time 8.1 seconds
Started Jul 19 05:36:30 PM PDT 24
Finished Jul 19 05:36:54 PM PDT 24
Peak memory 233268 kb
Host smart-a08ebab3-68be-452e-8a59-50c890f9ce2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091666082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2091666082
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4145185419
Short name T566
Test name
Test status
Simulation time 15758401 ps
CPU time 0.74 seconds
Started Jul 19 05:36:52 PM PDT 24
Finished Jul 19 05:36:56 PM PDT 24
Peak memory 205764 kb
Host smart-178ccada-7493-44ee-9d70-31c819a0c321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145185419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4145185419
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3701095387
Short name T970
Test name
Test status
Simulation time 3635539206 ps
CPU time 10.59 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:37:05 PM PDT 24
Peak memory 233228 kb
Host smart-155413bd-a486-45d9-ab67-08ecb5634512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701095387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3701095387
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4226199372
Short name T364
Test name
Test status
Simulation time 27363159 ps
CPU time 0.79 seconds
Started Jul 19 05:36:42 PM PDT 24
Finished Jul 19 05:36:50 PM PDT 24
Peak memory 206896 kb
Host smart-4fc7c6e7-e878-4e6b-af37-c45e9e3ff22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226199372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4226199372
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2266707922
Short name T179
Test name
Test status
Simulation time 24946048977 ps
CPU time 97.09 seconds
Started Jul 19 05:36:50 PM PDT 24
Finished Jul 19 05:38:31 PM PDT 24
Peak memory 258128 kb
Host smart-735d51bd-3e4a-4675-8e25-b14a98b3fd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266707922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2266707922
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3889898988
Short name T233
Test name
Test status
Simulation time 26986244803 ps
CPU time 44.08 seconds
Started Jul 19 05:36:49 PM PDT 24
Finished Jul 19 05:37:36 PM PDT 24
Peak memory 251376 kb
Host smart-deee2910-9bc9-4703-917c-0a067dd79993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889898988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3889898988
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.46160468
Short name T328
Test name
Test status
Simulation time 2484723282 ps
CPU time 34.38 seconds
Started Jul 19 05:36:53 PM PDT 24
Finished Jul 19 05:37:30 PM PDT 24
Peak memory 237484 kb
Host smart-71523f99-0f2f-44e4-a2fc-433b80e23c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46160468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.46160468
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3626485763
Short name T556
Test name
Test status
Simulation time 123898525380 ps
CPU time 167.56 seconds
Started Jul 19 05:36:54 PM PDT 24
Finished Jul 19 05:39:44 PM PDT 24
Peak memory 252980 kb
Host smart-1c117193-0b14-43b3-b985-929c13b4a47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626485763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3626485763
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1495234671
Short name T459
Test name
Test status
Simulation time 584783089 ps
CPU time 10.18 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:37:05 PM PDT 24
Peak memory 233092 kb
Host smart-d63e775f-a0ee-47d6-b9d7-e2b60365c323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495234671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1495234671
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3141404679
Short name T283
Test name
Test status
Simulation time 3566863929 ps
CPU time 13.82 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:37:08 PM PDT 24
Peak memory 233312 kb
Host smart-8dc0e617-9b8c-46ac-a488-95d78f6bc308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141404679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3141404679
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1530577924
Short name T33
Test name
Test status
Simulation time 14197647 ps
CPU time 1.02 seconds
Started Jul 19 05:36:42 PM PDT 24
Finished Jul 19 05:36:50 PM PDT 24
Peak memory 218408 kb
Host smart-d4a2dabe-cc49-4e6a-9112-3d84aa7f6e3f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530577924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1530577924
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1899282677
Short name T413
Test name
Test status
Simulation time 6095123925 ps
CPU time 19.56 seconds
Started Jul 19 05:36:52 PM PDT 24
Finished Jul 19 05:37:15 PM PDT 24
Peak memory 241344 kb
Host smart-efbac75e-2acc-4522-8d01-1077adbf8ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899282677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1899282677
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2267574827
Short name T788
Test name
Test status
Simulation time 429361453 ps
CPU time 3.24 seconds
Started Jul 19 05:36:52 PM PDT 24
Finished Jul 19 05:36:59 PM PDT 24
Peak memory 233060 kb
Host smart-5e573322-fff2-4d73-aa0a-607c038d0fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267574827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2267574827
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3930243253
Short name T704
Test name
Test status
Simulation time 1354771443 ps
CPU time 9.16 seconds
Started Jul 19 05:36:50 PM PDT 24
Finished Jul 19 05:37:03 PM PDT 24
Peak memory 222452 kb
Host smart-a3e142e9-2280-4899-b1a0-27a36243968b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3930243253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3930243253
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2441592642
Short name T768
Test name
Test status
Simulation time 48587299 ps
CPU time 0.96 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:36:55 PM PDT 24
Peak memory 207816 kb
Host smart-bdb45788-89d4-4424-a514-2b1ccf62212d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441592642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2441592642
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1565931349
Short name T828
Test name
Test status
Simulation time 8509591493 ps
CPU time 14.08 seconds
Started Jul 19 05:36:43 PM PDT 24
Finished Jul 19 05:37:04 PM PDT 24
Peak memory 216716 kb
Host smart-dbe250b4-bf30-4866-843d-df72ef4d1cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565931349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1565931349
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1121873376
Short name T803
Test name
Test status
Simulation time 1988244597 ps
CPU time 4.85 seconds
Started Jul 19 05:36:43 PM PDT 24
Finished Jul 19 05:36:54 PM PDT 24
Peak memory 216656 kb
Host smart-70f35ff8-ed8e-41ad-a503-1a7fe85390d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121873376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1121873376
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1676453348
Short name T882
Test name
Test status
Simulation time 79767779 ps
CPU time 1.23 seconds
Started Jul 19 05:36:42 PM PDT 24
Finished Jul 19 05:36:51 PM PDT 24
Peak memory 216732 kb
Host smart-50eb4c69-24c2-45ea-8e11-09de405ec774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676453348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1676453348
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3665115286
Short name T926
Test name
Test status
Simulation time 98079309 ps
CPU time 0.7 seconds
Started Jul 19 05:36:41 PM PDT 24
Finished Jul 19 05:36:50 PM PDT 24
Peak memory 205920 kb
Host smart-7e86301a-8755-4c0d-bb10-471efec3aeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665115286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3665115286
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.45273215
Short name T257
Test name
Test status
Simulation time 418138418 ps
CPU time 2.98 seconds
Started Jul 19 05:36:53 PM PDT 24
Finished Jul 19 05:36:59 PM PDT 24
Peak memory 233048 kb
Host smart-f8b49039-5991-451d-9c74-3b1d6f55cec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45273215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.45273215
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.949653953
Short name T589
Test name
Test status
Simulation time 36295959 ps
CPU time 0.69 seconds
Started Jul 19 05:36:50 PM PDT 24
Finished Jul 19 05:36:54 PM PDT 24
Peak memory 205172 kb
Host smart-78585d34-2cb6-4004-af87-b3425e255b9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949653953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.949653953
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.211630348
Short name T89
Test name
Test status
Simulation time 1121403373 ps
CPU time 15.71 seconds
Started Jul 19 05:36:52 PM PDT 24
Finished Jul 19 05:37:11 PM PDT 24
Peak memory 233096 kb
Host smart-4a2c341c-f5b7-4a63-9935-f5ec54d68c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211630348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.211630348
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.13704324
Short name T995
Test name
Test status
Simulation time 47158103 ps
CPU time 0.76 seconds
Started Jul 19 05:36:52 PM PDT 24
Finished Jul 19 05:36:56 PM PDT 24
Peak memory 206164 kb
Host smart-18fd56f4-2618-4625-86a7-d8f163abb5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13704324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.13704324
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2674254602
Short name T176
Test name
Test status
Simulation time 6153118408 ps
CPU time 81.18 seconds
Started Jul 19 05:36:50 PM PDT 24
Finished Jul 19 05:38:14 PM PDT 24
Peak memory 252896 kb
Host smart-d742b16f-ee9e-46b4-9b13-cee544b37f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674254602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2674254602
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1829331101
Short name T49
Test name
Test status
Simulation time 20178883337 ps
CPU time 232.5 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:40:47 PM PDT 24
Peak memory 272600 kb
Host smart-13833897-c927-4677-baef-fd4e6237bee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829331101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1829331101
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3280338248
Short name T927
Test name
Test status
Simulation time 3010145296 ps
CPU time 53.59 seconds
Started Jul 19 05:36:49 PM PDT 24
Finished Jul 19 05:37:46 PM PDT 24
Peak memory 233256 kb
Host smart-fea0670d-775c-40d2-b8a0-34a5602047bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280338248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3280338248
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.323943486
Short name T220
Test name
Test status
Simulation time 3978045342 ps
CPU time 83.51 seconds
Started Jul 19 05:36:49 PM PDT 24
Finished Jul 19 05:38:16 PM PDT 24
Peak memory 249612 kb
Host smart-7ab7626c-9417-42cf-9559-d96541e0d390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323943486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.323943486
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.709563172
Short name T54
Test name
Test status
Simulation time 62330044 ps
CPU time 2.66 seconds
Started Jul 19 05:36:50 PM PDT 24
Finished Jul 19 05:36:56 PM PDT 24
Peak memory 232844 kb
Host smart-62bbb174-88e9-4f87-ae73-031865cc9b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709563172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.709563172
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3298554407
Short name T745
Test name
Test status
Simulation time 110817917 ps
CPU time 2.61 seconds
Started Jul 19 05:36:50 PM PDT 24
Finished Jul 19 05:36:56 PM PDT 24
Peak memory 232796 kb
Host smart-30d2d19f-7f6d-4808-8d4b-29edb299ea6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298554407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3298554407
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3931543803
Short name T793
Test name
Test status
Simulation time 32942013 ps
CPU time 1.08 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:36:56 PM PDT 24
Peak memory 217140 kb
Host smart-69f1954d-510c-47ee-b9f5-b401c7bfdaf2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931543803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3931543803
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3708952698
Short name T537
Test name
Test status
Simulation time 102120261 ps
CPU time 2.18 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:36:57 PM PDT 24
Peak memory 224304 kb
Host smart-258c94fc-fc89-4d87-aa1b-eec6f83e215d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708952698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3708952698
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3867633789
Short name T289
Test name
Test status
Simulation time 1453433201 ps
CPU time 11.25 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:37:06 PM PDT 24
Peak memory 250488 kb
Host smart-64e7ce2b-dd73-4294-98e3-5b07e3cfecc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867633789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3867633789
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2660820218
Short name T592
Test name
Test status
Simulation time 2582365967 ps
CPU time 9.53 seconds
Started Jul 19 05:36:53 PM PDT 24
Finished Jul 19 05:37:05 PM PDT 24
Peak memory 219840 kb
Host smart-8be5a83d-c8e6-4071-a8bc-b38aa33c79e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2660820218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2660820218
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3975397866
Short name T929
Test name
Test status
Simulation time 30586015797 ps
CPU time 121.93 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:38:56 PM PDT 24
Peak memory 241544 kb
Host smart-09f7df11-434c-4bc2-9bd9-db4162d792d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975397866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3975397866
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3643178492
Short name T627
Test name
Test status
Simulation time 41994258702 ps
CPU time 39.39 seconds
Started Jul 19 05:36:52 PM PDT 24
Finished Jul 19 05:37:35 PM PDT 24
Peak memory 217012 kb
Host smart-989bab71-78de-40a8-9d6a-b659c55b0eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643178492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3643178492
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1816005712
Short name T644
Test name
Test status
Simulation time 18919972060 ps
CPU time 12.14 seconds
Started Jul 19 05:36:50 PM PDT 24
Finished Jul 19 05:37:06 PM PDT 24
Peak memory 216872 kb
Host smart-d2760a8c-0ede-440d-9ae9-b5a8f2f90df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816005712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1816005712
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1855629042
Short name T342
Test name
Test status
Simulation time 65027273 ps
CPU time 2.71 seconds
Started Jul 19 05:36:53 PM PDT 24
Finished Jul 19 05:36:59 PM PDT 24
Peak memory 216608 kb
Host smart-905fb778-32af-49df-a9b3-6ca7a7120e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855629042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1855629042
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2985602647
Short name T427
Test name
Test status
Simulation time 240584658 ps
CPU time 0.87 seconds
Started Jul 19 05:36:52 PM PDT 24
Finished Jul 19 05:36:56 PM PDT 24
Peak memory 206356 kb
Host smart-4730e0a8-c250-4aab-a7c4-266d971ccd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985602647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2985602647
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3500109606
Short name T765
Test name
Test status
Simulation time 5542296472 ps
CPU time 18.48 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:37:13 PM PDT 24
Peak memory 233196 kb
Host smart-cf76f737-90f5-4e73-80b5-3b53eed8ec36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500109606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3500109606
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2766776418
Short name T812
Test name
Test status
Simulation time 12233654 ps
CPU time 0.71 seconds
Started Jul 19 05:37:04 PM PDT 24
Finished Jul 19 05:37:05 PM PDT 24
Peak memory 205784 kb
Host smart-fa4880f3-5720-4639-a44d-bf5309300103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766776418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2766776418
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1104772333
Short name T708
Test name
Test status
Simulation time 636230604 ps
CPU time 8.57 seconds
Started Jul 19 05:36:58 PM PDT 24
Finished Jul 19 05:37:08 PM PDT 24
Peak memory 233160 kb
Host smart-010ab842-9b53-489e-9460-4a35d7a872e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104772333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1104772333
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3240625019
Short name T960
Test name
Test status
Simulation time 26913557 ps
CPU time 0.8 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:36:55 PM PDT 24
Peak memory 207184 kb
Host smart-9d21bfc2-4421-49fc-ac2c-8d5f99c21ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240625019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3240625019
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3711126588
Short name T208
Test name
Test status
Simulation time 10883115515 ps
CPU time 68.7 seconds
Started Jul 19 05:36:56 PM PDT 24
Finished Jul 19 05:38:06 PM PDT 24
Peak memory 255160 kb
Host smart-4143df7f-356f-4e6e-9eb0-7cbe4d97b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711126588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3711126588
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.11738128
Short name T31
Test name
Test status
Simulation time 44346542710 ps
CPU time 299.63 seconds
Started Jul 19 05:36:57 PM PDT 24
Finished Jul 19 05:41:58 PM PDT 24
Peak memory 264040 kb
Host smart-1bed1881-267a-4bb6-acd5-821cea146570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11738128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.11738128
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3533569523
Short name T990
Test name
Test status
Simulation time 8215242678 ps
CPU time 51.52 seconds
Started Jul 19 05:36:59 PM PDT 24
Finished Jul 19 05:37:52 PM PDT 24
Peak memory 266140 kb
Host smart-bf85dd4d-301f-4f5d-b578-b6ecb39969f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533569523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3533569523
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1358407526
Short name T1020
Test name
Test status
Simulation time 118132443 ps
CPU time 4.39 seconds
Started Jul 19 05:36:58 PM PDT 24
Finished Jul 19 05:37:04 PM PDT 24
Peak memory 233212 kb
Host smart-94f29fcc-6abe-4738-a28c-fcb6485aa8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358407526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1358407526
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.843263387
Short name T833
Test name
Test status
Simulation time 2618659683 ps
CPU time 25.63 seconds
Started Jul 19 05:37:02 PM PDT 24
Finished Jul 19 05:37:29 PM PDT 24
Peak memory 221328 kb
Host smart-355ddef3-6bc6-47e0-ab99-0b4f37dd4fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843263387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.843263387
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.160316947
Short name T421
Test name
Test status
Simulation time 30141758263 ps
CPU time 95.25 seconds
Started Jul 19 05:36:58 PM PDT 24
Finished Jul 19 05:38:35 PM PDT 24
Peak memory 238880 kb
Host smart-b04016d3-2684-437d-a203-cef1b4fb1d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160316947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.160316947
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2122794749
Short name T974
Test name
Test status
Simulation time 95663553 ps
CPU time 1.1 seconds
Started Jul 19 05:36:49 PM PDT 24
Finished Jul 19 05:36:54 PM PDT 24
Peak memory 217152 kb
Host smart-c14d76ea-9b5d-4b83-b393-ad4e633dfbcd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122794749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2122794749
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.875369146
Short name T955
Test name
Test status
Simulation time 72717949 ps
CPU time 2.11 seconds
Started Jul 19 05:36:56 PM PDT 24
Finished Jul 19 05:37:00 PM PDT 24
Peak memory 224556 kb
Host smart-044bb6a6-df2c-4bbd-9dfa-de81efe79823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875369146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.875369146
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2762020704
Short name T632
Test name
Test status
Simulation time 36677330590 ps
CPU time 20.49 seconds
Started Jul 19 05:36:57 PM PDT 24
Finished Jul 19 05:37:19 PM PDT 24
Peak memory 241072 kb
Host smart-85e78398-4808-433f-b020-0dee22c70b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762020704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2762020704
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3157653999
Short name T463
Test name
Test status
Simulation time 2340835588 ps
CPU time 12.47 seconds
Started Jul 19 05:36:59 PM PDT 24
Finished Jul 19 05:37:13 PM PDT 24
Peak memory 223576 kb
Host smart-0c7b9c4e-4064-4434-8a96-2f054c780b62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3157653999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3157653999
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.259259870
Short name T653
Test name
Test status
Simulation time 640980105350 ps
CPU time 763.14 seconds
Started Jul 19 05:36:59 PM PDT 24
Finished Jul 19 05:49:44 PM PDT 24
Peak memory 268952 kb
Host smart-829f9357-17d2-4b12-9699-78ecdcebfad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259259870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.259259870
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3990798255
Short name T71
Test name
Test status
Simulation time 3541246665 ps
CPU time 5.5 seconds
Started Jul 19 05:36:50 PM PDT 24
Finished Jul 19 05:36:59 PM PDT 24
Peak memory 216828 kb
Host smart-fdfb74ad-5965-4c1d-b09b-26f28ecb14da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990798255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3990798255
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2026279400
Short name T816
Test name
Test status
Simulation time 14074995758 ps
CPU time 4.99 seconds
Started Jul 19 05:36:51 PM PDT 24
Finished Jul 19 05:36:59 PM PDT 24
Peak memory 216680 kb
Host smart-79bb81dd-48df-4092-b69e-5a463005d85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026279400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2026279400
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4022946956
Short name T940
Test name
Test status
Simulation time 70979879 ps
CPU time 0.84 seconds
Started Jul 19 05:36:52 PM PDT 24
Finished Jul 19 05:36:56 PM PDT 24
Peak memory 206280 kb
Host smart-dcb72f58-ad9e-4a31-8bd6-f9437fe2c148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022946956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4022946956
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.666097920
Short name T741
Test name
Test status
Simulation time 18599782 ps
CPU time 0.71 seconds
Started Jul 19 05:36:50 PM PDT 24
Finished Jul 19 05:36:55 PM PDT 24
Peak memory 206328 kb
Host smart-4313ba7b-1565-4627-9dad-6e520f8ed55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666097920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.666097920
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3374775480
Short name T900
Test name
Test status
Simulation time 3678212628 ps
CPU time 5.46 seconds
Started Jul 19 05:36:59 PM PDT 24
Finished Jul 19 05:37:06 PM PDT 24
Peak memory 225080 kb
Host smart-1e207bb7-876d-4e3a-968a-f7ffc4da315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374775480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3374775480
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1140459608
Short name T519
Test name
Test status
Simulation time 10882068 ps
CPU time 0.74 seconds
Started Jul 19 05:37:06 PM PDT 24
Finished Jul 19 05:37:08 PM PDT 24
Peak memory 205700 kb
Host smart-879927fd-59bb-4c41-bbda-5e7ca4314c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140459608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1140459608
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1174257377
Short name T196
Test name
Test status
Simulation time 110180143 ps
CPU time 2.41 seconds
Started Jul 19 05:36:57 PM PDT 24
Finished Jul 19 05:37:01 PM PDT 24
Peak memory 224876 kb
Host smart-3a45db04-9f0b-4dcb-8955-b90aa9acf22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174257377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1174257377
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2467715815
Short name T447
Test name
Test status
Simulation time 16420344 ps
CPU time 0.81 seconds
Started Jul 19 05:36:59 PM PDT 24
Finished Jul 19 05:37:02 PM PDT 24
Peak memory 206892 kb
Host smart-f5964001-72b6-4575-9f53-7777580ae47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467715815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2467715815
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.977477401
Short name T838
Test name
Test status
Simulation time 85203203573 ps
CPU time 186.06 seconds
Started Jul 19 05:37:07 PM PDT 24
Finished Jul 19 05:40:14 PM PDT 24
Peak memory 266040 kb
Host smart-39dd3560-1bd3-470f-a429-5992429f7078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977477401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.977477401
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4062537544
Short name T227
Test name
Test status
Simulation time 2825005418 ps
CPU time 57.93 seconds
Started Jul 19 05:37:06 PM PDT 24
Finished Jul 19 05:38:06 PM PDT 24
Peak memory 249740 kb
Host smart-3288b3ed-0bde-4be5-b32e-ef4c3395fbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062537544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4062537544
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1024949869
Short name T957
Test name
Test status
Simulation time 52810251495 ps
CPU time 91.9 seconds
Started Jul 19 05:37:04 PM PDT 24
Finished Jul 19 05:38:37 PM PDT 24
Peak memory 266744 kb
Host smart-47ce7695-43f2-40af-9757-b9a3213fc677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024949869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1024949869
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.226132460
Short name T497
Test name
Test status
Simulation time 382339848 ps
CPU time 4.31 seconds
Started Jul 19 05:36:58 PM PDT 24
Finished Jul 19 05:37:04 PM PDT 24
Peak memory 233120 kb
Host smart-39c0cda3-d0ba-4422-907b-e92eb3d8a05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226132460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.226132460
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2455701641
Short name T526
Test name
Test status
Simulation time 13610008276 ps
CPU time 82.58 seconds
Started Jul 19 05:36:57 PM PDT 24
Finished Jul 19 05:38:21 PM PDT 24
Peak memory 249704 kb
Host smart-c9f80dc8-3511-4827-be28-5a916c96dbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455701641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2455701641
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4242984021
Short name T647
Test name
Test status
Simulation time 468651655 ps
CPU time 7.1 seconds
Started Jul 19 05:36:59 PM PDT 24
Finished Jul 19 05:37:08 PM PDT 24
Peak memory 224904 kb
Host smart-44e46622-11db-47fa-a829-c94966e0696b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242984021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4242984021
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1703726044
Short name T810
Test name
Test status
Simulation time 1102220768 ps
CPU time 4.1 seconds
Started Jul 19 05:37:15 PM PDT 24
Finished Jul 19 05:37:21 PM PDT 24
Peak memory 233128 kb
Host smart-7127caf8-ea63-41b6-994a-4c5048b8f63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703726044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1703726044
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.473069868
Short name T1021
Test name
Test status
Simulation time 144186411 ps
CPU time 1.04 seconds
Started Jul 19 05:36:58 PM PDT 24
Finished Jul 19 05:37:01 PM PDT 24
Peak memory 217128 kb
Host smart-1cea291e-7916-441c-b5d3-a97504b5f6a6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473069868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.473069868
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.373439122
Short name T461
Test name
Test status
Simulation time 25506213153 ps
CPU time 17.22 seconds
Started Jul 19 05:37:03 PM PDT 24
Finished Jul 19 05:37:21 PM PDT 24
Peak memory 233240 kb
Host smart-a25a2dab-155b-4c80-ac28-661db572af35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373439122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.373439122
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2798622341
Short name T818
Test name
Test status
Simulation time 6366843939 ps
CPU time 6.08 seconds
Started Jul 19 05:37:03 PM PDT 24
Finished Jul 19 05:37:10 PM PDT 24
Peak memory 225072 kb
Host smart-093f8070-280b-46ba-80f5-f73b84c8af54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798622341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2798622341
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2118550134
Short name T1006
Test name
Test status
Simulation time 981063261 ps
CPU time 11.78 seconds
Started Jul 19 05:37:04 PM PDT 24
Finished Jul 19 05:37:16 PM PDT 24
Peak memory 222124 kb
Host smart-36247c61-003a-4bea-99ec-163ba96dc2d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2118550134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2118550134
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1228493985
Short name T13
Test name
Test status
Simulation time 2123340476 ps
CPU time 24.37 seconds
Started Jul 19 05:37:04 PM PDT 24
Finished Jul 19 05:37:30 PM PDT 24
Peak memory 237256 kb
Host smart-490fc2da-c0f8-487d-a7c6-ab72c8af73a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228493985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1228493985
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3965288175
Short name T496
Test name
Test status
Simulation time 1457787566 ps
CPU time 25.35 seconds
Started Jul 19 05:36:58 PM PDT 24
Finished Jul 19 05:37:24 PM PDT 24
Peak memory 216712 kb
Host smart-345d4202-0f09-4e3c-918a-2a554211dc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965288175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3965288175
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.603965552
Short name T361
Test name
Test status
Simulation time 385545464 ps
CPU time 2.95 seconds
Started Jul 19 05:36:56 PM PDT 24
Finished Jul 19 05:37:01 PM PDT 24
Peak memory 216728 kb
Host smart-10162f74-3b3a-42d1-99c0-a24b030d381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603965552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.603965552
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3834925568
Short name T344
Test name
Test status
Simulation time 10916745 ps
CPU time 0.73 seconds
Started Jul 19 05:37:01 PM PDT 24
Finished Jul 19 05:37:03 PM PDT 24
Peak memory 205928 kb
Host smart-6eadb1a4-67ac-4376-80b3-94470cc76479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834925568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3834925568
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2159792060
Short name T904
Test name
Test status
Simulation time 58352446 ps
CPU time 0.86 seconds
Started Jul 19 05:36:57 PM PDT 24
Finished Jul 19 05:37:00 PM PDT 24
Peak memory 206268 kb
Host smart-bf066d11-5973-4db7-aaec-cc6dc32794b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159792060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2159792060
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.406228875
Short name T262
Test name
Test status
Simulation time 404033793 ps
CPU time 3.17 seconds
Started Jul 19 05:36:59 PM PDT 24
Finished Jul 19 05:37:04 PM PDT 24
Peak memory 224952 kb
Host smart-55d4cd89-599c-4665-83ee-7787ffbfc5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406228875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.406228875
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3913465661
Short name T867
Test name
Test status
Simulation time 11540835 ps
CPU time 0.74 seconds
Started Jul 19 05:37:14 PM PDT 24
Finished Jul 19 05:37:16 PM PDT 24
Peak memory 206080 kb
Host smart-0b84841e-db66-4bed-a4f3-a7a269a268b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913465661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3913465661
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1565328228
Short name T490
Test name
Test status
Simulation time 208525829 ps
CPU time 2.8 seconds
Started Jul 19 05:37:07 PM PDT 24
Finished Jul 19 05:37:11 PM PDT 24
Peak memory 233196 kb
Host smart-e30caae5-151f-4698-b97f-d5fcbd6f2cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565328228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1565328228
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1877905827
Short name T356
Test name
Test status
Simulation time 14158266 ps
CPU time 0.73 seconds
Started Jul 19 05:37:09 PM PDT 24
Finished Jul 19 05:37:12 PM PDT 24
Peak memory 207200 kb
Host smart-f3cb1f6e-7408-410c-8dba-f0699f1c69f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877905827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1877905827
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2112582682
Short name T274
Test name
Test status
Simulation time 6639567495 ps
CPU time 36.36 seconds
Started Jul 19 05:37:13 PM PDT 24
Finished Jul 19 05:37:50 PM PDT 24
Peak memory 252492 kb
Host smart-7383fa93-53fd-41ee-94be-4fbbb717377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112582682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2112582682
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2604045463
Short name T140
Test name
Test status
Simulation time 42916370089 ps
CPU time 107.1 seconds
Started Jul 19 05:37:07 PM PDT 24
Finished Jul 19 05:38:56 PM PDT 24
Peak memory 251956 kb
Host smart-7e3b92b8-b7b9-4294-b0a3-afad40b9032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604045463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2604045463
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.144745411
Short name T315
Test name
Test status
Simulation time 10695396405 ps
CPU time 69.28 seconds
Started Jul 19 05:37:05 PM PDT 24
Finished Jul 19 05:38:15 PM PDT 24
Peak memory 255848 kb
Host smart-7527381b-2843-417a-8747-94beecbb740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144745411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.144745411
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.384579979
Short name T857
Test name
Test status
Simulation time 872533754 ps
CPU time 10.18 seconds
Started Jul 19 05:37:08 PM PDT 24
Finished Jul 19 05:37:19 PM PDT 24
Peak memory 249560 kb
Host smart-433fc9db-9c78-4431-a1e5-f00e9c09cbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384579979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.384579979
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.517482835
Short name T94
Test name
Test status
Simulation time 920832986 ps
CPU time 6.93 seconds
Started Jul 19 05:37:08 PM PDT 24
Finished Jul 19 05:37:16 PM PDT 24
Peak memory 235504 kb
Host smart-f6a0b894-1a15-4f6d-ab0b-f608f550bdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517482835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.517482835
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.4092741783
Short name T875
Test name
Test status
Simulation time 491321412 ps
CPU time 3.57 seconds
Started Jul 19 05:37:05 PM PDT 24
Finished Jul 19 05:37:10 PM PDT 24
Peak memory 224860 kb
Host smart-eb861764-54af-42cd-b3fd-3fd231bacca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092741783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4092741783
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3008647009
Short name T979
Test name
Test status
Simulation time 1884800184 ps
CPU time 16.68 seconds
Started Jul 19 05:37:07 PM PDT 24
Finished Jul 19 05:37:25 PM PDT 24
Peak memory 224900 kb
Host smart-38231c1a-5ccd-45bd-b428-4570e7536d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008647009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3008647009
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.4224285538
Short name T34
Test name
Test status
Simulation time 85605509 ps
CPU time 1.07 seconds
Started Jul 19 05:37:04 PM PDT 24
Finished Jul 19 05:37:07 PM PDT 24
Peak memory 217116 kb
Host smart-235165ae-f388-4998-8a5c-430cda08e465
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224285538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.4224285538
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1256093730
Short name T731
Test name
Test status
Simulation time 417698791 ps
CPU time 3.6 seconds
Started Jul 19 05:37:07 PM PDT 24
Finished Jul 19 05:37:12 PM PDT 24
Peak memory 224904 kb
Host smart-86a0989d-c4d8-4fe9-a8ab-dbde1865e2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256093730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1256093730
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2105011162
Short name T8
Test name
Test status
Simulation time 950808466 ps
CPU time 4.43 seconds
Started Jul 19 05:37:04 PM PDT 24
Finished Jul 19 05:37:09 PM PDT 24
Peak memory 224972 kb
Host smart-391dc30e-f9dc-420b-907c-5816c54fd81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105011162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2105011162
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2608782255
Short name T516
Test name
Test status
Simulation time 2720872477 ps
CPU time 11.81 seconds
Started Jul 19 05:37:07 PM PDT 24
Finished Jul 19 05:37:20 PM PDT 24
Peak memory 222656 kb
Host smart-22807d5f-d655-415b-9442-6da48cf8104e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2608782255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2608782255
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2077669122
Short name T655
Test name
Test status
Simulation time 9226771405 ps
CPU time 35.92 seconds
Started Jul 19 05:37:09 PM PDT 24
Finished Jul 19 05:37:46 PM PDT 24
Peak memory 220744 kb
Host smart-2ef3b55f-5a11-4b68-8d0e-fcc50bd16fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077669122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2077669122
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.4252730895
Short name T568
Test name
Test status
Simulation time 11801756 ps
CPU time 0.7 seconds
Started Jul 19 05:37:09 PM PDT 24
Finished Jul 19 05:37:11 PM PDT 24
Peak memory 205996 kb
Host smart-dc0dc22a-14a3-46c6-b8ed-a6d3e13a17dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252730895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.4252730895
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1362807822
Short name T570
Test name
Test status
Simulation time 61427699 ps
CPU time 1 seconds
Started Jul 19 05:37:05 PM PDT 24
Finished Jul 19 05:37:07 PM PDT 24
Peak memory 207460 kb
Host smart-833ffc4d-679a-4523-8d8b-040c6755e7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362807822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1362807822
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3667920862
Short name T717
Test name
Test status
Simulation time 69902072 ps
CPU time 0.75 seconds
Started Jul 19 05:37:10 PM PDT 24
Finished Jul 19 05:37:12 PM PDT 24
Peak memory 206268 kb
Host smart-c28c746b-4439-49ca-99e4-d2114c60276f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667920862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3667920862
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.289672302
Short name T747
Test name
Test status
Simulation time 2478827405 ps
CPU time 2.38 seconds
Started Jul 19 05:37:05 PM PDT 24
Finished Jul 19 05:37:09 PM PDT 24
Peak memory 224816 kb
Host smart-f58f7d8e-5d8f-4051-9362-33550060d0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289672302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.289672302
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3322724470
Short name T663
Test name
Test status
Simulation time 42936767 ps
CPU time 0.71 seconds
Started Jul 19 05:37:14 PM PDT 24
Finished Jul 19 05:37:17 PM PDT 24
Peak memory 205204 kb
Host smart-a69f390d-f9ed-47d3-87f9-cb7de3de9ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322724470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3322724470
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2113181846
Short name T921
Test name
Test status
Simulation time 16377517 ps
CPU time 0.75 seconds
Started Jul 19 05:37:13 PM PDT 24
Finished Jul 19 05:37:14 PM PDT 24
Peak memory 207212 kb
Host smart-af8c31db-9434-49cf-9b06-e03e54ace6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113181846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2113181846
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1683597692
Short name T486
Test name
Test status
Simulation time 45689738 ps
CPU time 0.81 seconds
Started Jul 19 05:37:17 PM PDT 24
Finished Jul 19 05:37:19 PM PDT 24
Peak memory 216280 kb
Host smart-12d8b322-4566-4ae5-9ce5-4e24b9028c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683597692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1683597692
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2840510151
Short name T237
Test name
Test status
Simulation time 83554829382 ps
CPU time 209.85 seconds
Started Jul 19 05:37:13 PM PDT 24
Finished Jul 19 05:40:44 PM PDT 24
Peak memory 257792 kb
Host smart-7d0f4956-fe78-4d0b-aa94-0f107d3e5deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840510151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2840510151
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2940490493
Short name T886
Test name
Test status
Simulation time 6357388183 ps
CPU time 51.7 seconds
Started Jul 19 05:37:14 PM PDT 24
Finished Jul 19 05:38:07 PM PDT 24
Peak memory 237816 kb
Host smart-6ddeea05-574d-424c-81f9-e68f0342e6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940490493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2940490493
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1024412076
Short name T324
Test name
Test status
Simulation time 5868801844 ps
CPU time 14.57 seconds
Started Jul 19 05:37:14 PM PDT 24
Finished Jul 19 05:37:30 PM PDT 24
Peak memory 233304 kb
Host smart-20ad06be-1354-4c6b-b162-d3b972f6449d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024412076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1024412076
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2877446406
Short name T1009
Test name
Test status
Simulation time 5926884616 ps
CPU time 59.84 seconds
Started Jul 19 05:37:15 PM PDT 24
Finished Jul 19 05:38:16 PM PDT 24
Peak memory 255452 kb
Host smart-8cf20686-7a40-4d47-a04d-4488b5057d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877446406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2877446406
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1724019403
Short name T693
Test name
Test status
Simulation time 559138201 ps
CPU time 5.45 seconds
Started Jul 19 05:37:13 PM PDT 24
Finished Jul 19 05:37:20 PM PDT 24
Peak memory 233116 kb
Host smart-4a5f9e66-9bfb-451a-81cf-b89bdeeb5454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724019403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1724019403
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1719430143
Short name T585
Test name
Test status
Simulation time 4074028673 ps
CPU time 47.75 seconds
Started Jul 19 05:37:15 PM PDT 24
Finished Jul 19 05:38:04 PM PDT 24
Peak memory 241384 kb
Host smart-9c3d1553-b82e-4af6-bc99-117e1c48c221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719430143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1719430143
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.623973049
Short name T651
Test name
Test status
Simulation time 31796738 ps
CPU time 1 seconds
Started Jul 19 05:37:13 PM PDT 24
Finished Jul 19 05:37:15 PM PDT 24
Peak memory 218456 kb
Host smart-6a372c31-b387-485e-9e1c-850321d38aad
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623973049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.623973049
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3465101014
Short name T309
Test name
Test status
Simulation time 7622466411 ps
CPU time 17.14 seconds
Started Jul 19 05:37:14 PM PDT 24
Finished Jul 19 05:37:33 PM PDT 24
Peak memory 234336 kb
Host smart-13f4a8cd-8b11-46b3-b8d5-38e779f9842e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465101014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3465101014
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.4026492241
Short name T782
Test name
Test status
Simulation time 1008403673 ps
CPU time 8.43 seconds
Started Jul 19 05:37:14 PM PDT 24
Finished Jul 19 05:37:24 PM PDT 24
Peak memory 233176 kb
Host smart-9fb4a35c-1790-4e60-82d1-4f7fd9a75df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026492241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.4026492241
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3359779424
Short name T533
Test name
Test status
Simulation time 941240943 ps
CPU time 7.54 seconds
Started Jul 19 05:37:15 PM PDT 24
Finished Jul 19 05:37:24 PM PDT 24
Peak memory 220708 kb
Host smart-a3801489-d7c7-4c25-8b27-6ba8ab11e591
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3359779424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3359779424
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.832690996
Short name T170
Test name
Test status
Simulation time 21723842280 ps
CPU time 133.3 seconds
Started Jul 19 05:37:14 PM PDT 24
Finished Jul 19 05:39:29 PM PDT 24
Peak memory 253560 kb
Host smart-164f7a27-e76b-4049-8cb8-100d45c4cb24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832690996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.832690996
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3949625352
Short name T729
Test name
Test status
Simulation time 7610927844 ps
CPU time 34.79 seconds
Started Jul 19 05:37:15 PM PDT 24
Finished Jul 19 05:37:51 PM PDT 24
Peak memory 217072 kb
Host smart-c7e976e9-b0eb-4796-88b9-072cd4ad29e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949625352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3949625352
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1836879050
Short name T352
Test name
Test status
Simulation time 8086250445 ps
CPU time 12.77 seconds
Started Jul 19 05:37:13 PM PDT 24
Finished Jul 19 05:37:27 PM PDT 24
Peak memory 216756 kb
Host smart-1d0d05db-fcdf-4975-8fc3-29f97a3795ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836879050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1836879050
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.284150297
Short name T546
Test name
Test status
Simulation time 156757044 ps
CPU time 1.59 seconds
Started Jul 19 05:37:17 PM PDT 24
Finished Jul 19 05:37:19 PM PDT 24
Peak memory 216632 kb
Host smart-a5b62101-8505-4171-b457-6e9dd1aa5aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284150297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.284150297
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4290334332
Short name T529
Test name
Test status
Simulation time 27513751 ps
CPU time 0.89 seconds
Started Jul 19 05:37:17 PM PDT 24
Finished Jul 19 05:37:19 PM PDT 24
Peak memory 206528 kb
Host smart-a103338a-34b4-4dd9-95f5-fa1474027a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290334332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4290334332
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1105067865
Short name T618
Test name
Test status
Simulation time 3838658766 ps
CPU time 6.47 seconds
Started Jul 19 05:37:14 PM PDT 24
Finished Jul 19 05:37:21 PM PDT 24
Peak memory 233208 kb
Host smart-5d10e2b3-61ed-43cb-8a35-e778e6dc281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105067865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1105067865
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2405171738
Short name T384
Test name
Test status
Simulation time 19789899 ps
CPU time 0.73 seconds
Started Jul 19 05:37:22 PM PDT 24
Finished Jul 19 05:37:25 PM PDT 24
Peak memory 205200 kb
Host smart-803674c4-b392-421a-92ba-f2324e6e8342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405171738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2405171738
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3784115127
Short name T806
Test name
Test status
Simulation time 1283872965 ps
CPU time 13.39 seconds
Started Jul 19 05:37:23 PM PDT 24
Finished Jul 19 05:37:38 PM PDT 24
Peak memory 224940 kb
Host smart-7190e98a-4863-4763-b684-e4d922cb9356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784115127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3784115127
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1706585004
Short name T756
Test name
Test status
Simulation time 76445539 ps
CPU time 0.8 seconds
Started Jul 19 05:37:16 PM PDT 24
Finished Jul 19 05:37:18 PM PDT 24
Peak memory 207272 kb
Host smart-40bd4601-f36d-4753-83fa-717665dcf93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706585004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1706585004
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3937876393
Short name T293
Test name
Test status
Simulation time 20371398292 ps
CPU time 130.12 seconds
Started Jul 19 05:37:33 PM PDT 24
Finished Jul 19 05:39:45 PM PDT 24
Peak memory 255008 kb
Host smart-34ab54e8-631c-419a-a138-5770e004dd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937876393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3937876393
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2271982245
Short name T213
Test name
Test status
Simulation time 145118769036 ps
CPU time 724.58 seconds
Started Jul 19 05:37:22 PM PDT 24
Finished Jul 19 05:49:27 PM PDT 24
Peak memory 265604 kb
Host smart-b90ae5fb-d3e8-4dce-9522-1c94a39f18e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271982245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2271982245
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1148216854
Short name T640
Test name
Test status
Simulation time 88099687473 ps
CPU time 222.26 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:41:16 PM PDT 24
Peak memory 254756 kb
Host smart-e4ca9cae-3990-461e-aae6-b87deeb142be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148216854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1148216854
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.773165743
Short name T248
Test name
Test status
Simulation time 268407204 ps
CPU time 3.42 seconds
Started Jul 19 05:37:23 PM PDT 24
Finished Jul 19 05:37:29 PM PDT 24
Peak memory 224920 kb
Host smart-df6939a2-836b-42a8-a855-64a34a316733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773165743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.773165743
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.478769208
Short name T732
Test name
Test status
Simulation time 23518525548 ps
CPU time 162.17 seconds
Started Jul 19 05:37:30 PM PDT 24
Finished Jul 19 05:40:15 PM PDT 24
Peak memory 249620 kb
Host smart-f7e72f8b-e057-4499-8862-f5cc3dce1210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478769208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.478769208
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1680868611
Short name T819
Test name
Test status
Simulation time 28860051 ps
CPU time 2.16 seconds
Started Jul 19 05:37:24 PM PDT 24
Finished Jul 19 05:37:28 PM PDT 24
Peak memory 224084 kb
Host smart-070b4018-37fe-40a9-812e-47bb0aa6b2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680868611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1680868611
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3481847403
Short name T215
Test name
Test status
Simulation time 2000589696 ps
CPU time 8.59 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:37:42 PM PDT 24
Peak memory 224864 kb
Host smart-e0c41c8b-c586-4b9a-8fc7-d46bd44651ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481847403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3481847403
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1789605767
Short name T703
Test name
Test status
Simulation time 92821150 ps
CPU time 1.08 seconds
Started Jul 19 05:37:12 PM PDT 24
Finished Jul 19 05:37:14 PM PDT 24
Peak memory 217120 kb
Host smart-92b19930-bc50-4022-ba14-1f52f6e0050d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789605767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1789605767
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3831628673
Short name T270
Test name
Test status
Simulation time 6018088180 ps
CPU time 18.12 seconds
Started Jul 19 05:37:24 PM PDT 24
Finished Jul 19 05:37:44 PM PDT 24
Peak memory 233308 kb
Host smart-7c041598-441a-437d-a7e6-f24cd32b633d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831628673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3831628673
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3939728455
Short name T524
Test name
Test status
Simulation time 14183534935 ps
CPU time 8.64 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:37:42 PM PDT 24
Peak memory 224996 kb
Host smart-2b521d5f-ae20-4dff-b204-15f3ba8b9ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939728455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3939728455
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3659737947
Short name T947
Test name
Test status
Simulation time 938514788 ps
CPU time 10.63 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:37:44 PM PDT 24
Peak memory 219232 kb
Host smart-e867fd0f-3b18-42e7-920e-92a1c4bf45cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3659737947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3659737947
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1463300566
Short name T341
Test name
Test status
Simulation time 573883357 ps
CPU time 7.35 seconds
Started Jul 19 05:37:15 PM PDT 24
Finished Jul 19 05:37:24 PM PDT 24
Peak memory 216600 kb
Host smart-b6dba2f5-2e67-48e8-b128-0880f024b14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463300566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1463300566
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4204511502
Short name T72
Test name
Test status
Simulation time 2352608291 ps
CPU time 2.45 seconds
Started Jul 19 05:37:15 PM PDT 24
Finished Jul 19 05:37:19 PM PDT 24
Peak memory 208308 kb
Host smart-1f65f5aa-7802-461a-b48f-2d96bd904131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204511502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4204511502
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3057685924
Short name T949
Test name
Test status
Simulation time 69522507 ps
CPU time 0.98 seconds
Started Jul 19 05:37:25 PM PDT 24
Finished Jul 19 05:37:27 PM PDT 24
Peak memory 207384 kb
Host smart-d36029e8-2a06-4add-b1e5-182a7e83f793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057685924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3057685924
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2350597375
Short name T631
Test name
Test status
Simulation time 72042521 ps
CPU time 0.86 seconds
Started Jul 19 05:37:22 PM PDT 24
Finished Jul 19 05:37:24 PM PDT 24
Peak memory 206496 kb
Host smart-93a6854d-a4bd-449f-ac77-5380e522ea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350597375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2350597375
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1043764381
Short name T254
Test name
Test status
Simulation time 189229407 ps
CPU time 3.26 seconds
Started Jul 19 05:37:20 PM PDT 24
Finished Jul 19 05:37:25 PM PDT 24
Peak memory 233080 kb
Host smart-3c5f2d79-c065-415b-9458-a88437ad0617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043764381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1043764381
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.165826152
Short name T602
Test name
Test status
Simulation time 47731185 ps
CPU time 0.74 seconds
Started Jul 19 05:37:29 PM PDT 24
Finished Jul 19 05:37:32 PM PDT 24
Peak memory 205748 kb
Host smart-17254cd4-9887-41af-90d0-b0c3d240c5d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165826152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.165826152
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.888280235
Short name T962
Test name
Test status
Simulation time 50364533 ps
CPU time 2.1 seconds
Started Jul 19 05:37:29 PM PDT 24
Finished Jul 19 05:37:34 PM PDT 24
Peak memory 224452 kb
Host smart-6a8f8990-b124-431a-9b05-8b85a393512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888280235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.888280235
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3699387499
Short name T397
Test name
Test status
Simulation time 24088331 ps
CPU time 0.75 seconds
Started Jul 19 05:37:32 PM PDT 24
Finished Jul 19 05:37:35 PM PDT 24
Peak memory 206840 kb
Host smart-c90600d9-c56c-4653-bb78-94acda097032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699387499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3699387499
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2005377476
Short name T308
Test name
Test status
Simulation time 1811832941 ps
CPU time 10.38 seconds
Started Jul 19 05:37:32 PM PDT 24
Finished Jul 19 05:37:45 PM PDT 24
Peak memory 233164 kb
Host smart-6316d2d1-b2aa-415f-a087-f33b875f5c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005377476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2005377476
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.210927488
Short name T504
Test name
Test status
Simulation time 3841842482 ps
CPU time 31.2 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:38:04 PM PDT 24
Peak memory 224884 kb
Host smart-4050485f-8c8c-4f79-b33e-c30249f70a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210927488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.210927488
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3707693180
Short name T953
Test name
Test status
Simulation time 159303938 ps
CPU time 3.28 seconds
Started Jul 19 05:37:29 PM PDT 24
Finished Jul 19 05:37:34 PM PDT 24
Peak memory 233160 kb
Host smart-3832ba50-2a2d-4181-a976-442ea4567388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707693180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3707693180
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2197070131
Short name T381
Test name
Test status
Simulation time 12740681 ps
CPU time 0.79 seconds
Started Jul 19 05:37:30 PM PDT 24
Finished Jul 19 05:37:33 PM PDT 24
Peak memory 216312 kb
Host smart-ef8e3114-7cf4-4b68-8a2d-5fbb3c53d1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197070131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2197070131
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1298202138
Short name T597
Test name
Test status
Simulation time 88988236 ps
CPU time 3.74 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:37:37 PM PDT 24
Peak memory 224956 kb
Host smart-8b6e839d-0e5e-49fa-a216-f6b89fe05d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298202138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1298202138
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.4135105674
Short name T252
Test name
Test status
Simulation time 5751040256 ps
CPU time 56.58 seconds
Started Jul 19 05:37:29 PM PDT 24
Finished Jul 19 05:38:28 PM PDT 24
Peak memory 233304 kb
Host smart-a8a07352-6d55-481d-8580-774f173fa8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135105674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4135105674
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.382171984
Short name T879
Test name
Test status
Simulation time 68909738 ps
CPU time 1.08 seconds
Started Jul 19 05:37:22 PM PDT 24
Finished Jul 19 05:37:25 PM PDT 24
Peak memory 217164 kb
Host smart-4c4a64e7-c712-4bed-9169-c4501a682635
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382171984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.382171984
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1451630160
Short name T269
Test name
Test status
Simulation time 443092858 ps
CPU time 3.77 seconds
Started Jul 19 05:37:32 PM PDT 24
Finished Jul 19 05:37:38 PM PDT 24
Peak memory 233116 kb
Host smart-c11f4b44-715e-473e-9909-6af86b448650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451630160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1451630160
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3690881825
Short name T652
Test name
Test status
Simulation time 10407124756 ps
CPU time 134.02 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:39:47 PM PDT 24
Peak memory 256756 kb
Host smart-6d9f5e17-d4a6-407a-9d3a-3361805ea1ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690881825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3690881825
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.964926557
Short name T619
Test name
Test status
Simulation time 3620302685 ps
CPU time 16.27 seconds
Started Jul 19 05:37:24 PM PDT 24
Finished Jul 19 05:37:42 PM PDT 24
Peak memory 216792 kb
Host smart-fe9a5f5b-4e09-458d-8174-5e8218c5c42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964926557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.964926557
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1019344425
Short name T662
Test name
Test status
Simulation time 828664983 ps
CPU time 6.42 seconds
Started Jul 19 05:37:21 PM PDT 24
Finished Jul 19 05:37:28 PM PDT 24
Peak memory 216608 kb
Host smart-e773bc32-3c96-4371-a5d8-5eaa281564bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019344425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1019344425
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1524375405
Short name T909
Test name
Test status
Simulation time 816164344 ps
CPU time 6.25 seconds
Started Jul 19 05:37:22 PM PDT 24
Finished Jul 19 05:37:29 PM PDT 24
Peak memory 216700 kb
Host smart-870e05d2-9ecd-441e-8dca-0fd658fa1996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524375405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1524375405
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.68662547
Short name T522
Test name
Test status
Simulation time 108110246 ps
CPU time 0.8 seconds
Started Jul 19 05:37:20 PM PDT 24
Finished Jul 19 05:37:23 PM PDT 24
Peak memory 206236 kb
Host smart-4c8ec7b6-fee9-4bf2-8aaa-446c1c1abf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68662547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.68662547
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.165208397
Short name T137
Test name
Test status
Simulation time 912901848 ps
CPU time 8.95 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:37:42 PM PDT 24
Peak memory 233084 kb
Host smart-13bce63d-c80d-4562-af16-804a5f161c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165208397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.165208397
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1150072562
Short name T75
Test name
Test status
Simulation time 17193557 ps
CPU time 0.73 seconds
Started Jul 19 05:37:40 PM PDT 24
Finished Jul 19 05:37:42 PM PDT 24
Peak memory 205184 kb
Host smart-01a73967-c04e-4597-8cd9-48f987625fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150072562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1150072562
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.865116920
Short name T255
Test name
Test status
Simulation time 83286144 ps
CPU time 2.23 seconds
Started Jul 19 05:37:40 PM PDT 24
Finished Jul 19 05:37:44 PM PDT 24
Peak memory 224944 kb
Host smart-7853772c-5a84-48bb-8c9d-fa4f3ab67197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865116920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.865116920
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3639591875
Short name T802
Test name
Test status
Simulation time 18544892 ps
CPU time 0.83 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:37:34 PM PDT 24
Peak memory 206860 kb
Host smart-dfb65721-2d75-4faf-b62a-3b0852d1e2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639591875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3639591875
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2733461520
Short name T35
Test name
Test status
Simulation time 134777290086 ps
CPU time 217.61 seconds
Started Jul 19 05:37:40 PM PDT 24
Finished Jul 19 05:41:19 PM PDT 24
Peak memory 262796 kb
Host smart-b368b5a2-ac21-4e57-9df2-261d0096def4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733461520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2733461520
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3677153665
Short name T901
Test name
Test status
Simulation time 88470181134 ps
CPU time 206.63 seconds
Started Jul 19 05:37:41 PM PDT 24
Finished Jul 19 05:41:10 PM PDT 24
Peak memory 250864 kb
Host smart-26b7514f-b63a-4394-bfbb-bc640179eb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677153665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3677153665
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2082384556
Short name T474
Test name
Test status
Simulation time 756073231 ps
CPU time 14.23 seconds
Started Jul 19 05:37:40 PM PDT 24
Finished Jul 19 05:37:55 PM PDT 24
Peak memory 233124 kb
Host smart-19ddb850-b393-45c4-8023-c9482643478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082384556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2082384556
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2749875525
Short name T697
Test name
Test status
Simulation time 341447343 ps
CPU time 8.9 seconds
Started Jul 19 05:37:42 PM PDT 24
Finished Jul 19 05:37:52 PM PDT 24
Peak memory 224960 kb
Host smart-9f29f51b-9c30-49bb-8950-526f26830746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749875525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2749875525
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3671414023
Short name T895
Test name
Test status
Simulation time 318425571 ps
CPU time 6.05 seconds
Started Jul 19 05:37:30 PM PDT 24
Finished Jul 19 05:37:38 PM PDT 24
Peak memory 233136 kb
Host smart-f0dc5906-da98-46a7-bfe8-57b437d7f2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671414023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3671414023
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1559364472
Short name T924
Test name
Test status
Simulation time 89290932 ps
CPU time 2.55 seconds
Started Jul 19 05:37:30 PM PDT 24
Finished Jul 19 05:37:35 PM PDT 24
Peak memory 224940 kb
Host smart-94d20e9f-2e31-404a-b3c5-1a9e21540711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559364472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1559364472
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2574897129
Short name T823
Test name
Test status
Simulation time 16999668 ps
CPU time 1 seconds
Started Jul 19 05:37:32 PM PDT 24
Finished Jul 19 05:37:35 PM PDT 24
Peak memory 218368 kb
Host smart-4fe4186d-bcc0-4ff5-9bfc-2449d1e4cb3c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574897129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2574897129
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1489520603
Short name T247
Test name
Test status
Simulation time 2313180271 ps
CPU time 13.05 seconds
Started Jul 19 05:37:28 PM PDT 24
Finished Jul 19 05:37:44 PM PDT 24
Peak memory 233220 kb
Host smart-c3b03f0d-d4e5-46d4-824e-5364ac09a1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489520603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1489520603
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1680557173
Short name T264
Test name
Test status
Simulation time 23612568910 ps
CPU time 14.38 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:37:47 PM PDT 24
Peak memory 233264 kb
Host smart-bce9a77c-8dcc-4c25-ad15-33298324e4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680557173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1680557173
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3625076385
Short name T1011
Test name
Test status
Simulation time 260738341 ps
CPU time 4.35 seconds
Started Jul 19 05:37:42 PM PDT 24
Finished Jul 19 05:37:48 PM PDT 24
Peak memory 220728 kb
Host smart-1a9c4003-07c1-4932-80ba-8552654a06a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3625076385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3625076385
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1197329452
Short name T625
Test name
Test status
Simulation time 3271103422 ps
CPU time 64.65 seconds
Started Jul 19 05:37:42 PM PDT 24
Finished Jul 19 05:38:49 PM PDT 24
Peak memory 256500 kb
Host smart-4a1955ee-82de-46c6-a641-2be989894ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197329452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1197329452
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1256334578
Short name T73
Test name
Test status
Simulation time 409431906 ps
CPU time 4.87 seconds
Started Jul 19 05:37:30 PM PDT 24
Finished Jul 19 05:37:37 PM PDT 24
Peak memory 216704 kb
Host smart-50789a3c-9df5-401f-b281-3d6110a83de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256334578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1256334578
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3721776025
Short name T935
Test name
Test status
Simulation time 2314764323 ps
CPU time 8.43 seconds
Started Jul 19 05:37:30 PM PDT 24
Finished Jul 19 05:37:40 PM PDT 24
Peak memory 216780 kb
Host smart-667a95a8-66f7-4369-8f3d-1c631d2cb78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721776025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3721776025
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2419600874
Short name T435
Test name
Test status
Simulation time 241317224 ps
CPU time 3.12 seconds
Started Jul 19 05:37:30 PM PDT 24
Finished Jul 19 05:37:36 PM PDT 24
Peak memory 216592 kb
Host smart-a564b66b-b2c9-46ee-a39a-a8c2706f39ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419600874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2419600874
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.482564457
Short name T409
Test name
Test status
Simulation time 25294180 ps
CPU time 0.84 seconds
Started Jul 19 05:37:31 PM PDT 24
Finished Jul 19 05:37:34 PM PDT 24
Peak memory 206292 kb
Host smart-ca798694-3d83-4859-a4c8-0eb6e9ca1e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482564457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.482564457
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1263913428
Short name T245
Test name
Test status
Simulation time 195294976 ps
CPU time 3.02 seconds
Started Jul 19 05:37:30 PM PDT 24
Finished Jul 19 05:37:35 PM PDT 24
Peak memory 233116 kb
Host smart-288ebbb5-a521-4679-80d1-935c8d2b535a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263913428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1263913428
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3859152537
Short name T448
Test name
Test status
Simulation time 26476014 ps
CPU time 0.7 seconds
Started Jul 19 05:34:54 PM PDT 24
Finished Jul 19 05:35:57 PM PDT 24
Peak memory 205132 kb
Host smart-52863da6-fce4-48a1-898f-739404643b20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859152537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
859152537
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3526502653
Short name T827
Test name
Test status
Simulation time 1020853290 ps
CPU time 8.23 seconds
Started Jul 19 05:34:46 PM PDT 24
Finished Jul 19 05:35:47 PM PDT 24
Peak memory 224956 kb
Host smart-6efe8a83-b6ce-46ff-a32c-ddd69c386435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526502653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3526502653
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1081516084
Short name T404
Test name
Test status
Simulation time 15144901 ps
CPU time 0.8 seconds
Started Jul 19 05:34:46 PM PDT 24
Finished Jul 19 05:35:39 PM PDT 24
Peak memory 207188 kb
Host smart-b705e92a-b0e7-4eaa-9a1c-795021e92b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081516084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1081516084
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1821169306
Short name T845
Test name
Test status
Simulation time 11490972394 ps
CPU time 78.32 seconds
Started Jul 19 05:34:45 PM PDT 24
Finished Jul 19 05:36:53 PM PDT 24
Peak memory 241484 kb
Host smart-00cd83ab-aa2e-407a-adc1-fec076d47eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821169306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1821169306
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1692803779
Short name T956
Test name
Test status
Simulation time 98975272307 ps
CPU time 305.84 seconds
Started Jul 19 05:34:54 PM PDT 24
Finished Jul 19 05:41:02 PM PDT 24
Peak memory 257680 kb
Host smart-ed7763e2-ed5a-47af-95d9-2907775c87ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692803779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1692803779
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3161938508
Short name T711
Test name
Test status
Simulation time 5739510951 ps
CPU time 88.17 seconds
Started Jul 19 05:34:55 PM PDT 24
Finished Jul 19 05:37:24 PM PDT 24
Peak memory 253816 kb
Host smart-d6fa7a31-65d2-4359-b5f0-af2f3b48305a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161938508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3161938508
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3525926410
Short name T221
Test name
Test status
Simulation time 14948077292 ps
CPU time 98.63 seconds
Started Jul 19 05:34:57 PM PDT 24
Finished Jul 19 05:37:37 PM PDT 24
Peak memory 271256 kb
Host smart-0f7bde40-bfa6-4402-b13d-7d31ee51ee29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525926410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3525926410
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1185452948
Short name T253
Test name
Test status
Simulation time 9783856914 ps
CPU time 9.51 seconds
Started Jul 19 05:34:54 PM PDT 24
Finished Jul 19 05:36:06 PM PDT 24
Peak memory 233388 kb
Host smart-3d9fb67a-6688-46b4-94a3-8e0054c3c0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185452948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1185452948
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1275715320
Short name T265
Test name
Test status
Simulation time 1878144334 ps
CPU time 17.15 seconds
Started Jul 19 05:34:55 PM PDT 24
Finished Jul 19 05:36:13 PM PDT 24
Peak memory 238876 kb
Host smart-db112e9c-e511-4c3c-9aef-0b4aa694de30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275715320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1275715320
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3520577976
Short name T586
Test name
Test status
Simulation time 110233281 ps
CPU time 0.99 seconds
Started Jul 19 05:34:45 PM PDT 24
Finished Jul 19 05:35:36 PM PDT 24
Peak memory 218364 kb
Host smart-413f27ba-030a-4940-9701-d7927105e175
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520577976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3520577976
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.657752579
Short name T817
Test name
Test status
Simulation time 4708163301 ps
CPU time 10.05 seconds
Started Jul 19 05:34:56 PM PDT 24
Finished Jul 19 05:36:08 PM PDT 24
Peak memory 233292 kb
Host smart-ae63f8c2-41f9-433d-a6d2-a07cea443719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657752579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
657752579
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2993842564
Short name T464
Test name
Test status
Simulation time 566842300 ps
CPU time 4.42 seconds
Started Jul 19 05:34:48 PM PDT 24
Finished Jul 19 05:35:47 PM PDT 24
Peak memory 224884 kb
Host smart-bc827943-3422-40c8-829d-ba5689c5c46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993842564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2993842564
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2262493497
Short name T155
Test name
Test status
Simulation time 1449961907 ps
CPU time 10.21 seconds
Started Jul 19 05:34:57 PM PDT 24
Finished Jul 19 05:36:09 PM PDT 24
Peak memory 219136 kb
Host smart-14590ab1-bed3-46a5-bd90-29bb1be139bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2262493497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2262493497
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2152795165
Short name T64
Test name
Test status
Simulation time 86749113 ps
CPU time 1.24 seconds
Started Jul 19 05:34:54 PM PDT 24
Finished Jul 19 05:35:57 PM PDT 24
Peak memory 235788 kb
Host smart-a43d710d-fa8f-403d-9ace-96089c2a5925
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152795165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2152795165
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1173530398
Short name T297
Test name
Test status
Simulation time 56864277234 ps
CPU time 671.82 seconds
Started Jul 19 05:34:54 PM PDT 24
Finished Jul 19 05:47:08 PM PDT 24
Peak memory 288496 kb
Host smart-b52cecc0-eb13-4ca6-8d8b-7e1c94a3f4a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173530398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1173530398
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.990097925
Short name T452
Test name
Test status
Simulation time 1865019753 ps
CPU time 17.85 seconds
Started Jul 19 05:34:48 PM PDT 24
Finished Jul 19 05:36:00 PM PDT 24
Peak memory 216664 kb
Host smart-8e3782b5-b938-4481-8b7e-6a2a24f9d566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990097925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.990097925
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1432669537
Short name T387
Test name
Test status
Simulation time 2512813981 ps
CPU time 6.75 seconds
Started Jul 19 05:34:47 PM PDT 24
Finished Jul 19 05:35:45 PM PDT 24
Peak memory 216776 kb
Host smart-ccbbec00-1fbe-4351-9bd3-2b1995e557a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432669537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1432669537
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3993945047
Short name T483
Test name
Test status
Simulation time 11431256 ps
CPU time 0.78 seconds
Started Jul 19 05:34:46 PM PDT 24
Finished Jul 19 05:35:36 PM PDT 24
Peak memory 206260 kb
Host smart-8bdac2f5-fa09-447b-96d1-ca756d7261e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993945047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3993945047
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2499131053
Short name T690
Test name
Test status
Simulation time 117377361 ps
CPU time 0.71 seconds
Started Jul 19 05:34:57 PM PDT 24
Finished Jul 19 05:35:59 PM PDT 24
Peak memory 206260 kb
Host smart-b3b0a9a0-faf4-4b3a-bde9-d0ea899487ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499131053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2499131053
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2739363429
Short name T883
Test name
Test status
Simulation time 49541563199 ps
CPU time 38.7 seconds
Started Jul 19 05:34:47 PM PDT 24
Finished Jul 19 05:36:18 PM PDT 24
Peak memory 240896 kb
Host smart-bb87d297-916d-45ce-86da-4e0574aa4df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739363429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2739363429
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2148917648
Short name T62
Test name
Test status
Simulation time 12774207 ps
CPU time 0.72 seconds
Started Jul 19 05:37:42 PM PDT 24
Finished Jul 19 05:37:44 PM PDT 24
Peak memory 205184 kb
Host smart-71056779-440a-4ad0-875a-07f0efc6138b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148917648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2148917648
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1921954771
Short name T801
Test name
Test status
Simulation time 1478659107 ps
CPU time 21.24 seconds
Started Jul 19 05:37:41 PM PDT 24
Finished Jul 19 05:38:04 PM PDT 24
Peak memory 224888 kb
Host smart-abe7a199-83f2-4cc8-b89a-fd3910e7395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921954771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1921954771
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.670875769
Short name T907
Test name
Test status
Simulation time 49285767 ps
CPU time 0.76 seconds
Started Jul 19 05:37:38 PM PDT 24
Finished Jul 19 05:37:40 PM PDT 24
Peak memory 207188 kb
Host smart-3757fc4e-f93e-4656-bb49-61847c9a36db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670875769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.670875769
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1016807798
Short name T310
Test name
Test status
Simulation time 6950880227 ps
CPU time 46.68 seconds
Started Jul 19 05:37:40 PM PDT 24
Finished Jul 19 05:38:27 PM PDT 24
Peak memory 236644 kb
Host smart-1cf8d795-59f9-484b-a568-f711be807823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016807798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1016807798
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1720008098
Short name T795
Test name
Test status
Simulation time 10051084508 ps
CPU time 138.06 seconds
Started Jul 19 05:37:40 PM PDT 24
Finished Jul 19 05:39:59 PM PDT 24
Peak memory 255324 kb
Host smart-de28515c-1af1-421e-80be-c03f61addcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720008098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1720008098
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3892029961
Short name T52
Test name
Test status
Simulation time 39886324618 ps
CPU time 205.6 seconds
Started Jul 19 05:37:42 PM PDT 24
Finished Jul 19 05:41:09 PM PDT 24
Peak memory 257876 kb
Host smart-54aafad9-0bf0-48f1-80e4-eeec84ddccce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892029961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3892029961
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1408563683
Short name T439
Test name
Test status
Simulation time 112244715 ps
CPU time 5.33 seconds
Started Jul 19 05:37:42 PM PDT 24
Finished Jul 19 05:37:49 PM PDT 24
Peak memory 224916 kb
Host smart-20e40887-9ab1-4c65-b4a4-f026e098e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408563683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1408563683
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.105714424
Short name T305
Test name
Test status
Simulation time 136378060804 ps
CPU time 285.97 seconds
Started Jul 19 05:37:42 PM PDT 24
Finished Jul 19 05:42:30 PM PDT 24
Peak memory 271856 kb
Host smart-850c81fc-b81b-49aa-8be7-5c9e0294ab12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105714424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.105714424
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.979998642
Short name T554
Test name
Test status
Simulation time 82950070 ps
CPU time 2.6 seconds
Started Jul 19 05:37:40 PM PDT 24
Finished Jul 19 05:37:43 PM PDT 24
Peak memory 232852 kb
Host smart-fd8b0686-3e0a-4954-ba18-c4c176be23ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979998642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.979998642
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4005796310
Short name T260
Test name
Test status
Simulation time 12886263388 ps
CPU time 26.29 seconds
Started Jul 19 05:37:40 PM PDT 24
Finished Jul 19 05:38:08 PM PDT 24
Peak memory 225068 kb
Host smart-467453ed-7a2e-41e1-8bdc-cd082f2ac744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005796310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4005796310
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1054591693
Short name T210
Test name
Test status
Simulation time 575925938 ps
CPU time 4.78 seconds
Started Jul 19 05:37:41 PM PDT 24
Finished Jul 19 05:37:48 PM PDT 24
Peak memory 224952 kb
Host smart-ee3dba7b-2f6d-4713-a398-8974b1751d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054591693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1054591693
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.392707187
Short name T785
Test name
Test status
Simulation time 1270772695 ps
CPU time 6.52 seconds
Started Jul 19 05:37:39 PM PDT 24
Finished Jul 19 05:37:46 PM PDT 24
Peak memory 233092 kb
Host smart-547501c3-1959-4a1f-b66e-9dcfabc7e7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392707187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.392707187
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3038526746
Short name T685
Test name
Test status
Simulation time 149779358 ps
CPU time 4.73 seconds
Started Jul 19 05:37:41 PM PDT 24
Finished Jul 19 05:37:48 PM PDT 24
Peak memory 223056 kb
Host smart-3ec01989-f1ab-4eba-91db-77ea1c41c56a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3038526746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3038526746
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3702807624
Short name T307
Test name
Test status
Simulation time 89342707316 ps
CPU time 235.58 seconds
Started Jul 19 05:37:41 PM PDT 24
Finished Jul 19 05:41:38 PM PDT 24
Peak memory 250896 kb
Host smart-c373fca3-c6e5-4979-ac5b-7d7e500ea8aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702807624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3702807624
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3078170606
Short name T681
Test name
Test status
Simulation time 444797028 ps
CPU time 2.96 seconds
Started Jul 19 05:37:41 PM PDT 24
Finished Jul 19 05:37:46 PM PDT 24
Peak memory 216788 kb
Host smart-836a53f2-e94b-4191-8c32-7f8d00a5fc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078170606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3078170606
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3780948813
Short name T917
Test name
Test status
Simulation time 69879399197 ps
CPU time 11.42 seconds
Started Jul 19 05:37:39 PM PDT 24
Finished Jul 19 05:37:51 PM PDT 24
Peak memory 217988 kb
Host smart-467dcd91-6fde-4d7c-a5fa-0e2dff2b0442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780948813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3780948813
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.780602269
Short name T583
Test name
Test status
Simulation time 94248235 ps
CPU time 3.49 seconds
Started Jul 19 05:37:41 PM PDT 24
Finished Jul 19 05:37:46 PM PDT 24
Peak memory 216700 kb
Host smart-93b5995f-e6cd-4a74-a65d-2c3cebbc7f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780602269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.780602269
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1799147525
Short name T607
Test name
Test status
Simulation time 37605962 ps
CPU time 0.71 seconds
Started Jul 19 05:37:42 PM PDT 24
Finished Jul 19 05:37:45 PM PDT 24
Peak memory 205944 kb
Host smart-d5fc4099-88ec-414b-b78a-3c30ed75145d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799147525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1799147525
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4155390819
Short name T610
Test name
Test status
Simulation time 11699415103 ps
CPU time 23.68 seconds
Started Jul 19 05:37:40 PM PDT 24
Finished Jul 19 05:38:05 PM PDT 24
Peak memory 233272 kb
Host smart-9cfbd786-12e9-4cb3-b993-03dcf6d003b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155390819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4155390819
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3879741237
Short name T911
Test name
Test status
Simulation time 12462453 ps
CPU time 0.73 seconds
Started Jul 19 05:37:48 PM PDT 24
Finished Jul 19 05:37:50 PM PDT 24
Peak memory 205152 kb
Host smart-49a48b0c-10d7-43c1-ba28-b1eda40e6552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879741237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3879741237
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.176784260
Short name T367
Test name
Test status
Simulation time 243802858 ps
CPU time 1.99 seconds
Started Jul 19 05:37:44 PM PDT 24
Finished Jul 19 05:37:47 PM PDT 24
Peak memory 223516 kb
Host smart-97665990-e303-46ef-954d-3397582f4af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176784260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.176784260
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1807994796
Short name T579
Test name
Test status
Simulation time 17887775 ps
CPU time 0.77 seconds
Started Jul 19 05:37:40 PM PDT 24
Finished Jul 19 05:37:42 PM PDT 24
Peak memory 207204 kb
Host smart-9449558b-6807-44cc-8f67-b2ab052e1140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807994796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1807994796
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.319417408
Short name T637
Test name
Test status
Simulation time 36622820 ps
CPU time 0.76 seconds
Started Jul 19 05:37:47 PM PDT 24
Finished Jul 19 05:37:50 PM PDT 24
Peak memory 216312 kb
Host smart-5545b83b-ffa8-4738-970c-322c7b6ccc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319417408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.319417408
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.4124442250
Short name T713
Test name
Test status
Simulation time 10790316797 ps
CPU time 35.56 seconds
Started Jul 19 05:37:49 PM PDT 24
Finished Jul 19 05:38:26 PM PDT 24
Peak memory 241488 kb
Host smart-79d0fc69-5a9a-4b96-bc1e-3dff79ec1834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124442250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.4124442250
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.993369384
Short name T80
Test name
Test status
Simulation time 58845834386 ps
CPU time 158.35 seconds
Started Jul 19 05:37:45 PM PDT 24
Finished Jul 19 05:40:25 PM PDT 24
Peak memory 265644 kb
Host smart-b0371718-8bde-4b09-b792-a090587c4978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993369384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.993369384
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2584652254
Short name T2
Test name
Test status
Simulation time 269163253 ps
CPU time 4.39 seconds
Started Jul 19 05:37:47 PM PDT 24
Finished Jul 19 05:37:53 PM PDT 24
Peak memory 224920 kb
Host smart-10113a14-4bd9-4ba5-9880-acc00455f184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584652254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2584652254
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.372031393
Short name T195
Test name
Test status
Simulation time 11393830043 ps
CPU time 90.2 seconds
Started Jul 19 05:37:47 PM PDT 24
Finished Jul 19 05:39:19 PM PDT 24
Peak memory 235760 kb
Host smart-d75e2ac4-0d16-4632-bd4d-65ae0ae1ff35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372031393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.372031393
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2387967452
Short name T674
Test name
Test status
Simulation time 1237143137 ps
CPU time 12.35 seconds
Started Jul 19 05:37:45 PM PDT 24
Finished Jul 19 05:37:59 PM PDT 24
Peak memory 233100 kb
Host smart-e1c6961c-9b96-4321-b107-25c270aba087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387967452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2387967452
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3333032873
Short name T259
Test name
Test status
Simulation time 11297334475 ps
CPU time 25.63 seconds
Started Jul 19 05:37:45 PM PDT 24
Finished Jul 19 05:38:12 PM PDT 24
Peak memory 233256 kb
Host smart-502b1f27-c86b-4edb-9da9-6033cbf73eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333032873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3333032873
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1398393859
Short name T770
Test name
Test status
Simulation time 121255020 ps
CPU time 3.71 seconds
Started Jul 19 05:37:44 PM PDT 24
Finished Jul 19 05:37:49 PM PDT 24
Peak memory 233688 kb
Host smart-903ee9be-c4f2-4bac-9bd2-cc1dd748dd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398393859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1398393859
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3567413892
Short name T268
Test name
Test status
Simulation time 34358056 ps
CPU time 2.34 seconds
Started Jul 19 05:37:47 PM PDT 24
Finished Jul 19 05:37:51 PM PDT 24
Peak memory 224952 kb
Host smart-ce875ac6-ff57-45d2-a974-b45d64eab127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567413892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3567413892
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3361556678
Short name T560
Test name
Test status
Simulation time 83811084 ps
CPU time 4.02 seconds
Started Jul 19 05:37:46 PM PDT 24
Finished Jul 19 05:37:51 PM PDT 24
Peak memory 223592 kb
Host smart-61d4d287-fdd7-4ec7-8f77-a58576f573d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3361556678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3361556678
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1320988964
Short name T20
Test name
Test status
Simulation time 52286438 ps
CPU time 1.19 seconds
Started Jul 19 05:37:47 PM PDT 24
Finished Jul 19 05:37:50 PM PDT 24
Peak memory 207232 kb
Host smart-18e55b3a-bf72-49ed-bfa1-dc30b48cd0e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320988964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1320988964
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3181594818
Short name T757
Test name
Test status
Simulation time 2873777054 ps
CPU time 12.37 seconds
Started Jul 19 05:37:41 PM PDT 24
Finished Jul 19 05:37:55 PM PDT 24
Peak memory 220364 kb
Host smart-13a7d363-7a7c-4ad8-986b-68ddf4b58fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181594818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3181594818
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3881359906
Short name T523
Test name
Test status
Simulation time 794558016 ps
CPU time 5.03 seconds
Started Jul 19 05:37:40 PM PDT 24
Finished Jul 19 05:37:47 PM PDT 24
Peak memory 216660 kb
Host smart-821df91a-6ef0-491f-9ce4-5bc142bb2964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881359906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3881359906
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3891662638
Short name T420
Test name
Test status
Simulation time 286306298 ps
CPU time 1.21 seconds
Started Jul 19 05:37:47 PM PDT 24
Finished Jul 19 05:37:50 PM PDT 24
Peak memory 207432 kb
Host smart-bf5a6457-ae3d-4428-be87-07bf9c8a71a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891662638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3891662638
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1026400322
Short name T552
Test name
Test status
Simulation time 78471823 ps
CPU time 0.75 seconds
Started Jul 19 05:37:47 PM PDT 24
Finished Jul 19 05:37:49 PM PDT 24
Peak memory 206180 kb
Host smart-d88a8a6c-f92e-4647-adb2-9ac7d11846fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026400322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1026400322
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3157309888
Short name T368
Test name
Test status
Simulation time 360413346 ps
CPU time 2.79 seconds
Started Jul 19 05:37:48 PM PDT 24
Finished Jul 19 05:37:52 PM PDT 24
Peak memory 232984 kb
Host smart-d4c4cef7-0944-4695-8946-4aca84d5e838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157309888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3157309888
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1421382360
Short name T500
Test name
Test status
Simulation time 20652925 ps
CPU time 0.76 seconds
Started Jul 19 05:37:55 PM PDT 24
Finished Jul 19 05:37:57 PM PDT 24
Peak memory 205744 kb
Host smart-133fb38d-3e1c-42f1-be91-b576f51ceff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421382360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1421382360
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2766059817
Short name T894
Test name
Test status
Simulation time 1294102423 ps
CPU time 13.8 seconds
Started Jul 19 05:37:49 PM PDT 24
Finished Jul 19 05:38:04 PM PDT 24
Peak memory 232860 kb
Host smart-f1f74fe6-6795-40d6-9fc6-219a67f559ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766059817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2766059817
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.938022406
Short name T26
Test name
Test status
Simulation time 16153293 ps
CPU time 0.76 seconds
Started Jul 19 05:37:44 PM PDT 24
Finished Jul 19 05:37:45 PM PDT 24
Peak memory 207216 kb
Host smart-f9bc862b-4e2e-4ce2-b590-d4c3e0904042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938022406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.938022406
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2111577187
Short name T57
Test name
Test status
Simulation time 61225038053 ps
CPU time 106.65 seconds
Started Jul 19 05:37:45 PM PDT 24
Finished Jul 19 05:39:33 PM PDT 24
Peak memory 249692 kb
Host smart-46fdb83f-c29d-4a73-938d-30e2f93c88be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111577187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2111577187
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2230934765
Short name T805
Test name
Test status
Simulation time 88900395306 ps
CPU time 430.56 seconds
Started Jul 19 05:37:53 PM PDT 24
Finished Jul 19 05:45:04 PM PDT 24
Peak memory 266092 kb
Host smart-ef3b4ac6-7fd5-4f9c-8379-aaf6bc9f7aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230934765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2230934765
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1816734229
Short name T145
Test name
Test status
Simulation time 166281961213 ps
CPU time 408.22 seconds
Started Jul 19 05:37:53 PM PDT 24
Finished Jul 19 05:44:42 PM PDT 24
Peak memory 273944 kb
Host smart-23a23c24-2275-4a4f-95fb-098fc307adb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816734229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1816734229
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.788531515
Short name T321
Test name
Test status
Simulation time 596244505 ps
CPU time 4.46 seconds
Started Jul 19 05:37:45 PM PDT 24
Finished Jul 19 05:37:51 PM PDT 24
Peak memory 225020 kb
Host smart-7b9bc702-7ead-42c1-a649-739f13fc13ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788531515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.788531515
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1304301279
Short name T550
Test name
Test status
Simulation time 887117302 ps
CPU time 16.83 seconds
Started Jul 19 05:37:48 PM PDT 24
Finished Jul 19 05:38:07 PM PDT 24
Peak memory 241348 kb
Host smart-b4c6a8d9-e7d9-4109-ba0c-4e5234dd8f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304301279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1304301279
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.152634444
Short name T761
Test name
Test status
Simulation time 54803330 ps
CPU time 3 seconds
Started Jul 19 05:37:44 PM PDT 24
Finished Jul 19 05:37:48 PM PDT 24
Peak memory 233092 kb
Host smart-4ad9f55f-105d-4f78-88e3-15295e883c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152634444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.152634444
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3328019724
Short name T203
Test name
Test status
Simulation time 24568888437 ps
CPU time 31.81 seconds
Started Jul 19 05:37:45 PM PDT 24
Finished Jul 19 05:38:19 PM PDT 24
Peak memory 233236 kb
Host smart-83f3f23e-63ff-44b9-81d0-dddf63fc25e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328019724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3328019724
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3998425198
Short name T272
Test name
Test status
Simulation time 1686968010 ps
CPU time 9.53 seconds
Started Jul 19 05:37:48 PM PDT 24
Finished Jul 19 05:37:59 PM PDT 24
Peak memory 249276 kb
Host smart-4aa77939-73d6-4987-b8de-224351230a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998425198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3998425198
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.201614664
Short name T1028
Test name
Test status
Simulation time 108638467 ps
CPU time 2.35 seconds
Started Jul 19 05:37:46 PM PDT 24
Finished Jul 19 05:37:49 PM PDT 24
Peak memory 223460 kb
Host smart-38e3bbca-9b5e-49b9-9e72-7bab87a2a697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201614664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.201614664
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3137775858
Short name T408
Test name
Test status
Simulation time 273015849 ps
CPU time 3.41 seconds
Started Jul 19 05:37:45 PM PDT 24
Finished Jul 19 05:37:50 PM PDT 24
Peak memory 223552 kb
Host smart-4e1106b8-18ad-4f88-99d7-4c6b214c84ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3137775858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3137775858
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3770099593
Short name T831
Test name
Test status
Simulation time 28046436226 ps
CPU time 125.44 seconds
Started Jul 19 05:37:51 PM PDT 24
Finished Jul 19 05:39:57 PM PDT 24
Peak memory 241548 kb
Host smart-a4b8b7e9-901d-4cb3-8e64-15af30148750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770099593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3770099593
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4027873537
Short name T333
Test name
Test status
Simulation time 285068971 ps
CPU time 5.59 seconds
Started Jul 19 05:37:49 PM PDT 24
Finished Jul 19 05:37:56 PM PDT 24
Peak memory 216708 kb
Host smart-d67949e1-a807-406b-9690-d14a679f7e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027873537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4027873537
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1509006012
Short name T569
Test name
Test status
Simulation time 529189037 ps
CPU time 1.24 seconds
Started Jul 19 05:37:48 PM PDT 24
Finished Jul 19 05:37:51 PM PDT 24
Peak memory 208180 kb
Host smart-bc135585-93aa-4e49-a69a-31ac76e637e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509006012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1509006012
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3964088399
Short name T430
Test name
Test status
Simulation time 1521979561 ps
CPU time 2.47 seconds
Started Jul 19 05:37:49 PM PDT 24
Finished Jul 19 05:37:53 PM PDT 24
Peak memory 216436 kb
Host smart-067588ef-7923-4e4d-98bd-525d936dcce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964088399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3964088399
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3478386907
Short name T735
Test name
Test status
Simulation time 55734590 ps
CPU time 0.78 seconds
Started Jul 19 05:37:45 PM PDT 24
Finished Jul 19 05:37:46 PM PDT 24
Peak memory 206296 kb
Host smart-ddb2c844-0892-4a21-9c7b-5e8b0e2e4f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478386907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3478386907
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.577394115
Short name T699
Test name
Test status
Simulation time 973981470 ps
CPU time 6.51 seconds
Started Jul 19 05:37:47 PM PDT 24
Finished Jul 19 05:37:56 PM PDT 24
Peak memory 233032 kb
Host smart-a11598a5-4607-44ad-9f8d-ae05cd466ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577394115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.577394115
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.74255751
Short name T59
Test name
Test status
Simulation time 155677119 ps
CPU time 0.7 seconds
Started Jul 19 05:37:53 PM PDT 24
Finished Jul 19 05:37:55 PM PDT 24
Peak memory 205792 kb
Host smart-c4e06d3f-42fb-4737-bad0-bf8c1ed76808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74255751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.74255751
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1038847053
Short name T479
Test name
Test status
Simulation time 160927722 ps
CPU time 4.08 seconds
Started Jul 19 05:37:53 PM PDT 24
Finished Jul 19 05:37:59 PM PDT 24
Peak memory 233128 kb
Host smart-cad04fa9-264a-4ae7-91cd-1a4c7723d9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038847053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1038847053
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3830015052
Short name T778
Test name
Test status
Simulation time 19210762 ps
CPU time 0.8 seconds
Started Jul 19 05:37:58 PM PDT 24
Finished Jul 19 05:38:01 PM PDT 24
Peak memory 206892 kb
Host smart-64e0ddc4-52c3-4805-8dc8-def97422473e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830015052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3830015052
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3339032578
Short name T798
Test name
Test status
Simulation time 81384483628 ps
CPU time 384.57 seconds
Started Jul 19 05:37:58 PM PDT 24
Finished Jul 19 05:44:24 PM PDT 24
Peak memory 249732 kb
Host smart-9370caf4-2b1e-4778-9ef6-f66125fdc738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339032578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3339032578
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2684770379
Short name T836
Test name
Test status
Simulation time 23776936965 ps
CPU time 223.61 seconds
Started Jul 19 05:37:59 PM PDT 24
Finished Jul 19 05:41:44 PM PDT 24
Peak memory 249752 kb
Host smart-bcb5b21a-7786-4b58-8242-e7f9cf14640f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684770379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2684770379
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2226069678
Short name T507
Test name
Test status
Simulation time 1198267909 ps
CPU time 8.89 seconds
Started Jul 19 05:37:53 PM PDT 24
Finished Jul 19 05:38:03 PM PDT 24
Peak memory 238948 kb
Host smart-f11335fa-d4b7-479e-a9c8-f0e889e40805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226069678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2226069678
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2476661315
Short name T635
Test name
Test status
Simulation time 334146687841 ps
CPU time 588.14 seconds
Started Jul 19 05:37:59 PM PDT 24
Finished Jul 19 05:47:49 PM PDT 24
Peak memory 264984 kb
Host smart-f560fcd7-6c75-4b91-96c8-1243338fa450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476661315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2476661315
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1298932588
Short name T728
Test name
Test status
Simulation time 633705030 ps
CPU time 3.3 seconds
Started Jul 19 05:37:54 PM PDT 24
Finished Jul 19 05:37:58 PM PDT 24
Peak memory 233108 kb
Host smart-e506ba85-5cd2-4373-881b-9b036d3ec3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298932588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1298932588
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2128682276
Short name T451
Test name
Test status
Simulation time 9371120047 ps
CPU time 67.21 seconds
Started Jul 19 05:37:55 PM PDT 24
Finished Jul 19 05:39:04 PM PDT 24
Peak memory 229272 kb
Host smart-52da334b-0c55-43b5-b257-d62a953e7c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128682276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2128682276
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.4016150611
Short name T301
Test name
Test status
Simulation time 5486094753 ps
CPU time 6.52 seconds
Started Jul 19 05:37:57 PM PDT 24
Finished Jul 19 05:38:05 PM PDT 24
Peak memory 225024 kb
Host smart-10486b44-c2d7-4210-b1c1-9157dda93682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016150611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.4016150611
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.624895201
Short name T650
Test name
Test status
Simulation time 1223794784 ps
CPU time 5.75 seconds
Started Jul 19 05:37:56 PM PDT 24
Finished Jul 19 05:38:03 PM PDT 24
Peak memory 233156 kb
Host smart-283cd597-5aa6-4e91-aded-55e286ea743f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624895201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.624895201
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1863744102
Short name T848
Test name
Test status
Simulation time 827590861 ps
CPU time 5.36 seconds
Started Jul 19 05:38:00 PM PDT 24
Finished Jul 19 05:38:07 PM PDT 24
Peak memory 220632 kb
Host smart-4cc654f2-6c83-4d08-82ec-bb159cd2c87b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1863744102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1863744102
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1638660296
Short name T525
Test name
Test status
Simulation time 1689294787 ps
CPU time 28.1 seconds
Started Jul 19 05:37:53 PM PDT 24
Finished Jul 19 05:38:23 PM PDT 24
Peak memory 218556 kb
Host smart-9c557446-0f68-4289-ab94-23c748b56213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638660296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1638660296
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3891386460
Short name T462
Test name
Test status
Simulation time 1674918101 ps
CPU time 5.44 seconds
Started Jul 19 05:37:55 PM PDT 24
Finished Jul 19 05:38:02 PM PDT 24
Peak memory 216676 kb
Host smart-27b9e09b-031d-4891-a3e7-87fcc02bb04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891386460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3891386460
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3032652609
Short name T726
Test name
Test status
Simulation time 52305142 ps
CPU time 1.63 seconds
Started Jul 19 05:37:54 PM PDT 24
Finished Jul 19 05:37:57 PM PDT 24
Peak memory 216724 kb
Host smart-2e98d44b-68bb-488e-974e-8b89e4c8bc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032652609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3032652609
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1191354559
Short name T599
Test name
Test status
Simulation time 71347961 ps
CPU time 0.93 seconds
Started Jul 19 05:37:52 PM PDT 24
Finished Jul 19 05:37:54 PM PDT 24
Peak memory 207308 kb
Host smart-7078a5ad-1eda-4de5-9ef0-302bf712f26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191354559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1191354559
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2474068775
Short name T12
Test name
Test status
Simulation time 13169840765 ps
CPU time 21.75 seconds
Started Jul 19 05:37:56 PM PDT 24
Finished Jul 19 05:38:20 PM PDT 24
Peak memory 225084 kb
Host smart-5b1c9325-c511-4b1e-8505-75172b56eaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474068775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2474068775
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.379512935
Short name T687
Test name
Test status
Simulation time 13354029 ps
CPU time 0.72 seconds
Started Jul 19 05:38:05 PM PDT 24
Finished Jul 19 05:38:07 PM PDT 24
Peak memory 205744 kb
Host smart-4f511370-710d-4a77-b738-f71fbc1c654e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379512935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.379512935
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.587423728
Short name T527
Test name
Test status
Simulation time 3670806296 ps
CPU time 10.71 seconds
Started Jul 19 05:38:10 PM PDT 24
Finished Jul 19 05:38:22 PM PDT 24
Peak memory 233248 kb
Host smart-8c9304ea-9654-4060-bf01-1621f423afcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587423728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.587423728
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3199739238
Short name T366
Test name
Test status
Simulation time 147298456 ps
CPU time 0.76 seconds
Started Jul 19 05:37:52 PM PDT 24
Finished Jul 19 05:37:54 PM PDT 24
Peak memory 207220 kb
Host smart-78219958-2a02-4363-8a35-4d7eebc73e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199739238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3199739238
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2343101658
Short name T1005
Test name
Test status
Simulation time 12749601901 ps
CPU time 46.51 seconds
Started Jul 19 05:38:08 PM PDT 24
Finished Jul 19 05:38:55 PM PDT 24
Peak memory 249656 kb
Host smart-1fc58a5d-4a6a-4a19-a1b0-20bc16c111de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343101658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2343101658
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.564009519
Short name T56
Test name
Test status
Simulation time 35014637773 ps
CPU time 154.21 seconds
Started Jul 19 05:38:02 PM PDT 24
Finished Jul 19 05:40:38 PM PDT 24
Peak memory 257916 kb
Host smart-bb7811f2-6560-4f1e-8524-565c50720f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564009519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.564009519
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.696879565
Short name T377
Test name
Test status
Simulation time 248355515 ps
CPU time 3.87 seconds
Started Jul 19 05:38:01 PM PDT 24
Finished Jul 19 05:38:07 PM PDT 24
Peak memory 233092 kb
Host smart-22cba1ab-e3d5-4a8c-8683-700840307f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696879565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.696879565
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1767080475
Short name T193
Test name
Test status
Simulation time 3032015710 ps
CPU time 52.11 seconds
Started Jul 19 05:38:10 PM PDT 24
Finished Jul 19 05:39:03 PM PDT 24
Peak memory 249664 kb
Host smart-19d8d9b3-6701-4101-8363-aa3ba61bcb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767080475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1767080475
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2605285654
Short name T1007
Test name
Test status
Simulation time 250783776 ps
CPU time 3.26 seconds
Started Jul 19 05:38:02 PM PDT 24
Finished Jul 19 05:38:07 PM PDT 24
Peak memory 233084 kb
Host smart-b5010bb5-bf0e-4351-9133-856ae0925625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605285654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2605285654
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1069071445
Short name T426
Test name
Test status
Simulation time 347721018 ps
CPU time 6.9 seconds
Started Jul 19 05:38:02 PM PDT 24
Finished Jul 19 05:38:11 PM PDT 24
Peak memory 233184 kb
Host smart-61866b0e-2399-48b4-a289-4162f755d27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069071445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1069071445
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3249551428
Short name T40
Test name
Test status
Simulation time 245884726 ps
CPU time 3.98 seconds
Started Jul 19 05:38:04 PM PDT 24
Finished Jul 19 05:38:09 PM PDT 24
Peak memory 225008 kb
Host smart-e9ebcce1-f01e-4527-ab90-3338c8c8ae05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249551428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3249551428
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.4114854767
Short name T821
Test name
Test status
Simulation time 58011284 ps
CPU time 2.37 seconds
Started Jul 19 05:38:05 PM PDT 24
Finished Jul 19 05:38:09 PM PDT 24
Peak memory 232856 kb
Host smart-b5ba01ae-88fa-4753-a370-16ef7cb54fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114854767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4114854767
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1208251568
Short name T391
Test name
Test status
Simulation time 587037541 ps
CPU time 12.2 seconds
Started Jul 19 05:38:02 PM PDT 24
Finished Jul 19 05:38:16 PM PDT 24
Peak memory 219568 kb
Host smart-02356566-6543-43cc-9d29-e05d6686d2e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1208251568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1208251568
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2612570324
Short name T1012
Test name
Test status
Simulation time 31015045586 ps
CPU time 203.86 seconds
Started Jul 19 05:38:01 PM PDT 24
Finished Jul 19 05:41:27 PM PDT 24
Peak memory 265336 kb
Host smart-2168b93b-d2ef-4a52-93f8-928af88e8676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612570324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2612570324
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.79124589
Short name T492
Test name
Test status
Simulation time 9754635497 ps
CPU time 40.67 seconds
Started Jul 19 05:38:01 PM PDT 24
Finished Jul 19 05:38:44 PM PDT 24
Peak memory 216740 kb
Host smart-8540fa3d-2396-4e73-8b5b-89c1c62acf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79124589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.79124589
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2678478142
Short name T578
Test name
Test status
Simulation time 8683690072 ps
CPU time 7.45 seconds
Started Jul 19 05:38:07 PM PDT 24
Finished Jul 19 05:38:15 PM PDT 24
Peak memory 216812 kb
Host smart-9ee3780f-7171-4c4e-9c46-c64e93c8933e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678478142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2678478142
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2879943412
Short name T608
Test name
Test status
Simulation time 59312954 ps
CPU time 0.85 seconds
Started Jul 19 05:38:09 PM PDT 24
Finished Jul 19 05:38:11 PM PDT 24
Peak memory 206872 kb
Host smart-c8eb42c7-b7ce-457d-8364-e986015953ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879943412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2879943412
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1946203176
Short name T993
Test name
Test status
Simulation time 184688794 ps
CPU time 0.9 seconds
Started Jul 19 05:38:02 PM PDT 24
Finished Jul 19 05:38:05 PM PDT 24
Peak memory 207316 kb
Host smart-2293251a-e90b-4bb6-803a-5cc015ffae6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946203176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1946203176
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.461213286
Short name T976
Test name
Test status
Simulation time 5726875461 ps
CPU time 11.51 seconds
Started Jul 19 05:38:01 PM PDT 24
Finished Jul 19 05:38:14 PM PDT 24
Peak memory 233264 kb
Host smart-368306a6-de94-45e3-b5de-323f3d870d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461213286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.461213286
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1150025436
Short name T744
Test name
Test status
Simulation time 16654821 ps
CPU time 0.7 seconds
Started Jul 19 05:38:09 PM PDT 24
Finished Jul 19 05:38:11 PM PDT 24
Peak memory 205764 kb
Host smart-ef6c7da8-1f97-4f9f-a858-b658ce85aace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150025436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1150025436
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.4273698740
Short name T558
Test name
Test status
Simulation time 1951366389 ps
CPU time 2.58 seconds
Started Jul 19 05:38:10 PM PDT 24
Finished Jul 19 05:38:14 PM PDT 24
Peak memory 224948 kb
Host smart-08fd4e58-0cc6-4356-9444-a1742d6857f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273698740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4273698740
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1557056168
Short name T1025
Test name
Test status
Simulation time 18221592 ps
CPU time 0.84 seconds
Started Jul 19 05:38:01 PM PDT 24
Finished Jul 19 05:38:03 PM PDT 24
Peak memory 207148 kb
Host smart-0a338c67-36e0-42ef-8ba7-9c3ba4738e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557056168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1557056168
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2333846984
Short name T313
Test name
Test status
Simulation time 32129106111 ps
CPU time 207.38 seconds
Started Jul 19 05:38:08 PM PDT 24
Finished Jul 19 05:41:37 PM PDT 24
Peak memory 241492 kb
Host smart-2e87925c-8d96-43f5-93a0-f6507b9a20b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333846984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2333846984
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1760150787
Short name T1000
Test name
Test status
Simulation time 22589630730 ps
CPU time 68.14 seconds
Started Jul 19 05:38:10 PM PDT 24
Finished Jul 19 05:39:19 PM PDT 24
Peak memory 252116 kb
Host smart-d47ddb3b-8a12-409e-9e0e-931dca6292c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760150787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1760150787
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.4065889321
Short name T555
Test name
Test status
Simulation time 370977793166 ps
CPU time 225.59 seconds
Started Jul 19 05:38:11 PM PDT 24
Finished Jul 19 05:41:58 PM PDT 24
Peak memory 252340 kb
Host smart-27698729-d961-4f15-9e8c-0e2b26fe83a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065889321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.4065889321
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1122602448
Short name T392
Test name
Test status
Simulation time 82204382 ps
CPU time 3.14 seconds
Started Jul 19 05:38:12 PM PDT 24
Finished Jul 19 05:38:16 PM PDT 24
Peak memory 233112 kb
Host smart-71cf49d8-059a-48e3-b3eb-4db435d09a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122602448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1122602448
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1574252311
Short name T304
Test name
Test status
Simulation time 15652728687 ps
CPU time 114.03 seconds
Started Jul 19 05:38:11 PM PDT 24
Finished Jul 19 05:40:06 PM PDT 24
Peak memory 254308 kb
Host smart-aeeecd04-e7fb-45f3-b29a-d09ee03c8bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574252311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1574252311
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4049925355
Short name T240
Test name
Test status
Simulation time 12771092094 ps
CPU time 30.29 seconds
Started Jul 19 05:38:11 PM PDT 24
Finished Jul 19 05:38:43 PM PDT 24
Peak memory 233256 kb
Host smart-c06b5102-c4cc-4879-883b-22f41057a155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049925355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4049925355
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2022824904
Short name T183
Test name
Test status
Simulation time 1949660731 ps
CPU time 2.69 seconds
Started Jul 19 05:38:04 PM PDT 24
Finished Jul 19 05:38:08 PM PDT 24
Peak memory 224932 kb
Host smart-3eaf4691-f6f1-4e29-8cdf-6c0e37bbd64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022824904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2022824904
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1446355981
Short name T475
Test name
Test status
Simulation time 19256692446 ps
CPU time 15.13 seconds
Started Jul 19 05:38:10 PM PDT 24
Finished Jul 19 05:38:26 PM PDT 24
Peak memory 233240 kb
Host smart-26e9084d-8314-4004-a61c-2c73bfa8fcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446355981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1446355981
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2224839043
Short name T870
Test name
Test status
Simulation time 6882203755 ps
CPU time 11.79 seconds
Started Jul 19 05:38:02 PM PDT 24
Finished Jul 19 05:38:16 PM PDT 24
Peak memory 233284 kb
Host smart-6eb2237b-3d63-460d-9045-f025489e054a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224839043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2224839043
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.738437143
Short name T481
Test name
Test status
Simulation time 5464742641 ps
CPU time 8.54 seconds
Started Jul 19 05:38:12 PM PDT 24
Finished Jul 19 05:38:21 PM PDT 24
Peak memory 223548 kb
Host smart-ed54c3c4-7522-42a2-9c3a-9c26a502f007
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=738437143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.738437143
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2736097096
Short name T755
Test name
Test status
Simulation time 152401827 ps
CPU time 1.02 seconds
Started Jul 19 05:38:09 PM PDT 24
Finished Jul 19 05:38:11 PM PDT 24
Peak memory 207176 kb
Host smart-6b91e717-d922-45df-942c-69f30d951998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736097096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2736097096
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1460602173
Short name T863
Test name
Test status
Simulation time 1793013778 ps
CPU time 13.55 seconds
Started Jul 19 05:38:07 PM PDT 24
Finished Jul 19 05:38:22 PM PDT 24
Peak memory 216736 kb
Host smart-5afc7c54-1d07-4db8-8e28-77498fdd19f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460602173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1460602173
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3731344033
Short name T789
Test name
Test status
Simulation time 4108469428 ps
CPU time 5.35 seconds
Started Jul 19 05:38:08 PM PDT 24
Finished Jul 19 05:38:14 PM PDT 24
Peak memory 216744 kb
Host smart-004636d9-0f7f-4b4a-bf51-81240904c91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731344033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3731344033
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2345556834
Short name T489
Test name
Test status
Simulation time 82636429 ps
CPU time 1.21 seconds
Started Jul 19 05:38:00 PM PDT 24
Finished Jul 19 05:38:03 PM PDT 24
Peak memory 208344 kb
Host smart-230695f9-63cf-4136-a36b-c560db51f99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345556834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2345556834
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3397263852
Short name T659
Test name
Test status
Simulation time 34790324 ps
CPU time 0.83 seconds
Started Jul 19 05:38:01 PM PDT 24
Finished Jul 19 05:38:04 PM PDT 24
Peak memory 206272 kb
Host smart-4f530ab7-36ea-4837-ba7d-45f6826f6787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397263852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3397263852
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1527996450
Short name T506
Test name
Test status
Simulation time 13849153896 ps
CPU time 17 seconds
Started Jul 19 05:38:10 PM PDT 24
Finished Jul 19 05:38:28 PM PDT 24
Peak memory 248896 kb
Host smart-1cdcd727-64dc-4a47-adb1-415ccc547083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527996450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1527996450
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2208175168
Short name T399
Test name
Test status
Simulation time 22131161 ps
CPU time 0.72 seconds
Started Jul 19 05:38:19 PM PDT 24
Finished Jul 19 05:38:20 PM PDT 24
Peak memory 205820 kb
Host smart-2e39480e-b2f6-4f53-afa2-c38170a3dfb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208175168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2208175168
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.829302910
Short name T950
Test name
Test status
Simulation time 1582620995 ps
CPU time 5.69 seconds
Started Jul 19 05:38:20 PM PDT 24
Finished Jul 19 05:38:27 PM PDT 24
Peak memory 224820 kb
Host smart-bee1d295-46d6-4a8e-8c4f-2b885704f776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829302910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.829302910
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3159129079
Short name T482
Test name
Test status
Simulation time 35734185 ps
CPU time 0.76 seconds
Started Jul 19 05:38:09 PM PDT 24
Finished Jul 19 05:38:11 PM PDT 24
Peak memory 206868 kb
Host smart-881ca7df-8000-45a7-90d8-01a1fad3b95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159129079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3159129079
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2741859325
Short name T881
Test name
Test status
Simulation time 9964349120 ps
CPU time 44.71 seconds
Started Jul 19 05:38:20 PM PDT 24
Finished Jul 19 05:39:06 PM PDT 24
Peak memory 254700 kb
Host smart-2a2fc1cd-544d-408f-8bc7-55d8e0c58244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741859325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2741859325
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4169656780
Short name T241
Test name
Test status
Simulation time 87866660434 ps
CPU time 464.09 seconds
Started Jul 19 05:38:19 PM PDT 24
Finished Jul 19 05:46:05 PM PDT 24
Peak memory 258080 kb
Host smart-d5ff6d6b-5e82-4e43-b416-be8a4126d29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169656780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4169656780
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.525753500
Short name T30
Test name
Test status
Simulation time 10218542278 ps
CPU time 128.22 seconds
Started Jul 19 05:38:17 PM PDT 24
Finished Jul 19 05:40:26 PM PDT 24
Peak memory 249704 kb
Host smart-e118b1a4-b09a-4dd9-bd45-a1cd85e4657a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525753500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.525753500
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3787425700
Short name T153
Test name
Test status
Simulation time 1323546915 ps
CPU time 22.44 seconds
Started Jul 19 05:38:19 PM PDT 24
Finished Jul 19 05:38:43 PM PDT 24
Peak memory 233128 kb
Host smart-fa913196-d854-457b-9e01-888a030fdd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787425700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3787425700
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.963736411
Short name T219
Test name
Test status
Simulation time 12550849767 ps
CPU time 132.94 seconds
Started Jul 19 05:38:18 PM PDT 24
Finished Jul 19 05:40:32 PM PDT 24
Peak memory 254488 kb
Host smart-d8c817dc-3d5f-469b-85ac-fb98dffa8263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963736411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.963736411
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3644507930
Short name T843
Test name
Test status
Simulation time 100007121 ps
CPU time 2.14 seconds
Started Jul 19 05:38:11 PM PDT 24
Finished Jul 19 05:38:14 PM PDT 24
Peak memory 223612 kb
Host smart-26c0e272-8abc-4cbd-a206-8147bbef6f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644507930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3644507930
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.284863195
Short name T258
Test name
Test status
Simulation time 10207261877 ps
CPU time 20.63 seconds
Started Jul 19 05:38:09 PM PDT 24
Finished Jul 19 05:38:31 PM PDT 24
Peak memory 233284 kb
Host smart-b759378a-f6ad-49b2-b974-38c7e4eec9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284863195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.284863195
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.604670807
Short name T280
Test name
Test status
Simulation time 5548408607 ps
CPU time 6.94 seconds
Started Jul 19 05:38:10 PM PDT 24
Finished Jul 19 05:38:18 PM PDT 24
Peak memory 225044 kb
Host smart-255a8c7d-5ef8-4530-bb92-d23382585af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604670807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.604670807
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2113416404
Short name T851
Test name
Test status
Simulation time 7793022695 ps
CPU time 15.19 seconds
Started Jul 19 05:38:11 PM PDT 24
Finished Jul 19 05:38:27 PM PDT 24
Peak memory 241128 kb
Host smart-9b8c54b3-ce98-4a99-bdb2-090de7973aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113416404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2113416404
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2388888332
Short name T520
Test name
Test status
Simulation time 5333747120 ps
CPU time 10.16 seconds
Started Jul 19 05:38:18 PM PDT 24
Finished Jul 19 05:38:29 PM PDT 24
Peak memory 222036 kb
Host smart-22dd6369-c79a-4a2e-9539-ba85bc1c8802
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2388888332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2388888332
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3491423507
Short name T916
Test name
Test status
Simulation time 9180449688 ps
CPU time 69.65 seconds
Started Jul 19 05:38:20 PM PDT 24
Finished Jul 19 05:39:31 PM PDT 24
Peak memory 266104 kb
Host smart-ae8c0782-e979-4015-b319-ff868d880096
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491423507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3491423507
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1419170084
Short name T899
Test name
Test status
Simulation time 12644768095 ps
CPU time 33.29 seconds
Started Jul 19 05:38:08 PM PDT 24
Finished Jul 19 05:38:43 PM PDT 24
Peak memory 216808 kb
Host smart-a0c29177-b360-4873-b03b-3212e90a9030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419170084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1419170084
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1077851373
Short name T915
Test name
Test status
Simulation time 1739648403 ps
CPU time 5.71 seconds
Started Jul 19 05:38:08 PM PDT 24
Finished Jul 19 05:38:15 PM PDT 24
Peak memory 216656 kb
Host smart-6a46dda5-8603-46c8-8999-10890ff4e7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077851373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1077851373
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3943121257
Short name T424
Test name
Test status
Simulation time 30376008 ps
CPU time 0.77 seconds
Started Jul 19 05:38:08 PM PDT 24
Finished Jul 19 05:38:10 PM PDT 24
Peak memory 205928 kb
Host smart-d243766f-3f16-44fe-bd6f-d9dd2fa4cfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943121257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3943121257
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.814849093
Short name T551
Test name
Test status
Simulation time 54923238 ps
CPU time 0.99 seconds
Started Jul 19 05:38:09 PM PDT 24
Finished Jul 19 05:38:11 PM PDT 24
Peak memory 206484 kb
Host smart-c79c8866-fd5a-4ade-a21d-e8b0f5176fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814849093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.814849093
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.137892136
Short name T431
Test name
Test status
Simulation time 17721463545 ps
CPU time 14.95 seconds
Started Jul 19 05:38:18 PM PDT 24
Finished Jul 19 05:38:34 PM PDT 24
Peak memory 233224 kb
Host smart-c24a4dfe-261c-42a9-a328-58d3496a22db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137892136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.137892136
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2094073588
Short name T565
Test name
Test status
Simulation time 11581815 ps
CPU time 0.7 seconds
Started Jul 19 05:38:31 PM PDT 24
Finished Jul 19 05:38:33 PM PDT 24
Peak memory 205756 kb
Host smart-49342d53-adbb-47dc-9be6-981d801019ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094073588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2094073588
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.4038446860
Short name T825
Test name
Test status
Simulation time 252478704 ps
CPU time 2.86 seconds
Started Jul 19 05:38:19 PM PDT 24
Finished Jul 19 05:38:23 PM PDT 24
Peak memory 224892 kb
Host smart-06ef38b8-ee9b-47d1-91f4-d8794c63b04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038446860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.4038446860
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1621500990
Short name T1023
Test name
Test status
Simulation time 38635500 ps
CPU time 0.75 seconds
Started Jul 19 05:38:19 PM PDT 24
Finished Jul 19 05:38:21 PM PDT 24
Peak memory 207212 kb
Host smart-8cc71ad6-3129-4970-a597-ee9e29527904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621500990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1621500990
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.611470173
Short name T400
Test name
Test status
Simulation time 31575687828 ps
CPU time 182.45 seconds
Started Jul 19 05:38:19 PM PDT 24
Finished Jul 19 05:41:23 PM PDT 24
Peak memory 249664 kb
Host smart-0c09a8e8-5cc9-422e-a7fc-19ac231fc2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611470173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.611470173
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2742918534
Short name T985
Test name
Test status
Simulation time 25625413381 ps
CPU time 209.42 seconds
Started Jul 19 05:38:27 PM PDT 24
Finished Jul 19 05:41:58 PM PDT 24
Peak memory 250732 kb
Host smart-8d35391f-aad8-469f-8a55-e3f813124f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742918534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2742918534
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.715787043
Short name T598
Test name
Test status
Simulation time 33192196109 ps
CPU time 109.89 seconds
Started Jul 19 05:38:31 PM PDT 24
Finished Jul 19 05:40:22 PM PDT 24
Peak memory 239448 kb
Host smart-734e137b-2112-43a0-8102-8d8fc82f6f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715787043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.715787043
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2964035411
Short name T595
Test name
Test status
Simulation time 5460742253 ps
CPU time 54.49 seconds
Started Jul 19 05:38:16 PM PDT 24
Finished Jul 19 05:39:11 PM PDT 24
Peak memory 233352 kb
Host smart-391948bd-c017-4880-b0ac-5c8a314f4ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964035411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2964035411
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2989823269
Short name T808
Test name
Test status
Simulation time 16483784404 ps
CPU time 123.09 seconds
Started Jul 19 05:38:19 PM PDT 24
Finished Jul 19 05:40:24 PM PDT 24
Peak memory 250684 kb
Host smart-b57012da-4953-49c6-a6d7-a349ca22117b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989823269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2989823269
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2179543402
Short name T50
Test name
Test status
Simulation time 5865776552 ps
CPU time 15.4 seconds
Started Jul 19 05:38:16 PM PDT 24
Finished Jul 19 05:38:33 PM PDT 24
Peak memory 233248 kb
Host smart-e131e8ac-d505-4599-8056-54cde8d47cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179543402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2179543402
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1762733915
Short name T374
Test name
Test status
Simulation time 107381814 ps
CPU time 2.38 seconds
Started Jul 19 05:38:20 PM PDT 24
Finished Jul 19 05:38:24 PM PDT 24
Peak memory 223348 kb
Host smart-0c243f1c-9951-48cb-88fa-1201066809b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762733915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1762733915
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3836659093
Short name T576
Test name
Test status
Simulation time 140445004 ps
CPU time 2.19 seconds
Started Jul 19 05:38:17 PM PDT 24
Finished Jul 19 05:38:20 PM PDT 24
Peak memory 224912 kb
Host smart-0bc111f4-819d-4e57-b60a-2f51b11599e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836659093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3836659093
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3772322218
Short name T971
Test name
Test status
Simulation time 33548935 ps
CPU time 2.4 seconds
Started Jul 19 05:38:21 PM PDT 24
Finished Jul 19 05:38:24 PM PDT 24
Peak memory 233108 kb
Host smart-a556b6f6-5484-44bd-a53a-7e3e5d281d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772322218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3772322218
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2730488921
Short name T621
Test name
Test status
Simulation time 556776096 ps
CPU time 3.38 seconds
Started Jul 19 05:38:18 PM PDT 24
Finished Jul 19 05:38:23 PM PDT 24
Peak memory 220588 kb
Host smart-dedbdd49-ab3f-4a2f-8eb9-9439fa4256d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2730488921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2730488921
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2601559260
Short name T498
Test name
Test status
Simulation time 11251680680 ps
CPU time 78.23 seconds
Started Jul 19 05:38:27 PM PDT 24
Finished Jul 19 05:39:46 PM PDT 24
Peak memory 257236 kb
Host smart-f5787229-78ba-4560-955a-b3fd6ccc055a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601559260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2601559260
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.140636673
Short name T784
Test name
Test status
Simulation time 2202350651 ps
CPU time 11.09 seconds
Started Jul 19 05:38:19 PM PDT 24
Finished Jul 19 05:38:31 PM PDT 24
Peak memory 216808 kb
Host smart-ccd17ec6-55c5-4a99-9cae-4902c712233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140636673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.140636673
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3315771194
Short name T796
Test name
Test status
Simulation time 3020047159 ps
CPU time 5.67 seconds
Started Jul 19 05:38:17 PM PDT 24
Finished Jul 19 05:38:23 PM PDT 24
Peak memory 216848 kb
Host smart-0437f952-4d6a-48da-82c6-32ce71443e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315771194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3315771194
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4172047618
Short name T601
Test name
Test status
Simulation time 446536087 ps
CPU time 1.8 seconds
Started Jul 19 05:38:18 PM PDT 24
Finished Jul 19 05:38:21 PM PDT 24
Peak memory 216552 kb
Host smart-f8120e52-28b8-4c6b-9d07-451bd4bd4389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172047618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4172047618
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1985090717
Short name T347
Test name
Test status
Simulation time 53611751 ps
CPU time 0.83 seconds
Started Jul 19 05:38:19 PM PDT 24
Finished Jul 19 05:38:22 PM PDT 24
Peak memory 206428 kb
Host smart-8c9b0133-c4ea-404e-9079-1eb6df4fbc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985090717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1985090717
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3904210916
Short name T766
Test name
Test status
Simulation time 7670435139 ps
CPU time 10.69 seconds
Started Jul 19 05:38:19 PM PDT 24
Finished Jul 19 05:38:31 PM PDT 24
Peak memory 240776 kb
Host smart-e8d9461a-614c-488f-b28f-a6e136483b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904210916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3904210916
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2320462677
Short name T898
Test name
Test status
Simulation time 20697478 ps
CPU time 0.71 seconds
Started Jul 19 05:38:26 PM PDT 24
Finished Jul 19 05:38:28 PM PDT 24
Peak memory 205756 kb
Host smart-9a7c6177-80d6-4d8c-b4d8-3c0f25c31082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320462677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2320462677
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.4165757167
Short name T92
Test name
Test status
Simulation time 146398523 ps
CPU time 4.02 seconds
Started Jul 19 05:38:28 PM PDT 24
Finished Jul 19 05:38:34 PM PDT 24
Peak memory 224964 kb
Host smart-0d71e90f-45ac-411d-8062-9e02d3504a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165757167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.4165757167
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.375177936
Short name T76
Test name
Test status
Simulation time 49931209 ps
CPU time 0.77 seconds
Started Jul 19 05:38:28 PM PDT 24
Finished Jul 19 05:38:30 PM PDT 24
Peak memory 206884 kb
Host smart-9f41d692-9d65-4adb-aa93-1603764a1dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375177936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.375177936
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3575416513
Short name T282
Test name
Test status
Simulation time 56310191266 ps
CPU time 113.24 seconds
Started Jul 19 05:38:29 PM PDT 24
Finished Jul 19 05:40:24 PM PDT 24
Peak memory 255784 kb
Host smart-5d329c40-aca2-4fab-92da-9c5613a3c70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575416513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3575416513
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1312649416
Short name T1015
Test name
Test status
Simulation time 20365643354 ps
CPU time 87.38 seconds
Started Jul 19 05:38:30 PM PDT 24
Finished Jul 19 05:39:59 PM PDT 24
Peak memory 257464 kb
Host smart-83bc1fe4-b4d9-4845-b915-b99a1e8fbe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312649416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1312649416
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2136375386
Short name T146
Test name
Test status
Simulation time 39626464995 ps
CPU time 171.45 seconds
Started Jul 19 05:38:29 PM PDT 24
Finished Jul 19 05:41:23 PM PDT 24
Peak memory 265164 kb
Host smart-8cdc464b-142b-442e-8a29-926d5feeb296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136375386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2136375386
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1002146076
Short name T840
Test name
Test status
Simulation time 16480142 ps
CPU time 0.75 seconds
Started Jul 19 05:38:29 PM PDT 24
Finished Jul 19 05:38:32 PM PDT 24
Peak memory 216252 kb
Host smart-dfdc52d3-9ec0-4ba7-aa16-09b9176d2b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002146076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1002146076
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3287288484
Short name T267
Test name
Test status
Simulation time 1207912776 ps
CPU time 3.61 seconds
Started Jul 19 05:38:26 PM PDT 24
Finished Jul 19 05:38:31 PM PDT 24
Peak memory 224868 kb
Host smart-f5dc86da-d5d3-41af-b892-e391d4148fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287288484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3287288484
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.970130215
Short name T657
Test name
Test status
Simulation time 30333443 ps
CPU time 2.12 seconds
Started Jul 19 05:38:26 PM PDT 24
Finished Jul 19 05:38:30 PM PDT 24
Peak memory 224980 kb
Host smart-6661b378-4b9c-4a71-a52b-63a2ea85766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970130215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.970130215
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.951225741
Short name T275
Test name
Test status
Simulation time 3386020674 ps
CPU time 6.24 seconds
Started Jul 19 05:38:29 PM PDT 24
Finished Jul 19 05:38:37 PM PDT 24
Peak memory 233308 kb
Host smart-88e5a2de-7dc9-467d-9214-ea6299036121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951225741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.951225741
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2593037471
Short name T211
Test name
Test status
Simulation time 19751504608 ps
CPU time 28.19 seconds
Started Jul 19 05:38:28 PM PDT 24
Finished Jul 19 05:38:58 PM PDT 24
Peak memory 233208 kb
Host smart-846b805c-5e35-4ef5-bc0e-979fd9233963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593037471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2593037471
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.369883808
Short name T609
Test name
Test status
Simulation time 1554779965 ps
CPU time 11.94 seconds
Started Jul 19 05:38:26 PM PDT 24
Finished Jul 19 05:38:39 PM PDT 24
Peak memory 219576 kb
Host smart-35472484-96db-4ada-86b9-af512a495e9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=369883808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.369883808
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2285691792
Short name T314
Test name
Test status
Simulation time 119216133147 ps
CPU time 692.38 seconds
Started Jul 19 05:38:28 PM PDT 24
Finished Jul 19 05:50:02 PM PDT 24
Peak memory 270960 kb
Host smart-ab6b9831-5db5-421a-9dc0-ca41058f1d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285691792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2285691792
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1893975966
Short name T360
Test name
Test status
Simulation time 141945024 ps
CPU time 2.29 seconds
Started Jul 19 05:38:27 PM PDT 24
Finished Jul 19 05:38:31 PM PDT 24
Peak memory 216820 kb
Host smart-190f9ebc-bd96-48e9-a43e-7ad88879ec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893975966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1893975966
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2174826060
Short name T811
Test name
Test status
Simulation time 11931757 ps
CPU time 0.7 seconds
Started Jul 19 05:38:29 PM PDT 24
Finished Jul 19 05:38:32 PM PDT 24
Peak memory 205992 kb
Host smart-0c7ac9c3-6d82-4496-895f-6ca2341d7c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174826060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2174826060
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.757450998
Short name T958
Test name
Test status
Simulation time 453644864 ps
CPU time 4.46 seconds
Started Jul 19 05:38:26 PM PDT 24
Finished Jul 19 05:38:31 PM PDT 24
Peak memory 216652 kb
Host smart-b9fe8886-a3eb-4e27-81ec-95c278e48f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757450998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.757450998
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.8132767
Short name T349
Test name
Test status
Simulation time 199757228 ps
CPU time 0.84 seconds
Started Jul 19 05:38:27 PM PDT 24
Finished Jul 19 05:38:29 PM PDT 24
Peak memory 206280 kb
Host smart-5f67ac42-b374-46f9-b3e1-cd6ed9b52544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8132767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.8132767
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1780059699
Short name T671
Test name
Test status
Simulation time 3849020619 ps
CPU time 7.67 seconds
Started Jul 19 05:38:29 PM PDT 24
Finished Jul 19 05:38:38 PM PDT 24
Peak memory 225020 kb
Host smart-96f525b1-72ac-4721-800c-ca4dbe9c29f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780059699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1780059699
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.809905373
Short name T460
Test name
Test status
Simulation time 33725511 ps
CPU time 0.73 seconds
Started Jul 19 05:38:40 PM PDT 24
Finished Jul 19 05:38:42 PM PDT 24
Peak memory 206064 kb
Host smart-d6d48b9f-6c24-4bf5-b4fa-630cff69fcde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809905373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.809905373
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.184296598
Short name T198
Test name
Test status
Simulation time 104204682 ps
CPU time 2.63 seconds
Started Jul 19 05:38:26 PM PDT 24
Finished Jul 19 05:38:30 PM PDT 24
Peak memory 224884 kb
Host smart-b3bb0323-2f0c-48c8-bc5c-77c629446727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184296598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.184296598
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.665047298
Short name T938
Test name
Test status
Simulation time 63542319 ps
CPU time 0.76 seconds
Started Jul 19 05:38:25 PM PDT 24
Finished Jul 19 05:38:27 PM PDT 24
Peak memory 206200 kb
Host smart-6ba6f7a7-bc52-4c89-9c33-e5640df84171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665047298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.665047298
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2879813502
Short name T55
Test name
Test status
Simulation time 18491976628 ps
CPU time 39.6 seconds
Started Jul 19 05:38:28 PM PDT 24
Finished Jul 19 05:39:09 PM PDT 24
Peak memory 251576 kb
Host smart-a3184289-7d84-41ab-ade8-3904ff98a0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879813502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2879813502
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2511225785
Short name T584
Test name
Test status
Simulation time 863668772 ps
CPU time 4.5 seconds
Started Jul 19 05:38:28 PM PDT 24
Finished Jul 19 05:38:34 PM PDT 24
Peak memory 222880 kb
Host smart-d66df7d1-eb98-40d3-86d8-4f2f0c680405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511225785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2511225785
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.595862646
Short name T783
Test name
Test status
Simulation time 4628250449 ps
CPU time 46.04 seconds
Started Jul 19 05:38:27 PM PDT 24
Finished Jul 19 05:39:14 PM PDT 24
Peak memory 233336 kb
Host smart-36ed4c9d-3390-454f-864f-f8faaef4b451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595862646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.595862646
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.507399858
Short name T679
Test name
Test status
Simulation time 81076137 ps
CPU time 4.6 seconds
Started Jul 19 05:38:31 PM PDT 24
Finished Jul 19 05:38:37 PM PDT 24
Peak memory 241276 kb
Host smart-3f50c4fb-54e1-45bc-984d-8b8ae3178b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507399858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.507399858
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.517696367
Short name T839
Test name
Test status
Simulation time 49316797683 ps
CPU time 93.31 seconds
Started Jul 19 05:38:27 PM PDT 24
Finished Jul 19 05:40:02 PM PDT 24
Peak memory 249692 kb
Host smart-c88b3173-91f4-4ba7-ab52-fb31f2dfc433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517696367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.517696367
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2718330710
Short name T457
Test name
Test status
Simulation time 327125566 ps
CPU time 6.64 seconds
Started Jul 19 05:38:28 PM PDT 24
Finished Jul 19 05:38:37 PM PDT 24
Peak memory 233188 kb
Host smart-4a39e07f-2399-47ba-82c3-f6e8ea88757b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718330710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2718330710
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2234321439
Short name T733
Test name
Test status
Simulation time 1260803583 ps
CPU time 14.37 seconds
Started Jul 19 05:38:29 PM PDT 24
Finished Jul 19 05:38:45 PM PDT 24
Peak memory 241280 kb
Host smart-f56627d7-bbcc-44ea-9c08-79e09a3c9d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234321439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2234321439
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2898448765
Short name T596
Test name
Test status
Simulation time 359056776 ps
CPU time 2.2 seconds
Started Jul 19 05:38:29 PM PDT 24
Finished Jul 19 05:38:33 PM PDT 24
Peak memory 224888 kb
Host smart-0d807a3c-fe52-435e-9036-2850a5a26bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898448765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2898448765
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1122474582
Short name T119
Test name
Test status
Simulation time 1263051511 ps
CPU time 4.95 seconds
Started Jul 19 05:38:27 PM PDT 24
Finished Jul 19 05:38:34 PM PDT 24
Peak memory 233068 kb
Host smart-5c3d16d4-9d01-4777-844b-e5710641dbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122474582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1122474582
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1041479003
Short name T465
Test name
Test status
Simulation time 443111353 ps
CPU time 5.74 seconds
Started Jul 19 05:38:27 PM PDT 24
Finished Jul 19 05:38:34 PM PDT 24
Peak memory 223464 kb
Host smart-47a6913a-f4dc-49b9-8ba1-b7021439f296
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1041479003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1041479003
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3948264134
Short name T169
Test name
Test status
Simulation time 302057768 ps
CPU time 0.98 seconds
Started Jul 19 05:38:38 PM PDT 24
Finished Jul 19 05:38:40 PM PDT 24
Peak memory 207244 kb
Host smart-a96a77cb-b7e2-4231-b247-3edf2fa29ee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948264134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3948264134
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4264519736
Short name T889
Test name
Test status
Simulation time 54879852 ps
CPU time 0.72 seconds
Started Jul 19 05:38:28 PM PDT 24
Finished Jul 19 05:38:31 PM PDT 24
Peak memory 206036 kb
Host smart-b954b641-bb2f-43a9-bac2-af3fe35a4b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264519736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4264519736
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.782368278
Short name T499
Test name
Test status
Simulation time 3025861111 ps
CPU time 6.85 seconds
Started Jul 19 05:38:28 PM PDT 24
Finished Jul 19 05:38:36 PM PDT 24
Peak memory 216796 kb
Host smart-6169535b-c256-41b9-8917-c40a352be793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782368278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.782368278
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.193108007
Short name T503
Test name
Test status
Simulation time 179906312 ps
CPU time 2.65 seconds
Started Jul 19 05:38:27 PM PDT 24
Finished Jul 19 05:38:31 PM PDT 24
Peak memory 208364 kb
Host smart-da1539c9-acdd-4a4c-aa3e-f15e9e077b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193108007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.193108007
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1695649241
Short name T946
Test name
Test status
Simulation time 690031330 ps
CPU time 0.84 seconds
Started Jul 19 05:38:29 PM PDT 24
Finished Jul 19 05:38:32 PM PDT 24
Peak memory 206224 kb
Host smart-472119ba-24e2-458a-9242-94fe8072d6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695649241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1695649241
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3776686503
Short name T239
Test name
Test status
Simulation time 65466492379 ps
CPU time 16.11 seconds
Started Jul 19 05:38:29 PM PDT 24
Finished Jul 19 05:38:46 PM PDT 24
Peak memory 233172 kb
Host smart-c45a6db2-69e4-41e6-90c5-ed38d91a9018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776686503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3776686503
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1814100898
Short name T363
Test name
Test status
Simulation time 29188638 ps
CPU time 0.71 seconds
Started Jul 19 05:34:59 PM PDT 24
Finished Jul 19 05:36:02 PM PDT 24
Peak memory 205740 kb
Host smart-aa2b7502-c25e-4d00-bac4-7d56af601de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814100898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
814100898
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3887883603
Short name T1019
Test name
Test status
Simulation time 58722607 ps
CPU time 2.36 seconds
Started Jul 19 05:34:54 PM PDT 24
Finished Jul 19 05:35:58 PM PDT 24
Peak memory 232952 kb
Host smart-f31a53ef-017a-4f31-9654-7038b9ae6821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887883603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3887883603
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.133580292
Short name T142
Test name
Test status
Simulation time 33436726 ps
CPU time 0.76 seconds
Started Jul 19 05:34:56 PM PDT 24
Finished Jul 19 05:35:59 PM PDT 24
Peak memory 206900 kb
Host smart-522f85af-916c-466e-960f-281229dfe7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133580292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.133580292
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1466293827
Short name T181
Test name
Test status
Simulation time 6641754661 ps
CPU time 62.05 seconds
Started Jul 19 05:34:53 PM PDT 24
Finished Jul 19 05:36:58 PM PDT 24
Peak memory 256968 kb
Host smart-3afab086-ec4e-45e9-ad69-9fdcbf7c5368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466293827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1466293827
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.929623789
Short name T919
Test name
Test status
Simulation time 5110198309 ps
CPU time 81.54 seconds
Started Jul 19 05:34:55 PM PDT 24
Finished Jul 19 05:37:18 PM PDT 24
Peak memory 249684 kb
Host smart-f4a596b6-cbd3-4b3f-ad25-878096907013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929623789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
929623789
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.913142847
Short name T456
Test name
Test status
Simulation time 1105086993 ps
CPU time 9.52 seconds
Started Jul 19 05:34:53 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 220228 kb
Host smart-c502bf24-81aa-40ad-a07e-357769a34e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913142847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.913142847
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2086360237
Short name T800
Test name
Test status
Simulation time 1118373981 ps
CPU time 22.12 seconds
Started Jul 19 05:34:58 PM PDT 24
Finished Jul 19 05:36:23 PM PDT 24
Peak memory 249536 kb
Host smart-cd86ba90-b960-4846-96e5-5e7c31108089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086360237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2086360237
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3478724335
Short name T216
Test name
Test status
Simulation time 5855112943 ps
CPU time 7.75 seconds
Started Jul 19 05:34:55 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 233272 kb
Host smart-c0503b8a-ee6e-4ba9-b721-63d7d5b5f550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478724335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3478724335
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.891003454
Short name T292
Test name
Test status
Simulation time 5335316115 ps
CPU time 15.99 seconds
Started Jul 19 05:34:56 PM PDT 24
Finished Jul 19 05:36:14 PM PDT 24
Peak memory 241244 kb
Host smart-5114453b-cfcf-4f71-b5f8-b9e962962664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891003454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.891003454
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3288655008
Short name T669
Test name
Test status
Simulation time 32714357 ps
CPU time 1.09 seconds
Started Jul 19 05:34:57 PM PDT 24
Finished Jul 19 05:36:00 PM PDT 24
Peak memory 217100 kb
Host smart-826ed87e-a89a-4094-bcaf-c71a15ba935f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288655008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3288655008
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2514196984
Short name T559
Test name
Test status
Simulation time 1157979978 ps
CPU time 5.11 seconds
Started Jul 19 05:34:52 PM PDT 24
Finished Jul 19 05:35:58 PM PDT 24
Peak memory 224960 kb
Host smart-0d25f15d-fed5-4a43-b9c4-760ffb4827c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514196984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2514196984
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2888103627
Short name T972
Test name
Test status
Simulation time 2134274815 ps
CPU time 8.25 seconds
Started Jul 19 05:34:55 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 234168 kb
Host smart-e6283034-be3d-450e-bb40-e97f9cc3042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888103627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2888103627
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3891016579
Short name T395
Test name
Test status
Simulation time 3726172996 ps
CPU time 8.72 seconds
Started Jul 19 05:34:57 PM PDT 24
Finished Jul 19 05:36:07 PM PDT 24
Peak memory 220888 kb
Host smart-30c9976f-ba9e-40d6-a975-329cf4b4af0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3891016579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3891016579
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1225604399
Short name T66
Test name
Test status
Simulation time 75782959 ps
CPU time 0.97 seconds
Started Jul 19 05:34:57 PM PDT 24
Finished Jul 19 05:35:59 PM PDT 24
Peak memory 235732 kb
Host smart-7c0acf90-d25d-466a-a8c6-16779b999837
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225604399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1225604399
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1426522331
Short name T19
Test name
Test status
Simulation time 170064535 ps
CPU time 0.9 seconds
Started Jul 19 05:34:57 PM PDT 24
Finished Jul 19 05:35:59 PM PDT 24
Peak memory 206920 kb
Host smart-d7a1916f-f340-46f8-adc4-64d27035594c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426522331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1426522331
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3101635214
Short name T1027
Test name
Test status
Simulation time 993549771 ps
CPU time 10.64 seconds
Started Jul 19 05:34:58 PM PDT 24
Finished Jul 19 05:36:12 PM PDT 24
Peak memory 216976 kb
Host smart-861a72a0-598c-4aee-8fcb-b2ffff075586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101635214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3101635214
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.200500354
Short name T350
Test name
Test status
Simulation time 6376600959 ps
CPU time 9.29 seconds
Started Jul 19 05:34:55 PM PDT 24
Finished Jul 19 05:36:05 PM PDT 24
Peak memory 216832 kb
Host smart-a715de1d-7726-48b0-b7de-048e5a428f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200500354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.200500354
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2240961338
Short name T444
Test name
Test status
Simulation time 4003881130 ps
CPU time 2.76 seconds
Started Jul 19 05:34:58 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 216780 kb
Host smart-375e3eab-2833-48d9-ae51-72813fe06234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240961338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2240961338
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1843461229
Short name T87
Test name
Test status
Simulation time 1798215881 ps
CPU time 0.97 seconds
Started Jul 19 05:34:54 PM PDT 24
Finished Jul 19 05:35:57 PM PDT 24
Peak memory 206576 kb
Host smart-f359e4a7-50c8-4e3b-bd79-280dd97a036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843461229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1843461229
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2053037497
Short name T764
Test name
Test status
Simulation time 75621751 ps
CPU time 3.01 seconds
Started Jul 19 05:34:55 PM PDT 24
Finished Jul 19 05:35:59 PM PDT 24
Peak memory 233108 kb
Host smart-7f8f1690-def0-4b0a-aafe-50d36dfde760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053037497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2053037497
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3865767718
Short name T61
Test name
Test status
Simulation time 41268594 ps
CPU time 0.71 seconds
Started Jul 19 05:38:36 PM PDT 24
Finished Jul 19 05:38:38 PM PDT 24
Peak memory 205180 kb
Host smart-2e5e9819-671f-45f4-8019-7bc8c1684a24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865767718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3865767718
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1990081877
Short name T666
Test name
Test status
Simulation time 495727781 ps
CPU time 6.58 seconds
Started Jul 19 05:38:36 PM PDT 24
Finished Jul 19 05:38:44 PM PDT 24
Peak memory 233080 kb
Host smart-2181cba2-f6c6-4d0c-b6dc-a2d72d533b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990081877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1990081877
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2349699482
Short name T1018
Test name
Test status
Simulation time 51143737 ps
CPU time 0.8 seconds
Started Jul 19 05:38:37 PM PDT 24
Finished Jul 19 05:38:39 PM PDT 24
Peak memory 206864 kb
Host smart-c7e814f7-0b59-4ca8-9226-e66eb32450e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349699482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2349699482
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3149613623
Short name T753
Test name
Test status
Simulation time 995338666 ps
CPU time 23.59 seconds
Started Jul 19 05:38:36 PM PDT 24
Finished Jul 19 05:39:01 PM PDT 24
Peak memory 249552 kb
Host smart-2091370c-4bf9-43c0-8d79-c2819bfd9579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149613623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3149613623
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3378972592
Short name T299
Test name
Test status
Simulation time 66965660154 ps
CPU time 79.45 seconds
Started Jul 19 05:38:37 PM PDT 24
Finished Jul 19 05:39:58 PM PDT 24
Peak memory 234888 kb
Host smart-c3f0a455-c33a-4bd5-83ad-da8e062499cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378972592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3378972592
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.224871257
Short name T694
Test name
Test status
Simulation time 20906967 ps
CPU time 0.82 seconds
Started Jul 19 05:38:36 PM PDT 24
Finished Jul 19 05:38:38 PM PDT 24
Peak memory 217352 kb
Host smart-fbb4f9dc-9f7b-4350-9dca-fb76b51134c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224871257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.224871257
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1058508268
Short name T1024
Test name
Test status
Simulation time 125603290 ps
CPU time 6.36 seconds
Started Jul 19 05:38:36 PM PDT 24
Finished Jul 19 05:38:43 PM PDT 24
Peak memory 233128 kb
Host smart-da10c295-1e3c-4f29-8499-33119de771cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058508268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1058508268
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3013196976
Short name T994
Test name
Test status
Simulation time 6186136963 ps
CPU time 43.33 seconds
Started Jul 19 05:38:39 PM PDT 24
Finished Jul 19 05:39:23 PM PDT 24
Peak memory 237556 kb
Host smart-dbf30574-87ec-444e-a8c9-e4ec91ac87ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013196976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3013196976
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1953673145
Short name T232
Test name
Test status
Simulation time 8176554704 ps
CPU time 44.59 seconds
Started Jul 19 05:38:37 PM PDT 24
Finished Jul 19 05:39:23 PM PDT 24
Peak memory 225092 kb
Host smart-0ba74e91-3a62-4b55-a6ca-cf3bd1960cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953673145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1953673145
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1503071337
Short name T513
Test name
Test status
Simulation time 30785223 ps
CPU time 2.08 seconds
Started Jul 19 05:38:38 PM PDT 24
Finished Jul 19 05:38:41 PM PDT 24
Peak memory 224384 kb
Host smart-03c24c27-23fa-4016-b088-7e83aa24ab3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503071337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1503071337
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2048192369
Short name T286
Test name
Test status
Simulation time 57487561357 ps
CPU time 31.38 seconds
Started Jul 19 05:38:33 PM PDT 24
Finished Jul 19 05:39:05 PM PDT 24
Peak memory 233336 kb
Host smart-7ccd22fd-3aa2-4b6e-96bc-4491b844b055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048192369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2048192369
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4015963384
Short name T824
Test name
Test status
Simulation time 13395433844 ps
CPU time 9.01 seconds
Started Jul 19 05:38:34 PM PDT 24
Finished Jul 19 05:38:44 PM PDT 24
Peak memory 241000 kb
Host smart-218319e8-e475-4eaa-90ff-3d1bff3be6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015963384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4015963384
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.260756944
Short name T658
Test name
Test status
Simulation time 502869024 ps
CPU time 9.4 seconds
Started Jul 19 05:38:41 PM PDT 24
Finished Jul 19 05:38:51 PM PDT 24
Peak memory 220680 kb
Host smart-19202fef-d898-4878-b3ab-61d81aff9e65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=260756944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.260756944
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1385764840
Short name T716
Test name
Test status
Simulation time 75843969 ps
CPU time 0.94 seconds
Started Jul 19 05:38:36 PM PDT 24
Finished Jul 19 05:38:39 PM PDT 24
Peak memory 207196 kb
Host smart-755663bb-b618-4d5a-b2df-89a49fbcf76c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385764840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1385764840
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2159374286
Short name T441
Test name
Test status
Simulation time 404183252 ps
CPU time 4.96 seconds
Started Jul 19 05:38:39 PM PDT 24
Finished Jul 19 05:38:45 PM PDT 24
Peak memory 216692 kb
Host smart-4e0f617a-a61c-4bac-94e4-6965e8779410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159374286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2159374286
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1902884267
Short name T449
Test name
Test status
Simulation time 11856912075 ps
CPU time 12.11 seconds
Started Jul 19 05:38:36 PM PDT 24
Finished Jul 19 05:38:49 PM PDT 24
Peak memory 216788 kb
Host smart-ab55566e-9712-417d-bc95-62299b7b3341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902884267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1902884267
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2703221556
Short name T948
Test name
Test status
Simulation time 178115143 ps
CPU time 2.42 seconds
Started Jul 19 05:38:36 PM PDT 24
Finished Jul 19 05:38:39 PM PDT 24
Peak memory 216668 kb
Host smart-c3ace71d-1649-4cd0-8fca-5554dc148a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703221556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2703221556
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3777704428
Short name T355
Test name
Test status
Simulation time 152532944 ps
CPU time 0.88 seconds
Started Jul 19 05:38:36 PM PDT 24
Finished Jul 19 05:38:39 PM PDT 24
Peak memory 206292 kb
Host smart-43a03fd3-47d4-41dc-a7bb-0727c1729986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777704428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3777704428
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3153077000
Short name T837
Test name
Test status
Simulation time 2312357713 ps
CPU time 3.42 seconds
Started Jul 19 05:38:36 PM PDT 24
Finished Jul 19 05:38:41 PM PDT 24
Peak memory 225104 kb
Host smart-cda83c6b-e28d-49d7-a1a0-e4a88bddcbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153077000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3153077000
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3867696659
Short name T668
Test name
Test status
Simulation time 40060013 ps
CPU time 0.74 seconds
Started Jul 19 05:38:40 PM PDT 24
Finished Jul 19 05:38:42 PM PDT 24
Peak memory 205748 kb
Host smart-bd0ca1c7-07aa-406d-a25f-3809b52975d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867696659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3867696659
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1085794557
Short name T860
Test name
Test status
Simulation time 5422691311 ps
CPU time 15.76 seconds
Started Jul 19 05:38:42 PM PDT 24
Finished Jul 19 05:38:59 PM PDT 24
Peak memory 225004 kb
Host smart-d8bbda0a-9d29-444b-8fa9-dc6b1367d9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085794557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1085794557
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3972401692
Short name T834
Test name
Test status
Simulation time 50172116 ps
CPU time 0.73 seconds
Started Jul 19 05:38:36 PM PDT 24
Finished Jul 19 05:38:38 PM PDT 24
Peak memory 205860 kb
Host smart-302f58c1-765f-42d4-83cb-cd3b7b4e8219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972401692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3972401692
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2473487684
Short name T312
Test name
Test status
Simulation time 5472881048 ps
CPU time 96.79 seconds
Started Jul 19 05:38:46 PM PDT 24
Finished Jul 19 05:40:23 PM PDT 24
Peak memory 267624 kb
Host smart-1efe1e1b-d869-4382-b0ad-b145f2e751c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473487684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2473487684
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.168524015
Short name T330
Test name
Test status
Simulation time 4153891949 ps
CPU time 28.35 seconds
Started Jul 19 05:38:41 PM PDT 24
Finished Jul 19 05:39:10 PM PDT 24
Peak memory 218252 kb
Host smart-f5e3938f-03f4-4eff-8d4a-fa6ff8cda0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168524015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.168524015
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.149099292
Short name T614
Test name
Test status
Simulation time 3232737802 ps
CPU time 39.77 seconds
Started Jul 19 05:38:40 PM PDT 24
Finished Jul 19 05:39:21 PM PDT 24
Peak memory 231512 kb
Host smart-5d6c9d3b-fb97-4c03-a6e0-ee20b50a20e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149099292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.149099292
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3430123541
Short name T494
Test name
Test status
Simulation time 686223070 ps
CPU time 14.14 seconds
Started Jul 19 05:38:40 PM PDT 24
Finished Jul 19 05:38:56 PM PDT 24
Peak memory 233148 kb
Host smart-a8fda987-5caf-4404-b7bc-2b194321da54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430123541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3430123541
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3283820474
Short name T44
Test name
Test status
Simulation time 28337794499 ps
CPU time 121.61 seconds
Started Jul 19 05:38:41 PM PDT 24
Finished Jul 19 05:40:43 PM PDT 24
Peak memory 273712 kb
Host smart-d512e07d-b74e-4c4b-a38f-a9f5a412c16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283820474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3283820474
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2073980652
Short name T290
Test name
Test status
Simulation time 230663245 ps
CPU time 3.3 seconds
Started Jul 19 05:38:37 PM PDT 24
Finished Jul 19 05:38:41 PM PDT 24
Peak memory 233116 kb
Host smart-11eccfd8-0278-48f1-aad9-2599451ebafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073980652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2073980652
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1534190034
Short name T688
Test name
Test status
Simulation time 5597601326 ps
CPU time 34.42 seconds
Started Jul 19 05:38:34 PM PDT 24
Finished Jul 19 05:39:10 PM PDT 24
Peak memory 237580 kb
Host smart-4d339792-adff-42ae-a636-50af35289f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534190034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1534190034
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2232161832
Short name T1004
Test name
Test status
Simulation time 4758193328 ps
CPU time 7 seconds
Started Jul 19 05:38:37 PM PDT 24
Finished Jul 19 05:38:45 PM PDT 24
Peak memory 225040 kb
Host smart-79930446-ce7c-43d2-8ec2-9bf94de0dc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232161832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2232161832
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2558731568
Short name T429
Test name
Test status
Simulation time 10014185451 ps
CPU time 9.28 seconds
Started Jul 19 05:38:38 PM PDT 24
Finished Jul 19 05:38:48 PM PDT 24
Peak memory 225056 kb
Host smart-999b304b-43aa-45ab-8e52-feeaaac5834c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558731568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2558731568
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3091178869
Short name T852
Test name
Test status
Simulation time 652785230 ps
CPU time 3.54 seconds
Started Jul 19 05:38:40 PM PDT 24
Finished Jul 19 05:38:45 PM PDT 24
Peak memory 223596 kb
Host smart-00e3eab1-9428-41e9-a861-4e77602aab22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3091178869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3091178869
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3322956767
Short name T984
Test name
Test status
Simulation time 70603972961 ps
CPU time 173.12 seconds
Started Jul 19 05:38:42 PM PDT 24
Finished Jul 19 05:41:37 PM PDT 24
Peak memory 257836 kb
Host smart-5e147887-52f7-406e-bb6c-0706a2fa4292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322956767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3322956767
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.328635161
Short name T547
Test name
Test status
Simulation time 943564404 ps
CPU time 5.88 seconds
Started Jul 19 05:38:36 PM PDT 24
Finished Jul 19 05:38:43 PM PDT 24
Peak memory 217104 kb
Host smart-63328f43-448a-4b79-a045-f6aecadf65e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328635161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.328635161
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1271242364
Short name T471
Test name
Test status
Simulation time 1392589359 ps
CPU time 6.97 seconds
Started Jul 19 05:38:39 PM PDT 24
Finished Jul 19 05:38:47 PM PDT 24
Peak memory 216648 kb
Host smart-859655e3-943a-4920-be33-7541096d795b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271242364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1271242364
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.563342155
Short name T620
Test name
Test status
Simulation time 114663370 ps
CPU time 0.87 seconds
Started Jul 19 05:38:35 PM PDT 24
Finished Jul 19 05:38:37 PM PDT 24
Peak memory 207200 kb
Host smart-3c4dac64-fd96-4126-9e19-2907ae736cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563342155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.563342155
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2637162273
Short name T379
Test name
Test status
Simulation time 157999752 ps
CPU time 0.78 seconds
Started Jul 19 05:38:39 PM PDT 24
Finished Jul 19 05:38:41 PM PDT 24
Peak memory 206284 kb
Host smart-42c3e23e-34ab-4835-aacc-8ba3aa27c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637162273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2637162273
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4209065548
Short name T775
Test name
Test status
Simulation time 7328775101 ps
CPU time 7.32 seconds
Started Jul 19 05:38:42 PM PDT 24
Finished Jul 19 05:38:51 PM PDT 24
Peak memory 225036 kb
Host smart-b34dcf34-db25-4909-9a03-b5789550d29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209065548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4209065548
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1872968211
Short name T724
Test name
Test status
Simulation time 12454053 ps
CPU time 0.71 seconds
Started Jul 19 05:38:52 PM PDT 24
Finished Jul 19 05:38:54 PM PDT 24
Peak memory 205152 kb
Host smart-77d78499-3cc0-4016-bc4b-8c71183c7673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872968211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1872968211
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1418864202
Short name T740
Test name
Test status
Simulation time 177050819 ps
CPU time 2.52 seconds
Started Jul 19 05:38:40 PM PDT 24
Finished Jul 19 05:38:43 PM PDT 24
Peak memory 224832 kb
Host smart-733dbf78-40c1-47f8-ac9a-0a0c4b89ea93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418864202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1418864202
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2536654004
Short name T53
Test name
Test status
Simulation time 46018406 ps
CPU time 0.75 seconds
Started Jul 19 05:38:45 PM PDT 24
Finished Jul 19 05:38:47 PM PDT 24
Peak memory 205804 kb
Host smart-ad1a2981-8b9b-45e3-9008-c44cf740ba6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536654004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2536654004
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1483154636
Short name T1030
Test name
Test status
Simulation time 12295229341 ps
CPU time 164.42 seconds
Started Jul 19 05:38:53 PM PDT 24
Finished Jul 19 05:41:38 PM PDT 24
Peak memory 273508 kb
Host smart-c0bdb679-5b20-4680-8d41-4cdf66f7a722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483154636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1483154636
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.774421744
Short name T832
Test name
Test status
Simulation time 2668806616 ps
CPU time 61.53 seconds
Started Jul 19 05:38:51 PM PDT 24
Finished Jul 19 05:39:53 PM PDT 24
Peak memory 255744 kb
Host smart-410eee50-987c-44ae-a6d8-f31927060a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774421744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.774421744
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1435594471
Short name T689
Test name
Test status
Simulation time 8080672143 ps
CPU time 57.72 seconds
Started Jul 19 05:38:52 PM PDT 24
Finished Jul 19 05:39:51 PM PDT 24
Peak memory 250240 kb
Host smart-02e7054c-3dac-49d2-bb6c-0494dc9805e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435594471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1435594471
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.92552480
Short name T157
Test name
Test status
Simulation time 189459264 ps
CPU time 6.99 seconds
Started Jul 19 05:38:46 PM PDT 24
Finished Jul 19 05:38:54 PM PDT 24
Peak memory 233152 kb
Host smart-b6edd1e7-8f3a-431e-8ff1-f58fbda9d08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92552480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.92552480
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.282635504
Short name T296
Test name
Test status
Simulation time 351122229076 ps
CPU time 508.31 seconds
Started Jul 19 05:38:46 PM PDT 24
Finished Jul 19 05:47:15 PM PDT 24
Peak memory 273460 kb
Host smart-076fb9b4-a9f7-4400-ad59-fbbdad5a1610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282635504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.282635504
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3963081725
Short name T266
Test name
Test status
Simulation time 2561643745 ps
CPU time 5.22 seconds
Started Jul 19 05:38:42 PM PDT 24
Finished Jul 19 05:38:48 PM PDT 24
Peak memory 233212 kb
Host smart-4e1eef14-7645-4d58-8aea-1719fa65c48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963081725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3963081725
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.566703061
Short name T572
Test name
Test status
Simulation time 41235512 ps
CPU time 2.46 seconds
Started Jul 19 05:38:40 PM PDT 24
Finished Jul 19 05:38:43 PM PDT 24
Peak memory 232880 kb
Host smart-f518e750-e0f0-4ffb-b901-b844510d8343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566703061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.566703061
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1069826466
Short name T41
Test name
Test status
Simulation time 19603788332 ps
CPU time 17.73 seconds
Started Jul 19 05:38:42 PM PDT 24
Finished Jul 19 05:39:00 PM PDT 24
Peak memory 233320 kb
Host smart-08db5f76-3f12-4708-ae61-5dc2024d9c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069826466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1069826466
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.719009049
Short name T25
Test name
Test status
Simulation time 4135677319 ps
CPU time 14.87 seconds
Started Jul 19 05:38:43 PM PDT 24
Finished Jul 19 05:38:59 PM PDT 24
Peak memory 240976 kb
Host smart-6cac53d2-d370-4ec0-89c0-12acdaccda4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719009049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.719009049
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3951941091
Short name T480
Test name
Test status
Simulation time 5654508546 ps
CPU time 9.03 seconds
Started Jul 19 05:38:52 PM PDT 24
Finished Jul 19 05:39:02 PM PDT 24
Peak memory 223192 kb
Host smart-f345adbe-5d05-498c-98e8-bba46f76fe3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3951941091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3951941091
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4111873865
Short name T317
Test name
Test status
Simulation time 16813798328 ps
CPU time 173.26 seconds
Started Jul 19 05:38:52 PM PDT 24
Finished Jul 19 05:41:46 PM PDT 24
Peak memory 253388 kb
Host smart-307d8be1-81d0-4ef1-84fc-441ee9d578c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111873865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4111873865
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2782028160
Short name T986
Test name
Test status
Simulation time 16816773 ps
CPU time 0.75 seconds
Started Jul 19 05:38:46 PM PDT 24
Finished Jul 19 05:38:48 PM PDT 24
Peak memory 206296 kb
Host smart-791bea20-96b6-45dd-bd61-a371b133eb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782028160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2782028160
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1589579113
Short name T835
Test name
Test status
Simulation time 211434217 ps
CPU time 2.1 seconds
Started Jul 19 05:38:42 PM PDT 24
Finished Jul 19 05:38:45 PM PDT 24
Peak memory 216652 kb
Host smart-f343c855-c16a-49da-b5b5-bcbcdc82476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589579113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1589579113
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2987257948
Short name T340
Test name
Test status
Simulation time 25125705 ps
CPU time 0.84 seconds
Started Jul 19 05:38:47 PM PDT 24
Finished Jul 19 05:38:48 PM PDT 24
Peak memory 206272 kb
Host smart-4a53dd13-7820-4ad2-b265-063738effe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987257948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2987257948
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1052170744
Short name T22
Test name
Test status
Simulation time 92442464 ps
CPU time 0.81 seconds
Started Jul 19 05:38:46 PM PDT 24
Finished Jul 19 05:38:48 PM PDT 24
Peak memory 206224 kb
Host smart-d8c1a59e-7ed3-4a88-93f9-f662ec70c6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052170744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1052170744
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.97807677
Short name T466
Test name
Test status
Simulation time 25834081222 ps
CPU time 41.3 seconds
Started Jul 19 05:38:43 PM PDT 24
Finished Jul 19 05:39:25 PM PDT 24
Peak memory 237428 kb
Host smart-4c242b25-1ac9-4292-80d4-3d3f5222495e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97807677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.97807677
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3982430964
Short name T582
Test name
Test status
Simulation time 59732262 ps
CPU time 0.77 seconds
Started Jul 19 05:39:03 PM PDT 24
Finished Jul 19 05:39:05 PM PDT 24
Peak memory 205676 kb
Host smart-94c78d79-b92e-4b08-84ae-dcc120863893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982430964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3982430964
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.365830770
Short name T861
Test name
Test status
Simulation time 31424859 ps
CPU time 2.65 seconds
Started Jul 19 05:38:52 PM PDT 24
Finished Jul 19 05:38:55 PM PDT 24
Peak memory 232876 kb
Host smart-f2523d71-b4f2-4bde-ab1d-159b32980f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365830770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.365830770
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4170315748
Short name T931
Test name
Test status
Simulation time 127965517 ps
CPU time 0.77 seconds
Started Jul 19 05:38:53 PM PDT 24
Finished Jul 19 05:38:55 PM PDT 24
Peak memory 207180 kb
Host smart-8b918e31-3038-4a8c-b3e8-a45c2daf0793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170315748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4170315748
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1116165091
Short name T3
Test name
Test status
Simulation time 17812648559 ps
CPU time 43.61 seconds
Started Jul 19 05:39:00 PM PDT 24
Finished Jul 19 05:39:44 PM PDT 24
Peak memory 256256 kb
Host smart-be1f0c9a-589b-42ef-aecb-4bff09117c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116165091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1116165091
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3077649000
Short name T177
Test name
Test status
Simulation time 58928826940 ps
CPU time 212.37 seconds
Started Jul 19 05:39:02 PM PDT 24
Finished Jul 19 05:42:36 PM PDT 24
Peak memory 249636 kb
Host smart-86162f96-07cb-4bf1-844e-7b77db6cecaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077649000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3077649000
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3804232596
Short name T890
Test name
Test status
Simulation time 9030524664 ps
CPU time 86.65 seconds
Started Jul 19 05:39:00 PM PDT 24
Finished Jul 19 05:40:28 PM PDT 24
Peak memory 251964 kb
Host smart-08b827c0-6940-449e-850c-d59cc177adc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804232596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3804232596
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.186150309
Short name T320
Test name
Test status
Simulation time 34638022467 ps
CPU time 90.57 seconds
Started Jul 19 05:39:02 PM PDT 24
Finished Jul 19 05:40:34 PM PDT 24
Peak memory 250012 kb
Host smart-09c96ea8-0899-4dee-97f7-41888993aecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186150309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.186150309
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.594569612
Short name T722
Test name
Test status
Simulation time 69036977306 ps
CPU time 201.83 seconds
Started Jul 19 05:39:02 PM PDT 24
Finished Jul 19 05:42:25 PM PDT 24
Peak memory 250668 kb
Host smart-6a607b26-41bb-4962-ac3c-0f4b376c950c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594569612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.594569612
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4067698071
Short name T977
Test name
Test status
Simulation time 898086636 ps
CPU time 7.08 seconds
Started Jul 19 05:38:55 PM PDT 24
Finished Jul 19 05:39:03 PM PDT 24
Peak memory 224928 kb
Host smart-f395b41e-2cf5-4a6d-9f3c-055a9801fe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067698071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4067698071
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.979108450
Short name T626
Test name
Test status
Simulation time 7906848655 ps
CPU time 21.34 seconds
Started Jul 19 05:38:53 PM PDT 24
Finished Jul 19 05:39:16 PM PDT 24
Peak memory 225040 kb
Host smart-64f9d2e2-97e1-4cee-a2b6-ed91a4a9c9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979108450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.979108450
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1667173438
Short name T378
Test name
Test status
Simulation time 3874610532 ps
CPU time 4.1 seconds
Started Jul 19 05:38:53 PM PDT 24
Finished Jul 19 05:38:58 PM PDT 24
Peak memory 225048 kb
Host smart-1d6d38d9-de77-46d3-9984-93ee2a905d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667173438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1667173438
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2605138917
Short name T370
Test name
Test status
Simulation time 108204651 ps
CPU time 2.02 seconds
Started Jul 19 05:38:51 PM PDT 24
Finished Jul 19 05:38:53 PM PDT 24
Peak memory 223376 kb
Host smart-c2faec14-7a3d-4fa9-806b-7084e017a74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605138917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2605138917
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1074462646
Short name T557
Test name
Test status
Simulation time 29965290890 ps
CPU time 16.25 seconds
Started Jul 19 05:39:04 PM PDT 24
Finished Jul 19 05:39:22 PM PDT 24
Peak memory 222660 kb
Host smart-8c920810-30ff-450f-91d2-e2efa8a63dbe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1074462646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1074462646
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1407305707
Short name T234
Test name
Test status
Simulation time 34694809314 ps
CPU time 180.8 seconds
Started Jul 19 05:39:04 PM PDT 24
Finished Jul 19 05:42:07 PM PDT 24
Peak memory 268268 kb
Host smart-95304d95-9351-44b1-b39d-534a3c2e7a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407305707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1407305707
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1526800687
Short name T776
Test name
Test status
Simulation time 3331460382 ps
CPU time 26.71 seconds
Started Jul 19 05:38:54 PM PDT 24
Finished Jul 19 05:39:21 PM PDT 24
Peak memory 216792 kb
Host smart-ec122957-daaa-4208-9f0a-1bc6f5b4cc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526800687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1526800687
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2755333450
Short name T419
Test name
Test status
Simulation time 998143530 ps
CPU time 1.83 seconds
Started Jul 19 05:38:56 PM PDT 24
Finished Jul 19 05:38:58 PM PDT 24
Peak memory 208236 kb
Host smart-138d26ca-b3f6-48a4-a33e-9c80debe1d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755333450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2755333450
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1556895161
Short name T45
Test name
Test status
Simulation time 2378573220 ps
CPU time 4.54 seconds
Started Jul 19 05:38:52 PM PDT 24
Finished Jul 19 05:38:57 PM PDT 24
Peak memory 216704 kb
Host smart-8b4d4530-520a-4910-af22-a7aea4513a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556895161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1556895161
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2007125260
Short name T638
Test name
Test status
Simulation time 26932149 ps
CPU time 0.76 seconds
Started Jul 19 05:38:52 PM PDT 24
Finished Jul 19 05:38:54 PM PDT 24
Peak memory 206288 kb
Host smart-5534c71f-2dc8-4d08-8e47-e6f0f211d6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007125260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2007125260
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2033533946
Short name T876
Test name
Test status
Simulation time 9629119105 ps
CPU time 7.37 seconds
Started Jul 19 05:38:51 PM PDT 24
Finished Jul 19 05:38:59 PM PDT 24
Peak memory 225060 kb
Host smart-73071050-dbd3-42a8-96f0-2539d26272dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033533946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2033533946
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.14901834
Short name T966
Test name
Test status
Simulation time 10991118 ps
CPU time 0.71 seconds
Started Jul 19 05:39:03 PM PDT 24
Finished Jul 19 05:39:05 PM PDT 24
Peak memory 205752 kb
Host smart-cd33f750-d6de-4876-a20e-b735a1d7bb4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14901834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.14901834
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1109433175
Short name T51
Test name
Test status
Simulation time 257162489 ps
CPU time 5.4 seconds
Started Jul 19 05:39:02 PM PDT 24
Finished Jul 19 05:39:09 PM PDT 24
Peak memory 233196 kb
Host smart-9e72d2f5-c4a3-48ab-baea-7b29b8761780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109433175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1109433175
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1125802714
Short name T701
Test name
Test status
Simulation time 20451056 ps
CPU time 0.81 seconds
Started Jul 19 05:39:01 PM PDT 24
Finished Jul 19 05:39:03 PM PDT 24
Peak memory 206884 kb
Host smart-1daa80f2-e92b-4654-96f2-36c7f6cd069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125802714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1125802714
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2232316788
Short name T521
Test name
Test status
Simulation time 7186409673 ps
CPU time 61.09 seconds
Started Jul 19 05:39:02 PM PDT 24
Finished Jul 19 05:40:04 PM PDT 24
Peak memory 251724 kb
Host smart-34bedeac-5d37-421e-b943-73ddfddfe288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232316788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2232316788
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4131018448
Short name T335
Test name
Test status
Simulation time 13413299325 ps
CPU time 97.23 seconds
Started Jul 19 05:39:02 PM PDT 24
Finished Jul 19 05:40:41 PM PDT 24
Peak memory 249708 kb
Host smart-6846775c-da6b-44db-8e33-fcbfbbe5eebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131018448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4131018448
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1835296338
Short name T405
Test name
Test status
Simulation time 29957420552 ps
CPU time 61.83 seconds
Started Jul 19 05:39:02 PM PDT 24
Finished Jul 19 05:40:05 PM PDT 24
Peak memory 233296 kb
Host smart-8d727ec4-a05a-4b2f-a28a-363746101f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835296338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1835296338
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3721759366
Short name T815
Test name
Test status
Simulation time 2990611210 ps
CPU time 26.42 seconds
Started Jul 19 05:39:04 PM PDT 24
Finished Jul 19 05:39:32 PM PDT 24
Peak memory 225056 kb
Host smart-715e1bbc-9776-46cc-b233-21dabea31537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721759366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3721759366
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1847872871
Short name T223
Test name
Test status
Simulation time 2658983970 ps
CPU time 21.03 seconds
Started Jul 19 05:39:02 PM PDT 24
Finished Jul 19 05:39:24 PM PDT 24
Peak memory 225028 kb
Host smart-682a2a8f-90ce-455d-8bb3-401a5d2c7c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847872871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1847872871
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.177709462
Short name T281
Test name
Test status
Simulation time 10299200108 ps
CPU time 101.09 seconds
Started Jul 19 05:39:05 PM PDT 24
Finished Jul 19 05:40:47 PM PDT 24
Peak memory 233300 kb
Host smart-a0cc0b61-bf21-4f72-9447-ea7e084401b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177709462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.177709462
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3262670279
Short name T1001
Test name
Test status
Simulation time 686862141 ps
CPU time 5.52 seconds
Started Jul 19 05:39:04 PM PDT 24
Finished Jul 19 05:39:11 PM PDT 24
Peak memory 233132 kb
Host smart-3fe08849-e94a-4845-b735-529a48584b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262670279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3262670279
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3589408029
Short name T942
Test name
Test status
Simulation time 3089409986 ps
CPU time 14.07 seconds
Started Jul 19 05:39:07 PM PDT 24
Finished Jul 19 05:39:22 PM PDT 24
Peak memory 233276 kb
Host smart-507e4fa4-138f-40ca-86d4-a4bcbaeb5dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589408029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3589408029
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2068070627
Short name T152
Test name
Test status
Simulation time 2950517494 ps
CPU time 15.87 seconds
Started Jul 19 05:39:03 PM PDT 24
Finished Jul 19 05:39:20 PM PDT 24
Peak memory 222760 kb
Host smart-a0b29ef0-3b6c-4488-8c92-d496997aa818
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2068070627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2068070627
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2459525893
Short name T200
Test name
Test status
Simulation time 45734742784 ps
CPU time 99.12 seconds
Started Jul 19 05:39:00 PM PDT 24
Finished Jul 19 05:40:40 PM PDT 24
Peak memory 249688 kb
Host smart-5648a336-f365-46a1-bf19-9a62b4d64f44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459525893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2459525893
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.466170545
Short name T996
Test name
Test status
Simulation time 18735159317 ps
CPU time 31.14 seconds
Started Jul 19 05:39:01 PM PDT 24
Finished Jul 19 05:39:33 PM PDT 24
Peak memory 221200 kb
Host smart-9adda8ed-86cb-4c3d-8087-2d990f537aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466170545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.466170545
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.583864748
Short name T414
Test name
Test status
Simulation time 2206117750 ps
CPU time 6.24 seconds
Started Jul 19 05:39:02 PM PDT 24
Finished Jul 19 05:39:10 PM PDT 24
Peak memory 216824 kb
Host smart-28bddaae-3acf-4143-87b9-2fb889f21e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583864748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.583864748
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1116454007
Short name T1022
Test name
Test status
Simulation time 202246376 ps
CPU time 2.49 seconds
Started Jul 19 05:39:05 PM PDT 24
Finished Jul 19 05:39:09 PM PDT 24
Peak memory 216656 kb
Host smart-298ef3a5-451e-4a1e-b387-85070425080e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116454007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1116454007
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2604947083
Short name T411
Test name
Test status
Simulation time 35981597 ps
CPU time 0.74 seconds
Started Jul 19 05:39:01 PM PDT 24
Finished Jul 19 05:39:02 PM PDT 24
Peak memory 206236 kb
Host smart-31f3f860-173e-40e6-89ed-d1ac39259f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604947083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2604947083
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1341961005
Short name T263
Test name
Test status
Simulation time 14301727566 ps
CPU time 43.14 seconds
Started Jul 19 05:39:03 PM PDT 24
Finished Jul 19 05:39:47 PM PDT 24
Peak memory 249628 kb
Host smart-5ada2ed1-416b-4175-bbfc-3b76f8987a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341961005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1341961005
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2358289062
Short name T470
Test name
Test status
Simulation time 35047608 ps
CPU time 0.68 seconds
Started Jul 19 05:39:10 PM PDT 24
Finished Jul 19 05:39:13 PM PDT 24
Peak memory 206084 kb
Host smart-6ee6e48d-6cff-4796-9d7f-5d38976daf54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358289062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2358289062
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3979294436
Short name T27
Test name
Test status
Simulation time 438329040 ps
CPU time 4.5 seconds
Started Jul 19 05:39:09 PM PDT 24
Finished Jul 19 05:39:16 PM PDT 24
Peak memory 224896 kb
Host smart-a6008abd-d492-43c2-8f57-51a56846785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979294436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3979294436
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1414881368
Short name T670
Test name
Test status
Simulation time 32977566 ps
CPU time 0.83 seconds
Started Jul 19 05:39:01 PM PDT 24
Finished Jul 19 05:39:03 PM PDT 24
Peak memory 206868 kb
Host smart-675d2587-63e8-4a3e-a830-8bb030734e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414881368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1414881368
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.513030601
Short name T491
Test name
Test status
Simulation time 16982515 ps
CPU time 0.75 seconds
Started Jul 19 05:39:16 PM PDT 24
Finished Jul 19 05:39:17 PM PDT 24
Peak memory 216348 kb
Host smart-39b0e032-49a8-40f3-a8c9-175aeab4a7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513030601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.513030601
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.253461702
Short name T925
Test name
Test status
Simulation time 3291473137 ps
CPU time 67.35 seconds
Started Jul 19 05:39:09 PM PDT 24
Finished Jul 19 05:40:19 PM PDT 24
Peak memory 254468 kb
Host smart-ace39f6e-14fc-4f1f-9b54-3f50d777dbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253461702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.253461702
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3214797057
Short name T174
Test name
Test status
Simulation time 20022439440 ps
CPU time 285.15 seconds
Started Jul 19 05:39:08 PM PDT 24
Finished Jul 19 05:43:55 PM PDT 24
Peak memory 254800 kb
Host smart-a79e035d-619a-4b96-a2b7-947bd1a7e4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214797057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3214797057
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1497646985
Short name T853
Test name
Test status
Simulation time 3491444374 ps
CPU time 11.23 seconds
Started Jul 19 05:39:16 PM PDT 24
Finished Jul 19 05:39:29 PM PDT 24
Peak memory 233352 kb
Host smart-fac92675-870c-4f8b-8689-13359338a12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497646985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1497646985
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1879951492
Short name T311
Test name
Test status
Simulation time 15556793354 ps
CPU time 83.75 seconds
Started Jul 19 05:39:10 PM PDT 24
Finished Jul 19 05:40:36 PM PDT 24
Peak memory 269260 kb
Host smart-39c8f6b1-1118-45f0-b689-1f076ca235c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879951492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1879951492
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2756933036
Short name T402
Test name
Test status
Simulation time 1650228809 ps
CPU time 9.54 seconds
Started Jul 19 05:39:09 PM PDT 24
Finished Jul 19 05:39:22 PM PDT 24
Peak memory 224976 kb
Host smart-0b29b7c5-222f-4051-bd8f-acadc0c4ed8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756933036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2756933036
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1137350252
Short name T893
Test name
Test status
Simulation time 733845714 ps
CPU time 6.57 seconds
Started Jul 19 05:39:17 PM PDT 24
Finished Jul 19 05:39:26 PM PDT 24
Peak memory 233236 kb
Host smart-7a080f2a-634b-4132-a136-911acc33f6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137350252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1137350252
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2667777154
Short name T820
Test name
Test status
Simulation time 37064167 ps
CPU time 2.73 seconds
Started Jul 19 05:39:10 PM PDT 24
Finished Jul 19 05:39:15 PM PDT 24
Peak memory 233152 kb
Host smart-5d021d06-9682-4411-8f52-f7f0569f19d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667777154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2667777154
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3010420698
Short name T517
Test name
Test status
Simulation time 1160060467 ps
CPU time 5.45 seconds
Started Jul 19 05:39:07 PM PDT 24
Finished Jul 19 05:39:13 PM PDT 24
Peak memory 224908 kb
Host smart-d53dbaa1-141e-49a6-965f-343dc9012b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010420698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3010420698
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2702361481
Short name T872
Test name
Test status
Simulation time 292671593 ps
CPU time 5.02 seconds
Started Jul 19 05:39:09 PM PDT 24
Finished Jul 19 05:39:16 PM PDT 24
Peak memory 223272 kb
Host smart-1c0549bf-a0b3-4d74-9041-b8c07b50cd65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2702361481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2702361481
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.733813972
Short name T1031
Test name
Test status
Simulation time 76692785 ps
CPU time 1.27 seconds
Started Jul 19 05:39:11 PM PDT 24
Finished Jul 19 05:39:14 PM PDT 24
Peak memory 207592 kb
Host smart-e8227d45-d024-4a3b-b96b-950fa651a1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733813972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.733813972
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1565914439
Short name T702
Test name
Test status
Simulation time 25520954148 ps
CPU time 17.63 seconds
Started Jul 19 05:39:04 PM PDT 24
Finished Jul 19 05:39:23 PM PDT 24
Peak memory 216844 kb
Host smart-6fb8a594-ad99-4042-b6eb-1d3cf347870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565914439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1565914439
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3005532927
Short name T354
Test name
Test status
Simulation time 15101887539 ps
CPU time 9.42 seconds
Started Jul 19 05:39:01 PM PDT 24
Finished Jul 19 05:39:12 PM PDT 24
Peak memory 216904 kb
Host smart-b6a2a48c-46d8-4304-b736-af622fe7bc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005532927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3005532927
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2205483337
Short name T358
Test name
Test status
Simulation time 1033105374 ps
CPU time 3.03 seconds
Started Jul 19 05:39:08 PM PDT 24
Finished Jul 19 05:39:13 PM PDT 24
Peak memory 216724 kb
Host smart-807c43b8-cdca-4bcf-94c4-fee336f86672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205483337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2205483337
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.758600906
Short name T141
Test name
Test status
Simulation time 138658103 ps
CPU time 0.76 seconds
Started Jul 19 05:39:08 PM PDT 24
Finished Jul 19 05:39:10 PM PDT 24
Peak memory 206284 kb
Host smart-023d289b-8b09-4477-968b-26b0a1ba8bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758600906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.758600906
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.68329020
Short name T390
Test name
Test status
Simulation time 3277170910 ps
CPU time 4.76 seconds
Started Jul 19 05:39:10 PM PDT 24
Finished Jul 19 05:39:17 PM PDT 24
Peak memory 225040 kb
Host smart-8439cb44-e059-4684-8bf4-9d51e2b5a392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68329020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.68329020
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3282745782
Short name T844
Test name
Test status
Simulation time 23612864 ps
CPU time 0.71 seconds
Started Jul 19 05:39:15 PM PDT 24
Finished Jul 19 05:39:17 PM PDT 24
Peak memory 205780 kb
Host smart-a7e7e3ce-beac-4301-94eb-c0598bfd9115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282745782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3282745782
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2590546494
Short name T70
Test name
Test status
Simulation time 445305770 ps
CPU time 2.67 seconds
Started Jul 19 05:39:09 PM PDT 24
Finished Jul 19 05:39:13 PM PDT 24
Peak memory 224940 kb
Host smart-1286ac8e-437e-4907-8136-fe570758287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590546494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2590546494
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2041693614
Short name T941
Test name
Test status
Simulation time 28746163 ps
CPU time 0.8 seconds
Started Jul 19 05:39:08 PM PDT 24
Finished Jul 19 05:39:11 PM PDT 24
Peak memory 206892 kb
Host smart-952fd108-5bd3-4de0-b1aa-6e64602e55bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041693614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2041693614
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4078971167
Short name T564
Test name
Test status
Simulation time 191629964 ps
CPU time 0.92 seconds
Started Jul 19 05:39:10 PM PDT 24
Finished Jul 19 05:39:13 PM PDT 24
Peak memory 216504 kb
Host smart-98a346ca-a461-4a64-a425-2fdaf42ba1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078971167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4078971167
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3178194861
Short name T249
Test name
Test status
Simulation time 2573267914 ps
CPU time 28.67 seconds
Started Jul 19 05:39:10 PM PDT 24
Finished Jul 19 05:39:41 PM PDT 24
Peak memory 241492 kb
Host smart-dc811072-ad56-41f4-a30f-23ea76c8695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178194861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3178194861
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2731176597
Short name T199
Test name
Test status
Simulation time 27161182313 ps
CPU time 110.52 seconds
Started Jul 19 05:39:13 PM PDT 24
Finished Jul 19 05:41:05 PM PDT 24
Peak memory 264168 kb
Host smart-3088f06e-7878-49ad-82ce-7550fd5b5eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731176597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2731176597
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1104522254
Short name T325
Test name
Test status
Simulation time 1021746197 ps
CPU time 18.63 seconds
Started Jul 19 05:39:09 PM PDT 24
Finished Jul 19 05:39:30 PM PDT 24
Peak memory 233156 kb
Host smart-afd5eff6-c58d-4f42-903c-95b91cb86bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104522254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1104522254
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2824629308
Short name T1034
Test name
Test status
Simulation time 9458533737 ps
CPU time 34.86 seconds
Started Jul 19 05:39:09 PM PDT 24
Finished Jul 19 05:39:46 PM PDT 24
Peak memory 237680 kb
Host smart-3334f897-9c9f-43d2-acd7-0e3486547cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824629308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2824629308
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4259531320
Short name T542
Test name
Test status
Simulation time 193761221 ps
CPU time 5.01 seconds
Started Jul 19 05:39:12 PM PDT 24
Finished Jul 19 05:39:19 PM PDT 24
Peak memory 233108 kb
Host smart-e022770f-4077-44e7-af9e-a90b1248ee84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259531320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4259531320
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.208018539
Short name T865
Test name
Test status
Simulation time 1151770763 ps
CPU time 25.16 seconds
Started Jul 19 05:39:09 PM PDT 24
Finished Jul 19 05:39:37 PM PDT 24
Peak memory 233160 kb
Host smart-41a4cf7a-fded-4f36-882c-577ed9ac1482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208018539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.208018539
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.574045210
Short name T968
Test name
Test status
Simulation time 6970842740 ps
CPU time 21.36 seconds
Started Jul 19 05:39:08 PM PDT 24
Finished Jul 19 05:39:31 PM PDT 24
Peak memory 233308 kb
Host smart-a1329f87-1dbe-45e5-a914-84eac963ab4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574045210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.574045210
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1365901120
Short name T242
Test name
Test status
Simulation time 4703739607 ps
CPU time 12.28 seconds
Started Jul 19 05:39:09 PM PDT 24
Finished Jul 19 05:39:24 PM PDT 24
Peak memory 233216 kb
Host smart-b7880778-adab-4333-9e02-3d8a06515755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365901120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1365901120
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2724046605
Short name T154
Test name
Test status
Simulation time 658047584 ps
CPU time 3.84 seconds
Started Jul 19 05:39:11 PM PDT 24
Finished Jul 19 05:39:17 PM PDT 24
Peak memory 223576 kb
Host smart-617253e3-4cd8-4751-adbe-d3cfc427f3e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2724046605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2724046605
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2690615765
Short name T15
Test name
Test status
Simulation time 71897494 ps
CPU time 1 seconds
Started Jul 19 05:39:21 PM PDT 24
Finished Jul 19 05:39:24 PM PDT 24
Peak memory 207344 kb
Host smart-69b809f3-db7f-4707-ac89-b4f8ee58e71e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690615765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2690615765
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2249619313
Short name T612
Test name
Test status
Simulation time 5896576857 ps
CPU time 19.54 seconds
Started Jul 19 05:39:16 PM PDT 24
Finished Jul 19 05:39:38 PM PDT 24
Peak memory 216952 kb
Host smart-f3adca0d-a26e-4fa6-9f98-f9ef3a629bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249619313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2249619313
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4236586489
Short name T28
Test name
Test status
Simulation time 3332611686 ps
CPU time 12.41 seconds
Started Jul 19 05:39:11 PM PDT 24
Finished Jul 19 05:39:25 PM PDT 24
Peak memory 216796 kb
Host smart-755429e7-9b5f-4aa7-9ea8-380d0bf37551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236586489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4236586489
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.134683152
Short name T698
Test name
Test status
Simulation time 129087635 ps
CPU time 2.41 seconds
Started Jul 19 05:39:09 PM PDT 24
Finished Jul 19 05:39:14 PM PDT 24
Peak memory 216644 kb
Host smart-6032e30d-002e-48ba-9a6f-f1caef894f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134683152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.134683152
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.281181188
Short name T902
Test name
Test status
Simulation time 54348209 ps
CPU time 0.84 seconds
Started Jul 19 05:39:08 PM PDT 24
Finished Jul 19 05:39:10 PM PDT 24
Peak memory 206268 kb
Host smart-fb08b008-58d3-43bd-b48f-03c5cd4d1adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281181188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.281181188
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3257244134
Short name T388
Test name
Test status
Simulation time 1244386308 ps
CPU time 4.27 seconds
Started Jul 19 05:39:09 PM PDT 24
Finished Jul 19 05:39:15 PM PDT 24
Peak memory 233092 kb
Host smart-511e59d3-644e-4104-968a-f27f39e96fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257244134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3257244134
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.561897972
Short name T774
Test name
Test status
Simulation time 111745228 ps
CPU time 0.78 seconds
Started Jul 19 05:39:17 PM PDT 24
Finished Jul 19 05:39:19 PM PDT 24
Peak memory 205116 kb
Host smart-734dbe8f-db1b-44c6-8f10-e2bcd8d5f2b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561897972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.561897972
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3812166458
Short name T90
Test name
Test status
Simulation time 91695645 ps
CPU time 3.01 seconds
Started Jul 19 05:39:21 PM PDT 24
Finished Jul 19 05:39:26 PM PDT 24
Peak memory 225012 kb
Host smart-9073db9d-e480-473e-a5c6-5470cb7b2c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812166458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3812166458
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2911335234
Short name T983
Test name
Test status
Simulation time 20374370 ps
CPU time 0.82 seconds
Started Jul 19 05:39:17 PM PDT 24
Finished Jul 19 05:39:20 PM PDT 24
Peak memory 206780 kb
Host smart-d0b111e7-eb32-439d-aed6-832376bf0070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911335234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2911335234
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1406236606
Short name T750
Test name
Test status
Simulation time 4477471713 ps
CPU time 21.88 seconds
Started Jul 19 05:39:19 PM PDT 24
Finished Jul 19 05:39:43 PM PDT 24
Peak memory 249656 kb
Host smart-299e3907-ed4c-4d20-a96d-9b440cb05187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406236606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1406236606
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3553376770
Short name T337
Test name
Test status
Simulation time 8520817412 ps
CPU time 26.55 seconds
Started Jul 19 05:39:17 PM PDT 24
Finished Jul 19 05:39:45 PM PDT 24
Peak memory 218292 kb
Host smart-a4122220-cdfc-4567-834e-1dc88b8d7c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553376770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3553376770
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.464599072
Short name T214
Test name
Test status
Simulation time 10024517157 ps
CPU time 162.89 seconds
Started Jul 19 05:39:18 PM PDT 24
Finished Jul 19 05:42:03 PM PDT 24
Peak memory 257448 kb
Host smart-d6768132-9225-45b9-9019-83f6f3bbe9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464599072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.464599072
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.768230190
Short name T873
Test name
Test status
Simulation time 2485134848 ps
CPU time 36.71 seconds
Started Jul 19 05:39:16 PM PDT 24
Finished Jul 19 05:39:54 PM PDT 24
Peak memory 225024 kb
Host smart-13fbbeb9-6f71-4cea-9a71-cd0544a4825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768230190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.768230190
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.762481565
Short name T43
Test name
Test status
Simulation time 122872984199 ps
CPU time 177.19 seconds
Started Jul 19 05:39:16 PM PDT 24
Finished Jul 19 05:42:15 PM PDT 24
Peak memory 257080 kb
Host smart-a97a5b2f-36f8-4dff-8879-3cffe2d365e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762481565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.762481565
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2520344561
Short name T74
Test name
Test status
Simulation time 103062832 ps
CPU time 2.11 seconds
Started Jul 19 05:39:16 PM PDT 24
Finished Jul 19 05:39:20 PM PDT 24
Peak memory 224664 kb
Host smart-6117501a-4761-49b3-9494-bed2e15d82c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520344561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2520344561
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2932325506
Short name T603
Test name
Test status
Simulation time 1464659244 ps
CPU time 10.74 seconds
Started Jul 19 05:39:18 PM PDT 24
Finished Jul 19 05:39:31 PM PDT 24
Peak memory 233148 kb
Host smart-81cb872f-2f24-4394-bc1e-2eeea968b25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932325506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2932325506
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.511833239
Short name T138
Test name
Test status
Simulation time 3625003948 ps
CPU time 11.69 seconds
Started Jul 19 05:39:17 PM PDT 24
Finished Jul 19 05:39:31 PM PDT 24
Peak memory 233212 kb
Host smart-4071014e-1e87-4e28-9453-b2060e54c09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511833239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.511833239
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2052654075
Short name T422
Test name
Test status
Simulation time 143743139 ps
CPU time 2.24 seconds
Started Jul 19 05:39:18 PM PDT 24
Finished Jul 19 05:39:22 PM PDT 24
Peak memory 223528 kb
Host smart-c2e4d506-560e-4b59-a945-6d4ae371f736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052654075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2052654075
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2758061939
Short name T682
Test name
Test status
Simulation time 447789761 ps
CPU time 4.41 seconds
Started Jul 19 05:39:22 PM PDT 24
Finished Jul 19 05:39:28 PM PDT 24
Peak memory 219760 kb
Host smart-be9ad730-3cc3-44fc-8cb5-4e75b54e215b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2758061939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2758061939
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.522772513
Short name T478
Test name
Test status
Simulation time 1206220904 ps
CPU time 13.05 seconds
Started Jul 19 05:39:17 PM PDT 24
Finished Jul 19 05:39:32 PM PDT 24
Peak memory 216784 kb
Host smart-78f9711e-7cb4-4c1d-aba5-c627670d703e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522772513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.522772513
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3933860378
Short name T401
Test name
Test status
Simulation time 4307885318 ps
CPU time 5 seconds
Started Jul 19 05:39:18 PM PDT 24
Finished Jul 19 05:39:25 PM PDT 24
Peak memory 216764 kb
Host smart-3677c32a-de3b-43cb-a981-1a50d33c1f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933860378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3933860378
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.643659589
Short name T587
Test name
Test status
Simulation time 370139815 ps
CPU time 3.72 seconds
Started Jul 19 05:39:16 PM PDT 24
Finished Jul 19 05:39:22 PM PDT 24
Peak memory 216676 kb
Host smart-934bb8b2-531f-4255-a6f5-da0e505e801b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643659589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.643659589
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.947754089
Short name T575
Test name
Test status
Simulation time 130341400 ps
CPU time 1 seconds
Started Jul 19 05:39:18 PM PDT 24
Finished Jul 19 05:39:21 PM PDT 24
Peak memory 206172 kb
Host smart-1939709b-379b-4fc4-a7fb-ceedd2729f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947754089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.947754089
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2226516681
Short name T458
Test name
Test status
Simulation time 36670025100 ps
CPU time 16.57 seconds
Started Jul 19 05:39:18 PM PDT 24
Finished Jul 19 05:39:36 PM PDT 24
Peak memory 241356 kb
Host smart-c1b01fc9-8fc9-422f-8a51-0280b858de9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226516681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2226516681
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1285669217
Short name T60
Test name
Test status
Simulation time 34666549 ps
CPU time 0.71 seconds
Started Jul 19 05:39:24 PM PDT 24
Finished Jul 19 05:39:26 PM PDT 24
Peak memory 205784 kb
Host smart-785618e9-5609-407d-9a14-e976eae73a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285669217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1285669217
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2604859328
Short name T362
Test name
Test status
Simulation time 814282254 ps
CPU time 3.66 seconds
Started Jul 19 05:39:25 PM PDT 24
Finished Jul 19 05:39:33 PM PDT 24
Peak memory 233156 kb
Host smart-6a064ec5-88d9-4629-8e04-7fda2f68e314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604859328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2604859328
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1894597921
Short name T369
Test name
Test status
Simulation time 49913591 ps
CPU time 0.76 seconds
Started Jul 19 05:39:17 PM PDT 24
Finished Jul 19 05:39:19 PM PDT 24
Peak memory 206900 kb
Host smart-8ed44049-6abd-4dd7-b1ea-d318998a2c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894597921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1894597921
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.433193306
Short name T225
Test name
Test status
Simulation time 28524735335 ps
CPU time 263.4 seconds
Started Jul 19 05:39:24 PM PDT 24
Finished Jul 19 05:43:52 PM PDT 24
Peak memory 257052 kb
Host smart-b668e7cf-bde7-44c3-9b0d-fa23d01be95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433193306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.433193306
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.549053187
Short name T737
Test name
Test status
Simulation time 20901655950 ps
CPU time 164 seconds
Started Jul 19 05:39:26 PM PDT 24
Finished Jul 19 05:42:15 PM PDT 24
Peak memory 273380 kb
Host smart-6eec6b68-b889-47f9-937c-9fea593cdd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549053187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.549053187
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2071115398
Short name T144
Test name
Test status
Simulation time 98049916725 ps
CPU time 215.74 seconds
Started Jul 19 05:39:26 PM PDT 24
Finished Jul 19 05:43:06 PM PDT 24
Peak memory 241124 kb
Host smart-8c7e1758-45b1-4d99-a93e-a0cdcf3414ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071115398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2071115398
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1621314341
Short name T563
Test name
Test status
Simulation time 564087539 ps
CPU time 6.89 seconds
Started Jul 19 05:39:24 PM PDT 24
Finished Jul 19 05:39:34 PM PDT 24
Peak memory 233184 kb
Host smart-3bbe38ad-ebeb-4489-a9e8-08bc686190ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621314341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1621314341
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1785600046
Short name T244
Test name
Test status
Simulation time 25565239977 ps
CPU time 70.05 seconds
Started Jul 19 05:39:26 PM PDT 24
Finished Jul 19 05:40:40 PM PDT 24
Peak memory 253004 kb
Host smart-f7f84714-f0bc-4d61-bbe0-3956c6cbe112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785600046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1785600046
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3238256056
Short name T786
Test name
Test status
Simulation time 42660405 ps
CPU time 2.7 seconds
Started Jul 19 05:39:25 PM PDT 24
Finished Jul 19 05:39:32 PM PDT 24
Peak memory 233076 kb
Host smart-b4c2ff50-5699-4c71-829b-cc2196fe597b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238256056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3238256056
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2180213782
Short name T376
Test name
Test status
Simulation time 2910362159 ps
CPU time 34.75 seconds
Started Jul 19 05:39:29 PM PDT 24
Finished Jul 19 05:40:07 PM PDT 24
Peak memory 233232 kb
Host smart-e5378341-bab5-480e-902b-6d5283c0c88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180213782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2180213782
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1008061233
Short name T553
Test name
Test status
Simulation time 97672523 ps
CPU time 2.98 seconds
Started Jul 19 05:39:25 PM PDT 24
Finished Jul 19 05:39:33 PM PDT 24
Peak memory 233148 kb
Host smart-2e8c3733-155b-46a1-ba47-2cbaabc9026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008061233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1008061233
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3147060452
Short name T871
Test name
Test status
Simulation time 117911791 ps
CPU time 3.49 seconds
Started Jul 19 05:39:24 PM PDT 24
Finished Jul 19 05:39:29 PM PDT 24
Peak memory 224896 kb
Host smart-23b40c4c-9ed6-4b59-9796-71d916f5e9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147060452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3147060452
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2527039838
Short name T406
Test name
Test status
Simulation time 7769230794 ps
CPU time 15.87 seconds
Started Jul 19 05:39:22 PM PDT 24
Finished Jul 19 05:39:40 PM PDT 24
Peak memory 223492 kb
Host smart-a642bbd2-acbc-4a34-9641-fb7f99d28848
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2527039838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2527039838
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1827820242
Short name T17
Test name
Test status
Simulation time 94682971 ps
CPU time 0.91 seconds
Started Jul 19 05:39:25 PM PDT 24
Finished Jul 19 05:39:30 PM PDT 24
Peak memory 206928 kb
Host smart-cc90223d-396d-42f3-93c5-ef68caa9f123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827820242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1827820242
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4238724283
Short name T577
Test name
Test status
Simulation time 4797846299 ps
CPU time 30.46 seconds
Started Jul 19 05:39:16 PM PDT 24
Finished Jul 19 05:39:49 PM PDT 24
Peak memory 216880 kb
Host smart-63108d56-6127-4937-898e-c26bcd46b73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238724283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4238724283
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.526574537
Short name T700
Test name
Test status
Simulation time 5613661822 ps
CPU time 3.21 seconds
Started Jul 19 05:39:16 PM PDT 24
Finished Jul 19 05:39:21 PM PDT 24
Peak memory 216872 kb
Host smart-f3790ae5-6400-4b53-9035-1f1d0f297a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526574537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.526574537
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3769211033
Short name T859
Test name
Test status
Simulation time 935498295 ps
CPU time 1.17 seconds
Started Jul 19 05:39:26 PM PDT 24
Finished Jul 19 05:39:32 PM PDT 24
Peak memory 208028 kb
Host smart-67d47015-5426-4f12-a782-ffbf6aea1576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769211033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3769211033
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2764253385
Short name T442
Test name
Test status
Simulation time 42377127 ps
CPU time 0.87 seconds
Started Jul 19 05:39:16 PM PDT 24
Finished Jul 19 05:39:19 PM PDT 24
Peak memory 206288 kb
Host smart-89870036-b16b-4e8f-bf63-f4ec26d277de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764253385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2764253385
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1172861610
Short name T10
Test name
Test status
Simulation time 12008686795 ps
CPU time 12.16 seconds
Started Jul 19 05:39:24 PM PDT 24
Finished Jul 19 05:39:38 PM PDT 24
Peak memory 233212 kb
Host smart-720d39c4-0cbd-40f7-8ede-d61ed573217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172861610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1172861610
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2504161608
Short name T446
Test name
Test status
Simulation time 11879060 ps
CPU time 0.71 seconds
Started Jul 19 05:39:33 PM PDT 24
Finished Jul 19 05:39:38 PM PDT 24
Peak memory 205168 kb
Host smart-292c128e-4706-442a-a8b7-914a389af0b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504161608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2504161608
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.439495428
Short name T91
Test name
Test status
Simulation time 1233958376 ps
CPU time 4.42 seconds
Started Jul 19 05:39:23 PM PDT 24
Finished Jul 19 05:39:29 PM PDT 24
Peak memory 224888 kb
Host smart-d77b6b49-b9f5-4acc-97c8-f7810eee1500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439495428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.439495428
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.223606861
Short name T512
Test name
Test status
Simulation time 22218786 ps
CPU time 0.75 seconds
Started Jul 19 05:39:28 PM PDT 24
Finished Jul 19 05:39:33 PM PDT 24
Peak memory 205812 kb
Host smart-38a5dff2-835f-4595-a811-019e9a1eb0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223606861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.223606861
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1498507399
Short name T752
Test name
Test status
Simulation time 6334951102 ps
CPU time 11.98 seconds
Started Jul 19 05:39:33 PM PDT 24
Finished Jul 19 05:39:50 PM PDT 24
Peak memory 241476 kb
Host smart-fa42dc01-cbad-4808-a334-1325413c2541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498507399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1498507399
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.4275781314
Short name T543
Test name
Test status
Simulation time 23622109874 ps
CPU time 184.2 seconds
Started Jul 19 05:39:31 PM PDT 24
Finished Jul 19 05:42:39 PM PDT 24
Peak memory 241228 kb
Host smart-92a58571-0fda-4a0e-b17d-da7a159dff18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275781314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4275781314
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.56458157
Short name T591
Test name
Test status
Simulation time 1150664532 ps
CPU time 18.44 seconds
Started Jul 19 05:39:36 PM PDT 24
Finished Jul 19 05:40:01 PM PDT 24
Peak memory 233136 kb
Host smart-6dd98bce-3435-492e-a3f7-fd092651f385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56458157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.56458157
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.988598923
Short name T322
Test name
Test status
Simulation time 1574613496 ps
CPU time 9.93 seconds
Started Jul 19 05:39:29 PM PDT 24
Finished Jul 19 05:39:42 PM PDT 24
Peak memory 224868 kb
Host smart-0b3ceda1-18cf-4977-b66f-9d30087006df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988598923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.988598923
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3758090514
Short name T773
Test name
Test status
Simulation time 62566780468 ps
CPU time 83.98 seconds
Started Jul 19 05:39:29 PM PDT 24
Finished Jul 19 05:40:57 PM PDT 24
Peak memory 250232 kb
Host smart-fc99787f-07f6-4fb2-89f1-1cd2c1e16631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758090514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3758090514
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1385631409
Short name T567
Test name
Test status
Simulation time 142358290 ps
CPU time 2.74 seconds
Started Jul 19 05:39:25 PM PDT 24
Finished Jul 19 05:39:32 PM PDT 24
Peak memory 224856 kb
Host smart-f17f09b4-cfd7-462c-8a3e-cf2a3b612905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385631409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1385631409
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1996075442
Short name T987
Test name
Test status
Simulation time 5364324468 ps
CPU time 58.75 seconds
Started Jul 19 05:39:26 PM PDT 24
Finished Jul 19 05:40:30 PM PDT 24
Peak memory 235296 kb
Host smart-fcf1b2e4-1cbc-4d62-9ad0-0d88664e445d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996075442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1996075442
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3908193002
Short name T777
Test name
Test status
Simulation time 17419162237 ps
CPU time 27.08 seconds
Started Jul 19 05:39:26 PM PDT 24
Finished Jul 19 05:39:58 PM PDT 24
Peak memory 241476 kb
Host smart-2328a5cc-77f1-4ef3-b90c-517b22a2cfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908193002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3908193002
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.40012099
Short name T751
Test name
Test status
Simulation time 56588951 ps
CPU time 2.26 seconds
Started Jul 19 05:39:25 PM PDT 24
Finished Jul 19 05:39:31 PM PDT 24
Peak memory 224620 kb
Host smart-4f434335-dce5-404c-9ffd-75a23a5ac240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40012099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.40012099
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3016751007
Short name T530
Test name
Test status
Simulation time 2951103020 ps
CPU time 7.11 seconds
Started Jul 19 05:39:26 PM PDT 24
Finished Jul 19 05:39:38 PM PDT 24
Peak memory 219940 kb
Host smart-3ebb4781-4e35-4728-bd15-9a3edcbd97b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3016751007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3016751007
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1378113441
Short name T339
Test name
Test status
Simulation time 15516301655 ps
CPU time 41.37 seconds
Started Jul 19 05:39:27 PM PDT 24
Finished Jul 19 05:40:12 PM PDT 24
Peak memory 216808 kb
Host smart-fe538afd-0b63-4f32-be19-878e06431d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378113441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1378113441
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3507322321
Short name T763
Test name
Test status
Simulation time 8189901636 ps
CPU time 7.77 seconds
Started Jul 19 05:39:24 PM PDT 24
Finished Jul 19 05:39:34 PM PDT 24
Peak memory 216792 kb
Host smart-71fe4b57-8ff5-4784-bbf2-61b14c33c57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507322321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3507322321
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.613817920
Short name T7
Test name
Test status
Simulation time 391341247 ps
CPU time 2.64 seconds
Started Jul 19 05:39:26 PM PDT 24
Finished Jul 19 05:39:33 PM PDT 24
Peak memory 216672 kb
Host smart-5bad7906-9ca7-4203-aa3e-4506630b95b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613817920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.613817920
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1456495550
Short name T628
Test name
Test status
Simulation time 81641937 ps
CPU time 1.01 seconds
Started Jul 19 05:39:24 PM PDT 24
Finished Jul 19 05:39:28 PM PDT 24
Peak memory 207304 kb
Host smart-0c6d5554-a3ff-4e6c-8afd-c940f9fa5eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456495550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1456495550
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3657761483
Short name T209
Test name
Test status
Simulation time 4602550670 ps
CPU time 14.36 seconds
Started Jul 19 05:39:26 PM PDT 24
Finished Jul 19 05:39:44 PM PDT 24
Peak memory 225040 kb
Host smart-9932c591-57dd-46f2-b05a-a1bbea0cd86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657761483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3657761483
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3996565957
Short name T515
Test name
Test status
Simulation time 38545317 ps
CPU time 0.71 seconds
Started Jul 19 05:35:03 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 205740 kb
Host smart-aed4ae74-f1c6-4826-b22d-0afcc0a09108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996565957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
996565957
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2425844162
Short name T1035
Test name
Test status
Simulation time 32545996 ps
CPU time 2.57 seconds
Started Jul 19 05:35:03 PM PDT 24
Finished Jul 19 05:36:06 PM PDT 24
Peak memory 233128 kb
Host smart-860af952-0c63-4601-ba31-34228145e98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425844162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2425844162
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3300552752
Short name T1013
Test name
Test status
Simulation time 46752060 ps
CPU time 0.8 seconds
Started Jul 19 05:35:01 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 205760 kb
Host smart-b189f8e1-c451-4899-97f4-4f8fe0f3f7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300552752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3300552752
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.910665217
Short name T284
Test name
Test status
Simulation time 6276663550 ps
CPU time 59.19 seconds
Started Jul 19 05:35:03 PM PDT 24
Finished Jul 19 05:37:04 PM PDT 24
Peak memory 254064 kb
Host smart-6abadaf2-6eb0-4a34-8e7b-29e0ca5123da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910665217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.910665217
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2788821646
Short name T937
Test name
Test status
Simulation time 7060197600 ps
CPU time 93.4 seconds
Started Jul 19 05:35:03 PM PDT 24
Finished Jul 19 05:37:38 PM PDT 24
Peak memory 265920 kb
Host smart-b1482b68-6856-46c3-bb9f-d159ad03cddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788821646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2788821646
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3782686338
Short name T493
Test name
Test status
Simulation time 841316923 ps
CPU time 16.23 seconds
Started Jul 19 05:35:02 PM PDT 24
Finished Jul 19 05:36:19 PM PDT 24
Peak memory 224348 kb
Host smart-85e19b09-f797-4069-8a1c-a180f81afa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782686338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3782686338
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3630820444
Short name T319
Test name
Test status
Simulation time 14869857583 ps
CPU time 42.28 seconds
Started Jul 19 05:35:02 PM PDT 24
Finished Jul 19 05:36:45 PM PDT 24
Peak memory 251500 kb
Host smart-401d344b-443f-4c1b-a78a-6dbe1edb6bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630820444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3630820444
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.576831445
Short name T891
Test name
Test status
Simulation time 3572234171 ps
CPU time 60.19 seconds
Started Jul 19 05:35:02 PM PDT 24
Finished Jul 19 05:37:03 PM PDT 24
Peak memory 252404 kb
Host smart-5d060cdb-4e09-48d3-8588-4fe1b00b0e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576831445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
576831445
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2949397651
Short name T228
Test name
Test status
Simulation time 3834350913 ps
CPU time 12.83 seconds
Started Jul 19 05:35:01 PM PDT 24
Finished Jul 19 05:36:16 PM PDT 24
Peak memory 225040 kb
Host smart-6ffbc0f1-d7a2-4bdc-8ec6-b90a6686d2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949397651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2949397651
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2950956952
Short name T88
Test name
Test status
Simulation time 5094568524 ps
CPU time 40.95 seconds
Started Jul 19 05:35:00 PM PDT 24
Finished Jul 19 05:36:43 PM PDT 24
Peak memory 233268 kb
Host smart-193e98aa-888e-404b-a75b-8a0e087726c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950956952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2950956952
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4293271330
Short name T826
Test name
Test status
Simulation time 50753880 ps
CPU time 1.05 seconds
Started Jul 19 05:35:03 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 218368 kb
Host smart-c2b7822a-7c60-46e5-86bd-943d5b9d9424
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293271330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4293271330
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3593031125
Short name T488
Test name
Test status
Simulation time 351543591 ps
CPU time 3.64 seconds
Started Jul 19 05:35:02 PM PDT 24
Finished Jul 19 05:36:07 PM PDT 24
Peak memory 224904 kb
Host smart-978adb4b-861f-4c7b-86ca-02d350440f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593031125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3593031125
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.4138021553
Short name T403
Test name
Test status
Simulation time 9834971794 ps
CPU time 12.45 seconds
Started Jul 19 05:35:03 PM PDT 24
Finished Jul 19 05:36:17 PM PDT 24
Peak memory 241200 kb
Host smart-ccbb9c00-2645-47d9-83d9-a6589d61fef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138021553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4138021553
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1790368772
Short name T373
Test name
Test status
Simulation time 725582513 ps
CPU time 8.28 seconds
Started Jul 19 05:35:01 PM PDT 24
Finished Jul 19 05:36:11 PM PDT 24
Peak memory 220584 kb
Host smart-310335b8-1b11-4b2d-a2e7-4ccaedf4e364
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1790368772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1790368772
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.247922191
Short name T68
Test name
Test status
Simulation time 387137009 ps
CPU time 1.2 seconds
Started Jul 19 05:35:02 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 236784 kb
Host smart-4d9c8db0-f815-43cf-9755-496dea6ca504
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247922191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.247922191
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.570849548
Short name T385
Test name
Test status
Simulation time 12987918 ps
CPU time 0.74 seconds
Started Jul 19 05:35:03 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 206340 kb
Host smart-36ea69ba-c53e-4ea6-86db-aa9caa9dd688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570849548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.570849548
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3980122300
Short name T5
Test name
Test status
Simulation time 39179042049 ps
CPU time 21.7 seconds
Started Jul 19 05:35:03 PM PDT 24
Finished Jul 19 05:36:26 PM PDT 24
Peak memory 217860 kb
Host smart-4117e47a-0334-4c0e-bdfd-4a15e8dd9f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980122300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3980122300
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2522801325
Short name T46
Test name
Test status
Simulation time 1941038560 ps
CPU time 4.1 seconds
Started Jul 19 05:35:01 PM PDT 24
Finished Jul 19 05:36:07 PM PDT 24
Peak memory 216636 kb
Host smart-4f8cc911-b31e-4441-9ad5-a431d987a0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522801325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2522801325
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2068728851
Short name T600
Test name
Test status
Simulation time 69664727 ps
CPU time 0.98 seconds
Started Jul 19 05:35:03 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 206292 kb
Host smart-ff83b456-1105-438f-aeb4-206ec39e319b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068728851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2068728851
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3404761757
Short name T544
Test name
Test status
Simulation time 8931774703 ps
CPU time 33.74 seconds
Started Jul 19 05:35:02 PM PDT 24
Finished Jul 19 05:36:37 PM PDT 24
Peak memory 241420 kb
Host smart-36a337ab-a9dc-4fea-9b8b-cb2b60bde292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404761757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3404761757
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.750874072
Short name T1008
Test name
Test status
Simulation time 13107117 ps
CPU time 0.73 seconds
Started Jul 19 05:39:42 PM PDT 24
Finished Jul 19 05:39:50 PM PDT 24
Peak memory 205744 kb
Host smart-b2305b5b-5e7d-4091-9efe-c42d6358f64c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750874072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.750874072
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.180906030
Short name T639
Test name
Test status
Simulation time 825823971 ps
CPU time 6.02 seconds
Started Jul 19 05:39:32 PM PDT 24
Finished Jul 19 05:39:43 PM PDT 24
Peak memory 224908 kb
Host smart-07f6f399-db62-4e1a-8696-0a825c7dbc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180906030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.180906030
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1270718769
Short name T813
Test name
Test status
Simulation time 76553532 ps
CPU time 0.86 seconds
Started Jul 19 05:39:31 PM PDT 24
Finished Jul 19 05:39:36 PM PDT 24
Peak memory 206920 kb
Host smart-774e3737-f071-4417-a690-65c74048c873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270718769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1270718769
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.469174007
Short name T468
Test name
Test status
Simulation time 5658922872 ps
CPU time 52.17 seconds
Started Jul 19 05:39:42 PM PDT 24
Finished Jul 19 05:40:41 PM PDT 24
Peak memory 249668 kb
Host smart-3c3f0845-21d7-48f6-bdd5-435ad3ff3e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469174007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.469174007
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3174160510
Short name T143
Test name
Test status
Simulation time 9995922183 ps
CPU time 115.7 seconds
Started Jul 19 05:39:44 PM PDT 24
Finished Jul 19 05:41:47 PM PDT 24
Peak memory 257840 kb
Host smart-ab1dfd38-acf2-45c2-a809-039f5fe44119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174160510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3174160510
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3346405552
Short name T147
Test name
Test status
Simulation time 155126857029 ps
CPU time 136.2 seconds
Started Jul 19 05:39:41 PM PDT 24
Finished Jul 19 05:42:05 PM PDT 24
Peak memory 257680 kb
Host smart-8e777511-25a3-4591-9ab5-f47654b65368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346405552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3346405552
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2311537874
Short name T346
Test name
Test status
Simulation time 1568948856 ps
CPU time 13.07 seconds
Started Jul 19 05:39:47 PM PDT 24
Finished Jul 19 05:40:07 PM PDT 24
Peak memory 233184 kb
Host smart-a67b02a6-ff67-4b45-a9b9-41c751dc1702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311537874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2311537874
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3839257724
Short name T910
Test name
Test status
Simulation time 3237807926 ps
CPU time 20.41 seconds
Started Jul 19 05:39:42 PM PDT 24
Finished Jul 19 05:40:10 PM PDT 24
Peak memory 248984 kb
Host smart-edba2c36-3930-4c75-ac33-a3a6263f466e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839257724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3839257724
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4077385271
Short name T212
Test name
Test status
Simulation time 691722241 ps
CPU time 7.81 seconds
Started Jul 19 05:39:33 PM PDT 24
Finished Jul 19 05:39:45 PM PDT 24
Peak memory 233184 kb
Host smart-892d0e09-262d-4072-a0b1-e32ee280554b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077385271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4077385271
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1984058544
Short name T780
Test name
Test status
Simulation time 135277150 ps
CPU time 3.4 seconds
Started Jul 19 05:39:34 PM PDT 24
Finished Jul 19 05:39:44 PM PDT 24
Peak memory 224912 kb
Host smart-3fe37266-136c-42c6-b8f6-cfb3c410ab6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984058544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1984058544
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2279158448
Short name T636
Test name
Test status
Simulation time 35368305 ps
CPU time 2.84 seconds
Started Jul 19 05:39:29 PM PDT 24
Finished Jul 19 05:39:36 PM PDT 24
Peak memory 232856 kb
Host smart-ee4600b6-7ca5-44e4-9f07-0948b88ac20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279158448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2279158448
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.351487491
Short name T989
Test name
Test status
Simulation time 242284531 ps
CPU time 4.16 seconds
Started Jul 19 05:39:32 PM PDT 24
Finished Jul 19 05:39:40 PM PDT 24
Peak memory 224948 kb
Host smart-04995fd2-0e81-44e4-b773-ee0662157335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351487491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.351487491
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2848599691
Short name T36
Test name
Test status
Simulation time 5807979183 ps
CPU time 4.32 seconds
Started Jul 19 05:39:42 PM PDT 24
Finished Jul 19 05:39:54 PM PDT 24
Peak memory 220504 kb
Host smart-2396b9de-d574-47c1-80c2-b1a39d9c3158
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2848599691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2848599691
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4033128229
Short name T864
Test name
Test status
Simulation time 186154859543 ps
CPU time 555.51 seconds
Started Jul 19 05:39:42 PM PDT 24
Finished Jul 19 05:49:05 PM PDT 24
Peak memory 282240 kb
Host smart-21f3f00b-bb0a-46bd-bda8-311a6cec92d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033128229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4033128229
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.617118133
Short name T629
Test name
Test status
Simulation time 1473817396 ps
CPU time 15 seconds
Started Jul 19 05:39:35 PM PDT 24
Finished Jul 19 05:39:57 PM PDT 24
Peak memory 216924 kb
Host smart-9eeb2328-b8e5-4c79-98d6-a6a1ebbc27d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617118133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.617118133
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3667712555
Short name T939
Test name
Test status
Simulation time 13892720 ps
CPU time 0.71 seconds
Started Jul 19 05:39:33 PM PDT 24
Finished Jul 19 05:39:38 PM PDT 24
Peak memory 206032 kb
Host smart-885e2329-95fe-4eda-b8cc-5576c4e62b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667712555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3667712555
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1619428945
Short name T981
Test name
Test status
Simulation time 235212866 ps
CPU time 1.86 seconds
Started Jul 19 05:39:34 PM PDT 24
Finished Jul 19 05:39:42 PM PDT 24
Peak memory 216460 kb
Host smart-117b0fc2-b824-4334-98ba-c63788a6aded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619428945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1619428945
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3308872300
Short name T944
Test name
Test status
Simulation time 90014932 ps
CPU time 0.84 seconds
Started Jul 19 05:39:35 PM PDT 24
Finished Jul 19 05:39:42 PM PDT 24
Peak memory 206268 kb
Host smart-c0424cce-c45d-4376-b286-a86fe67a2b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308872300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3308872300
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.945167153
Short name T641
Test name
Test status
Simulation time 698400526 ps
CPU time 5.37 seconds
Started Jul 19 05:39:33 PM PDT 24
Finished Jul 19 05:39:44 PM PDT 24
Peak memory 238724 kb
Host smart-a2313d6c-6fd8-48e0-b7bf-ccb9a37de45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945167153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.945167153
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3003311240
Short name T799
Test name
Test status
Simulation time 13749458 ps
CPU time 0.73 seconds
Started Jul 19 05:39:50 PM PDT 24
Finished Jul 19 05:39:57 PM PDT 24
Peak memory 206088 kb
Host smart-634bcb84-27d4-4057-b4db-4c94b58634fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003311240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3003311240
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1757582190
Short name T686
Test name
Test status
Simulation time 2059999160 ps
CPU time 12.69 seconds
Started Jul 19 05:39:42 PM PDT 24
Finished Jul 19 05:40:02 PM PDT 24
Peak memory 224884 kb
Host smart-ba2e0360-5aef-4e42-adff-d1f0a1d6a010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757582190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1757582190
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3837525046
Short name T664
Test name
Test status
Simulation time 23201241 ps
CPU time 0.8 seconds
Started Jul 19 05:39:44 PM PDT 24
Finished Jul 19 05:39:52 PM PDT 24
Peak memory 207148 kb
Host smart-844d80ba-d2e1-4096-b56f-76ade3c5a585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837525046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3837525046
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1694077759
Short name T416
Test name
Test status
Simulation time 16802997533 ps
CPU time 126.58 seconds
Started Jul 19 05:39:51 PM PDT 24
Finished Jul 19 05:42:05 PM PDT 24
Peak memory 253572 kb
Host smart-25d3d0f3-b023-44c9-bfef-5bcf50b25580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694077759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1694077759
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2930914514
Short name T278
Test name
Test status
Simulation time 20890410032 ps
CPU time 115.23 seconds
Started Jul 19 05:39:53 PM PDT 24
Finished Jul 19 05:41:56 PM PDT 24
Peak memory 233308 kb
Host smart-9c08c33e-1c13-4300-9d6b-e5ce63fc7969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930914514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2930914514
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3673802286
Short name T224
Test name
Test status
Simulation time 15815040520 ps
CPU time 111.44 seconds
Started Jul 19 05:39:52 PM PDT 24
Finished Jul 19 05:41:50 PM PDT 24
Peak memory 273392 kb
Host smart-58df49a6-6dd9-47dd-b247-0ddecd3b15b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673802286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3673802286
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3641238765
Short name T759
Test name
Test status
Simulation time 651622968 ps
CPU time 7.95 seconds
Started Jul 19 05:39:41 PM PDT 24
Finished Jul 19 05:39:57 PM PDT 24
Peak memory 241356 kb
Host smart-135ee1cf-92a1-4d13-ac39-ab3c4ec1c3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641238765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3641238765
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.41019999
Short name T908
Test name
Test status
Simulation time 55746832151 ps
CPU time 364.55 seconds
Started Jul 19 05:39:42 PM PDT 24
Finished Jul 19 05:45:54 PM PDT 24
Peak memory 251264 kb
Host smart-61364edd-96c1-4864-a3ae-3616b2ec49ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41019999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.41019999
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1905160903
Short name T869
Test name
Test status
Simulation time 1979459753 ps
CPU time 16.47 seconds
Started Jul 19 05:39:47 PM PDT 24
Finished Jul 19 05:40:10 PM PDT 24
Peak memory 233164 kb
Host smart-61c61dd9-94d0-4ef1-924e-63dfe87a7ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905160903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1905160903
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1158429300
Short name T772
Test name
Test status
Simulation time 916294101 ps
CPU time 10.88 seconds
Started Jul 19 05:39:42 PM PDT 24
Finished Jul 19 05:40:00 PM PDT 24
Peak memory 224968 kb
Host smart-1be0f2a3-af7f-49b9-817a-a6adfd343ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158429300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1158429300
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2197862900
Short name T139
Test name
Test status
Simulation time 85797427713 ps
CPU time 21.06 seconds
Started Jul 19 05:39:42 PM PDT 24
Finished Jul 19 05:40:10 PM PDT 24
Peak memory 241412 kb
Host smart-e90f43cc-58c5-42ce-8c88-744ae3184c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197862900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2197862900
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3124437174
Short name T725
Test name
Test status
Simulation time 3016303256 ps
CPU time 15.18 seconds
Started Jul 19 05:39:47 PM PDT 24
Finished Jul 19 05:40:09 PM PDT 24
Peak memory 241232 kb
Host smart-f45bd7e0-eb9c-4ae3-b3db-5074163337bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124437174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3124437174
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.583923206
Short name T792
Test name
Test status
Simulation time 612858071 ps
CPU time 4.21 seconds
Started Jul 19 05:39:53 PM PDT 24
Finished Jul 19 05:40:05 PM PDT 24
Peak memory 222156 kb
Host smart-4487683a-88e4-4d83-a156-1a66a434155e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=583923206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.583923206
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2674316614
Short name T642
Test name
Test status
Simulation time 579117906 ps
CPU time 8.3 seconds
Started Jul 19 05:39:40 PM PDT 24
Finished Jul 19 05:39:56 PM PDT 24
Peak memory 216808 kb
Host smart-54628c95-4fc1-40d2-972c-2078d9ba57a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674316614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2674316614
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3055944956
Short name T804
Test name
Test status
Simulation time 885169281 ps
CPU time 6.56 seconds
Started Jul 19 05:39:44 PM PDT 24
Finished Jul 19 05:39:58 PM PDT 24
Peak memory 216656 kb
Host smart-f0b4322c-a127-47e0-be16-0498c6181b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055944956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3055944956
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3110322482
Short name T842
Test name
Test status
Simulation time 44068708 ps
CPU time 0.68 seconds
Started Jul 19 05:39:43 PM PDT 24
Finished Jul 19 05:39:51 PM PDT 24
Peak memory 205836 kb
Host smart-48c96fd4-75bb-40a6-ad6d-262e50d88580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110322482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3110322482
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1436437529
Short name T562
Test name
Test status
Simulation time 131722704 ps
CPU time 0.74 seconds
Started Jul 19 05:39:44 PM PDT 24
Finished Jul 19 05:39:52 PM PDT 24
Peak memory 206244 kb
Host smart-08d85e64-95cd-4ace-968f-8e875f989ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436437529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1436437529
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2958465457
Short name T905
Test name
Test status
Simulation time 4829934667 ps
CPU time 14.59 seconds
Started Jul 19 05:39:43 PM PDT 24
Finished Jul 19 05:40:04 PM PDT 24
Peak memory 233252 kb
Host smart-d99e29d6-be23-48cb-a105-0835f5e82b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958465457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2958465457
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2817744030
Short name T807
Test name
Test status
Simulation time 11685106 ps
CPU time 0.76 seconds
Started Jul 19 05:39:49 PM PDT 24
Finished Jul 19 05:39:57 PM PDT 24
Peak memory 205788 kb
Host smart-82d1b3d8-eb0f-4315-88fe-ab928537c9f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817744030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2817744030
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4003919905
Short name T571
Test name
Test status
Simulation time 460361718 ps
CPU time 2.36 seconds
Started Jul 19 05:39:51 PM PDT 24
Finished Jul 19 05:40:00 PM PDT 24
Peak memory 224656 kb
Host smart-d5ea9afb-919d-463d-87c7-18fffd2fb50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003919905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4003919905
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2263040033
Short name T348
Test name
Test status
Simulation time 108442931 ps
CPU time 0.76 seconds
Started Jul 19 05:39:51 PM PDT 24
Finished Jul 19 05:39:59 PM PDT 24
Peak memory 206900 kb
Host smart-bbbc91ac-bd5d-442c-83fd-c0e673818055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263040033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2263040033
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2469849168
Short name T178
Test name
Test status
Simulation time 8424315255 ps
CPU time 29.93 seconds
Started Jul 19 05:39:52 PM PDT 24
Finished Jul 19 05:40:30 PM PDT 24
Peak memory 253360 kb
Host smart-17595aa5-a338-464d-ac94-f3fff4c69da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469849168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2469849168
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4036595639
Short name T920
Test name
Test status
Simulation time 2049668862 ps
CPU time 28.59 seconds
Started Jul 19 05:39:51 PM PDT 24
Finished Jul 19 05:40:26 PM PDT 24
Peak memory 233208 kb
Host smart-4a598ff3-fbe3-43bc-843c-78454972bbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036595639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4036595639
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4138616150
Short name T218
Test name
Test status
Simulation time 15752551925 ps
CPU time 127.05 seconds
Started Jul 19 05:39:57 PM PDT 24
Finished Jul 19 05:42:11 PM PDT 24
Peak memory 265072 kb
Host smart-5a7711d7-a0ac-4e13-bfa0-96e6ea5c8005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138616150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4138616150
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1643403555
Short name T1029
Test name
Test status
Simulation time 5320896910 ps
CPU time 11.82 seconds
Started Jul 19 05:39:49 PM PDT 24
Finished Jul 19 05:40:08 PM PDT 24
Peak memory 233308 kb
Host smart-48abe7c9-02d3-4edc-886d-5be042980a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643403555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1643403555
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3399231640
Short name T923
Test name
Test status
Simulation time 21409368782 ps
CPU time 41.44 seconds
Started Jul 19 05:39:52 PM PDT 24
Finished Jul 19 05:40:41 PM PDT 24
Peak memory 250664 kb
Host smart-03c24999-d228-491e-bddb-4c8291f8acda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399231640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3399231640
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3306904664
Short name T928
Test name
Test status
Simulation time 245271515 ps
CPU time 5.61 seconds
Started Jul 19 05:39:51 PM PDT 24
Finished Jul 19 05:40:04 PM PDT 24
Peak memory 233080 kb
Host smart-84b12056-28ba-4299-b48c-3400272e2ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306904664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3306904664
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1160035146
Short name T472
Test name
Test status
Simulation time 2928540959 ps
CPU time 30.11 seconds
Started Jul 19 05:39:49 PM PDT 24
Finished Jul 19 05:40:27 PM PDT 24
Peak memory 233364 kb
Host smart-e4a6442a-fcea-4a98-98fb-b06c7963ca48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160035146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1160035146
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.596822340
Short name T574
Test name
Test status
Simulation time 19979381649 ps
CPU time 17.32 seconds
Started Jul 19 05:39:51 PM PDT 24
Finished Jul 19 05:40:15 PM PDT 24
Peak memory 233304 kb
Host smart-8e6722ba-a229-46bf-a4e0-6e779590045c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596822340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.596822340
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.902473215
Short name T502
Test name
Test status
Simulation time 7443333004 ps
CPU time 9.21 seconds
Started Jul 19 05:39:50 PM PDT 24
Finished Jul 19 05:40:06 PM PDT 24
Peak memory 225052 kb
Host smart-1621e250-b3fc-4fe4-81db-2d3bdb9f426e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902473215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.902473215
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3906487706
Short name T443
Test name
Test status
Simulation time 228001524 ps
CPU time 4.84 seconds
Started Jul 19 05:39:53 PM PDT 24
Finished Jul 19 05:40:06 PM PDT 24
Peak memory 223284 kb
Host smart-173dc729-a1f8-4745-9a5e-6f22cb27dd90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3906487706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3906487706
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1735296877
Short name T171
Test name
Test status
Simulation time 54639797633 ps
CPU time 425.22 seconds
Started Jul 19 05:39:50 PM PDT 24
Finished Jul 19 05:47:03 PM PDT 24
Peak memory 269444 kb
Host smart-eb16c16b-7c72-4670-b969-a72e7bf3b1ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735296877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1735296877
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.108362551
Short name T331
Test name
Test status
Simulation time 7788167747 ps
CPU time 44.91 seconds
Started Jul 19 05:39:51 PM PDT 24
Finished Jul 19 05:40:43 PM PDT 24
Peak memory 216824 kb
Host smart-71b65b79-9cdd-48f2-be5d-fea656ffe238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108362551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.108362551
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.840421751
Short name T501
Test name
Test status
Simulation time 42955840850 ps
CPU time 12.42 seconds
Started Jul 19 05:39:51 PM PDT 24
Finished Jul 19 05:40:10 PM PDT 24
Peak memory 217880 kb
Host smart-c4409e65-7d96-4af5-8363-1f6fc34c9038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840421751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.840421751
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2514935772
Short name T6
Test name
Test status
Simulation time 210079664 ps
CPU time 1.14 seconds
Started Jul 19 05:39:52 PM PDT 24
Finished Jul 19 05:40:00 PM PDT 24
Peak memory 208264 kb
Host smart-89ef7a32-e11b-44ab-8876-b2337d469f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514935772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2514935772
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1273460112
Short name T410
Test name
Test status
Simulation time 114277820 ps
CPU time 0.75 seconds
Started Jul 19 05:39:50 PM PDT 24
Finished Jul 19 05:39:57 PM PDT 24
Peak memory 206292 kb
Host smart-172984da-7c46-44fb-822c-f50cd9f48d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273460112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1273460112
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.793427954
Short name T371
Test name
Test status
Simulation time 154459808 ps
CPU time 2.66 seconds
Started Jul 19 05:39:51 PM PDT 24
Finished Jul 19 05:40:01 PM PDT 24
Peak memory 224608 kb
Host smart-359b3629-b71c-4c92-969c-839adbf9d82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793427954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.793427954
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3790096102
Short name T473
Test name
Test status
Simulation time 35401351 ps
CPU time 0.68 seconds
Started Jul 19 05:40:11 PM PDT 24
Finished Jul 19 05:40:22 PM PDT 24
Peak memory 205752 kb
Host smart-ddad2351-b301-4d79-b50c-80a5dff008c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790096102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3790096102
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2114439940
Short name T771
Test name
Test status
Simulation time 151958848 ps
CPU time 2.83 seconds
Started Jul 19 05:39:59 PM PDT 24
Finished Jul 19 05:40:08 PM PDT 24
Peak memory 224996 kb
Host smart-ef683ac7-e924-4d47-8294-c0d0d0d0390b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114439940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2114439940
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4015515761
Short name T437
Test name
Test status
Simulation time 29527321 ps
CPU time 0.77 seconds
Started Jul 19 05:39:52 PM PDT 24
Finished Jul 19 05:40:00 PM PDT 24
Peak memory 207188 kb
Host smart-3bbf9c9b-7961-41d9-8c42-711d63b492fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015515761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4015515761
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1836056855
Short name T24
Test name
Test status
Simulation time 96776690692 ps
CPU time 166.61 seconds
Started Jul 19 05:39:59 PM PDT 24
Finished Jul 19 05:42:52 PM PDT 24
Peak memory 239636 kb
Host smart-88df20c2-162c-41d5-aaeb-847a7c148da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836056855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1836056855
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3349280158
Short name T809
Test name
Test status
Simulation time 58992624846 ps
CPU time 256.76 seconds
Started Jul 19 05:40:00 PM PDT 24
Finished Jul 19 05:44:22 PM PDT 24
Peak memory 266048 kb
Host smart-f744daeb-3e2b-41bd-87f0-588bcd799664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349280158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3349280158
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3373668288
Short name T327
Test name
Test status
Simulation time 1392171957 ps
CPU time 10.51 seconds
Started Jul 19 05:40:00 PM PDT 24
Finished Jul 19 05:40:16 PM PDT 24
Peak memory 253148 kb
Host smart-79bbd4be-658c-4cb4-b6ed-ab334a034371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373668288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3373668288
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3067229766
Short name T1010
Test name
Test status
Simulation time 6782574117 ps
CPU time 24.22 seconds
Started Jul 19 05:39:58 PM PDT 24
Finished Jul 19 05:40:28 PM PDT 24
Peak memory 236796 kb
Host smart-4d753fa3-f470-4896-800b-fb36ed5151fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067229766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3067229766
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1217458733
Short name T710
Test name
Test status
Simulation time 2824076315 ps
CPU time 6.05 seconds
Started Jul 19 05:40:10 PM PDT 24
Finished Jul 19 05:40:25 PM PDT 24
Peak memory 225016 kb
Host smart-080f045b-df2c-41b0-9b36-b846c13dcddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217458733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1217458733
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3637721071
Short name T718
Test name
Test status
Simulation time 1063158197 ps
CPU time 15.12 seconds
Started Jul 19 05:40:00 PM PDT 24
Finished Jul 19 05:40:21 PM PDT 24
Peak memory 234240 kb
Host smart-3c7c1ca3-339a-43dd-b40c-156a7a8f93a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637721071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3637721071
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.174539751
Short name T534
Test name
Test status
Simulation time 522105248 ps
CPU time 3.39 seconds
Started Jul 19 05:39:58 PM PDT 24
Finished Jul 19 05:40:08 PM PDT 24
Peak memory 224880 kb
Host smart-4c2aa9d9-d551-4a8d-88e7-8443870ee0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174539751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.174539751
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1619036135
Short name T536
Test name
Test status
Simulation time 3598044372 ps
CPU time 15.58 seconds
Started Jul 19 05:40:01 PM PDT 24
Finished Jul 19 05:40:21 PM PDT 24
Peak memory 249508 kb
Host smart-68e59fd4-2d00-4ac2-af61-1494068d8fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619036135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1619036135
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4194815123
Short name T372
Test name
Test status
Simulation time 544424771 ps
CPU time 3.93 seconds
Started Jul 19 05:39:59 PM PDT 24
Finished Jul 19 05:40:09 PM PDT 24
Peak memory 223372 kb
Host smart-566008d1-7a8c-411e-b1b2-8262f07ac0ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4194815123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4194815123
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3642626385
Short name T998
Test name
Test status
Simulation time 12929370001 ps
CPU time 72.94 seconds
Started Jul 19 05:39:59 PM PDT 24
Finished Jul 19 05:41:18 PM PDT 24
Peak memory 256312 kb
Host smart-fd28f8d5-8376-441a-8eb9-5834eb5ed8b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642626385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3642626385
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3612597463
Short name T1032
Test name
Test status
Simulation time 2950949598 ps
CPU time 17.13 seconds
Started Jul 19 05:39:52 PM PDT 24
Finished Jul 19 05:40:16 PM PDT 24
Peak memory 216776 kb
Host smart-1f18f502-33e5-428d-a00c-dfca93e000cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612597463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3612597463
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3562980255
Short name T476
Test name
Test status
Simulation time 3361799921 ps
CPU time 3.49 seconds
Started Jul 19 05:39:50 PM PDT 24
Finished Jul 19 05:40:01 PM PDT 24
Peak memory 216828 kb
Host smart-d7a2ec97-2c82-425f-a863-276f5fee41ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562980255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3562980255
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2973123467
Short name T1033
Test name
Test status
Simulation time 32120483 ps
CPU time 0.75 seconds
Started Jul 19 05:39:58 PM PDT 24
Finished Jul 19 05:40:05 PM PDT 24
Peak memory 205952 kb
Host smart-fb477700-d136-40c2-b60f-ac9aa9de08a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973123467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2973123467
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2203168918
Short name T417
Test name
Test status
Simulation time 127647018 ps
CPU time 0.84 seconds
Started Jul 19 05:40:01 PM PDT 24
Finished Jul 19 05:40:07 PM PDT 24
Peak memory 206336 kb
Host smart-e76c6ddd-5f96-4884-8078-58e7dc660684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203168918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2203168918
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1270121365
Short name T754
Test name
Test status
Simulation time 266614506 ps
CPU time 3.93 seconds
Started Jul 19 05:39:57 PM PDT 24
Finished Jul 19 05:40:08 PM PDT 24
Peak memory 224920 kb
Host smart-d03ee0c9-52b9-4e5c-b5f0-fcc82d13607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270121365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1270121365
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3021549385
Short name T386
Test name
Test status
Simulation time 53339266 ps
CPU time 0.74 seconds
Started Jul 19 05:40:10 PM PDT 24
Finished Jul 19 05:40:18 PM PDT 24
Peak memory 205180 kb
Host smart-1fe7500f-73d2-4083-98af-dce9f02498b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021549385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3021549385
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2491801443
Short name T617
Test name
Test status
Simulation time 359557516 ps
CPU time 6.57 seconds
Started Jul 19 05:39:58 PM PDT 24
Finished Jul 19 05:40:11 PM PDT 24
Peak memory 233136 kb
Host smart-e8098e5c-a10d-4055-8396-eb355d65f773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491801443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2491801443
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.4027245807
Short name T720
Test name
Test status
Simulation time 17134826 ps
CPU time 0.79 seconds
Started Jul 19 05:40:01 PM PDT 24
Finished Jul 19 05:40:07 PM PDT 24
Peak memory 206792 kb
Host smart-61c6ef0e-f8be-4064-9cf3-5e321900081d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027245807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.4027245807
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.789004061
Short name T318
Test name
Test status
Simulation time 20402628609 ps
CPU time 101.92 seconds
Started Jul 19 05:39:59 PM PDT 24
Finished Jul 19 05:41:47 PM PDT 24
Peak memory 257848 kb
Host smart-c6697e21-3921-4c0b-bdc7-2ded648a2f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789004061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.789004061
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.4124289254
Short name T303
Test name
Test status
Simulation time 125737297504 ps
CPU time 333.68 seconds
Started Jul 19 05:39:58 PM PDT 24
Finished Jul 19 05:45:38 PM PDT 24
Peak memory 257872 kb
Host smart-d75a5b87-6d18-455d-9c16-d023d7b85d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124289254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4124289254
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.201377738
Short name T180
Test name
Test status
Simulation time 2298538615 ps
CPU time 48.07 seconds
Started Jul 19 05:40:13 PM PDT 24
Finished Jul 19 05:41:09 PM PDT 24
Peak memory 241472 kb
Host smart-daed5976-3f94-4487-b32f-c805261c0309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201377738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.201377738
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.174052093
Short name T357
Test name
Test status
Simulation time 512526613 ps
CPU time 12.39 seconds
Started Jul 19 05:39:57 PM PDT 24
Finished Jul 19 05:40:17 PM PDT 24
Peak memory 241340 kb
Host smart-309deddd-bcb2-48f1-af1f-12f5d7b4649d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174052093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.174052093
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.300981518
Short name T276
Test name
Test status
Simulation time 2165983641 ps
CPU time 25.82 seconds
Started Jul 19 05:39:59 PM PDT 24
Finished Jul 19 05:40:30 PM PDT 24
Peak memory 249608 kb
Host smart-8879ee98-fde4-4b62-a50f-0a740643b577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300981518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.300981518
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3609486857
Short name T383
Test name
Test status
Simulation time 2245832239 ps
CPU time 24.18 seconds
Started Jul 19 05:40:10 PM PDT 24
Finished Jul 19 05:40:43 PM PDT 24
Peak memory 225016 kb
Host smart-157e56a9-e103-44fa-b04f-cfd52a5d0a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609486857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3609486857
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2364076798
Short name T606
Test name
Test status
Simulation time 2012206526 ps
CPU time 7.22 seconds
Started Jul 19 05:40:10 PM PDT 24
Finished Jul 19 05:40:30 PM PDT 24
Peak memory 240784 kb
Host smart-90dc477c-6fba-4ff3-80c6-053e638f4d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364076798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2364076798
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1119155837
Short name T954
Test name
Test status
Simulation time 721951504 ps
CPU time 3.34 seconds
Started Jul 19 05:39:59 PM PDT 24
Finished Jul 19 05:40:08 PM PDT 24
Peak memory 224956 kb
Host smart-ee23c9af-229a-4c96-a132-863927bcdbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119155837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1119155837
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1463889785
Short name T453
Test name
Test status
Simulation time 9975873203 ps
CPU time 7.76 seconds
Started Jul 19 05:40:03 PM PDT 24
Finished Jul 19 05:40:15 PM PDT 24
Peak memory 239980 kb
Host smart-90aa22a3-265b-4665-8166-192beed81c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463889785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1463889785
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2632775087
Short name T156
Test name
Test status
Simulation time 185720167 ps
CPU time 4.17 seconds
Started Jul 19 05:40:00 PM PDT 24
Finished Jul 19 05:40:09 PM PDT 24
Peak memory 223212 kb
Host smart-ae41966d-74e8-41d8-8b87-74ec5295470a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2632775087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2632775087
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2450496985
Short name T964
Test name
Test status
Simulation time 2778194315 ps
CPU time 81.16 seconds
Started Jul 19 05:40:09 PM PDT 24
Finished Jul 19 05:41:37 PM PDT 24
Peak memory 254896 kb
Host smart-f591c692-cb73-49e5-95ed-910870d0e913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450496985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2450496985
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2734916752
Short name T684
Test name
Test status
Simulation time 22620122837 ps
CPU time 15.87 seconds
Started Jul 19 05:39:59 PM PDT 24
Finished Jul 19 05:40:21 PM PDT 24
Peak memory 216764 kb
Host smart-c6de554d-63dd-427f-b0e4-c89f7c50b81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734916752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2734916752
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1562944842
Short name T86
Test name
Test status
Simulation time 6917078000 ps
CPU time 10.45 seconds
Started Jul 19 05:40:00 PM PDT 24
Finished Jul 19 05:40:16 PM PDT 24
Peak memory 216836 kb
Host smart-14b515f2-e2e9-4068-82cd-523d03b5edec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562944842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1562944842
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.337058277
Short name T545
Test name
Test status
Simulation time 414154173 ps
CPU time 6.15 seconds
Started Jul 19 05:39:58 PM PDT 24
Finished Jul 19 05:40:10 PM PDT 24
Peak memory 216728 kb
Host smart-18aaccac-8c40-467a-b35d-d03c9d0713d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337058277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.337058277
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.369142580
Short name T858
Test name
Test status
Simulation time 120184718 ps
CPU time 0.91 seconds
Started Jul 19 05:40:02 PM PDT 24
Finished Jul 19 05:40:08 PM PDT 24
Peak memory 207308 kb
Host smart-2509a984-23cc-4436-af62-329442fc4267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369142580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.369142580
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3525310977
Short name T394
Test name
Test status
Simulation time 45820320458 ps
CPU time 36.68 seconds
Started Jul 19 05:40:10 PM PDT 24
Finished Jul 19 05:40:55 PM PDT 24
Peak memory 240976 kb
Host smart-11ddc4a0-c3e7-4758-997f-3a227ae4073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525310977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3525310977
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1355154873
Short name T645
Test name
Test status
Simulation time 14653596 ps
CPU time 0.72 seconds
Started Jul 19 05:40:09 PM PDT 24
Finished Jul 19 05:40:17 PM PDT 24
Peak memory 205744 kb
Host smart-280605e4-00fc-4943-b9a6-85d0512d534b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355154873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1355154873
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3109018790
Short name T425
Test name
Test status
Simulation time 1045562082 ps
CPU time 7.17 seconds
Started Jul 19 05:40:09 PM PDT 24
Finished Jul 19 05:40:24 PM PDT 24
Peak memory 233096 kb
Host smart-5bedfc4f-ba9d-4e73-bba6-078e45bf385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109018790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3109018790
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.979924043
Short name T351
Test name
Test status
Simulation time 111325638 ps
CPU time 0.76 seconds
Started Jul 19 05:40:07 PM PDT 24
Finished Jul 19 05:40:14 PM PDT 24
Peak memory 206836 kb
Host smart-bde5789f-a245-48ae-8162-3390de657ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979924043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.979924043
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.588055265
Short name T980
Test name
Test status
Simulation time 19357097199 ps
CPU time 82.4 seconds
Started Jul 19 05:40:11 PM PDT 24
Finished Jul 19 05:41:41 PM PDT 24
Peak memory 249700 kb
Host smart-2741b31b-6182-4887-ab11-523962b4f25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588055265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.588055265
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.577890461
Short name T549
Test name
Test status
Simulation time 2397732808 ps
CPU time 13.67 seconds
Started Jul 19 05:40:10 PM PDT 24
Finished Jul 19 05:40:30 PM PDT 24
Peak memory 218228 kb
Host smart-8987343b-8791-49d0-bf62-f0aa59ab3f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577890461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.577890461
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3226896085
Short name T683
Test name
Test status
Simulation time 2531779598 ps
CPU time 26.25 seconds
Started Jul 19 05:40:09 PM PDT 24
Finished Jul 19 05:40:42 PM PDT 24
Peak memory 249724 kb
Host smart-200b4d14-d0e2-4475-9b50-5ba4293bcdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226896085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3226896085
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2200427901
Short name T695
Test name
Test status
Simulation time 21078311287 ps
CPU time 100.46 seconds
Started Jul 19 05:40:08 PM PDT 24
Finished Jul 19 05:41:55 PM PDT 24
Peak memory 253660 kb
Host smart-40100b27-de07-44c6-9790-f1c7157cd73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200427901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2200427901
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2996513397
Short name T855
Test name
Test status
Simulation time 202597741 ps
CPU time 4.31 seconds
Started Jul 19 05:40:08 PM PDT 24
Finished Jul 19 05:40:20 PM PDT 24
Peak memory 224876 kb
Host smart-8ae6a07d-be2a-466f-bdf1-d7e85fe7c209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996513397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2996513397
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4042550978
Short name T661
Test name
Test status
Simulation time 685320907 ps
CPU time 10.72 seconds
Started Jul 19 05:40:11 PM PDT 24
Finished Jul 19 05:40:29 PM PDT 24
Peak memory 224952 kb
Host smart-444af5cf-9d80-4b64-9a19-a507cb4ce88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042550978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4042550978
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2148138280
Short name T714
Test name
Test status
Simulation time 1166753046 ps
CPU time 3.45 seconds
Started Jul 19 05:40:08 PM PDT 24
Finished Jul 19 05:40:17 PM PDT 24
Peak memory 233176 kb
Host smart-ca476df1-ae14-41c6-a5ea-a2edac2c0813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148138280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2148138280
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1656472187
Short name T885
Test name
Test status
Simulation time 104850931 ps
CPU time 2.7 seconds
Started Jul 19 05:40:13 PM PDT 24
Finished Jul 19 05:40:24 PM PDT 24
Peak memory 233112 kb
Host smart-59312838-131a-4bcf-8ace-91230c834aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656472187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1656472187
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.766530079
Short name T538
Test name
Test status
Simulation time 480068397 ps
CPU time 6.66 seconds
Started Jul 19 05:40:09 PM PDT 24
Finished Jul 19 05:40:23 PM PDT 24
Peak memory 219676 kb
Host smart-9f397e3f-0fc5-4485-80fa-a3df27a93b8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=766530079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.766530079
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1195451610
Short name T77
Test name
Test status
Simulation time 44173078 ps
CPU time 0.98 seconds
Started Jul 19 05:40:07 PM PDT 24
Finished Jul 19 05:40:15 PM PDT 24
Peak memory 207384 kb
Host smart-356ac233-3174-457c-85f2-a56202aba7ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195451610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1195451610
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3877095768
Short name T428
Test name
Test status
Simulation time 6237463075 ps
CPU time 34.41 seconds
Started Jul 19 05:40:13 PM PDT 24
Finished Jul 19 05:40:55 PM PDT 24
Peak memory 216924 kb
Host smart-7377113b-4c25-40fc-bf08-1e12aa918d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877095768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3877095768
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2740365293
Short name T676
Test name
Test status
Simulation time 4949598684 ps
CPU time 11.01 seconds
Started Jul 19 05:40:12 PM PDT 24
Finished Jul 19 05:40:32 PM PDT 24
Peak memory 216848 kb
Host smart-b2d1c73e-4eea-4fb9-a053-e703d97dea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740365293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2740365293
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.816339597
Short name T418
Test name
Test status
Simulation time 15221286 ps
CPU time 0.71 seconds
Started Jul 19 05:40:09 PM PDT 24
Finished Jul 19 05:40:17 PM PDT 24
Peak memory 205968 kb
Host smart-d5b33e46-5cf3-46cd-8fda-069a260ab945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816339597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.816339597
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.769489284
Short name T407
Test name
Test status
Simulation time 150421331 ps
CPU time 0.95 seconds
Started Jul 19 05:40:14 PM PDT 24
Finished Jul 19 05:40:23 PM PDT 24
Peak memory 207256 kb
Host smart-7549e886-16ab-4948-af3b-03e20662dd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769489284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.769489284
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.4011613074
Short name T739
Test name
Test status
Simulation time 15018261204 ps
CPU time 16.19 seconds
Started Jul 19 05:40:10 PM PDT 24
Finished Jul 19 05:40:33 PM PDT 24
Peak memory 233244 kb
Host smart-48a11184-6227-46f0-bafe-9dc5ebde864f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011613074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.4011613074
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1485198423
Short name T914
Test name
Test status
Simulation time 19199635 ps
CPU time 0.71 seconds
Started Jul 19 05:40:17 PM PDT 24
Finished Jul 19 05:40:24 PM PDT 24
Peak memory 205752 kb
Host smart-de3d94d1-14da-4359-ba0b-0208a625ecdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485198423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1485198423
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.238782466
Short name T590
Test name
Test status
Simulation time 146634105 ps
CPU time 2.73 seconds
Started Jul 19 05:40:17 PM PDT 24
Finished Jul 19 05:40:26 PM PDT 24
Peak memory 233156 kb
Host smart-6775f1fc-04e1-48f2-ad1c-96aa609e63de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238782466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.238782466
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3596025316
Short name T623
Test name
Test status
Simulation time 157106167 ps
CPU time 0.81 seconds
Started Jul 19 05:40:08 PM PDT 24
Finished Jul 19 05:40:16 PM PDT 24
Peak memory 206896 kb
Host smart-4292d8b1-3001-40d4-874c-d964691ad831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596025316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3596025316
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4184082266
Short name T781
Test name
Test status
Simulation time 185507188852 ps
CPU time 227.89 seconds
Started Jul 19 05:40:18 PM PDT 24
Finished Jul 19 05:44:12 PM PDT 24
Peak memory 249768 kb
Host smart-6ab87fd4-c6cc-450f-ac5c-4233aea38cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184082266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4184082266
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4020811149
Short name T952
Test name
Test status
Simulation time 2813931041 ps
CPU time 19.38 seconds
Started Jul 19 05:40:16 PM PDT 24
Finished Jul 19 05:40:43 PM PDT 24
Peak memory 225076 kb
Host smart-36b97eac-929e-466f-973f-636acecbbe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020811149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4020811149
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.762284197
Short name T201
Test name
Test status
Simulation time 46168259775 ps
CPU time 53.62 seconds
Started Jul 19 05:40:17 PM PDT 24
Finished Jul 19 05:41:17 PM PDT 24
Peak memory 249656 kb
Host smart-a581716d-07a4-41bb-a2fd-55cef01dc9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762284197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.762284197
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1673044109
Short name T673
Test name
Test status
Simulation time 670867085 ps
CPU time 5.76 seconds
Started Jul 19 05:40:15 PM PDT 24
Finished Jul 19 05:40:29 PM PDT 24
Peak memory 224936 kb
Host smart-4a3aee14-b1ab-46ad-8626-6ff95f88c90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673044109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1673044109
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2383667158
Short name T235
Test name
Test status
Simulation time 104925805531 ps
CPU time 92.33 seconds
Started Jul 19 05:40:18 PM PDT 24
Finished Jul 19 05:41:56 PM PDT 24
Peak memory 235604 kb
Host smart-9b7188d3-30b1-47de-910f-73001406c1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383667158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2383667158
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1699504375
Short name T469
Test name
Test status
Simulation time 2116293324 ps
CPU time 8.79 seconds
Started Jul 19 05:40:16 PM PDT 24
Finished Jul 19 05:40:32 PM PDT 24
Peak memory 234032 kb
Host smart-4004fbe2-160e-4f4c-966f-d0cc4819733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699504375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1699504375
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2176968129
Short name T454
Test name
Test status
Simulation time 1930266662 ps
CPU time 6.3 seconds
Started Jul 19 05:40:13 PM PDT 24
Finished Jul 19 05:40:28 PM PDT 24
Peak memory 224936 kb
Host smart-f1746607-b74d-4e5c-954f-4698d2b9c061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176968129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2176968129
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1324027286
Short name T912
Test name
Test status
Simulation time 624930580 ps
CPU time 6.6 seconds
Started Jul 19 05:40:19 PM PDT 24
Finished Jul 19 05:40:31 PM PDT 24
Peak memory 222480 kb
Host smart-19e12061-6e88-4878-9031-30218bc42794
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1324027286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1324027286
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1069099608
Short name T951
Test name
Test status
Simulation time 15538183390 ps
CPU time 81.99 seconds
Started Jul 19 05:40:19 PM PDT 24
Finished Jul 19 05:41:46 PM PDT 24
Peak memory 225164 kb
Host smart-9e84e6ab-3a29-408a-804c-0469afc8ec72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069099608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1069099608
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3866992071
Short name T992
Test name
Test status
Simulation time 664630820 ps
CPU time 2.76 seconds
Started Jul 19 05:40:11 PM PDT 24
Finished Jul 19 05:40:22 PM PDT 24
Peak memory 216632 kb
Host smart-2c66c988-09f9-444f-83b3-a71d677fe6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866992071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3866992071
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2568940236
Short name T707
Test name
Test status
Simulation time 3442562066 ps
CPU time 6.21 seconds
Started Jul 19 05:40:13 PM PDT 24
Finished Jul 19 05:40:27 PM PDT 24
Peak memory 216764 kb
Host smart-bd6b73a1-68ad-4140-990b-c6741d8b2824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568940236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2568940236
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1951108552
Short name T375
Test name
Test status
Simulation time 558478611 ps
CPU time 8.03 seconds
Started Jul 19 05:40:08 PM PDT 24
Finished Jul 19 05:40:24 PM PDT 24
Peak memory 216652 kb
Host smart-9ef11f61-d51a-48dd-b700-300897e312a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951108552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1951108552
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3586943236
Short name T738
Test name
Test status
Simulation time 15988344 ps
CPU time 0.74 seconds
Started Jul 19 05:40:12 PM PDT 24
Finished Jul 19 05:40:21 PM PDT 24
Peak memory 206272 kb
Host smart-e6f6bfe1-2c58-42e6-982c-14c6c47bbdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586943236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3586943236
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.507962338
Short name T509
Test name
Test status
Simulation time 30208230655 ps
CPU time 21.49 seconds
Started Jul 19 05:40:18 PM PDT 24
Finished Jul 19 05:40:46 PM PDT 24
Peak memory 225072 kb
Host smart-f40da1de-1a25-41f1-bb13-eec7cbfef9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507962338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.507962338
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2799812297
Short name T749
Test name
Test status
Simulation time 12778800 ps
CPU time 0.71 seconds
Started Jul 19 05:40:25 PM PDT 24
Finished Jul 19 05:40:27 PM PDT 24
Peak memory 205168 kb
Host smart-b4c02202-1e5e-40f4-9e58-7761e6941ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799812297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2799812297
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3482160092
Short name T487
Test name
Test status
Simulation time 125959619 ps
CPU time 2.57 seconds
Started Jul 19 05:40:19 PM PDT 24
Finished Jul 19 05:40:27 PM PDT 24
Peak memory 224928 kb
Host smart-deb1f8c3-269b-4a85-8b46-a138d1d5ebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482160092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3482160092
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.348941480
Short name T721
Test name
Test status
Simulation time 23196027 ps
CPU time 0.82 seconds
Started Jul 19 05:40:17 PM PDT 24
Finished Jul 19 05:40:24 PM PDT 24
Peak memory 206896 kb
Host smart-0daf86b3-e059-4b98-9870-a73341699d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348941480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.348941480
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.406438148
Short name T300
Test name
Test status
Simulation time 3107115329 ps
CPU time 56.44 seconds
Started Jul 19 05:40:27 PM PDT 24
Finished Jul 19 05:41:25 PM PDT 24
Peak memory 252636 kb
Host smart-ebfcbb65-d842-4647-bba7-f3a615b1acd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406438148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.406438148
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3522735768
Short name T47
Test name
Test status
Simulation time 23453994489 ps
CPU time 226.06 seconds
Started Jul 19 05:40:27 PM PDT 24
Finished Jul 19 05:44:15 PM PDT 24
Peak memory 253972 kb
Host smart-d29b0873-0d00-446d-9163-6b477ed74b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522735768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3522735768
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4124851032
Short name T888
Test name
Test status
Simulation time 29304155839 ps
CPU time 217.53 seconds
Started Jul 19 05:40:24 PM PDT 24
Finished Jul 19 05:44:04 PM PDT 24
Peak memory 251924 kb
Host smart-a7ef14c5-4904-413e-a883-f9ddfc2750f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124851032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4124851032
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.167367644
Short name T719
Test name
Test status
Simulation time 1805118106 ps
CPU time 9.09 seconds
Started Jul 19 05:40:28 PM PDT 24
Finished Jul 19 05:40:38 PM PDT 24
Peak memory 233180 kb
Host smart-f3197c4b-e175-4adc-b1db-dfdb6c305313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167367644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.167367644
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2044279331
Short name T316
Test name
Test status
Simulation time 3133494556 ps
CPU time 57.96 seconds
Started Jul 19 05:40:30 PM PDT 24
Finished Jul 19 05:41:30 PM PDT 24
Peak memory 248892 kb
Host smart-fc4439c3-dbf8-4df2-b0eb-e871f88a25ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044279331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2044279331
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.532573043
Short name T217
Test name
Test status
Simulation time 6922741557 ps
CPU time 8.35 seconds
Started Jul 19 05:40:17 PM PDT 24
Finished Jul 19 05:40:32 PM PDT 24
Peak memory 219436 kb
Host smart-160f4e8d-0ab6-4eac-8f5d-4f25bbfe1d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532573043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.532573043
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.936773466
Short name T878
Test name
Test status
Simulation time 3201206195 ps
CPU time 14.6 seconds
Started Jul 19 05:40:20 PM PDT 24
Finished Jul 19 05:40:40 PM PDT 24
Peak memory 233244 kb
Host smart-3348feef-5073-4d0c-a175-18eada8fb621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936773466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.936773466
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4030712906
Short name T999
Test name
Test status
Simulation time 15545275076 ps
CPU time 7.88 seconds
Started Jul 19 05:40:20 PM PDT 24
Finished Jul 19 05:40:33 PM PDT 24
Peak memory 235748 kb
Host smart-63587a65-9535-4527-a12d-35dade400361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030712906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4030712906
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1717886920
Short name T961
Test name
Test status
Simulation time 13306414812 ps
CPU time 22.02 seconds
Started Jul 19 05:40:20 PM PDT 24
Finished Jul 19 05:40:47 PM PDT 24
Peak memory 249360 kb
Host smart-bf696851-f04e-41c8-829c-edaaffe7b0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717886920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1717886920
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3230542608
Short name T1016
Test name
Test status
Simulation time 1203170054 ps
CPU time 15.16 seconds
Started Jul 19 05:40:25 PM PDT 24
Finished Jul 19 05:40:42 PM PDT 24
Peak memory 222988 kb
Host smart-4afe3930-7c9d-4837-b61e-38ee34418ff9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3230542608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3230542608
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1886883737
Short name T334
Test name
Test status
Simulation time 5296638058 ps
CPU time 9.81 seconds
Started Jul 19 05:40:17 PM PDT 24
Finished Jul 19 05:40:33 PM PDT 24
Peak memory 220396 kb
Host smart-5dcded9c-5a80-4bec-a499-ce3c46719dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886883737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1886883737
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3060481220
Short name T791
Test name
Test status
Simulation time 17754333180 ps
CPU time 10.64 seconds
Started Jul 19 05:40:19 PM PDT 24
Finished Jul 19 05:40:35 PM PDT 24
Peak memory 216836 kb
Host smart-e3482ed0-6020-4794-bf65-d8a2826c0a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060481220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3060481220
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3365927130
Short name T561
Test name
Test status
Simulation time 45010206 ps
CPU time 1.41 seconds
Started Jul 19 05:40:16 PM PDT 24
Finished Jul 19 05:40:25 PM PDT 24
Peak memory 216664 kb
Host smart-872bf569-ef44-40e3-87b7-2b5ae6d03eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365927130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3365927130
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4130177901
Short name T936
Test name
Test status
Simulation time 17084949 ps
CPU time 0.71 seconds
Started Jul 19 05:40:17 PM PDT 24
Finished Jul 19 05:40:24 PM PDT 24
Peak memory 205884 kb
Host smart-b6012f02-59b8-43de-9195-4fe9e293f081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130177901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4130177901
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2981218085
Short name T727
Test name
Test status
Simulation time 2154707494 ps
CPU time 7.09 seconds
Started Jul 19 05:40:20 PM PDT 24
Finished Jul 19 05:40:32 PM PDT 24
Peak memory 236904 kb
Host smart-7f43250f-c61a-4edd-989d-f6b49f45604b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981218085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2981218085
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1057568592
Short name T922
Test name
Test status
Simulation time 17037027 ps
CPU time 0.75 seconds
Started Jul 19 05:40:35 PM PDT 24
Finished Jul 19 05:40:38 PM PDT 24
Peak memory 206084 kb
Host smart-215579ec-5706-4789-ac8e-9418958c826d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057568592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1057568592
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.110484931
Short name T505
Test name
Test status
Simulation time 699145895 ps
CPU time 10.08 seconds
Started Jul 19 05:40:32 PM PDT 24
Finished Jul 19 05:40:44 PM PDT 24
Peak memory 224944 kb
Host smart-3fccf1c6-4253-4041-bc93-419ad4f794d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110484931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.110484931
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1709489198
Short name T412
Test name
Test status
Simulation time 79242229 ps
CPU time 0.8 seconds
Started Jul 19 05:40:32 PM PDT 24
Finished Jul 19 05:40:34 PM PDT 24
Peak memory 207212 kb
Host smart-cd9e2f85-d522-4e2d-b7df-e24459e74149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709489198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1709489198
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3673964867
Short name T38
Test name
Test status
Simulation time 13958396295 ps
CPU time 188.09 seconds
Started Jul 19 05:40:37 PM PDT 24
Finished Jul 19 05:43:47 PM PDT 24
Peak memory 274220 kb
Host smart-1a2474dc-af77-4c8e-81f3-18a431f7d197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673964867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3673964867
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3934489406
Short name T23
Test name
Test status
Simulation time 2862843264 ps
CPU time 5.97 seconds
Started Jul 19 05:40:37 PM PDT 24
Finished Jul 19 05:40:46 PM PDT 24
Peak memory 217996 kb
Host smart-4fc87db4-48ce-42f3-a5ce-4c4be3f03cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934489406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3934489406
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2005388068
Short name T906
Test name
Test status
Simulation time 1876984336 ps
CPU time 7.89 seconds
Started Jul 19 05:40:25 PM PDT 24
Finished Jul 19 05:40:35 PM PDT 24
Peak memory 224876 kb
Host smart-b033e433-e51a-4136-88b4-e5f210bd2935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005388068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2005388068
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2177673017
Short name T648
Test name
Test status
Simulation time 37489992179 ps
CPU time 133.06 seconds
Started Jul 19 05:40:27 PM PDT 24
Finished Jul 19 05:42:42 PM PDT 24
Peak memory 251636 kb
Host smart-e12b8607-c458-4062-b0de-cbb57a5770c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177673017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2177673017
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1825596238
Short name T206
Test name
Test status
Simulation time 979218688 ps
CPU time 5.72 seconds
Started Jul 19 05:40:23 PM PDT 24
Finished Jul 19 05:40:32 PM PDT 24
Peak memory 233148 kb
Host smart-afc10071-6e1d-4582-a867-dccfcb1b2357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825596238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1825596238
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1379835755
Short name T854
Test name
Test status
Simulation time 40972052 ps
CPU time 2.71 seconds
Started Jul 19 05:40:26 PM PDT 24
Finished Jul 19 05:40:30 PM PDT 24
Peak memory 233112 kb
Host smart-4e073fdc-11ab-4437-909a-ae8ebe71a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379835755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1379835755
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.948246928
Short name T396
Test name
Test status
Simulation time 30915822 ps
CPU time 2.12 seconds
Started Jul 19 05:40:27 PM PDT 24
Finished Jul 19 05:40:31 PM PDT 24
Peak memory 224320 kb
Host smart-30753cba-1d31-4001-aaeb-a484e95e2d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948246928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.948246928
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1522392500
Short name T438
Test name
Test status
Simulation time 1025811180 ps
CPU time 8.9 seconds
Started Jul 19 05:40:27 PM PDT 24
Finished Jul 19 05:40:38 PM PDT 24
Peak memory 233092 kb
Host smart-6ed837cc-9902-4db6-9a2a-555045969328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522392500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1522392500
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2041964744
Short name T158
Test name
Test status
Simulation time 242084250 ps
CPU time 4.99 seconds
Started Jul 19 05:40:34 PM PDT 24
Finished Jul 19 05:40:40 PM PDT 24
Peak memory 219724 kb
Host smart-cd34145e-d801-44fc-a81c-4fd4e59327c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2041964744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2041964744
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3960453786
Short name T231
Test name
Test status
Simulation time 53870501709 ps
CPU time 234.46 seconds
Started Jul 19 05:40:34 PM PDT 24
Finished Jul 19 05:44:31 PM PDT 24
Peak memory 266072 kb
Host smart-4bf71210-9bbb-448c-b535-5afd4338185b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960453786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3960453786
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2698403237
Short name T691
Test name
Test status
Simulation time 7519724466 ps
CPU time 21.76 seconds
Started Jul 19 05:40:32 PM PDT 24
Finished Jul 19 05:40:55 PM PDT 24
Peak memory 216976 kb
Host smart-25c6019e-f7b4-4cc6-a24f-780e59713e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698403237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2698403237
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.4005556792
Short name T866
Test name
Test status
Simulation time 2120640095 ps
CPU time 7.17 seconds
Started Jul 19 05:40:33 PM PDT 24
Finished Jul 19 05:40:41 PM PDT 24
Peak memory 216644 kb
Host smart-abcd6b5a-86b4-4878-95a8-aaec110601a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005556792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4005556792
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1301114289
Short name T588
Test name
Test status
Simulation time 35920806 ps
CPU time 1.22 seconds
Started Jul 19 05:40:26 PM PDT 24
Finished Jul 19 05:40:28 PM PDT 24
Peak memory 208508 kb
Host smart-3c552c1f-5d19-4227-aff9-374cdc842212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301114289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1301114289
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4037164704
Short name T934
Test name
Test status
Simulation time 157688669 ps
CPU time 0.9 seconds
Started Jul 19 05:40:32 PM PDT 24
Finished Jul 19 05:40:34 PM PDT 24
Peak memory 206344 kb
Host smart-20a7759c-daac-4fb4-9674-29ada7586bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037164704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4037164704
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.355470003
Short name T256
Test name
Test status
Simulation time 7845253397 ps
CPU time 13.7 seconds
Started Jul 19 05:40:34 PM PDT 24
Finished Jul 19 05:40:49 PM PDT 24
Peak memory 237604 kb
Host smart-7e1e2156-4422-41e3-8176-79777d6a70ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355470003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.355470003
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1389164138
Short name T532
Test name
Test status
Simulation time 41893021 ps
CPU time 0.75 seconds
Started Jul 19 05:40:47 PM PDT 24
Finished Jul 19 05:40:48 PM PDT 24
Peak memory 205088 kb
Host smart-ecf6daf6-6475-4772-9dd8-68431ea5b2e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389164138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1389164138
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1122861648
Short name T616
Test name
Test status
Simulation time 577622109 ps
CPU time 2.96 seconds
Started Jul 19 05:40:34 PM PDT 24
Finished Jul 19 05:40:38 PM PDT 24
Peak memory 224928 kb
Host smart-f2abcadf-1ffb-43fb-9431-a4eee39b18a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122861648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1122861648
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2036585181
Short name T897
Test name
Test status
Simulation time 18943730 ps
CPU time 0.84 seconds
Started Jul 19 05:40:36 PM PDT 24
Finished Jul 19 05:40:40 PM PDT 24
Peak memory 207208 kb
Host smart-7ae7117c-ca5d-4552-aa9c-ffc6a9e02641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036585181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2036585181
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2775705774
Short name T634
Test name
Test status
Simulation time 50278638 ps
CPU time 0.76 seconds
Started Jul 19 05:40:37 PM PDT 24
Finished Jul 19 05:40:40 PM PDT 24
Peak memory 216180 kb
Host smart-27bcea40-9d56-4c41-99d4-7a8f6833c3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775705774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2775705774
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3388637191
Short name T151
Test name
Test status
Simulation time 35928200106 ps
CPU time 343.56 seconds
Started Jul 19 05:40:46 PM PDT 24
Finished Jul 19 05:46:31 PM PDT 24
Peak memory 250960 kb
Host smart-7a9e5405-2a3f-4d11-8070-a6b577c5eafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388637191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3388637191
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.861363753
Short name T967
Test name
Test status
Simulation time 11106598033 ps
CPU time 21.09 seconds
Started Jul 19 05:40:35 PM PDT 24
Finished Jul 19 05:40:58 PM PDT 24
Peak memory 225052 kb
Host smart-22f12b5c-fe02-420f-9460-1c6794f5947c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861363753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.861363753
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3593799017
Short name T539
Test name
Test status
Simulation time 13687817898 ps
CPU time 31.61 seconds
Started Jul 19 05:40:39 PM PDT 24
Finished Jul 19 05:41:12 PM PDT 24
Peak memory 249632 kb
Host smart-ef057adc-74b5-4bd1-a7d6-d16a4fec2512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593799017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3593799017
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1503525074
Short name T678
Test name
Test status
Simulation time 55386322 ps
CPU time 2.42 seconds
Started Jul 19 05:40:37 PM PDT 24
Finished Jul 19 05:40:42 PM PDT 24
Peak memory 233124 kb
Host smart-55ad9549-d6cf-48a9-b600-a088ca9f83c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503525074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1503525074
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1806889509
Short name T118
Test name
Test status
Simulation time 6340654613 ps
CPU time 18.33 seconds
Started Jul 19 05:40:36 PM PDT 24
Finished Jul 19 05:40:56 PM PDT 24
Peak memory 234260 kb
Host smart-95314b45-4c17-4ecd-be7f-85ebe10b5a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806889509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1806889509
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.546721808
Short name T913
Test name
Test status
Simulation time 436645654 ps
CPU time 2.77 seconds
Started Jul 19 05:40:37 PM PDT 24
Finished Jul 19 05:40:42 PM PDT 24
Peak memory 233116 kb
Host smart-89c34427-19a4-423e-9b67-b5d0f84958cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546721808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.546721808
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.697241896
Short name T997
Test name
Test status
Simulation time 1450565993 ps
CPU time 6.54 seconds
Started Jul 19 05:40:36 PM PDT 24
Finished Jul 19 05:40:44 PM PDT 24
Peak memory 233152 kb
Host smart-2b4fd2ea-6e94-4772-be88-74a32523426b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697241896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.697241896
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3181270401
Short name T548
Test name
Test status
Simulation time 597046244 ps
CPU time 3.71 seconds
Started Jul 19 05:40:35 PM PDT 24
Finished Jul 19 05:40:41 PM PDT 24
Peak memory 221132 kb
Host smart-8968119e-368e-44fb-a06d-650b16a5ee4e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3181270401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3181270401
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4277369630
Short name T1003
Test name
Test status
Simulation time 2720373514 ps
CPU time 70.09 seconds
Started Jul 19 05:40:46 PM PDT 24
Finished Jul 19 05:41:57 PM PDT 24
Peak memory 257764 kb
Host smart-6f39f5dc-f562-40fd-ac34-1de8556861c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277369630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4277369630
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1609638075
Short name T336
Test name
Test status
Simulation time 10242524556 ps
CPU time 57.34 seconds
Started Jul 19 05:40:33 PM PDT 24
Finished Jul 19 05:41:32 PM PDT 24
Peak memory 216808 kb
Host smart-01264f7b-f56d-432a-aea9-3d24701fdd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609638075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1609638075
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.4076317379
Short name T787
Test name
Test status
Simulation time 776690197 ps
CPU time 1.89 seconds
Started Jul 19 05:40:37 PM PDT 24
Finished Jul 19 05:40:41 PM PDT 24
Peak memory 207980 kb
Host smart-26601a8e-cd2f-411c-8c45-a1e9c32f78be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076317379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.4076317379
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3527327593
Short name T847
Test name
Test status
Simulation time 51356371 ps
CPU time 0.81 seconds
Started Jul 19 05:40:36 PM PDT 24
Finished Jul 19 05:40:39 PM PDT 24
Peak memory 207028 kb
Host smart-7c709fb1-182d-447b-be75-e9795af02aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527327593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3527327593
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.121106887
Short name T393
Test name
Test status
Simulation time 145294373 ps
CPU time 0.77 seconds
Started Jul 19 05:40:39 PM PDT 24
Finished Jul 19 05:40:41 PM PDT 24
Peak memory 206300 kb
Host smart-62e2bf9d-bc46-4fc5-a145-4db033c3f185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121106887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.121106887
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1928926815
Short name T767
Test name
Test status
Simulation time 6917519839 ps
CPU time 9.81 seconds
Started Jul 19 05:40:35 PM PDT 24
Finished Jul 19 05:40:47 PM PDT 24
Peak memory 225060 kb
Host smart-5c302734-19e3-4cd6-962a-7957d56384f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928926815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1928926815
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3038584673
Short name T382
Test name
Test status
Simulation time 18287862 ps
CPU time 0.7 seconds
Started Jul 19 05:35:09 PM PDT 24
Finished Jul 19 05:36:11 PM PDT 24
Peak memory 205792 kb
Host smart-d2137e4c-0f73-49c3-b133-d2ba999d4c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038584673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
038584673
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2774720045
Short name T287
Test name
Test status
Simulation time 209465884 ps
CPU time 3.9 seconds
Started Jul 19 05:35:10 PM PDT 24
Finished Jul 19 05:36:17 PM PDT 24
Peak memory 233168 kb
Host smart-b2835d6f-1784-4431-bde8-8e6e26ee13ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774720045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2774720045
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1328600129
Short name T633
Test name
Test status
Simulation time 14880371 ps
CPU time 0.78 seconds
Started Jul 19 05:35:01 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 206196 kb
Host smart-5c9f962f-fec2-485d-8c2a-0cdc4eadca6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328600129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1328600129
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2571842038
Short name T182
Test name
Test status
Simulation time 9546923782 ps
CPU time 55.86 seconds
Started Jul 19 05:35:12 PM PDT 24
Finished Jul 19 05:37:11 PM PDT 24
Peak memory 251936 kb
Host smart-526b37bb-474f-43b2-9307-5b176ee1df60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571842038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2571842038
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3626067651
Short name T1002
Test name
Test status
Simulation time 48838599978 ps
CPU time 465.5 seconds
Started Jul 19 05:35:14 PM PDT 24
Finished Jul 19 05:44:02 PM PDT 24
Peak memory 256896 kb
Host smart-79924a94-f5d3-4c3e-946a-afd4fd373f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626067651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3626067651
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2499858753
Short name T615
Test name
Test status
Simulation time 3943661526 ps
CPU time 89.75 seconds
Started Jul 19 05:35:10 PM PDT 24
Finished Jul 19 05:37:42 PM PDT 24
Peak memory 249692 kb
Host smart-3068ffb4-6c9c-4df0-b45e-05f6c7b45e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499858753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2499858753
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2939947876
Short name T326
Test name
Test status
Simulation time 3265412050 ps
CPU time 29.45 seconds
Started Jul 19 05:35:12 PM PDT 24
Finished Jul 19 05:36:45 PM PDT 24
Peak memory 249660 kb
Host smart-d2a1d554-aac0-4b93-b2c6-488e4daff5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939947876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2939947876
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2603685591
Short name T742
Test name
Test status
Simulation time 121114813514 ps
CPU time 204.01 seconds
Started Jul 19 05:35:14 PM PDT 24
Finished Jul 19 05:39:40 PM PDT 24
Peak memory 250792 kb
Host smart-3b1e865a-8baa-4347-b8a4-34c390f1d67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603685591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2603685591
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2171493231
Short name T692
Test name
Test status
Simulation time 417683712 ps
CPU time 6.54 seconds
Started Jul 19 05:35:14 PM PDT 24
Finished Jul 19 05:36:23 PM PDT 24
Peak memory 228548 kb
Host smart-90e642cf-383f-4ff1-82fb-5daedd78f8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171493231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2171493231
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1816110727
Short name T822
Test name
Test status
Simulation time 33962038318 ps
CPU time 45.59 seconds
Started Jul 19 05:35:13 PM PDT 24
Finished Jul 19 05:37:01 PM PDT 24
Peak memory 224924 kb
Host smart-9e9e774e-47ff-411b-a967-2db60dfdf8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816110727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1816110727
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1658353691
Short name T715
Test name
Test status
Simulation time 50112972 ps
CPU time 1.01 seconds
Started Jul 19 05:35:01 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 217148 kb
Host smart-a29a8725-bb43-4047-a61b-6de6909c9c6a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658353691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1658353691
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2848461974
Short name T236
Test name
Test status
Simulation time 1726409608 ps
CPU time 10.3 seconds
Started Jul 19 05:35:10 PM PDT 24
Finished Jul 19 05:36:23 PM PDT 24
Peak memory 233116 kb
Host smart-9584d09e-5cb1-4e15-9b68-3afefe76944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848461974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2848461974
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.756084297
Short name T291
Test name
Test status
Simulation time 79633966177 ps
CPU time 12.92 seconds
Started Jul 19 05:35:10 PM PDT 24
Finished Jul 19 05:36:26 PM PDT 24
Peak memory 224936 kb
Host smart-02de2ac0-2b86-4e67-b987-d5748b8e7780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756084297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.756084297
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.59144026
Short name T794
Test name
Test status
Simulation time 198307640 ps
CPU time 4.12 seconds
Started Jul 19 05:35:11 PM PDT 24
Finished Jul 19 05:36:17 PM PDT 24
Peak memory 223420 kb
Host smart-6b721880-b91d-43ed-836b-95a9694fad06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=59144026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct
.59144026
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.647896971
Short name T743
Test name
Test status
Simulation time 6520714839 ps
CPU time 21.32 seconds
Started Jul 19 05:35:02 PM PDT 24
Finished Jul 19 05:36:24 PM PDT 24
Peak memory 216800 kb
Host smart-016ff957-f765-4aed-8627-4acb448d7aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647896971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.647896971
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3889130023
Short name T829
Test name
Test status
Simulation time 12877761202 ps
CPU time 10.26 seconds
Started Jul 19 05:35:02 PM PDT 24
Finished Jul 19 05:36:13 PM PDT 24
Peak memory 216788 kb
Host smart-a10dfcfc-c56a-4d8f-90c6-deba58d964e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889130023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3889130023
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2492967999
Short name T338
Test name
Test status
Simulation time 1730880576 ps
CPU time 11.19 seconds
Started Jul 19 05:35:12 PM PDT 24
Finished Jul 19 05:36:25 PM PDT 24
Peak memory 216656 kb
Host smart-709d5587-080c-4156-8ddf-b5366b9c56a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492967999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2492967999
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1875272925
Short name T959
Test name
Test status
Simulation time 85426532 ps
CPU time 0.82 seconds
Started Jul 19 05:35:01 PM PDT 24
Finished Jul 19 05:36:04 PM PDT 24
Peak memory 206192 kb
Host smart-dc009504-9faf-4631-a831-299bf562b591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875272925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1875272925
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1982846924
Short name T874
Test name
Test status
Simulation time 1812766182 ps
CPU time 7.49 seconds
Started Jul 19 05:35:09 PM PDT 24
Finished Jul 19 05:36:20 PM PDT 24
Peak memory 224888 kb
Host smart-78f6d782-a977-410c-a144-0f5115b7ee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982846924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1982846924
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.254217842
Short name T630
Test name
Test status
Simulation time 11958138 ps
CPU time 0.71 seconds
Started Jul 19 05:35:19 PM PDT 24
Finished Jul 19 05:36:20 PM PDT 24
Peak memory 205704 kb
Host smart-234d37ea-c012-4221-a98c-520ed8ea44d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254217842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.254217842
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2682692632
Short name T136
Test name
Test status
Simulation time 53557561 ps
CPU time 2.3 seconds
Started Jul 19 05:35:10 PM PDT 24
Finished Jul 19 05:36:15 PM PDT 24
Peak memory 232860 kb
Host smart-2cf5667c-5889-4e6c-88e7-59bdfba86f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682692632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2682692632
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1148968626
Short name T969
Test name
Test status
Simulation time 62796242 ps
CPU time 0.78 seconds
Started Jul 19 05:35:12 PM PDT 24
Finished Jul 19 05:36:16 PM PDT 24
Peak memory 207224 kb
Host smart-1afa4e1d-b4bc-42d2-8424-e14213c9024e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148968626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1148968626
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.239400378
Short name T398
Test name
Test status
Simulation time 2214727999 ps
CPU time 38.39 seconds
Started Jul 19 05:35:10 PM PDT 24
Finished Jul 19 05:36:51 PM PDT 24
Peak memory 249980 kb
Host smart-259c6264-0c30-4bbf-9fb5-b1619eb77379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239400378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.239400378
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3873603299
Short name T229
Test name
Test status
Simulation time 16221151305 ps
CPU time 90.64 seconds
Started Jul 19 05:35:13 PM PDT 24
Finished Jul 19 05:37:47 PM PDT 24
Peak memory 265320 kb
Host smart-7e952cdc-00fc-4c02-b714-e1549dfa5bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873603299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3873603299
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4064540325
Short name T672
Test name
Test status
Simulation time 245177829 ps
CPU time 2.48 seconds
Started Jul 19 05:35:13 PM PDT 24
Finished Jul 19 05:36:18 PM PDT 24
Peak memory 218020 kb
Host smart-5268f5de-bab1-4d40-aa6a-f2b54af42aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064540325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4064540325
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1986537035
Short name T769
Test name
Test status
Simulation time 1075825385 ps
CPU time 16.83 seconds
Started Jul 19 05:35:12 PM PDT 24
Finished Jul 19 05:36:32 PM PDT 24
Peak memory 241352 kb
Host smart-5b243d8b-d61f-4983-827f-2ab5e8cb2896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986537035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1986537035
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2586801492
Short name T353
Test name
Test status
Simulation time 56063885 ps
CPU time 0.78 seconds
Started Jul 19 05:35:11 PM PDT 24
Finished Jul 19 05:36:14 PM PDT 24
Peak memory 216224 kb
Host smart-1ebd7777-60c0-4ef3-9069-ebf71aa08fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586801492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2586801492
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.130906079
Short name T117
Test name
Test status
Simulation time 1358724687 ps
CPU time 7.08 seconds
Started Jul 19 05:35:14 PM PDT 24
Finished Jul 19 05:36:23 PM PDT 24
Peak memory 233184 kb
Host smart-d31eccc8-7528-4a62-b18d-db0a85abd019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130906079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.130906079
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2176749608
Short name T841
Test name
Test status
Simulation time 3389781368 ps
CPU time 25.73 seconds
Started Jul 19 05:35:10 PM PDT 24
Finished Jul 19 05:36:39 PM PDT 24
Peak memory 241176 kb
Host smart-32dff7ed-524c-42d4-bd8d-46d1bfb5523b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176749608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2176749608
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1424267972
Short name T380
Test name
Test status
Simulation time 14669254 ps
CPU time 1.07 seconds
Started Jul 19 05:35:10 PM PDT 24
Finished Jul 19 05:36:13 PM PDT 24
Peak memory 217152 kb
Host smart-c618ee86-538c-4ab7-b804-47b43d061b8a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424267972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1424267972
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.204099361
Short name T943
Test name
Test status
Simulation time 3001291524 ps
CPU time 10.39 seconds
Started Jul 19 05:35:14 PM PDT 24
Finished Jul 19 05:36:27 PM PDT 24
Peak memory 225092 kb
Host smart-1eeed035-64d8-45fc-9a81-f5a68ba2ee42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204099361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
204099361
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.958679293
Short name T849
Test name
Test status
Simulation time 3842817573 ps
CPU time 13.97 seconds
Started Jul 19 05:35:10 PM PDT 24
Finished Jul 19 05:36:26 PM PDT 24
Peak memory 225028 kb
Host smart-1fa447e2-8a0d-491a-a836-18c19ac5d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958679293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.958679293
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1609790273
Short name T58
Test name
Test status
Simulation time 1084855949 ps
CPU time 10.32 seconds
Started Jul 19 05:35:11 PM PDT 24
Finished Jul 19 05:36:24 PM PDT 24
Peak memory 219292 kb
Host smart-24316cd2-cadc-4b64-9abe-4140647d4dbc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1609790273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1609790273
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.60746548
Short name T14
Test name
Test status
Simulation time 263691357 ps
CPU time 1.07 seconds
Started Jul 19 05:35:20 PM PDT 24
Finished Jul 19 05:36:21 PM PDT 24
Peak memory 207808 kb
Host smart-016b55f5-ac16-416e-9757-8a431222c2e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60746548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_
all.60746548
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.655984335
Short name T973
Test name
Test status
Simulation time 2014099471 ps
CPU time 21.88 seconds
Started Jul 19 05:35:11 PM PDT 24
Finished Jul 19 05:36:36 PM PDT 24
Peak memory 220548 kb
Host smart-133372e1-42bc-4d10-9052-823658fb4753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655984335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.655984335
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1234009668
Short name T654
Test name
Test status
Simulation time 271785925 ps
CPU time 2.76 seconds
Started Jul 19 05:35:14 PM PDT 24
Finished Jul 19 05:36:19 PM PDT 24
Peak memory 216700 kb
Host smart-ecd52826-1b50-4863-99d2-7c0ccde253b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234009668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1234009668
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1886305972
Short name T723
Test name
Test status
Simulation time 741425210 ps
CPU time 2.12 seconds
Started Jul 19 05:35:13 PM PDT 24
Finished Jul 19 05:36:19 PM PDT 24
Peak memory 216648 kb
Host smart-b4915263-1d38-458d-a0b0-d335fddc3a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886305972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1886305972
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.313864536
Short name T1014
Test name
Test status
Simulation time 69847962 ps
CPU time 0.83 seconds
Started Jul 19 05:35:11 PM PDT 24
Finished Jul 19 05:36:15 PM PDT 24
Peak memory 206276 kb
Host smart-c7483355-539b-4cea-996d-157b31517502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313864536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.313864536
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1927197188
Short name T573
Test name
Test status
Simulation time 327463114 ps
CPU time 4.21 seconds
Started Jul 19 05:35:15 PM PDT 24
Finished Jul 19 05:36:21 PM PDT 24
Peak memory 233188 kb
Host smart-2b467e2e-c7be-45dc-a3e4-f423e39fa6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927197188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1927197188
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3463885894
Short name T540
Test name
Test status
Simulation time 16214474 ps
CPU time 0.76 seconds
Started Jul 19 05:35:34 PM PDT 24
Finished Jul 19 05:36:27 PM PDT 24
Peak memory 206088 kb
Host smart-d2939912-7b65-4a0f-882c-2677e0863b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463885894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
463885894
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1223435708
Short name T250
Test name
Test status
Simulation time 284321730 ps
CPU time 2.25 seconds
Started Jul 19 05:35:25 PM PDT 24
Finished Jul 19 05:36:25 PM PDT 24
Peak memory 224824 kb
Host smart-64c1ffb4-2c0c-45c0-a988-22a3920fc307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223435708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1223435708
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3313138285
Short name T440
Test name
Test status
Simulation time 65182994 ps
CPU time 0.84 seconds
Started Jul 19 05:35:20 PM PDT 24
Finished Jul 19 05:36:21 PM PDT 24
Peak memory 207164 kb
Host smart-e0786879-81fd-4264-aa4e-faa1f526ee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313138285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3313138285
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1350407512
Short name T850
Test name
Test status
Simulation time 15777177990 ps
CPU time 37.65 seconds
Started Jul 19 05:35:34 PM PDT 24
Finished Jul 19 05:37:04 PM PDT 24
Peak memory 249624 kb
Host smart-fb27c7f6-f7dd-420b-b56d-8d41f3ec4bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350407512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1350407512
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.286898455
Short name T29
Test name
Test status
Simulation time 15972687125 ps
CPU time 162.88 seconds
Started Jul 19 05:35:33 PM PDT 24
Finished Jul 19 05:39:09 PM PDT 24
Peak memory 255468 kb
Host smart-a4880073-63f5-4634-9cd5-61edcbbb225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286898455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.286898455
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1075251865
Short name T779
Test name
Test status
Simulation time 50167424163 ps
CPU time 89.53 seconds
Started Jul 19 05:35:38 PM PDT 24
Finished Jul 19 05:37:57 PM PDT 24
Peak memory 254392 kb
Host smart-4f3d89b7-2785-4746-a5f8-7b89a01e0557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075251865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1075251865
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2390936918
Short name T535
Test name
Test status
Simulation time 6899095417 ps
CPU time 42.24 seconds
Started Jul 19 05:35:26 PM PDT 24
Finished Jul 19 05:37:06 PM PDT 24
Peak memory 233284 kb
Host smart-4a0e68e9-fca1-4c77-8269-f5202d83c62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390936918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2390936918
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2939310981
Short name T1017
Test name
Test status
Simulation time 31816469215 ps
CPU time 66.98 seconds
Started Jul 19 05:35:28 PM PDT 24
Finished Jul 19 05:37:31 PM PDT 24
Peak memory 253624 kb
Host smart-714c3fa2-b91d-4e58-942b-44f6cc37d6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939310981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2939310981
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3631079724
Short name T918
Test name
Test status
Simulation time 109391175 ps
CPU time 3.82 seconds
Started Jul 19 05:35:27 PM PDT 24
Finished Jul 19 05:36:28 PM PDT 24
Peak memory 233100 kb
Host smart-ad4afc01-bbb7-42e3-9c0e-981d7ba48c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631079724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3631079724
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3513823005
Short name T680
Test name
Test status
Simulation time 6182197541 ps
CPU time 8.86 seconds
Started Jul 19 05:35:26 PM PDT 24
Finished Jul 19 05:36:32 PM PDT 24
Peak memory 233268 kb
Host smart-0401bcbd-b3ad-459a-945a-5395b1dbf54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513823005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3513823005
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2984653453
Short name T604
Test name
Test status
Simulation time 43723004 ps
CPU time 1.01 seconds
Started Jul 19 05:35:17 PM PDT 24
Finished Jul 19 05:36:20 PM PDT 24
Peak memory 218384 kb
Host smart-ffe7dad6-7ff0-4ed1-865d-2c80ad76363b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984653453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2984653453
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1176789351
Short name T285
Test name
Test status
Simulation time 920636360 ps
CPU time 5.26 seconds
Started Jul 19 05:35:29 PM PDT 24
Finished Jul 19 05:36:30 PM PDT 24
Peak memory 225020 kb
Host smart-e6ab9fab-6be3-4a7b-b43b-c5d1c8b0f616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176789351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1176789351
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2967686575
Short name T593
Test name
Test status
Simulation time 3283196811 ps
CPU time 5.3 seconds
Started Jul 19 05:35:26 PM PDT 24
Finished Jul 19 05:36:28 PM PDT 24
Peak memory 220324 kb
Host smart-53131750-8bbd-4112-92e2-5e5389f24451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967686575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2967686575
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.612573092
Short name T528
Test name
Test status
Simulation time 5539357265 ps
CPU time 19.21 seconds
Started Jul 19 05:35:25 PM PDT 24
Finished Jul 19 05:36:42 PM PDT 24
Peak memory 220548 kb
Host smart-09d453c9-1e40-41e0-8700-471d9945d637
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=612573092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.612573092
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3065290919
Short name T148
Test name
Test status
Simulation time 60329000304 ps
CPU time 550.16 seconds
Started Jul 19 05:35:33 PM PDT 24
Finished Jul 19 05:45:36 PM PDT 24
Peak memory 255704 kb
Host smart-9212389b-538c-4e1e-a32d-7c9476f613cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065290919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3065290919
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.175471250
Short name T963
Test name
Test status
Simulation time 2153074865 ps
CPU time 10.26 seconds
Started Jul 19 05:35:17 PM PDT 24
Finished Jul 19 05:36:29 PM PDT 24
Peak memory 216828 kb
Host smart-816e9d73-7b2e-4345-a73d-67a3309becf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175471250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.175471250
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3436890280
Short name T432
Test name
Test status
Simulation time 11265376284 ps
CPU time 13.28 seconds
Started Jul 19 05:35:20 PM PDT 24
Finished Jul 19 05:36:33 PM PDT 24
Peak memory 216792 kb
Host smart-deb13aad-07f3-47ff-b141-ab2e63b95ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436890280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3436890280
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2388651215
Short name T988
Test name
Test status
Simulation time 155621946 ps
CPU time 1.46 seconds
Started Jul 19 05:35:28 PM PDT 24
Finished Jul 19 05:36:26 PM PDT 24
Peak memory 216700 kb
Host smart-5855fbe1-51f2-444a-9b3c-02b345906103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388651215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2388651215
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3719941438
Short name T846
Test name
Test status
Simulation time 371364320 ps
CPU time 0.89 seconds
Started Jul 19 05:35:19 PM PDT 24
Finished Jul 19 05:36:20 PM PDT 24
Peak memory 207308 kb
Host smart-28552cf2-73d7-4ac1-b2aa-4d32d8e857c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719941438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3719941438
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.832903881
Short name T580
Test name
Test status
Simulation time 5167323965 ps
CPU time 11.91 seconds
Started Jul 19 05:35:27 PM PDT 24
Finished Jul 19 05:36:36 PM PDT 24
Peak memory 241436 kb
Host smart-b0c2edeb-92a7-4ca8-bc4d-9ed59cd82cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832903881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.832903881
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3470379830
Short name T896
Test name
Test status
Simulation time 31825595 ps
CPU time 0.69 seconds
Started Jul 19 05:35:52 PM PDT 24
Finished Jul 19 05:36:33 PM PDT 24
Peak memory 205172 kb
Host smart-f2427acd-4f89-40da-ada5-e9e31f0289b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470379830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
470379830
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3180562505
Short name T862
Test name
Test status
Simulation time 42909815 ps
CPU time 2.72 seconds
Started Jul 19 05:35:44 PM PDT 24
Finished Jul 19 05:36:32 PM PDT 24
Peak memory 233156 kb
Host smart-7e7512e0-36d6-4fb0-bea7-bd72828413f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180562505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3180562505
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2243665032
Short name T880
Test name
Test status
Simulation time 18561650 ps
CPU time 0.77 seconds
Started Jul 19 05:35:35 PM PDT 24
Finished Jul 19 05:36:27 PM PDT 24
Peak memory 205836 kb
Host smart-1a9a3976-740d-4f93-9d0e-fa5d1c1e7981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243665032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2243665032
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1343225120
Short name T746
Test name
Test status
Simulation time 10872714504 ps
CPU time 92.69 seconds
Started Jul 19 05:35:53 PM PDT 24
Finished Jul 19 05:38:05 PM PDT 24
Peak memory 252156 kb
Host smart-6bc29f05-3465-4c0e-80b7-cd5c905e5d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343225120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1343225120
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.513509502
Short name T930
Test name
Test status
Simulation time 103396486569 ps
CPU time 466.48 seconds
Started Jul 19 05:35:52 PM PDT 24
Finished Jul 19 05:44:19 PM PDT 24
Peak memory 255876 kb
Host smart-74b26fc3-c9bc-431d-a988-3970ee05964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513509502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.513509502
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.839146892
Short name T877
Test name
Test status
Simulation time 39749618782 ps
CPU time 356.32 seconds
Started Jul 19 05:35:51 PM PDT 24
Finished Jul 19 05:42:29 PM PDT 24
Peak memory 257276 kb
Host smart-9193c918-cf09-4a41-9777-19952d9eb83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839146892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
839146892
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.662170151
Short name T991
Test name
Test status
Simulation time 19577966761 ps
CPU time 35.48 seconds
Started Jul 19 05:35:44 PM PDT 24
Finished Jul 19 05:37:05 PM PDT 24
Peak memory 239604 kb
Host smart-301bc887-4d66-4558-ae5f-44fcef1ef46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662170151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.662170151
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.4184590648
Short name T656
Test name
Test status
Simulation time 37807383 ps
CPU time 0.76 seconds
Started Jul 19 05:35:44 PM PDT 24
Finished Jul 19 05:36:30 PM PDT 24
Peak memory 216280 kb
Host smart-a9325d0a-17bb-493a-b8d3-447d245ee659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184590648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.4184590648
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2863985957
Short name T613
Test name
Test status
Simulation time 104700014 ps
CPU time 2.51 seconds
Started Jul 19 05:35:44 PM PDT 24
Finished Jul 19 05:36:32 PM PDT 24
Peak memory 232916 kb
Host smart-5f7fb1a3-b4c2-452f-8bcf-9cceacb80fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863985957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2863985957
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1730114271
Short name T581
Test name
Test status
Simulation time 2624901398 ps
CPU time 28.27 seconds
Started Jul 19 05:35:43 PM PDT 24
Finished Jul 19 05:36:57 PM PDT 24
Peak memory 233196 kb
Host smart-145e6393-e892-427a-88cd-239c8a26f10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730114271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1730114271
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1055227253
Short name T975
Test name
Test status
Simulation time 29222303 ps
CPU time 1.07 seconds
Started Jul 19 05:35:35 PM PDT 24
Finished Jul 19 05:36:27 PM PDT 24
Peak memory 218444 kb
Host smart-e58fbaea-87a7-449e-981f-359016b8cafe
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055227253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1055227253
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2411378187
Short name T302
Test name
Test status
Simulation time 3799348873 ps
CPU time 12.59 seconds
Started Jul 19 05:35:43 PM PDT 24
Finished Jul 19 05:36:42 PM PDT 24
Peak memory 233180 kb
Host smart-f6fd31f9-dcb0-45eb-872e-6e7ea1ee52b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411378187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2411378187
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4037440679
Short name T365
Test name
Test status
Simulation time 19445256332 ps
CPU time 39.6 seconds
Started Jul 19 05:35:45 PM PDT 24
Finished Jul 19 05:37:09 PM PDT 24
Peak memory 233236 kb
Host smart-492d2a1b-3130-4578-ae15-54a8ee63b0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037440679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4037440679
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.13537954
Short name T643
Test name
Test status
Simulation time 715627906 ps
CPU time 4.73 seconds
Started Jul 19 05:35:52 PM PDT 24
Finished Jul 19 05:36:37 PM PDT 24
Peak memory 219288 kb
Host smart-06359265-0680-4f45-8bad-8d923ceef3b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=13537954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct
.13537954
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.193800693
Short name T667
Test name
Test status
Simulation time 1645971511 ps
CPU time 22.8 seconds
Started Jul 19 05:35:35 PM PDT 24
Finished Jul 19 05:36:49 PM PDT 24
Peak memory 216720 kb
Host smart-389daa09-3205-4d9d-b1c9-57ad7749a9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193800693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.193800693
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2515163619
Short name T945
Test name
Test status
Simulation time 800699644 ps
CPU time 3.39 seconds
Started Jul 19 05:35:34 PM PDT 24
Finished Jul 19 05:36:29 PM PDT 24
Peak memory 216744 kb
Host smart-588ad489-a689-4c75-9052-5b882e0ddcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515163619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2515163619
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.760249318
Short name T736
Test name
Test status
Simulation time 39247510 ps
CPU time 1.34 seconds
Started Jul 19 05:35:44 PM PDT 24
Finished Jul 19 05:36:31 PM PDT 24
Peak memory 216476 kb
Host smart-c9a4409c-0d07-4258-ba96-79a080d4d64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760249318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.760249318
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3030921693
Short name T660
Test name
Test status
Simulation time 333012607 ps
CPU time 0.97 seconds
Started Jul 19 05:35:44 PM PDT 24
Finished Jul 19 05:36:30 PM PDT 24
Peak memory 207300 kb
Host smart-c630bfa4-36ad-47b7-a523-caa5bff22731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030921693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3030921693
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.244417190
Short name T1026
Test name
Test status
Simulation time 11202137965 ps
CPU time 12.23 seconds
Started Jul 19 05:35:43 PM PDT 24
Finished Jul 19 05:36:42 PM PDT 24
Peak memory 225080 kb
Host smart-eadefce6-bc9d-4d33-9904-b12450410472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244417190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.244417190
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2736906600
Short name T434
Test name
Test status
Simulation time 35540386 ps
CPU time 0.74 seconds
Started Jul 19 05:36:22 PM PDT 24
Finished Jul 19 05:36:45 PM PDT 24
Peak memory 205724 kb
Host smart-1295f7ee-d3c0-4a6f-97aa-f082c09a6799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736906600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
736906600
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.4056270446
Short name T868
Test name
Test status
Simulation time 79226452 ps
CPU time 2.99 seconds
Started Jul 19 05:35:57 PM PDT 24
Finished Jul 19 05:36:37 PM PDT 24
Peak memory 224908 kb
Host smart-2327f483-0a00-4282-81c9-060fa772f522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056270446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4056270446
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1599322675
Short name T696
Test name
Test status
Simulation time 51527159 ps
CPU time 0.78 seconds
Started Jul 19 05:35:53 PM PDT 24
Finished Jul 19 05:36:33 PM PDT 24
Peak memory 206888 kb
Host smart-768fdbea-a3e7-486f-b9a9-f8f23bec59d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599322675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1599322675
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.518678342
Short name T709
Test name
Test status
Simulation time 39904536050 ps
CPU time 75.83 seconds
Started Jul 19 05:36:06 PM PDT 24
Finished Jul 19 05:37:54 PM PDT 24
Peak memory 241552 kb
Host smart-8ead9c9a-d5e1-4d4e-8f79-01e870940eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518678342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.518678342
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2747861098
Short name T605
Test name
Test status
Simulation time 7257990736 ps
CPU time 112.82 seconds
Started Jul 19 05:36:15 PM PDT 24
Finished Jul 19 05:38:34 PM PDT 24
Peak memory 256628 kb
Host smart-7482fecc-abb5-48c0-96b8-be2418888797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747861098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2747861098
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2288321687
Short name T149
Test name
Test status
Simulation time 150333095413 ps
CPU time 368.45 seconds
Started Jul 19 05:36:15 PM PDT 24
Finished Jul 19 05:42:50 PM PDT 24
Peak memory 257872 kb
Host smart-32557ca0-a498-4748-a391-de646219f65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288321687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2288321687
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1064448556
Short name T856
Test name
Test status
Simulation time 8171437742 ps
CPU time 31.7 seconds
Started Jul 19 05:35:59 PM PDT 24
Finished Jul 19 05:37:06 PM PDT 24
Peak memory 233256 kb
Host smart-4a12dc34-eea2-493a-a01a-26d17ad69362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064448556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1064448556
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.371937137
Short name T222
Test name
Test status
Simulation time 52455506566 ps
CPU time 83.82 seconds
Started Jul 19 05:36:00 PM PDT 24
Finished Jul 19 05:37:59 PM PDT 24
Peak memory 241432 kb
Host smart-685611df-7f39-4d42-b808-b13eabb59501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371937137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
371937137
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1888308009
Short name T611
Test name
Test status
Simulation time 826196825 ps
CPU time 5.06 seconds
Started Jul 19 05:35:51 PM PDT 24
Finished Jul 19 05:36:38 PM PDT 24
Peak memory 224928 kb
Host smart-638c6f20-b598-4c18-af17-eac87f075a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888308009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1888308009
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1001470320
Short name T760
Test name
Test status
Simulation time 5537285846 ps
CPU time 15.76 seconds
Started Jul 19 05:35:51 PM PDT 24
Finished Jul 19 05:36:48 PM PDT 24
Peak memory 225028 kb
Host smart-15b0fb0a-8395-43f5-8075-8c491b14b46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001470320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1001470320
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.820092253
Short name T514
Test name
Test status
Simulation time 16421161 ps
CPU time 1.04 seconds
Started Jul 19 05:35:51 PM PDT 24
Finished Jul 19 05:36:34 PM PDT 24
Peak memory 217124 kb
Host smart-c4d8257a-a83e-4011-8705-7fcc80e75277
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820092253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.820092253
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4080889434
Short name T279
Test name
Test status
Simulation time 140040004 ps
CPU time 3.14 seconds
Started Jul 19 05:35:56 PM PDT 24
Finished Jul 19 05:36:37 PM PDT 24
Peak memory 233184 kb
Host smart-908b75fa-3f69-4907-b861-784fca416a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080889434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4080889434
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1630361331
Short name T965
Test name
Test status
Simulation time 3686007329 ps
CPU time 5.58 seconds
Started Jul 19 05:35:51 PM PDT 24
Finished Jul 19 05:36:38 PM PDT 24
Peak memory 233160 kb
Host smart-88bc5d9b-7fb7-4877-93a4-16190a1089ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630361331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1630361331
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1357569728
Short name T135
Test name
Test status
Simulation time 139204886 ps
CPU time 3.48 seconds
Started Jul 19 05:35:57 PM PDT 24
Finished Jul 19 05:36:38 PM PDT 24
Peak memory 220680 kb
Host smart-15c97643-57b9-438a-95d9-15a8bf7396a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1357569728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1357569728
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1682741727
Short name T887
Test name
Test status
Simulation time 10416238058 ps
CPU time 16.07 seconds
Started Jul 19 05:35:53 PM PDT 24
Finished Jul 19 05:36:49 PM PDT 24
Peak memory 216892 kb
Host smart-c6a53b58-fad5-4e26-8b87-135557ba7992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682741727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1682741727
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4218486137
Short name T624
Test name
Test status
Simulation time 1055645409 ps
CPU time 3.86 seconds
Started Jul 19 05:35:51 PM PDT 24
Finished Jul 19 05:36:36 PM PDT 24
Peak memory 216648 kb
Host smart-f0db2202-db20-4e86-8e1d-a75c51209673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218486137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4218486137
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.56180800
Short name T675
Test name
Test status
Simulation time 173351473 ps
CPU time 1.74 seconds
Started Jul 19 05:35:52 PM PDT 24
Finished Jul 19 05:36:34 PM PDT 24
Peak memory 216676 kb
Host smart-5703f9e8-113f-49d9-8fca-bdd870203698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56180800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.56180800
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4096764653
Short name T677
Test name
Test status
Simulation time 92810546 ps
CPU time 0.98 seconds
Started Jul 19 05:35:53 PM PDT 24
Finished Jul 19 05:36:34 PM PDT 24
Peak memory 206216 kb
Host smart-1e8de679-bbe2-4174-a51b-72069b8dbf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096764653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4096764653
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1536690311
Short name T433
Test name
Test status
Simulation time 289796898 ps
CPU time 2.37 seconds
Started Jul 19 05:35:57 PM PDT 24
Finished Jul 19 05:36:37 PM PDT 24
Peak memory 224628 kb
Host smart-b94cda5a-546f-418f-a142-94ee95eee3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536690311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1536690311
Directory /workspace/9.spi_device_upload/latest
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