Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2720187	1			T1	1		T2	185		T3	533
all_values[1]	2720187	1			T1	1		T2	185		T3	533
all_values[2]	2720187	1			T1	1		T2	185		T3	533
all_values[3]	2720187	1			T1	1		T2	185		T3	533
all_values[4]	2720187	1			T1	1		T2	185		T3	533
all_values[5]	2720187	1			T1	1		T2	185		T3	533
all_values[6]	2720187	1			T1	1		T2	185		T3	533
all_values[7]	2720187	1			T1	1		T2	185		T3	533

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21388306

1

T1

8

T2

1480

T3

4264

auto[1]

373190

1

T15

25

T16

19137

T18

2129

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21732092

1

T1

8

T2

1480

T3

4264

auto[1]

29404

1

T15

14

T25

705

T16

267

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2659455	1			T1	1		T2	185		T3	533
all_values[0]	auto[0]	auto[1]	13676	1			T25	392		T16	104		T18	48
all_values[0]	auto[1]	auto[0]	46163	1			T15	2		T16	3160		T18	1885
all_values[0]	auto[1]	auto[1]	893	1			T16	29		T18	214		T20	1
all_values[1]	auto[0]	auto[0]	2689264	1			T1	1		T2	185		T3	533
all_values[1]	auto[0]	auto[1]	8905	1			T25	197		T16	94		T18	134
all_values[1]	auto[1]	auto[0]	21675	1			T15	6		T20	8		T21	6
all_values[1]	auto[1]	auto[1]	343	1			T18	3		T20	1		T21	3
all_values[2]	auto[0]	auto[0]	2679474	1			T1	1		T2	185		T3	533
all_values[2]	auto[0]	auto[1]	3292	1			T25	116		T16	25		T18	111
all_values[2]	auto[1]	auto[0]	37088	1			T15	5		T16	3181		T18	1
all_values[2]	auto[1]	auto[1]	333	1			T15	1		T16	8		T18	3
all_values[3]	auto[0]	auto[0]	2685707	1			T1	1		T2	185		T3	533
all_values[3]	auto[0]	auto[1]	211	1			T18	5		T20	4		T21	2
all_values[3]	auto[1]	auto[0]	34059	1			T15	1		T21	5		T36	6
all_values[3]	auto[1]	auto[1]	210	1			T18	3		T20	3		T21	1
all_values[4]	auto[0]	auto[0]	2639044	1			T1	1		T2	185		T3	533
all_values[4]	auto[0]	auto[1]	220	1			T15	3		T18	1		T20	3
all_values[4]	auto[1]	auto[0]	80738	1			T16	3187		T18	2		T20	3
all_values[4]	auto[1]	auto[1]	185	1			T15	1		T16	3		T18	2
all_values[5]	auto[0]	auto[0]	2705567	1			T1	1		T2	185		T3	533
all_values[5]	auto[0]	auto[1]	171	1			T18	2		T20	3		T21	2
all_values[5]	auto[1]	auto[0]	14270	1			T15	4		T16	3187		T18	5
all_values[5]	auto[1]	auto[1]	179	1			T15	2		T16	2		T18	2
all_values[6]	auto[0]	auto[0]	2694314	1			T1	1		T2	185		T3	533
all_values[6]	auto[0]	auto[1]	209	1			T15	2		T18	6		T20	2
all_values[6]	auto[1]	auto[0]	25462	1			T16	3189		T18	2		T20	7
all_values[6]	auto[1]	auto[1]	202	1			T15	2		T16	1		T20	2
all_values[7]	auto[0]	auto[0]	2608611	1			T1	1		T2	185		T3	533
all_values[7]	auto[0]	auto[1]	186	1			T15	3		T18	3		T20	4
all_values[7]	auto[1]	auto[0]	111201	1			T15	1		T16	3189		T18	4
all_values[7]	auto[1]	auto[1]	189	1			T16	1		T18	3		T20	1