Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37148	1			T1	8		T2	17		T3	67
auto[SpiFlashAddrCfg]	8086	1			T1	2		T2	10		T8	12
auto[SpiFlashAddr3b]	9838	1			T1	2		T2	3		T3	8
auto[SpiFlashAddr4b]	7966	1			T1	6		T2	10		T3	12

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35248

1

T2

28

T3

87

T4

14

auto[1]

27790

1

T1

18

T2

12

T12

63

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33038

1

T1

4

T2

29

T3

77

auto[1]

30000

1

T1

14

T2

11

T3

10

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41941	1			T1	8		T2	16		T3	73
values[1]	1171	1			T2	5		T8	2		T12	4
values[2]	1487	1			T2	1		T12	10		T13	9
values[3]	1601	1			T2	5		T3	6		T12	6
values[4]	1614	1			T3	2		T8	4		T12	10
values[5]	1536	1			T1	4		T2	6		T12	2
values[6]	1558	1			T2	1		T3	2		T4	12
values[7]	1597	1			T1	2		T2	2		T3	2
values[8]	10533	1			T1	4		T2	4		T3	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33009

1

T1

18

T2

40

T3

87

auto[1]

30029

1

T12

180

T48

6

T25

316

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

59512

1

T1

18

T2

40

T3

85

write

3526

1

T3

2

T8

8

T12

14

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20633

1

T1

8

T2

17

T3

12

valids[0x1]

42405

1

T1

10

T2

23

T3

75

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1654	1			T2	1		T5	4		T12	7
internal_process_ops[0x5a]	1634	1			T2	1		T12	11		T13	5
internal_process_ops[0x05]	22321	1			T2	3		T3	63		T8	2
internal_process_ops[0x35]	1701	1			T1	8		T2	1		T12	8
internal_process_ops[0x15]	1581	1			T12	7		T13	2		T14	4
internal_process_ops[0x03]	1071	1			T2	1		T12	3		T13	6
internal_process_ops[0x0b]	1086	1			T2	1		T3	4		T4	2
internal_process_ops[0x3b]	1181	1			T2	2		T4	6		T5	4
internal_process_ops[0x6b]	1139	1			T1	2		T2	3		T3	2
internal_process_ops[0xbb]	1102	1			T1	2		T2	3		T4	6
internal_process_ops[0xeb]	1142	1			T1	2		T2	3		T3	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61261

1

T1

18

T2

40

T3

87

auto[1]

1777

1

T12

5

T13

4

T14

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60526

1

T1

18

T2

40

T3

83

auto[1]

2512

1

T3

4

T12

9

T13

11

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10610

1

T2

12

T3

65

T5

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7785

1

T1

8

T2

5

T13

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2116

1

T2

7

T8

12

T13

16

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1901

1

T1

2

T2

3

T13

16

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2632

1

T2

3

T3

8

T4

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2280

1

T1

2

T13

23

T14

7

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2099

1

T2

6

T3

12

T5

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1943

1

T1

6

T2

4

T13

12

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

116

1

T3

2

T16

3

T81

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

103

1

T13

2

T14

1

T16

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

109

1

T13

3

T14

1

T16

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

113

1

T16

2

T52

2

T20

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

120

1

T13

1

T16

1

T79

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

66

1

T16

7

T56

1

T163

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

99

1

T13

1

T16

1

T56

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

114

1

T13

1

T47

1

T56

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

130

1

T15

1

T16

2

T20

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

96

1

T16

2

T20

3

T22

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

91

1

T13

2

T16

2

T53

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

120

1

T50

2

T16

2

T53

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

99

1

T8

8

T16

3

T164

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

70

1

T13

1

T53

1

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

83

1

T16

2

T21

1

T165

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

114

1

T16

2

T56

2

T166

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10729

1

T12

53

T25

101

T18

154

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7118

1

T12

22

T25

68

T18

180

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1641

1

T12

23

T48

4

T25

20

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1548

1

T12

11

T25

15

T18

35

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2062

1

T12

15

T25

18

T80

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1963

1

T12

20

T25

27

T18

24

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1596

1

T12

16

T48

2

T25

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1489

1

T12

6

T25

20

T18

25

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

114

1

T12

2

T25

2

T18

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

122

1

T12

2

T25

2

T18

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

109

1

T12

1

T18

2

T71

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

120

1

T12

1

T25

2

T18

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

125

1

T12

1

T25

1

T18

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

126

1

T25

2

T18

1

T71

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

107

1

T12

2

T25

6

T18

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

123

1

T71

1

T167

1

T90

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

113

1

T12

2

T25

1

T18

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

106

1

T25

1

T18

4

T71

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

105

1

T71

2

T167

3

T86

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

140

1

T25

6

T18

1

T90

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

131

1

T12

1

T18

3

T71

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

126

1

T12

2

T25

1

T167

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

98

1

T25

2

T167

1

T168

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

118

1

T25

3

T18

1

T71

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3998	1			T2	5		T3	2		T13	28
auto[0]	values[0]	valids[0x1]	17251	1			T1	8		T2	11		T3	71
auto[0]	values[1]	valids[0x1]	579	1			T2	5		T8	2		T13	4
auto[0]	values[2]	valids[0x0]	563	1			T2	1		T13	7		T14	1
auto[0]	values[2]	valids[0x1]	274	1			T13	2		T14	2		T57	2
auto[0]	values[3]	valids[0x0]	619	1			T2	4		T3	4		T13	4
auto[0]	values[3]	valids[0x1]	311	1			T2	1		T3	2		T16	3
auto[0]	values[4]	valids[0x0]	615	1			T3	2		T8	4		T13	5
auto[0]	values[4]	valids[0x1]	347	1			T13	5		T14	5		T16	7
auto[0]	values[5]	valids[0x0]	536	1			T1	4		T2	3		T13	9
auto[0]	values[5]	valids[0x1]	326	1			T2	3		T13	1		T14	2
auto[0]	values[6]	valids[0x0]	579	1			T2	1		T4	12		T13	5
auto[0]	values[6]	valids[0x1]	311	1			T3	2		T5	6		T13	2
auto[0]	values[7]	valids[0x0]	568	1			T1	2		T2	2		T3	2
auto[0]	values[7]	valids[0x1]	324	1			T8	2		T13	3		T14	2
auto[0]	values[8]	valids[0x0]	3672	1			T1	2		T2	1		T3	2
auto[0]	values[8]	valids[0x1]	2136	1			T1	2		T2	3		T4	2
auto[1]	values[0]	valids[0x0]	4249	1			T12	38		T25	56		T18	70
auto[1]	values[0]	valids[0x1]	16443	1			T12	62		T25	152		T80	1
auto[1]	values[1]	valids[0x1]	592	1			T12	4		T25	7		T18	14
auto[1]	values[2]	valids[0x0]	402	1			T12	4		T25	5		T18	10
auto[1]	values[2]	valids[0x1]	248	1			T12	6		T18	7		T71	2
auto[1]	values[3]	valids[0x0]	409	1			T12	3		T25	5		T18	9
auto[1]	values[3]	valids[0x1]	262	1			T12	3		T25	6		T18	6
auto[1]	values[4]	valids[0x0]	411	1			T12	5		T25	3		T80	1
auto[1]	values[4]	valids[0x1]	241	1			T12	5		T25	3		T18	2
auto[1]	values[5]	valids[0x0]	397	1			T12	2		T25	6		T18	3
auto[1]	values[5]	valids[0x1]	277	1			T18	2		T167	9		T168	2
auto[1]	values[6]	valids[0x0]	384	1			T12	1		T25	7		T18	3
auto[1]	values[6]	valids[0x1]	284	1			T25	1		T18	4		T71	2
auto[1]	values[7]	valids[0x0]	444	1			T12	4		T25	4		T18	15
auto[1]	values[7]	valids[0x1]	261	1			T25	7		T18	2		T71	2
auto[1]	values[8]	valids[0x0]	2787	1			T12	28		T48	6		T25	23
auto[1]	values[8]	valids[0x1]	1938	1			T12	15		T25	31		T18	28