Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3300685

1

T1

1

T2

2573

T3

9

auto[1]

33487

1

T3

63

T12

259

T13

48

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

770167

1

T1

1

T2

86

T3

9

auto[1]

2564005

1

T2

2487

T3

63

T8

4762

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	694955	1			T1	1		T2	21		T3	72
auto[524288:1048575]	380894	1			T4	3894		T12	186		T13	562
auto[1048576:1572863]	379668	1			T4	307		T12	963		T14	15
auto[1572864:2097151]	359608	1			T2	8		T4	7693		T12	3776
auto[2097152:2621439]	388242	1			T2	291		T4	600		T12	5719
auto[2621440:3145727]	384629	1			T2	14		T4	4446		T12	545
auto[3145728:3670015]	415507	1			T2	2239		T4	2567		T12	5332
auto[3670016:4194303]	330669	1			T4	1424		T12	21		T13	359

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2599315

1

T1

1

T2

2573

T3

69

auto[1]

734857

1

T3

3

T4

22608

T12

6

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2839724

1

T1

1

T2

2557

T3

72

auto[1]

494448

1

T2

16

T12

2381

T13

3294

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	170489	1			T1	1		T2	5		T3	5
auto[0]	auto[0]	auto[0:524287]	auto[1]	432002	1			T3	4		T8	4762		T12	1033
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	68215	1			T4	3894		T12	24		T13	34
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	249649	1			T12	158		T13	512		T14	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	85255	1			T4	307		T12	39		T14	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	232511	1			T12	918		T14	1		T58	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	82706	1			T2	8		T4	7693		T12	38
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	207707	1			T12	2142		T25	1219		T39	527
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	77808	1			T2	32		T4	600		T12	26
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	254922	1			T2	259		T12	5393		T14	2612
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	87992	1			T2	14		T4	4446		T12	26
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	231525	1			T25	2804		T16	6102		T18	1537
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	94313	1			T2	11		T4	2567		T12	43
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	260077	1			T2	2228		T12	5285		T14	196
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	85679	1			T4	1424		T12	2		T13	72
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	191682	1			T14	4583		T25	123		T16	3107
auto[0]	auto[1]	auto[0:524287]	auto[0]	2847	1			T2	16		T12	32		T18	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	83922	1			T18	256		T54	48		T90	1734
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2622	1			T13	9		T16	4		T18	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	56114	1			T18	11		T71	3270		T53	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2914	1			T12	6		T16	5		T18	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	54733	1			T16	2786		T18	2		T71	384
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1456	1			T12	56		T59	2		T25	10
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	62865	1			T12	1302		T25	772		T18	513
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	832	1			T12	28		T13	2		T15	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	51709	1			T12	272		T15	1		T18	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	899	1			T12	4		T13	8		T14	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	60413	1			T12	512		T15	256		T25	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1295	1			T12	4		T13	41		T14	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	55725	1			T13	2962		T14	2756		T25	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	711	1			T12	10		T13	9		T25	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	49096	1			T13	256		T167	257		T90	133
auto[1]	auto[0]	auto[0:524287]	auto[0]	540	1			T3	4		T25	1		T16	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	4161	1			T3	59		T16	51		T70	12
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	492	1			T12	4		T16	2		T53	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3411	1			T16	71		T53	5		T168	24
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	399	1			T14	1		T25	2		T16	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2550	1			T14	12		T25	7		T16	135
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	396	1			T13	5		T25	2		T16	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3652	1			T12	100		T25	1		T16	25
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	316	1			T13	8		T14	2		T25	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1817	1			T14	23		T25	8		T16	25
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	365	1			T25	5		T16	5		T18	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2708	1			T25	12		T16	12		T18	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	354	1			T13	6		T25	1		T16	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3115	1			T25	2		T16	33		T167	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	475	1			T13	22		T16	2		T18	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2441	1			T16	68		T18	6		T167	53
auto[1]	auto[1]	auto[0:524287]	auto[0]	133	1			T12	5		T168	1		T193	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	861	1			T168	29		T193	23		T187	6
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	75	1			T13	7		T18	3		T53	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	316	1			T18	36		T53	49		T21	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	114	1			T16	2		T18	2		T71	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1192	1			T16	3		T18	13		T167	98
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	99	1			T12	15		T25	2		T71	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	727	1			T12	123		T25	5		T71	28
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	78	1			T15	1		T18	2		T63	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	760	1			T15	53		T18	2		T232	6
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	95	1			T12	3		T25	1		T16	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	632	1			T25	1		T20	9		T56	68
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	107	1			T14	1		T25	1		T71	16
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	521	1			T14	1		T25	1		T71	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	96	1			T12	9		T167	1		T90	11
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	489	1			T167	1		T249	5		T56	8

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2086395	1			T1	1		T2	2557		T3	9
auto[0]	auto[0]	auto[1]	726137	1			T4	22608		T48	720		T58	3475
auto[0]	auto[1]	auto[0]	480105	1			T2	16		T12	2226		T13	3287
auto[0]	auto[1]	auto[1]	8048	1			T14	1		T59	1		T167	2
auto[1]	auto[0]	auto[0]	26670	1			T3	60		T12	103		T13	33
auto[1]	auto[0]	auto[1]	522	1			T3	3		T12	1		T13	8
auto[1]	auto[1]	auto[0]	6145	1			T12	150		T13	6		T14	2
auto[1]	auto[1]	auto[1]	150	1			T12	5		T13	1		T18	1