Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2720187	1			T1	1		T2	185		T3	533
all_pins[1]	2720187	1			T1	1		T2	185		T3	533
all_pins[2]	2720187	1			T1	1		T2	185		T3	533
all_pins[3]	2720187	1			T1	1		T2	185		T3	533
all_pins[4]	2720187	1			T1	1		T2	185		T3	533
all_pins[5]	2720187	1			T1	1		T2	185		T3	533
all_pins[6]	2720187	1			T1	1		T2	185		T3	533
all_pins[7]	2720187	1			T1	1		T2	185		T3	533

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21733724	1			T1	8		T2	1480		T3	4264
values[0x1]	27772	1			T15	6		T16	3302		T18	246
transitions[0x0=>0x1]	27176	1			T15	4		T16	3241		T18	240
transitions[0x1=>0x0]	27185	1			T15	4		T16	3241		T18	240

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2719231	1			T1	1		T2	185		T3	533
all_pins[0]	values[0x1]	956	1			T16	44		T18	230		T20	1
all_pins[0]	transitions[0x0=>0x1]	789	1			T16	44		T18	230		T21	2
all_pins[0]	transitions[0x1=>0x0]	186	1			T18	3		T21	2		T161	5
all_pins[1]	values[0x0]	2719834	1			T1	1		T2	185		T3	533
all_pins[1]	values[0x1]	353	1			T18	3		T20	1		T21	3
all_pins[1]	transitions[0x0=>0x1]	265	1			T18	1		T20	1		T21	2
all_pins[1]	transitions[0x1=>0x0]	267	1			T15	1		T16	16		T18	1
all_pins[2]	values[0x0]	2719832	1			T1	1		T2	185		T3	533
all_pins[2]	values[0x1]	355	1			T15	1		T16	16		T18	3
all_pins[2]	transitions[0x0=>0x1]	305	1			T15	1		T16	16		T18	1
all_pins[2]	transitions[0x1=>0x0]	160	1			T18	1		T20	2		T21	1
all_pins[3]	values[0x0]	2719977	1			T1	1		T2	185		T3	533
all_pins[3]	values[0x1]	210	1			T18	3		T20	3		T21	1
all_pins[3]	transitions[0x0=>0x1]	154	1			T18	2		T20	3		T36	1
all_pins[3]	transitions[0x1=>0x0]	129	1			T15	1		T16	3		T18	1
all_pins[4]	values[0x0]	2720002	1			T1	1		T2	185		T3	533
all_pins[4]	values[0x1]	185	1			T15	1		T16	3		T18	2
all_pins[4]	transitions[0x0=>0x1]	150	1			T16	1		T18	2		T20	1
all_pins[4]	transitions[0x1=>0x0]	618	1			T15	1		T16	58		T18	2
all_pins[5]	values[0x0]	2719534	1			T1	1		T2	185		T3	533
all_pins[5]	values[0x1]	653	1			T15	2		T16	60		T18	2
all_pins[5]	transitions[0x0=>0x1]	553	1			T15	1		T16	2		T18	2
all_pins[5]	transitions[0x1=>0x0]	24771	1			T15	1		T16	3120		T21	5
all_pins[6]	values[0x0]	2695316	1			T1	1		T2	185		T3	533
all_pins[6]	values[0x1]	24871	1			T15	2		T16	3178		T20	2
all_pins[6]	transitions[0x0=>0x1]	24823	1			T15	2		T16	3177		T20	1
all_pins[6]	transitions[0x1=>0x0]	141	1			T18	3		T36	1		T161	2
all_pins[7]	values[0x0]	2719998	1			T1	1		T2	185		T3	533
all_pins[7]	values[0x1]	189	1			T16	1		T18	3		T20	1
all_pins[7]	transitions[0x0=>0x1]	137	1			T16	1		T18	2		T20	1
all_pins[7]	transitions[0x1=>0x0]	913	1			T16	44		T18	229		T20	1