Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18257

1

T2

28

T3

87

T4

14

auto[1]

14752

1

T1

18

T2

12

T13

68

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5144	1			T5	10		T57	22		T16	442
values[1]	4015	1			T14	20		T50	22		T68	4
values[2]	3816	1			T13	20		T14	33		T16	64
values[3]	3594	1			T2	20		T13	60		T14	22
values[4]	3917	1			T13	20		T58	2		T181	4
values[5]	3943	1			T3	87		T4	14		T13	20
values[6]	4147	1			T1	18		T2	20		T13	20
values[7]	4433	1			T8	26		T13	20		T14	45

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4543	1			T2	20		T13	20		T14	45
values[1]	3784	1			T4	14		T13	20		T16	23
values[2]	4462	1			T8	26		T13	60		T181	4
values[3]	4279	1			T13	20		T14	20		T27	22
values[4]	4169	1			T1	18		T50	22		T58	2
values[5]	4072	1			T15	74		T67	2		T93	10
values[6]	3419	1			T3	87		T13	20		T14	22
values[7]	4281	1			T2	20		T5	10		T13	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	265	1			T16	125		T166	8		T22	10
auto[0]	values[0]	values[1]	225	1			T16	14		T20	12		T250	12
auto[0]	values[0]	values[2]	324	1			T47	9		T56	4		T132	12
auto[0]	values[0]	values[3]	429	1			T56	11		T186	6		T192	107
auto[0]	values[0]	values[4]	290	1			T53	13		T20	16		T251	4
auto[0]	values[0]	values[5]	435	1			T53	12		T189	9		T252	10
auto[0]	values[0]	values[6]	339	1			T16	88		T22	11		T198	28
auto[0]	values[0]	values[7]	334	1			T5	10		T16	46		T233	14
auto[0]	values[1]	values[0]	439	1			T16	14		T187	18		T253	229
auto[0]	values[1]	values[1]	280	1			T83	12		T254	14		T153	12
auto[0]	values[1]	values[2]	208	1			T68	4		T16	9		T84	10
auto[0]	values[1]	values[3]	318	1			T14	15		T165	14		T153	11
auto[0]	values[1]	values[4]	285	1			T21	13		T165	11		T255	8
auto[0]	values[1]	values[5]	212	1			T248	16		T22	34		T163	12
auto[0]	values[1]	values[6]	196	1			T189	13		T234	11		T223	17
auto[0]	values[1]	values[7]	349	1			T16	12		T256	32		T163	8
auto[0]	values[2]	values[0]	247	1			T16	17		T257	8		T20	24
auto[0]	values[2]	values[1]	327	1			T20	22		T258	6		T153	75
auto[0]	values[2]	values[2]	361	1			T13	11		T189	14		T234	18
auto[0]	values[2]	values[3]	282	1			T259	2		T21	15		T260	8
auto[0]	values[2]	values[4]	240	1			T16	11		T261	26		T238	15
auto[0]	values[2]	values[5]	443	1			T198	203		T262	15		T199	17
auto[0]	values[2]	values[6]	222	1			T16	19		T198	13		T263	14
auto[0]	values[2]	values[7]	330	1			T14	22		T54	12		T21	17
auto[0]	values[3]	values[0]	230	1			T2	13		T53	17		T244	10
auto[0]	values[3]	values[1]	174	1			T13	12		T191	8		T195	5
auto[0]	values[3]	values[2]	256	1			T13	18		T190	14		T234	12
auto[0]	values[3]	values[3]	206	1			T20	9		T153	11		T189	24
auto[0]	values[3]	values[4]	425	1			T54	14		T247	24		T198	8
auto[0]	values[3]	values[5]	315	1			T191	14		T190	16		T235	9
auto[0]	values[3]	values[6]	138	1			T14	16		T243	14		T47	21
auto[0]	values[3]	values[7]	296	1			T53	11		T163	12		T187	16
auto[0]	values[4]	values[0]	307	1			T13	10		T20	29		T56	9
auto[0]	values[4]	values[1]	247	1			T202	8		T264	12		T212	12
auto[0]	values[4]	values[2]	214	1			T181	4		T22	8		T265	12
auto[0]	values[4]	values[3]	339	1			T163	12		T192	15		T203	38
auto[0]	values[4]	values[4]	205	1			T58	2		T214	18		T187	8
auto[0]	values[4]	values[5]	238	1			T15	11		T93	10		T20	17
auto[0]	values[4]	values[6]	385	1			T56	23		T165	15		T153	15
auto[0]	values[4]	values[7]	265	1			T266	52		T187	23		T153	11
auto[0]	values[5]	values[0]	270	1			T56	89		T226	13		T189	15
auto[0]	values[5]	values[1]	414	1			T4	14		T54	15		T267	8
auto[0]	values[5]	values[2]	306	1			T268	4		T22	35		T190	4
auto[0]	values[5]	values[3]	347	1			T13	14		T54	11		T21	17
auto[0]	values[5]	values[4]	175	1			T16	45		T269	11		T270	62
auto[0]	values[5]	values[5]	217	1			T54	8		T186	11		T271	16
auto[0]	values[5]	values[6]	296	1			T3	87		T91	4		T189	14
auto[0]	values[5]	values[7]	177	1			T22	10		T191	14		T221	8
auto[0]	values[6]	values[0]	299	1			T16	24		T81	14		T165	8
auto[0]	values[6]	values[1]	162	1			T70	32		T163	7		T272	14
auto[0]	values[6]	values[2]	397	1			T56	8		T153	14		T189	12
auto[0]	values[6]	values[3]	322	1			T27	22		T54	8		T20	28
auto[0]	values[6]	values[4]	212	1			T47	14		T166	12		T165	9
auto[0]	values[6]	values[5]	145	1			T67	2		T16	12		T187	8
auto[0]	values[6]	values[6]	173	1			T13	12		T56	13		T252	9
auto[0]	values[6]	values[7]	366	1			T2	15		T54	9		T273	2
auto[0]	values[7]	values[0]	327	1			T14	41		T274	2		T164	12
auto[0]	values[7]	values[1]	202	1			T229	14		T22	11		T187	17
auto[0]	values[7]	values[2]	362	1			T8	26		T187	10		T217	9
auto[0]	values[7]	values[3]	273	1			T16	13		T226	14		T236	12
auto[0]	values[7]	values[4]	212	1			T59	14		T16	10		T53	14
auto[0]	values[7]	values[5]	356	1			T275	10		T22	8		T276	14
auto[0]	values[7]	values[6]	215	1			T39	10		T20	14		T153	59
auto[0]	values[7]	values[7]	412	1			T13	15		T16	17		T79	10
auto[1]	values[0]	values[0]	291	1			T16	144		T166	17		T22	25
auto[1]	values[0]	values[1]	208	1			T16	9		T20	9		T189	51
auto[1]	values[0]	values[2]	356	1			T47	12		T56	41		T198	33
auto[1]	values[0]	values[3]	292	1			T56	9		T186	16		T192	72
auto[1]	values[0]	values[4]	454	1			T53	18		T277	4		T20	8
auto[1]	values[0]	values[5]	400	1			T53	90		T189	11		T252	10
auto[1]	values[0]	values[6]	362	1			T16	10		T22	11		T198	92
auto[1]	values[0]	values[7]	140	1			T57	22		T16	6		T198	12
auto[1]	values[1]	values[0]	271	1			T16	14		T187	8		T153	14
auto[1]	values[1]	values[1]	317	1			T153	8		T189	2		T236	9
auto[1]	values[1]	values[2]	239	1			T16	73		T153	8		T190	9
auto[1]	values[1]	values[3]	200	1			T14	5		T55	12		T165	6
auto[1]	values[1]	values[4]	256	1			T50	22		T21	7		T165	9
auto[1]	values[1]	values[5]	132	1			T22	12		T163	8		T187	9
auto[1]	values[1]	values[6]	79	1			T189	7		T234	9		T223	3
auto[1]	values[1]	values[7]	234	1			T16	10		T163	12		T187	11
auto[1]	values[2]	values[0]	217	1			T16	3		T219	16		T20	17
auto[1]	values[2]	values[1]	155	1			T20	9		T153	10		T189	8
auto[1]	values[2]	values[2]	268	1			T13	9		T189	6		T234	10
auto[1]	values[2]	values[3]	71	1			T21	5		T236	12		T199	6
auto[1]	values[2]	values[4]	227	1			T16	9		T278	2		T238	5
auto[1]	values[2]	values[5]	168	1			T52	12		T279	16		T198	9
auto[1]	values[2]	values[6]	71	1			T16	5		T198	7		T204	12
auto[1]	values[2]	values[7]	187	1			T14	11		T54	8		T21	9
auto[1]	values[3]	values[0]	183	1			T2	7		T53	74		T20	12
auto[1]	values[3]	values[1]	178	1			T13	8		T191	12		T195	21
auto[1]	values[3]	values[2]	236	1			T13	22		T190	6		T234	8
auto[1]	values[3]	values[3]	245	1			T20	11		T153	37		T189	4
auto[1]	values[3]	values[4]	248	1			T54	6		T198	12		T154	10
auto[1]	values[3]	values[5]	141	1			T191	6		T190	11		T235	11
auto[1]	values[3]	values[6]	156	1			T14	6		T47	8		T163	10
auto[1]	values[3]	values[7]	167	1			T53	9		T163	8		T187	4
auto[1]	values[4]	values[0]	264	1			T13	10		T20	7		T56	17
auto[1]	values[4]	values[1]	123	1			T212	8		T141	6		T200	9
auto[1]	values[4]	values[2]	116	1			T22	12		T191	8		T280	18
auto[1]	values[4]	values[3]	237	1			T163	8		T192	5		T203	16
auto[1]	values[4]	values[4]	297	1			T187	13		T189	8		T223	10
auto[1]	values[4]	values[5]	193	1			T15	63		T20	10		T22	6
auto[1]	values[4]	values[6]	183	1			T56	9		T165	5		T153	5
auto[1]	values[4]	values[7]	304	1			T187	18		T153	116		T189	14
auto[1]	values[5]	values[0]	349	1			T56	7		T226	177		T189	5
auto[1]	values[5]	values[1]	301	1			T54	5		T56	8		T198	105
auto[1]	values[5]	values[2]	219	1			T22	15		T190	16		T154	7
auto[1]	values[5]	values[3]	155	1			T13	6		T54	9		T21	7
auto[1]	values[5]	values[4]	182	1			T16	8		T269	17		T270	12
auto[1]	values[5]	values[5]	205	1			T54	12		T186	17		T203	4
auto[1]	values[5]	values[6]	201	1			T189	8		T203	9		T215	93
auto[1]	values[5]	values[7]	129	1			T22	35		T191	6		T217	17
auto[1]	values[6]	values[0]	399	1			T16	8		T165	12		T192	7
auto[1]	values[6]	values[1]	73	1			T163	13		T165	12		T186	11
auto[1]	values[6]	values[2]	320	1			T56	16		T153	68		T189	8
auto[1]	values[6]	values[3]	216	1			T94	8		T54	12		T20	8
auto[1]	values[6]	values[4]	253	1			T1	18		T47	16		T166	8
auto[1]	values[6]	values[5]	223	1			T16	8		T187	12		T188	4
auto[1]	values[6]	values[6]	279	1			T13	8		T56	7		T252	11
auto[1]	values[6]	values[7]	308	1			T2	5		T54	11		T183	5
auto[1]	values[7]	values[0]	185	1			T14	4		T56	12		T165	12
auto[1]	values[7]	values[1]	398	1			T22	29		T187	7		T189	192
auto[1]	values[7]	values[2]	280	1			T187	19		T217	11		T64	14
auto[1]	values[7]	values[3]	347	1			T16	7		T226	8		T236	8
auto[1]	values[7]	values[4]	208	1			T16	15		T53	6		T22	40
auto[1]	values[7]	values[5]	249	1			T22	19		T189	6		T190	10
auto[1]	values[7]	values[6]	124	1			T20	8		T153	8		T186	9
auto[1]	values[7]	values[7]	283	1			T13	5		T16	3		T20	50