Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	413	1			T13	2		T14	1		T39	8
auto[ReadAddrCrossIntoMailbox]	287	1			T13	6		T14	1		T16	3
auto[ReadAddrCrossOutOfMailbox]	304	1			T13	7		T16	3		T53	3
auto[ReadAddrCrossAllMailbox]	240	1			T13	4		T16	1		T53	2
auto[ReadAddrOutsideMailbox]	3765	1			T1	6		T2	13		T3	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2448

1

T1

3

T2

8

T3

4

auto[1]

2561

1

T1

3

T2

5

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	802	1			T2	1		T13	6		T14	1
read_ops[0x0b]	820	1			T2	1		T3	4		T4	2
read_ops[0x3b]	886	1			T2	2		T4	6		T8	4
read_ops[0x6b]	825	1			T1	2		T2	3		T3	2
read_ops[0xbb]	817	1			T1	2		T2	3		T4	6
read_ops[0xeb]	859	1			T1	2		T2	3		T3	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T39	2		T16	1		T20	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T13	1		T39	2		T16	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T13	1		T22	1		T163	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T13	1		T20	1		T198	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T13	1		T53	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T56	2		T187	1		T198	3
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T233	2		T20	1		T247	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T13	1		T233	2		T247	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T13	1		T50	1		T16	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	324	1			T2	1		T14	1		T50	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T67	1		T21	1		T247	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T67	1		T53	1		T247	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T21	1		T247	1		T56	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T16	1		T247	1		T187	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	13	1			T53	1		T191	2		T188	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T53	1		T54	1		T198	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T16	1		T56	1		T22	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T13	1		T198	3		T153	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T2	1		T3	2		T4	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	323	1			T3	2		T4	1		T8	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T83	2		T20	2		T247	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T83	2		T21	1		T247	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T247	1		T187	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T13	1		T247	1		T56	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T13	1		T16	1		T56	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T54	1		T186	1		T262	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T53	1		T20	1		T56	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T53	1		T47	1		T166	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	316	1			T4	3		T8	2		T13	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T2	2		T4	3		T8	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T39	1		T53	1		T20	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T39	1		T16	3		T21	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T13	1		T20	1		T166	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T14	1		T166	1		T22	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T13	1		T247	1		T47	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T13	1		T21	1		T247	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T13	1		T259	1		T56	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T259	1		T21	2		T47	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	322	1			T1	1		T2	1		T3	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T1	1		T2	2		T3	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T39	1		T20	2		T247	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T14	1		T39	1		T16	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T166	1		T165	1		T187	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T13	1		T16	1		T21	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T166	1		T191	1		T205	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T16	2		T190	1		T186	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T13	1		T20	1		T247	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T20	1		T247	1		T22	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T1	1		T2	3		T4	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T1	1		T4	3		T13	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T233	1		T21	2		T189	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T13	1		T53	1		T233	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T233	1		T187	1		T189	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T13	1		T16	1		T233	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T13	1		T166	1		T187	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T13	2		T187	2		T198	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T223	2		T281	1		T282	3
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T22	2		T198	1		T191	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	360	1			T1	1		T2	3		T3	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T1	1		T3	1		T13	1