Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	860	1			T15	4		T16	4		T18	11
all_values[1]	860	1			T15	4		T16	4		T18	11
all_values[2]	860	1			T15	4		T16	4		T18	11
all_values[3]	860	1			T15	4		T16	4		T18	11
all_values[4]	860	1			T15	4		T16	4		T18	11
all_values[5]	860	1			T15	4		T16	4		T18	11
all_values[6]	860	1			T15	4		T16	4		T18	11
all_values[7]	860	1			T15	4		T16	4		T18	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3623

1

T15

22

T16

16

T18

52

auto[1]

3257

1

T15

10

T16

16

T18

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2801

1

T15

15

T16

14

T18

29

auto[1]

4079

1

T15

17

T16

18

T18

59

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3945

1

T15

22

T16

18

T18

46

auto[1]

2935

1

T15

10

T16

14

T18

42

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	143	1			T15	2		T20	1		T21	1
all_values[0]	auto[0]	auto[0]	auto[1]	85	1			T18	1		T21	1		T36	2
all_values[0]	auto[0]	auto[1]	auto[0]	175	1			T15	1		T18	3		T20	4
all_values[0]	auto[0]	auto[1]	auto[1]	76	1			T16	1		T18	1		T21	2
all_values[0]	auto[1]	auto[0]	auto[1]	213	1			T15	1		T16	1		T18	4
all_values[0]	auto[1]	auto[1]	auto[1]	168	1			T16	2		T18	2		T20	2
all_values[1]	auto[0]	auto[0]	auto[0]	157	1			T15	1		T16	3		T20	1
all_values[1]	auto[0]	auto[0]	auto[1]	91	1			T18	2		T36	3		T161	2
all_values[1]	auto[0]	auto[1]	auto[0]	139	1			T15	2		T20	6		T21	5
all_values[1]	auto[0]	auto[1]	auto[1]	83	1			T18	1		T36	1		T161	1
all_values[1]	auto[1]	auto[0]	auto[1]	204	1			T15	1		T16	1		T18	6
all_values[1]	auto[1]	auto[1]	auto[1]	186	1			T18	2		T20	2		T21	5
all_values[2]	auto[0]	auto[0]	auto[0]	203	1			T15	1		T18	1		T20	4
all_values[2]	auto[0]	auto[0]	auto[1]	86	1			T16	1		T18	1		T21	4
all_values[2]	auto[0]	auto[1]	auto[0]	152	1			T15	2		T18	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[1]	66	1			T16	1		T18	2		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	187	1			T16	2		T18	3		T20	2
all_values[2]	auto[1]	auto[1]	auto[1]	166	1			T15	1		T18	3		T20	2
all_values[3]	auto[0]	auto[0]	auto[0]	153	1			T15	2		T16	3		T18	2
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T18	1		T20	2		T21	1
all_values[3]	auto[0]	auto[1]	auto[0]	170	1			T15	1		T21	2		T36	3
all_values[3]	auto[0]	auto[1]	auto[1]	90	1			T18	2		T161	1		T162	1
all_values[3]	auto[1]	auto[0]	auto[1]	186	1			T15	1		T16	1		T18	4
all_values[3]	auto[1]	auto[1]	auto[1]	174	1			T18	2		T20	5		T21	3
all_values[4]	auto[0]	auto[0]	auto[0]	184	1			T18	5		T20	2		T161	7
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T15	3		T20	3		T21	2
all_values[4]	auto[0]	auto[1]	auto[0]	137	1			T18	2		T20	1		T36	3
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T16	1		T36	4		T161	1
all_values[4]	auto[1]	auto[0]	auto[1]	218	1			T15	1		T16	1		T18	2
all_values[4]	auto[1]	auto[1]	auto[1]	167	1			T16	2		T18	2		T20	1
all_values[5]	auto[0]	auto[0]	auto[0]	274	1			T15	1		T16	1		T18	2
all_values[5]	auto[0]	auto[1]	auto[0]	236	1			T15	1		T16	1		T18	5
all_values[5]	auto[1]	auto[0]	auto[1]	185	1			T15	1		T18	2		T20	3
all_values[5]	auto[1]	auto[1]	auto[1]	165	1			T15	1		T16	2		T18	2
all_values[6]	auto[0]	auto[0]	auto[0]	164	1			T16	1		T18	3		T21	1
all_values[6]	auto[0]	auto[0]	auto[1]	88	1			T15	2		T18	3		T21	2
all_values[6]	auto[0]	auto[1]	auto[0]	158	1			T16	2		T18	1		T20	4
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T15	1		T20	1		T21	2
all_values[6]	auto[1]	auto[0]	auto[1]	190	1			T15	1		T18	3		T20	2
all_values[6]	auto[1]	auto[1]	auto[1]	181	1			T16	1		T18	1		T20	3
all_values[7]	auto[0]	auto[0]	auto[0]	186	1			T15	1		T16	1		T18	1
all_values[7]	auto[0]	auto[0]	auto[1]	72	1			T15	1		T18	2		T20	1
all_values[7]	auto[0]	auto[1]	auto[0]	170	1			T16	2		T18	3		T21	3
all_values[7]	auto[0]	auto[1]	auto[1]	87	1			T18	1		T20	1		T161	1
all_values[7]	auto[1]	auto[0]	auto[1]	187	1			T15	2		T18	4		T20	4
all_values[7]	auto[1]	auto[1]	auto[1]	158	1			T16	1		T20	1		T21	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal