Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg
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Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv



Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 11 0 11 100.00
Crosses 30 0 30 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_active 2 0 2 100.00 100 1 1 2
cp_is_hw_return 2 0 2 100.00 100 1 1 2
cp_is_write 2 0 2 100.00 100 1 1 2
cp_locality 5 0 5 100.00 100 1 1 0


Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 30 0 30 100.00 100 1 1 0


Summary for Variable cp_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1717 1 T7 16 T10 3 T11 15
auto[1] 1803 1 T7 14 T10 1 T11 13



Summary for Variable cp_is_hw_return

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_hw_return

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1876 1 T10 4 T25 17 T26 15
auto[1] 1644 1 T7 30 T11 28 T30 9



Summary for Variable cp_is_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2819 1 T7 30 T10 4 T11 28
auto[1] 701 1 T25 9 T26 4 T38 5



Summary for Variable cp_locality

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_locality

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid[0] 709 1 T7 6 T11 5 T30 3
valid[1] 704 1 T7 6 T11 10 T30 2
valid[2] 698 1 T7 6 T10 3 T11 4
valid[3] 705 1 T7 8 T10 1 T11 5
valid[4] 704 1 T7 4 T11 4 T30 1



Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 30 0 30 100.00
Automatically Generated Cross Bins 30 0 30 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_all

Bins
cp_is_writecp_activecp_localitycp_is_hw_returnCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] valid[0] auto[0] 110 1 T25 1 T26 2 T38 1
auto[0] auto[0] valid[0] auto[1] 165 1 T7 1 T11 2 T30 1
auto[0] auto[0] valid[1] auto[0] 109 1 T25 1 T26 2 T16 3
auto[0] auto[0] valid[1] auto[1] 149 1 T7 4 T11 5 T30 2
auto[0] auto[0] valid[2] auto[0] 118 1 T10 3 T26 1 T16 1
auto[0] auto[0] valid[2] auto[1] 175 1 T7 3 T11 1 T30 1
auto[0] auto[0] valid[3] auto[0] 115 1 T16 1 T323 2 T167 1
auto[0] auto[0] valid[3] auto[1] 146 1 T7 6 T11 4 T33 1
auto[0] auto[0] valid[4] auto[0] 105 1 T16 1 T62 1 T20 1
auto[0] auto[0] valid[4] auto[1] 175 1 T7 2 T11 3 T30 1
auto[0] auto[1] valid[0] auto[0] 143 1 T25 1 T26 2 T16 2
auto[0] auto[1] valid[0] auto[1] 163 1 T7 5 T11 3 T30 2
auto[0] auto[1] valid[1] auto[0] 123 1 T25 1 T26 2 T16 2
auto[0] auto[1] valid[1] auto[1] 178 1 T7 2 T11 5 T31 1
auto[0] auto[1] valid[2] auto[0] 112 1 T25 1 T26 1 T18 2
auto[0] auto[1] valid[2] auto[1] 162 1 T7 3 T11 3 T30 1
auto[0] auto[1] valid[3] auto[0] 127 1 T10 1 T25 1 T38 1
auto[0] auto[1] valid[3] auto[1] 178 1 T7 2 T11 1 T30 1
auto[0] auto[1] valid[4] auto[0] 113 1 T25 2 T26 1 T16 3
auto[0] auto[1] valid[4] auto[1] 153 1 T7 2 T11 1 T33 3
auto[1] auto[0] valid[0] auto[0] 68 1 T18 2 T321 2 T325 1
auto[1] auto[0] valid[1] auto[0] 71 1 T25 1 T38 1 T321 1
auto[1] auto[0] valid[2] auto[0] 66 1 T25 1 T26 1 T18 2
auto[1] auto[0] valid[3] auto[0] 66 1 T26 1 T16 2 T62 1
auto[1] auto[0] valid[4] auto[0] 79 1 T25 1 T38 1 T18 2
auto[1] auto[1] valid[0] auto[0] 60 1 T38 1 T323 1 T325 1
auto[1] auto[1] valid[1] auto[0] 74 1 T25 3 T18 3 T62 1
auto[1] auto[1] valid[2] auto[0] 65 1 T25 1 T26 1 T38 1
auto[1] auto[1] valid[3] auto[0] 73 1 T25 2 T26 1 T38 1
auto[1] auto[1] valid[4] auto[0] 79 1 T16 1 T18 2 T21 2


User Defined Cross Bins for cr_all

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 0 Illegal

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