Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48750

1

T10

51

T29

8

T25

456

auto[1]

18605

1

T7

471

T10

24

T11

405

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49414

1

T7

471

T10

56

T11

405

auto[1]

17941

1

T10

19

T29

6

T25

170

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34681	1			T7	225		T10	41		T11	215
others[1]	5763	1			T7	49		T10	8		T11	25
others[2]	5703	1			T7	45		T10	6		T11	29
others[3]	6442	1			T7	47		T10	10		T11	43
interest[1]	3600	1			T7	22		T10	2		T11	25
interest[4]	22764	1			T7	159		T10	33		T11	142
interest[64]	11166	1			T7	83		T10	8		T11	68

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15753	1			T10	17		T29	1		T25	140
auto[0]	auto[0]	others[1]	2649	1			T10	5		T25	20		T26	22
auto[0]	auto[0]	others[2]	2599	1			T10	2		T25	28		T26	22
auto[0]	auto[0]	others[3]	2908	1			T10	3		T25	28		T26	27
auto[0]	auto[0]	interest[1]	1669	1			T10	1		T25	19		T26	13
auto[0]	auto[0]	interest[4]	10295	1			T10	15		T29	1		T25	83
auto[0]	auto[0]	interest[64]	5231	1			T10	4		T29	1		T25	51
auto[0]	auto[1]	others[0]	9748	1			T7	225		T10	14		T11	215
auto[0]	auto[1]	others[1]	1591	1			T7	49		T10	2		T11	25
auto[0]	auto[1]	others[2]	1559	1			T7	45		T10	2		T11	29
auto[0]	auto[1]	others[3]	1763	1			T7	47		T10	4		T11	43
auto[0]	auto[1]	interest[1]	976	1			T7	22		T11	25		T33	19
auto[0]	auto[1]	interest[4]	6418	1			T7	159		T10	10		T11	142
auto[0]	auto[1]	interest[64]	2968	1			T7	83		T10	2		T11	68
auto[1]	auto[0]	others[0]	9180	1			T10	10		T29	4		T25	96
auto[1]	auto[0]	others[1]	1523	1			T10	1		T25	13		T26	13
auto[1]	auto[0]	others[2]	1545	1			T10	2		T25	13		T26	7
auto[1]	auto[0]	others[3]	1771	1			T10	3		T25	15		T26	16
auto[1]	auto[0]	interest[1]	955	1			T10	1		T25	6		T26	4
auto[1]	auto[0]	interest[4]	6051	1			T10	8		T29	1		T25	68
auto[1]	auto[0]	interest[64]	2967	1			T10	2		T29	2		T25	27

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal