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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T123 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.424497775 Jul 20 05:29:31 PM PDT 24 Jul 20 05:29:35 PM PDT 24 124950464 ps
T1044 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2486543569 Jul 20 05:29:22 PM PDT 24 Jul 20 05:29:23 PM PDT 24 40464594 ps
T1045 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2547641989 Jul 20 05:29:40 PM PDT 24 Jul 20 05:29:44 PM PDT 24 42292021 ps
T124 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2621783686 Jul 20 05:29:21 PM PDT 24 Jul 20 05:29:47 PM PDT 24 2285593287 ps
T125 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3567064930 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:41 PM PDT 24 427531417 ps
T1046 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.269130206 Jul 20 05:29:56 PM PDT 24 Jul 20 05:29:58 PM PDT 24 16762011 ps
T116 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3602361431 Jul 20 05:29:43 PM PDT 24 Jul 20 05:29:46 PM PDT 24 635820568 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2654792392 Jul 20 05:29:31 PM PDT 24 Jul 20 05:29:34 PM PDT 24 16122333 ps
T1048 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1908715324 Jul 20 05:30:01 PM PDT 24 Jul 20 05:30:02 PM PDT 24 79460697 ps
T1049 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3927894727 Jul 20 05:29:57 PM PDT 24 Jul 20 05:29:59 PM PDT 24 35110369 ps
T126 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1480159311 Jul 20 05:29:37 PM PDT 24 Jul 20 05:29:41 PM PDT 24 169318932 ps
T113 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1254281092 Jul 20 05:29:21 PM PDT 24 Jul 20 05:29:26 PM PDT 24 105351999 ps
T99 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3455557399 Jul 20 05:29:38 PM PDT 24 Jul 20 05:29:42 PM PDT 24 299114709 ps
T127 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.786989743 Jul 20 05:29:46 PM PDT 24 Jul 20 05:29:49 PM PDT 24 69378785 ps
T128 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2818758950 Jul 20 05:29:38 PM PDT 24 Jul 20 05:29:42 PM PDT 24 1286940561 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.520486499 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:33 PM PDT 24 33148996 ps
T151 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2951201722 Jul 20 05:29:45 PM PDT 24 Jul 20 05:29:47 PM PDT 24 53517935 ps
T1051 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1651884411 Jul 20 05:29:28 PM PDT 24 Jul 20 05:29:30 PM PDT 24 151811703 ps
T152 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3995027571 Jul 20 05:29:31 PM PDT 24 Jul 20 05:29:42 PM PDT 24 4632974750 ps
T101 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2809948234 Jul 20 05:29:46 PM PDT 24 Jul 20 05:29:50 PM PDT 24 58971479 ps
T1052 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2209182558 Jul 20 05:29:46 PM PDT 24 Jul 20 05:29:48 PM PDT 24 83801811 ps
T106 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2359980024 Jul 20 05:29:37 PM PDT 24 Jul 20 05:29:40 PM PDT 24 35844823 ps
T114 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3677140451 Jul 20 05:29:54 PM PDT 24 Jul 20 05:29:59 PM PDT 24 231901595 ps
T160 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3809648939 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:35 PM PDT 24 1989678672 ps
T1053 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3891401507 Jul 20 05:29:37 PM PDT 24 Jul 20 05:29:38 PM PDT 24 14848662 ps
T102 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.565328775 Jul 20 05:29:47 PM PDT 24 Jul 20 05:29:55 PM PDT 24 213204573 ps
T1054 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3597722860 Jul 20 05:29:57 PM PDT 24 Jul 20 05:29:59 PM PDT 24 13661337 ps
T1055 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3118662736 Jul 20 05:29:46 PM PDT 24 Jul 20 05:29:50 PM PDT 24 242072079 ps
T1056 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3728780271 Jul 20 05:29:38 PM PDT 24 Jul 20 05:29:43 PM PDT 24 58245224 ps
T1057 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2699104346 Jul 20 05:29:58 PM PDT 24 Jul 20 05:30:00 PM PDT 24 75329805 ps
T1058 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.891954982 Jul 20 05:29:38 PM PDT 24 Jul 20 05:29:41 PM PDT 24 136930686 ps
T1059 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.524692948 Jul 20 05:29:52 PM PDT 24 Jul 20 05:29:53 PM PDT 24 32245429 ps
T104 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1108289556 Jul 20 05:29:38 PM PDT 24 Jul 20 05:29:42 PM PDT 24 378832767 ps
T1060 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2213198619 Jul 20 05:29:05 PM PDT 24 Jul 20 05:29:07 PM PDT 24 19842479 ps
T103 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2787426156 Jul 20 05:29:48 PM PDT 24 Jul 20 05:30:12 PM PDT 24 1143820053 ps
T177 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1355029289 Jul 20 05:29:20 PM PDT 24 Jul 20 05:29:28 PM PDT 24 107909425 ps
T1061 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.26042398 Jul 20 05:29:40 PM PDT 24 Jul 20 05:29:45 PM PDT 24 301775603 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.369732737 Jul 20 05:29:22 PM PDT 24 Jul 20 05:29:24 PM PDT 24 14561488 ps
T129 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.749151301 Jul 20 05:29:22 PM PDT 24 Jul 20 05:30:01 PM PDT 24 9740689987 ps
T174 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3436467932 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:54 PM PDT 24 1780265195 ps
T87 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.416968629 Jul 20 05:29:06 PM PDT 24 Jul 20 05:29:08 PM PDT 24 42843421 ps
T1063 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3291708025 Jul 20 05:29:31 PM PDT 24 Jul 20 05:29:34 PM PDT 24 35227245 ps
T1064 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2691327730 Jul 20 05:29:45 PM PDT 24 Jul 20 05:29:47 PM PDT 24 22025283 ps
T108 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4077100824 Jul 20 05:29:29 PM PDT 24 Jul 20 05:29:32 PM PDT 24 90979374 ps
T1065 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3899788491 Jul 20 05:29:54 PM PDT 24 Jul 20 05:29:56 PM PDT 24 14141535 ps
T109 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1510256163 Jul 20 05:29:29 PM PDT 24 Jul 20 05:29:33 PM PDT 24 239029574 ps
T1066 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2476392726 Jul 20 05:29:46 PM PDT 24 Jul 20 05:29:50 PM PDT 24 566556429 ps
T130 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2272543494 Jul 20 05:29:37 PM PDT 24 Jul 20 05:29:39 PM PDT 24 57610799 ps
T1067 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.499758238 Jul 20 05:29:19 PM PDT 24 Jul 20 05:29:29 PM PDT 24 393114237 ps
T1068 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1280831861 Jul 20 05:29:31 PM PDT 24 Jul 20 05:29:37 PM PDT 24 601385084 ps
T1069 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1185078278 Jul 20 05:29:57 PM PDT 24 Jul 20 05:29:59 PM PDT 24 24262127 ps
T1070 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3093588569 Jul 20 05:29:49 PM PDT 24 Jul 20 05:29:52 PM PDT 24 28141945 ps
T1071 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.754056176 Jul 20 05:30:01 PM PDT 24 Jul 20 05:30:02 PM PDT 24 15941236 ps
T1072 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1373327954 Jul 20 05:29:38 PM PDT 24 Jul 20 05:29:40 PM PDT 24 19526289 ps
T1073 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1603786633 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:32 PM PDT 24 10303151 ps
T169 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4278756637 Jul 20 05:29:39 PM PDT 24 Jul 20 05:30:02 PM PDT 24 3951341060 ps
T111 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1370879311 Jul 20 05:29:49 PM PDT 24 Jul 20 05:29:52 PM PDT 24 97308055 ps
T1074 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3803596219 Jul 20 05:29:21 PM PDT 24 Jul 20 05:29:23 PM PDT 24 11772841 ps
T107 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3656459363 Jul 20 05:29:49 PM PDT 24 Jul 20 05:29:52 PM PDT 24 257501196 ps
T1075 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1327898803 Jul 20 05:29:58 PM PDT 24 Jul 20 05:29:59 PM PDT 24 120837578 ps
T1076 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1849935804 Jul 20 05:29:53 PM PDT 24 Jul 20 05:29:54 PM PDT 24 15413715 ps
T1077 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2587026632 Jul 20 05:29:54 PM PDT 24 Jul 20 05:29:56 PM PDT 24 11998090 ps
T1078 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2268929788 Jul 20 05:29:38 PM PDT 24 Jul 20 05:29:40 PM PDT 24 38337394 ps
T1079 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3399032904 Jul 20 05:29:54 PM PDT 24 Jul 20 05:29:56 PM PDT 24 10589389 ps
T1080 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3295390952 Jul 20 05:29:19 PM PDT 24 Jul 20 05:29:42 PM PDT 24 357258033 ps
T1081 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3598053469 Jul 20 05:29:20 PM PDT 24 Jul 20 05:29:26 PM PDT 24 221771410 ps
T1082 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2166399642 Jul 20 05:29:59 PM PDT 24 Jul 20 05:30:01 PM PDT 24 229519890 ps
T1083 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3682391513 Jul 20 05:29:48 PM PDT 24 Jul 20 05:29:51 PM PDT 24 49360148 ps
T112 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2583859213 Jul 20 05:29:50 PM PDT 24 Jul 20 05:29:53 PM PDT 24 109950447 ps
T1084 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.648849696 Jul 20 05:29:48 PM PDT 24 Jul 20 05:29:50 PM PDT 24 14568315 ps
T180 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3279454484 Jul 20 05:29:39 PM PDT 24 Jul 20 05:29:48 PM PDT 24 278374562 ps
T1085 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.348552547 Jul 20 05:29:48 PM PDT 24 Jul 20 05:29:52 PM PDT 24 339727338 ps
T1086 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2024882756 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:33 PM PDT 24 158950352 ps
T1087 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1374591128 Jul 20 05:29:39 PM PDT 24 Jul 20 05:29:43 PM PDT 24 176610410 ps
T171 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3816617671 Jul 20 05:29:49 PM PDT 24 Jul 20 05:30:09 PM PDT 24 414552486 ps
T1088 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1193131896 Jul 20 05:29:40 PM PDT 24 Jul 20 05:29:46 PM PDT 24 51229749 ps
T105 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2565295720 Jul 20 05:29:29 PM PDT 24 Jul 20 05:29:33 PM PDT 24 128769519 ps
T1089 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2504122758 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:33 PM PDT 24 204149255 ps
T170 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3774410695 Jul 20 05:29:46 PM PDT 24 Jul 20 05:30:11 PM PDT 24 1735343024 ps
T88 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2928931569 Jul 20 05:29:20 PM PDT 24 Jul 20 05:29:22 PM PDT 24 33116739 ps
T1090 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1703178069 Jul 20 05:29:31 PM PDT 24 Jul 20 05:29:34 PM PDT 24 227792744 ps
T115 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.223849779 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:36 PM PDT 24 319625026 ps
T172 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.191025003 Jul 20 05:29:31 PM PDT 24 Jul 20 05:29:54 PM PDT 24 2024280252 ps
T178 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4122833852 Jul 20 05:29:28 PM PDT 24 Jul 20 05:29:46 PM PDT 24 279418449 ps
T1091 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2167373758 Jul 20 05:29:08 PM PDT 24 Jul 20 05:29:09 PM PDT 24 47951711 ps
T1092 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.645898498 Jul 20 05:29:32 PM PDT 24 Jul 20 05:29:37 PM PDT 24 166280651 ps
T1093 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1768397992 Jul 20 05:29:20 PM PDT 24 Jul 20 05:29:21 PM PDT 24 19922252 ps
T1094 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.998125966 Jul 20 05:29:55 PM PDT 24 Jul 20 05:29:57 PM PDT 24 95741361 ps
T175 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3757922031 Jul 20 05:29:46 PM PDT 24 Jul 20 05:30:07 PM PDT 24 581338522 ps
T1095 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3146090267 Jul 20 05:29:21 PM PDT 24 Jul 20 05:29:24 PM PDT 24 36568142 ps
T1096 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.622381205 Jul 20 05:29:08 PM PDT 24 Jul 20 05:29:10 PM PDT 24 27254293 ps
T1097 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2164615134 Jul 20 05:29:55 PM PDT 24 Jul 20 05:29:58 PM PDT 24 38464039 ps
T1098 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3863438181 Jul 20 05:29:42 PM PDT 24 Jul 20 05:29:45 PM PDT 24 245915902 ps
T1099 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1951740836 Jul 20 05:29:39 PM PDT 24 Jul 20 05:29:42 PM PDT 24 17763382 ps
T1100 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2934965906 Jul 20 05:29:40 PM PDT 24 Jul 20 05:29:45 PM PDT 24 110020505 ps
T1101 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4151677328 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:32 PM PDT 24 17507276 ps
T1102 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2071807144 Jul 20 05:29:55 PM PDT 24 Jul 20 05:29:58 PM PDT 24 13685071 ps
T110 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1171026871 Jul 20 05:29:31 PM PDT 24 Jul 20 05:29:36 PM PDT 24 143097007 ps
T1103 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.970773391 Jul 20 05:30:02 PM PDT 24 Jul 20 05:30:04 PM PDT 24 28736245 ps
T1104 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.548814783 Jul 20 05:29:31 PM PDT 24 Jul 20 05:30:05 PM PDT 24 529743852 ps
T1105 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1652306231 Jul 20 05:29:47 PM PDT 24 Jul 20 05:29:53 PM PDT 24 86007029 ps
T1106 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.546117481 Jul 20 05:29:29 PM PDT 24 Jul 20 05:29:31 PM PDT 24 212171955 ps
T1107 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1558866990 Jul 20 05:29:36 PM PDT 24 Jul 20 05:29:40 PM PDT 24 102253488 ps
T1108 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1694770856 Jul 20 05:29:38 PM PDT 24 Jul 20 05:30:00 PM PDT 24 791119530 ps
T1109 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3954927969 Jul 20 05:29:46 PM PDT 24 Jul 20 05:29:50 PM PDT 24 90717219 ps
T176 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2888153596 Jul 20 05:29:34 PM PDT 24 Jul 20 05:29:58 PM PDT 24 1068284219 ps
T1110 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3521075023 Jul 20 05:29:55 PM PDT 24 Jul 20 05:29:58 PM PDT 24 26851708 ps
T1111 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1493690639 Jul 20 05:29:45 PM PDT 24 Jul 20 05:29:48 PM PDT 24 63974469 ps
T1112 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2422049500 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:33 PM PDT 24 29480431 ps
T89 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1772307950 Jul 20 05:29:31 PM PDT 24 Jul 20 05:29:34 PM PDT 24 37137458 ps
T1113 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.651677931 Jul 20 05:29:19 PM PDT 24 Jul 20 05:29:42 PM PDT 24 5359001009 ps
T1114 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2816072925 Jul 20 05:29:31 PM PDT 24 Jul 20 05:29:35 PM PDT 24 17577997 ps
T1115 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.711697751 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:32 PM PDT 24 13143191 ps
T1116 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3378212019 Jul 20 05:29:40 PM PDT 24 Jul 20 05:29:45 PM PDT 24 191467472 ps
T1117 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.504448633 Jul 20 05:29:53 PM PDT 24 Jul 20 05:29:54 PM PDT 24 61805282 ps
T1118 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2542676261 Jul 20 05:29:45 PM PDT 24 Jul 20 05:29:46 PM PDT 24 19790429 ps
T1119 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2528841260 Jul 20 05:29:10 PM PDT 24 Jul 20 05:29:23 PM PDT 24 193530213 ps
T1120 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3028834599 Jul 20 05:29:55 PM PDT 24 Jul 20 05:29:57 PM PDT 24 119772511 ps
T1121 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1150258116 Jul 20 05:29:29 PM PDT 24 Jul 20 05:29:32 PM PDT 24 161345873 ps
T1122 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2686596848 Jul 20 05:29:31 PM PDT 24 Jul 20 05:29:34 PM PDT 24 11423275 ps
T1123 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.244030353 Jul 20 05:29:48 PM PDT 24 Jul 20 05:29:51 PM PDT 24 69964594 ps
T1124 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2991199618 Jul 20 05:29:39 PM PDT 24 Jul 20 05:29:49 PM PDT 24 338375699 ps
T1125 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1572718222 Jul 20 05:29:08 PM PDT 24 Jul 20 05:29:11 PM PDT 24 36597743 ps
T1126 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1324875639 Jul 20 05:29:19 PM PDT 24 Jul 20 05:29:21 PM PDT 24 150560558 ps
T1127 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1014148242 Jul 20 05:30:01 PM PDT 24 Jul 20 05:30:02 PM PDT 24 32825919 ps
T1128 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2983157052 Jul 20 05:29:47 PM PDT 24 Jul 20 05:29:51 PM PDT 24 261021594 ps
T1129 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2896950863 Jul 20 05:29:38 PM PDT 24 Jul 20 05:29:40 PM PDT 24 14440998 ps
T1130 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2308944224 Jul 20 05:29:47 PM PDT 24 Jul 20 05:29:50 PM PDT 24 183065365 ps
T1131 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2564856991 Jul 20 05:29:54 PM PDT 24 Jul 20 05:29:57 PM PDT 24 11198626 ps
T179 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2760067340 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:53 PM PDT 24 946615501 ps
T1132 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1729021989 Jul 20 05:29:49 PM PDT 24 Jul 20 05:29:52 PM PDT 24 226684521 ps
T1133 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.558730650 Jul 20 05:29:49 PM PDT 24 Jul 20 05:29:53 PM PDT 24 62022677 ps
T1134 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1404132763 Jul 20 05:29:37 PM PDT 24 Jul 20 05:29:45 PM PDT 24 437581457 ps
T1135 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2639020335 Jul 20 05:29:30 PM PDT 24 Jul 20 05:29:36 PM PDT 24 302983809 ps
T1136 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1121991088 Jul 20 05:29:49 PM PDT 24 Jul 20 05:29:51 PM PDT 24 11971472 ps
T1137 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3175575103 Jul 20 05:29:20 PM PDT 24 Jul 20 05:29:23 PM PDT 24 106112978 ps
T1138 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3730122652 Jul 20 05:29:19 PM PDT 24 Jul 20 05:29:21 PM PDT 24 33483282 ps
T173 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1298055581 Jul 20 05:29:46 PM PDT 24 Jul 20 05:29:56 PM PDT 24 2330062454 ps
T1139 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.844827215 Jul 20 05:29:38 PM PDT 24 Jul 20 05:29:44 PM PDT 24 666864527 ps
T1140 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1056946660 Jul 20 05:29:43 PM PDT 24 Jul 20 05:29:46 PM PDT 24 409645372 ps
T1141 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2242467401 Jul 20 05:29:19 PM PDT 24 Jul 20 05:29:21 PM PDT 24 86952789 ps
T1142 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2188074516 Jul 20 05:29:49 PM PDT 24 Jul 20 05:29:53 PM PDT 24 36022738 ps
T1143 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3902732147 Jul 20 05:29:37 PM PDT 24 Jul 20 05:29:52 PM PDT 24 213567985 ps
T1144 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1686294450 Jul 20 05:29:39 PM PDT 24 Jul 20 05:29:44 PM PDT 24 645077573 ps
T1145 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4108565333 Jul 20 05:29:29 PM PDT 24 Jul 20 05:29:41 PM PDT 24 185974360 ps
T1146 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1448899896 Jul 20 05:29:22 PM PDT 24 Jul 20 05:29:26 PM PDT 24 353139183 ps
T1147 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.233765040 Jul 20 05:29:56 PM PDT 24 Jul 20 05:29:59 PM PDT 24 65830539 ps
T1148 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.473907014 Jul 20 05:29:31 PM PDT 24 Jul 20 05:29:35 PM PDT 24 67291777 ps
T1149 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2417602521 Jul 20 05:29:29 PM PDT 24 Jul 20 05:29:33 PM PDT 24 645835346 ps
T1150 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1358797336 Jul 20 05:29:10 PM PDT 24 Jul 20 05:29:12 PM PDT 24 97943552 ps
T1151 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.444237539 Jul 20 05:29:40 PM PDT 24 Jul 20 05:29:43 PM PDT 24 53461416 ps

Test location /workspace/coverage/default/24.spi_device_upload.620855624
Short name T3
Test name
Test status
Simulation time 48303969517 ps
CPU time 13.4 seconds
Started Jul 20 05:39:36 PM PDT 24
Finished Jul 20 05:39:50 PM PDT 24
Peak memory 225180 kb
Host smart-efc4fd5f-0d14-49fe-9755-55cbeabb1ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620855624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.620855624
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2734027790
Short name T16
Test name
Test status
Simulation time 18154475613 ps
CPU time 274.47 seconds
Started Jul 20 05:38:04 PM PDT 24
Finished Jul 20 05:42:40 PM PDT 24
Peak memory 282500 kb
Host smart-d7127617-8577-4751-8f28-6f147b99c6d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734027790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2734027790
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.732189294
Short name T11
Test name
Test status
Simulation time 14086489465 ps
CPU time 11.47 seconds
Started Jul 20 05:39:48 PM PDT 24
Finished Jul 20 05:40:01 PM PDT 24
Peak memory 216788 kb
Host smart-f9319eff-1e9b-4075-b001-bee2ed7fbb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732189294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.732189294
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1813423952
Short name T18
Test name
Test status
Simulation time 41435674951 ps
CPU time 117.54 seconds
Started Jul 20 05:40:43 PM PDT 24
Finished Jul 20 05:42:41 PM PDT 24
Peak memory 257476 kb
Host smart-cbf168bd-db1f-4838-b8fa-0c65b4ff4e01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813423952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1813423952
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1359049408
Short name T98
Test name
Test status
Simulation time 1067398956 ps
CPU time 21.18 seconds
Started Jul 20 05:29:19 PM PDT 24
Finished Jul 20 05:29:41 PM PDT 24
Peak memory 216072 kb
Host smart-b9abce52-44b4-4a1d-b8a8-7ce7781dc8b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359049408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1359049408
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4216601385
Short name T189
Test name
Test status
Simulation time 278292582450 ps
CPU time 564.99 seconds
Started Jul 20 05:41:16 PM PDT 24
Finished Jul 20 05:50:42 PM PDT 24
Peak memory 282544 kb
Host smart-c96b0e65-e700-48ba-9c65-35b438a11431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216601385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4216601385
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2044885307
Short name T75
Test name
Test status
Simulation time 16281066 ps
CPU time 0.75 seconds
Started Jul 20 05:37:13 PM PDT 24
Finished Jul 20 05:37:15 PM PDT 24
Peak memory 216484 kb
Host smart-29254cb7-7e6e-4fcb-92ea-6c71dc84e18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044885307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2044885307
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2078209260
Short name T13
Test name
Test status
Simulation time 89501528630 ps
CPU time 172.65 seconds
Started Jul 20 05:40:30 PM PDT 24
Finished Jul 20 05:43:24 PM PDT 24
Peak memory 253332 kb
Host smart-e9196031-3fb5-4b1f-9b96-66b755dc2cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078209260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2078209260
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.501949419
Short name T25
Test name
Test status
Simulation time 26315051822 ps
CPU time 255.74 seconds
Started Jul 20 05:39:22 PM PDT 24
Finished Jul 20 05:43:39 PM PDT 24
Peak memory 253368 kb
Host smart-38ffb767-c128-4706-af3d-e05506c2c2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501949419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.501949419
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3816035683
Short name T22
Test name
Test status
Simulation time 128009456899 ps
CPU time 316.42 seconds
Started Jul 20 05:40:18 PM PDT 24
Finished Jul 20 05:45:36 PM PDT 24
Peak memory 274032 kb
Host smart-7d5ebbd3-e3d5-4d38-ae8c-201c2f812a89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816035683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3816035683
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3648925938
Short name T199
Test name
Test status
Simulation time 105636262792 ps
CPU time 357.78 seconds
Started Jul 20 05:38:27 PM PDT 24
Finished Jul 20 05:44:25 PM PDT 24
Peak memory 256212 kb
Host smart-e39e0b81-f6dd-4e8b-94bf-5b7aedf30028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648925938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3648925938
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2734375743
Short name T20
Test name
Test status
Simulation time 165744989625 ps
CPU time 397.57 seconds
Started Jul 20 05:39:59 PM PDT 24
Finished Jul 20 05:46:37 PM PDT 24
Peak memory 255804 kb
Host smart-0cf22890-0005-4560-a5f8-3ee6ca34c0c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734375743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2734375743
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3455557399
Short name T99
Test name
Test status
Simulation time 299114709 ps
CPU time 3.64 seconds
Started Jul 20 05:29:38 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 217152 kb
Host smart-15b2a982-5eca-42ce-a222-5131079b1d36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455557399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3455557399
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4149307394
Short name T17
Test name
Test status
Simulation time 87928721 ps
CPU time 1.17 seconds
Started Jul 20 05:37:51 PM PDT 24
Finished Jul 20 05:37:54 PM PDT 24
Peak memory 236860 kb
Host smart-3cf6f138-c389-4abc-8f53-295579d2fd1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149307394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4149307394
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1475973996
Short name T186
Test name
Test status
Simulation time 222714700663 ps
CPU time 599.57 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:49:37 PM PDT 24
Peak memory 270508 kb
Host smart-5022789a-c77b-4bd3-aa34-93ec56514491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475973996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1475973996
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1132262731
Short name T48
Test name
Test status
Simulation time 200824500 ps
CPU time 8.95 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:11 PM PDT 24
Peak memory 233160 kb
Host smart-ecf5fb02-cb46-45af-ac32-e05d39403ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132262731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1132262731
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1953253736
Short name T141
Test name
Test status
Simulation time 13419515909 ps
CPU time 113.43 seconds
Started Jul 20 05:39:11 PM PDT 24
Finished Jul 20 05:41:05 PM PDT 24
Peak memory 263400 kb
Host smart-1a621050-168f-43fc-af02-b4efbc472169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953253736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1953253736
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2144886105
Short name T86
Test name
Test status
Simulation time 43969990404 ps
CPU time 395.83 seconds
Started Jul 20 05:39:02 PM PDT 24
Finished Jul 20 05:45:38 PM PDT 24
Peak memory 264196 kb
Host smart-95c5fa7e-9b93-42d7-bb7c-e4d1d14bcaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144886105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2144886105
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2360124570
Short name T200
Test name
Test status
Simulation time 38781134139 ps
CPU time 295.97 seconds
Started Jul 20 05:41:09 PM PDT 24
Finished Jul 20 05:46:06 PM PDT 24
Peak memory 253348 kb
Host smart-253c567a-a697-4490-9edf-99bd2e5a1de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360124570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2360124570
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2743326604
Short name T119
Test name
Test status
Simulation time 5204585635 ps
CPU time 32.23 seconds
Started Jul 20 05:29:19 PM PDT 24
Finished Jul 20 05:29:52 PM PDT 24
Peak memory 207924 kb
Host smart-e949d91d-c377-4ddd-af63-adba821d8d18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743326604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2743326604
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2357798168
Short name T9
Test name
Test status
Simulation time 65304231 ps
CPU time 1.13 seconds
Started Jul 20 05:37:25 PM PDT 24
Finished Jul 20 05:37:27 PM PDT 24
Peak memory 217120 kb
Host smart-93a2a47a-836d-4795-9d84-39bad42bbb42
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357798168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2357798168
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.680510998
Short name T56
Test name
Test status
Simulation time 16205205486 ps
CPU time 104.42 seconds
Started Jul 20 05:40:42 PM PDT 24
Finished Jul 20 05:42:28 PM PDT 24
Peak memory 254704 kb
Host smart-971a468a-e721-4db3-8fe9-e6123948879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680510998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.680510998
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3276044766
Short name T296
Test name
Test status
Simulation time 148994707511 ps
CPU time 312.59 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:45:14 PM PDT 24
Peak memory 251740 kb
Host smart-040aec29-a626-4c77-bd17-702f54531d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276044766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3276044766
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1418020826
Short name T305
Test name
Test status
Simulation time 48032525120 ps
CPU time 361.66 seconds
Started Jul 20 05:40:36 PM PDT 24
Finished Jul 20 05:46:39 PM PDT 24
Peak memory 281280 kb
Host smart-ac3cc227-9ed3-4f66-a30d-55b19e55a709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418020826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1418020826
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2766591240
Short name T162
Test name
Test status
Simulation time 36775433404 ps
CPU time 166.21 seconds
Started Jul 20 05:37:51 PM PDT 24
Finished Jul 20 05:40:39 PM PDT 24
Peak memory 255156 kb
Host smart-e2505040-cc5a-4887-a0c8-9d5379d4a288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766591240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2766591240
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.4198428545
Short name T163
Test name
Test status
Simulation time 1750782068 ps
CPU time 35.32 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:41:30 PM PDT 24
Peak memory 237920 kb
Host smart-e14d6a79-5ec0-4fe3-ac74-60f69a197229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198428545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.4198428545
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3649300825
Short name T303
Test name
Test status
Simulation time 364212613488 ps
CPU time 822.98 seconds
Started Jul 20 05:40:09 PM PDT 24
Finished Jul 20 05:53:53 PM PDT 24
Peak memory 267332 kb
Host smart-7cba056e-04f7-4615-bda0-621b6a24fa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649300825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3649300825
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2292115913
Short name T371
Test name
Test status
Simulation time 11558183 ps
CPU time 0.73 seconds
Started Jul 20 05:38:48 PM PDT 24
Finished Jul 20 05:38:49 PM PDT 24
Peak memory 205744 kb
Host smart-d67c346b-7e95-465e-a1a1-df8a057e3911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292115913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2292115913
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1652306231
Short name T1105
Test name
Test status
Simulation time 86007029 ps
CPU time 5.24 seconds
Started Jul 20 05:29:47 PM PDT 24
Finished Jul 20 05:29:53 PM PDT 24
Peak memory 216172 kb
Host smart-9118a893-1176-4e5a-b781-33f3f1ccdd15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652306231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1652306231
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.24883788
Short name T43
Test name
Test status
Simulation time 207305826000 ps
CPU time 643.58 seconds
Started Jul 20 05:38:20 PM PDT 24
Finished Jul 20 05:49:05 PM PDT 24
Peak memory 307024 kb
Host smart-ed16b386-f70a-41e1-9953-1c0f5d10572f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24883788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_
all.24883788
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3125952520
Short name T241
Test name
Test status
Simulation time 184952865524 ps
CPU time 393.06 seconds
Started Jul 20 05:38:53 PM PDT 24
Finished Jul 20 05:45:27 PM PDT 24
Peak memory 257224 kb
Host smart-c8277a89-5cf2-4134-858b-710406462af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125952520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3125952520
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3070200514
Short name T613
Test name
Test status
Simulation time 763551525091 ps
CPU time 595.4 seconds
Started Jul 20 05:39:15 PM PDT 24
Finished Jul 20 05:49:11 PM PDT 24
Peak memory 253908 kb
Host smart-314f3f64-b1ac-4a86-b2a5-fdc70e6d6e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070200514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3070200514
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2394207622
Short name T312
Test name
Test status
Simulation time 223683699 ps
CPU time 11.93 seconds
Started Jul 20 05:39:22 PM PDT 24
Finished Jul 20 05:39:35 PM PDT 24
Peak memory 241296 kb
Host smart-dcf9210e-ac72-456e-baa2-4c881be0fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394207622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2394207622
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2766457841
Short name T234
Test name
Test status
Simulation time 4505507102 ps
CPU time 91.09 seconds
Started Jul 20 05:40:19 PM PDT 24
Finished Jul 20 05:41:51 PM PDT 24
Peak memory 249704 kb
Host smart-68696c1c-f0e5-4e25-a8be-91275fd51601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766457841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2766457841
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3040736239
Short name T184
Test name
Test status
Simulation time 9992173002 ps
CPU time 135.85 seconds
Started Jul 20 05:41:22 PM PDT 24
Finished Jul 20 05:43:40 PM PDT 24
Peak memory 264648 kb
Host smart-6bf63549-3374-4a1b-8c40-ba4c4c205b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040736239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3040736239
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3757922031
Short name T175
Test name
Test status
Simulation time 581338522 ps
CPU time 19.92 seconds
Started Jul 20 05:29:46 PM PDT 24
Finished Jul 20 05:30:07 PM PDT 24
Peak memory 216112 kb
Host smart-9ec67562-9ab5-4db5-9606-63ee41c189d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757922031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3757922031
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1708841877
Short name T195
Test name
Test status
Simulation time 3150178574 ps
CPU time 64.44 seconds
Started Jul 20 05:38:28 PM PDT 24
Finished Jul 20 05:39:33 PM PDT 24
Peak memory 252440 kb
Host smart-842fb997-f9fc-4974-905d-357ec3f5ae59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708841877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1708841877
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2258576791
Short name T215
Test name
Test status
Simulation time 34788908113 ps
CPU time 121.53 seconds
Started Jul 20 05:40:04 PM PDT 24
Finished Jul 20 05:42:06 PM PDT 24
Peak memory 252352 kb
Host smart-3eb187f2-ff6a-4afb-bee0-4eb779bb77dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258576791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2258576791
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3457375744
Short name T607
Test name
Test status
Simulation time 141932912233 ps
CPU time 164.99 seconds
Started Jul 20 05:40:05 PM PDT 24
Finished Jul 20 05:42:50 PM PDT 24
Peak memory 257420 kb
Host smart-78ce0339-77b7-478e-81f3-71ecfb986df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457375744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3457375744
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2720926567
Short name T92
Test name
Test status
Simulation time 102419627 ps
CPU time 3.36 seconds
Started Jul 20 05:38:29 PM PDT 24
Finished Jul 20 05:38:33 PM PDT 24
Peak memory 233152 kb
Host smart-61e002fc-1535-4610-a90d-f224d3f1f98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720926567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2720926567
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2809948234
Short name T101
Test name
Test status
Simulation time 58971479 ps
CPU time 3.92 seconds
Started Jul 20 05:29:46 PM PDT 24
Finished Jul 20 05:29:50 PM PDT 24
Peak memory 216192 kb
Host smart-2f5a039c-8e0a-49ac-9e4d-9746122d96aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809948234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2809948234
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.565328775
Short name T102
Test name
Test status
Simulation time 213204573 ps
CPU time 6.96 seconds
Started Jul 20 05:29:47 PM PDT 24
Finished Jul 20 05:29:55 PM PDT 24
Peak memory 216028 kb
Host smart-19522e10-c6b3-42d2-8d91-d241c957eb24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565328775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.565328775
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1298055581
Short name T173
Test name
Test status
Simulation time 2330062454 ps
CPU time 8.98 seconds
Started Jul 20 05:29:46 PM PDT 24
Finished Jul 20 05:29:56 PM PDT 24
Peak memory 216720 kb
Host smart-ef76551a-2fdc-4424-986c-4b37dd55395e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298055581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1298055581
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3080309719
Short name T330
Test name
Test status
Simulation time 12171391965 ps
CPU time 39.01 seconds
Started Jul 20 05:37:15 PM PDT 24
Finished Jul 20 05:37:55 PM PDT 24
Peak memory 216796 kb
Host smart-798f1e4e-2fb2-46b1-974e-e31593052c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080309719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3080309719
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2398353624
Short name T864
Test name
Test status
Simulation time 2907886917 ps
CPU time 5.91 seconds
Started Jul 20 05:37:24 PM PDT 24
Finished Jul 20 05:37:31 PM PDT 24
Peak memory 238508 kb
Host smart-3cb5cc01-7b54-4937-b899-246d07151362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398353624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2398353624
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3338594601
Short name T801
Test name
Test status
Simulation time 1459627629 ps
CPU time 11.1 seconds
Started Jul 20 05:38:27 PM PDT 24
Finished Jul 20 05:38:38 PM PDT 24
Peak memory 224948 kb
Host smart-f25a6ebf-61b5-4885-96eb-b0c281d7b1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338594601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3338594601
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2984724640
Short name T291
Test name
Test status
Simulation time 88608295684 ps
CPU time 319.32 seconds
Started Jul 20 05:38:45 PM PDT 24
Finished Jul 20 05:44:04 PM PDT 24
Peak memory 257200 kb
Host smart-7b035c68-7d9b-4e2e-b3e8-fafed8c5f932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984724640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2984724640
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3717241428
Short name T304
Test name
Test status
Simulation time 12742509695 ps
CPU time 86.58 seconds
Started Jul 20 05:40:28 PM PDT 24
Finished Jul 20 05:41:56 PM PDT 24
Peak memory 261848 kb
Host smart-8ab8ba77-011e-4705-a6a5-57be94937bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717241428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3717241428
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1605029170
Short name T1
Test name
Test status
Simulation time 824766481 ps
CPU time 6.46 seconds
Started Jul 20 05:38:29 PM PDT 24
Finished Jul 20 05:38:36 PM PDT 24
Peak memory 233124 kb
Host smart-c15bc2a0-78a1-46df-9c86-bb9760a2c985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605029170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1605029170
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.416968629
Short name T87
Test name
Test status
Simulation time 42843421 ps
CPU time 0.9 seconds
Started Jul 20 05:29:06 PM PDT 24
Finished Jul 20 05:29:08 PM PDT 24
Peak memory 207536 kb
Host smart-fb0396b7-3a36-4173-ae6d-8fcbd49bcbf4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416968629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.416968629
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.651677931
Short name T1113
Test name
Test status
Simulation time 5359001009 ps
CPU time 22.74 seconds
Started Jul 20 05:29:19 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 216000 kb
Host smart-ea40ecaa-aac3-40b1-9eda-8635a2ac92a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651677931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.651677931
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1990041935
Short name T95
Test name
Test status
Simulation time 91383309 ps
CPU time 1.75 seconds
Started Jul 20 05:29:20 PM PDT 24
Finished Jul 20 05:29:23 PM PDT 24
Peak memory 215956 kb
Host smart-e3692483-3a3d-4ab2-a45c-6530f26ab0f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990041935 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1990041935
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2213198619
Short name T1060
Test name
Test status
Simulation time 19842479 ps
CPU time 1.15 seconds
Started Jul 20 05:29:05 PM PDT 24
Finished Jul 20 05:29:07 PM PDT 24
Peak memory 207960 kb
Host smart-f20fae85-0fed-43a8-83bb-36fba3af4f46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213198619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
213198619
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2167373758
Short name T1091
Test name
Test status
Simulation time 47951711 ps
CPU time 0.78 seconds
Started Jul 20 05:29:08 PM PDT 24
Finished Jul 20 05:29:09 PM PDT 24
Peak memory 204768 kb
Host smart-29a32639-c163-4a47-ae43-2debe05a1aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167373758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
167373758
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1358797336
Short name T1150
Test name
Test status
Simulation time 97943552 ps
CPU time 1.82 seconds
Started Jul 20 05:29:10 PM PDT 24
Finished Jul 20 05:29:12 PM PDT 24
Peak memory 216032 kb
Host smart-5f889113-d934-4527-86ef-c212afd9f7d8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358797336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1358797336
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.622381205
Short name T1096
Test name
Test status
Simulation time 27254293 ps
CPU time 0.65 seconds
Started Jul 20 05:29:08 PM PDT 24
Finished Jul 20 05:29:10 PM PDT 24
Peak memory 204324 kb
Host smart-c5a6e3fc-9c99-4138-9253-55db5eb7feda
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622381205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.622381205
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3598053469
Short name T1081
Test name
Test status
Simulation time 221771410 ps
CPU time 4.68 seconds
Started Jul 20 05:29:20 PM PDT 24
Finished Jul 20 05:29:26 PM PDT 24
Peak memory 216000 kb
Host smart-7dc6bd64-bb1f-41de-b266-f9e190ec659e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598053469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3598053469
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1572718222
Short name T1125
Test name
Test status
Simulation time 36597743 ps
CPU time 2.24 seconds
Started Jul 20 05:29:08 PM PDT 24
Finished Jul 20 05:29:11 PM PDT 24
Peak memory 216204 kb
Host smart-64f70508-608e-4453-af3d-1ef4db2af5ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572718222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
572718222
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2528841260
Short name T1119
Test name
Test status
Simulation time 193530213 ps
CPU time 12.96 seconds
Started Jul 20 05:29:10 PM PDT 24
Finished Jul 20 05:29:23 PM PDT 24
Peak memory 216016 kb
Host smart-10f5251d-0029-4869-a10c-ab972853843c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528841260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2528841260
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2621783686
Short name T124
Test name
Test status
Simulation time 2285593287 ps
CPU time 24.57 seconds
Started Jul 20 05:29:21 PM PDT 24
Finished Jul 20 05:29:47 PM PDT 24
Peak memory 216052 kb
Host smart-b0309d91-24cb-4a5c-a8df-00b18c3ae393
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621783686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2621783686
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3295390952
Short name T1080
Test name
Test status
Simulation time 357258033 ps
CPU time 22.24 seconds
Started Jul 20 05:29:19 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 207836 kb
Host smart-1b1cdc7e-9d72-459b-98f8-a4d1c1a6b4ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295390952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3295390952
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2928931569
Short name T88
Test name
Test status
Simulation time 33116739 ps
CPU time 1.13 seconds
Started Jul 20 05:29:20 PM PDT 24
Finished Jul 20 05:29:22 PM PDT 24
Peak memory 218012 kb
Host smart-259d13c3-c7b6-4084-bfb6-cee76aaa53c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928931569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2928931569
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1254281092
Short name T113
Test name
Test status
Simulation time 105351999 ps
CPU time 3.63 seconds
Started Jul 20 05:29:21 PM PDT 24
Finished Jul 20 05:29:26 PM PDT 24
Peak memory 218688 kb
Host smart-9a6981bc-ec38-464b-a879-765d55837db6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254281092 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1254281092
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3146090267
Short name T1095
Test name
Test status
Simulation time 36568142 ps
CPU time 1.4 seconds
Started Jul 20 05:29:21 PM PDT 24
Finished Jul 20 05:29:24 PM PDT 24
Peak memory 215992 kb
Host smart-28a8b9f8-4cee-4cdc-9a4a-0db2d9e30f11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146090267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
146090267
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2486543569
Short name T1044
Test name
Test status
Simulation time 40464594 ps
CPU time 0.72 seconds
Started Jul 20 05:29:22 PM PDT 24
Finished Jul 20 05:29:23 PM PDT 24
Peak memory 204436 kb
Host smart-eb4270ac-ed47-4bc9-ac7a-400db18e802b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486543569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
486543569
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2242467401
Short name T1141
Test name
Test status
Simulation time 86952789 ps
CPU time 1.19 seconds
Started Jul 20 05:29:19 PM PDT 24
Finished Jul 20 05:29:21 PM PDT 24
Peak memory 216020 kb
Host smart-43b455ab-cd9c-42bf-bf53-68eaa17d0ea6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242467401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2242467401
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.369732737
Short name T1062
Test name
Test status
Simulation time 14561488 ps
CPU time 0.66 seconds
Started Jul 20 05:29:22 PM PDT 24
Finished Jul 20 05:29:24 PM PDT 24
Peak memory 204308 kb
Host smart-59f62d7b-4e22-40d7-bd37-497dd9ec46f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369732737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.369732737
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1448899896
Short name T1146
Test name
Test status
Simulation time 353139183 ps
CPU time 3.08 seconds
Started Jul 20 05:29:22 PM PDT 24
Finished Jul 20 05:29:26 PM PDT 24
Peak memory 216040 kb
Host smart-fa35a01d-e8ea-4fb9-a365-f644902a6340
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448899896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1448899896
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2048959031
Short name T96
Test name
Test status
Simulation time 330105822 ps
CPU time 1.84 seconds
Started Jul 20 05:29:22 PM PDT 24
Finished Jul 20 05:29:25 PM PDT 24
Peak memory 216204 kb
Host smart-ba46195c-8d1e-4759-a41b-ff944657d3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048959031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
048959031
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1374591128
Short name T1087
Test name
Test status
Simulation time 176610410 ps
CPU time 2.68 seconds
Started Jul 20 05:29:39 PM PDT 24
Finished Jul 20 05:29:43 PM PDT 24
Peak memory 217164 kb
Host smart-82457ef3-d5d7-4958-bb2a-37f45a559b0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374591128 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1374591128
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2272543494
Short name T130
Test name
Test status
Simulation time 57610799 ps
CPU time 1.33 seconds
Started Jul 20 05:29:37 PM PDT 24
Finished Jul 20 05:29:39 PM PDT 24
Peak memory 207748 kb
Host smart-9809d7bd-33a8-4608-b5e2-72b39851f92a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272543494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2272543494
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2896950863
Short name T1129
Test name
Test status
Simulation time 14440998 ps
CPU time 0.7 seconds
Started Jul 20 05:29:38 PM PDT 24
Finished Jul 20 05:29:40 PM PDT 24
Peak memory 204744 kb
Host smart-08ac9a83-505c-4431-a82a-0c87e1cf292a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896950863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2896950863
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.844827215
Short name T1139
Test name
Test status
Simulation time 666864527 ps
CPU time 4.33 seconds
Started Jul 20 05:29:38 PM PDT 24
Finished Jul 20 05:29:44 PM PDT 24
Peak memory 215948 kb
Host smart-601fcb3a-4007-403d-a49d-c31b53aaa598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844827215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.844827215
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1373327954
Short name T1072
Test name
Test status
Simulation time 19526289 ps
CPU time 1.27 seconds
Started Jul 20 05:29:38 PM PDT 24
Finished Jul 20 05:29:40 PM PDT 24
Peak memory 216244 kb
Host smart-58d53d20-a135-4eaa-8f66-11f30fe22d6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373327954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1373327954
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3902732147
Short name T1143
Test name
Test status
Simulation time 213567985 ps
CPU time 13.61 seconds
Started Jul 20 05:29:37 PM PDT 24
Finished Jul 20 05:29:52 PM PDT 24
Peak memory 216012 kb
Host smart-ef7135b5-75e1-4dfb-879b-c678241a9bd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902732147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3902732147
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3602361431
Short name T116
Test name
Test status
Simulation time 635820568 ps
CPU time 2.85 seconds
Started Jul 20 05:29:43 PM PDT 24
Finished Jul 20 05:29:46 PM PDT 24
Peak memory 216964 kb
Host smart-38110fb1-e51d-4624-9395-898b2900bd11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602361431 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3602361431
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1480159311
Short name T126
Test name
Test status
Simulation time 169318932 ps
CPU time 2.44 seconds
Started Jul 20 05:29:37 PM PDT 24
Finished Jul 20 05:29:41 PM PDT 24
Peak memory 207836 kb
Host smart-b0d1a3da-93b8-49e5-8b23-79c95f37750d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480159311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1480159311
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1951740836
Short name T1099
Test name
Test status
Simulation time 17763382 ps
CPU time 0.78 seconds
Started Jul 20 05:29:39 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 204380 kb
Host smart-159b75fe-0085-4b19-95b5-0949d1b14d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951740836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1951740836
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2934965906
Short name T1100
Test name
Test status
Simulation time 110020505 ps
CPU time 2.76 seconds
Started Jul 20 05:29:40 PM PDT 24
Finished Jul 20 05:29:45 PM PDT 24
Peak memory 215864 kb
Host smart-b8e704e2-d4b4-46c7-8030-8389299b3d8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934965906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2934965906
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3279454484
Short name T180
Test name
Test status
Simulation time 278374562 ps
CPU time 7.53 seconds
Started Jul 20 05:29:39 PM PDT 24
Finished Jul 20 05:29:48 PM PDT 24
Peak memory 215992 kb
Host smart-55f847d8-3434-48d5-b64e-4dd3bfaaa68c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279454484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3279454484
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3728780271
Short name T1056
Test name
Test status
Simulation time 58245224 ps
CPU time 3.43 seconds
Started Jul 20 05:29:38 PM PDT 24
Finished Jul 20 05:29:43 PM PDT 24
Peak memory 218448 kb
Host smart-0decf5a2-4950-43e9-a0c5-431fa9a84923
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728780271 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3728780271
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.805077055
Short name T144
Test name
Test status
Simulation time 287865539 ps
CPU time 1.35 seconds
Started Jul 20 05:29:41 PM PDT 24
Finished Jul 20 05:29:44 PM PDT 24
Peak memory 207744 kb
Host smart-94f7ede2-dd1c-4e06-8b60-2f8e6fc66278
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805077055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.805077055
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.444237539
Short name T1151
Test name
Test status
Simulation time 53461416 ps
CPU time 0.78 seconds
Started Jul 20 05:29:40 PM PDT 24
Finished Jul 20 05:29:43 PM PDT 24
Peak memory 204332 kb
Host smart-252f8b3b-ff8f-49ca-8c9e-5508d28d7acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444237539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.444237539
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1056946660
Short name T1140
Test name
Test status
Simulation time 409645372 ps
CPU time 2.87 seconds
Started Jul 20 05:29:43 PM PDT 24
Finished Jul 20 05:29:46 PM PDT 24
Peak memory 215936 kb
Host smart-94d88667-058a-4141-87d9-52be371b5817
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056946660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1056946660
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1108289556
Short name T104
Test name
Test status
Simulation time 378832767 ps
CPU time 2.84 seconds
Started Jul 20 05:29:38 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 216100 kb
Host smart-50d8fe72-59df-4ee1-bf3f-8968a4c14791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108289556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1108289556
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4278756637
Short name T169
Test name
Test status
Simulation time 3951341060 ps
CPU time 21.93 seconds
Started Jul 20 05:29:39 PM PDT 24
Finished Jul 20 05:30:02 PM PDT 24
Peak memory 216096 kb
Host smart-92863d05-3692-4db4-9e9c-71cdb4e88ed5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278756637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4278756637
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3016917977
Short name T97
Test name
Test status
Simulation time 150860675 ps
CPU time 3 seconds
Started Jul 20 05:29:39 PM PDT 24
Finished Jul 20 05:29:43 PM PDT 24
Peak memory 217432 kb
Host smart-c9875158-cad9-45e0-9ece-d496d231e471
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016917977 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3016917977
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2818758950
Short name T128
Test name
Test status
Simulation time 1286940561 ps
CPU time 2.84 seconds
Started Jul 20 05:29:38 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 207824 kb
Host smart-0be3943b-c112-4bc8-aa1a-12b07a0de5ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818758950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2818758950
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1879350873
Short name T1039
Test name
Test status
Simulation time 71325040 ps
CPU time 0.69 seconds
Started Jul 20 05:29:36 PM PDT 24
Finished Jul 20 05:29:37 PM PDT 24
Peak memory 204760 kb
Host smart-b1fed989-9825-40df-9ed8-dd388aba07a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879350873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1879350873
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1686294450
Short name T1144
Test name
Test status
Simulation time 645077573 ps
CPU time 3.27 seconds
Started Jul 20 05:29:39 PM PDT 24
Finished Jul 20 05:29:44 PM PDT 24
Peak memory 216020 kb
Host smart-3f0dc453-b54c-4770-8452-91febfe1efd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686294450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1686294450
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.26042398
Short name T1061
Test name
Test status
Simulation time 301775603 ps
CPU time 2.3 seconds
Started Jul 20 05:29:40 PM PDT 24
Finished Jul 20 05:29:45 PM PDT 24
Peak memory 216128 kb
Host smart-23bde8ca-0710-4fec-90c9-6f6a8a1e5221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26042398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.26042398
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2991199618
Short name T1124
Test name
Test status
Simulation time 338375699 ps
CPU time 8.52 seconds
Started Jul 20 05:29:39 PM PDT 24
Finished Jul 20 05:29:49 PM PDT 24
Peak memory 215880 kb
Host smart-7eb4aa78-7e55-4f68-88f9-893465525753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991199618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2991199618
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2583859213
Short name T112
Test name
Test status
Simulation time 109950447 ps
CPU time 1.83 seconds
Started Jul 20 05:29:50 PM PDT 24
Finished Jul 20 05:29:53 PM PDT 24
Peak memory 217088 kb
Host smart-e919c417-cd05-4812-bede-f1107fec8b68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583859213 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2583859213
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.786989743
Short name T127
Test name
Test status
Simulation time 69378785 ps
CPU time 1.25 seconds
Started Jul 20 05:29:46 PM PDT 24
Finished Jul 20 05:29:49 PM PDT 24
Peak memory 216012 kb
Host smart-e4262c0d-b508-4afa-aece-2c1638e1ba11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786989743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.786989743
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2691327730
Short name T1064
Test name
Test status
Simulation time 22025283 ps
CPU time 0.75 seconds
Started Jul 20 05:29:45 PM PDT 24
Finished Jul 20 05:29:47 PM PDT 24
Peak memory 204508 kb
Host smart-0d71caab-872f-441b-b3e3-58f3477ef0b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691327730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2691327730
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2476392726
Short name T1066
Test name
Test status
Simulation time 566556429 ps
CPU time 3.2 seconds
Started Jul 20 05:29:46 PM PDT 24
Finished Jul 20 05:29:50 PM PDT 24
Peak memory 216016 kb
Host smart-3f43814e-cd39-4750-837b-797618e74903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476392726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2476392726
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3656459363
Short name T107
Test name
Test status
Simulation time 257501196 ps
CPU time 1.77 seconds
Started Jul 20 05:29:49 PM PDT 24
Finished Jul 20 05:29:52 PM PDT 24
Peak memory 216320 kb
Host smart-9b710dbb-2485-46ac-9a49-2edea797e3a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656459363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3656459363
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2787426156
Short name T103
Test name
Test status
Simulation time 1143820053 ps
CPU time 22.55 seconds
Started Jul 20 05:29:48 PM PDT 24
Finished Jul 20 05:30:12 PM PDT 24
Peak memory 216604 kb
Host smart-8041089d-e2ca-4d9f-ac57-ea134ff7c06d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787426156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2787426156
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2983157052
Short name T1128
Test name
Test status
Simulation time 261021594 ps
CPU time 3.31 seconds
Started Jul 20 05:29:47 PM PDT 24
Finished Jul 20 05:29:51 PM PDT 24
Peak memory 218692 kb
Host smart-3415a866-c458-4a11-81cc-d0ec935f141b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983157052 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2983157052
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1493690639
Short name T1111
Test name
Test status
Simulation time 63974469 ps
CPU time 1.22 seconds
Started Jul 20 05:29:45 PM PDT 24
Finished Jul 20 05:29:48 PM PDT 24
Peak memory 207736 kb
Host smart-0a4cba97-5f69-4841-9159-44b638b9fddf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493690639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1493690639
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2209182558
Short name T1052
Test name
Test status
Simulation time 83801811 ps
CPU time 0.67 seconds
Started Jul 20 05:29:46 PM PDT 24
Finished Jul 20 05:29:48 PM PDT 24
Peak memory 204428 kb
Host smart-2862b773-ff40-4980-b631-3c3143ff1570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209182558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2209182558
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2225938175
Short name T145
Test name
Test status
Simulation time 130180589 ps
CPU time 3.07 seconds
Started Jul 20 05:29:48 PM PDT 24
Finished Jul 20 05:29:52 PM PDT 24
Peak memory 216016 kb
Host smart-38565b6f-5758-405d-b2bd-2d39e1d81958
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225938175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2225938175
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.558730650
Short name T1133
Test name
Test status
Simulation time 62022677 ps
CPU time 1.9 seconds
Started Jul 20 05:29:49 PM PDT 24
Finished Jul 20 05:29:53 PM PDT 24
Peak memory 216236 kb
Host smart-d6f3b27d-0cd9-4752-b285-72214ab560ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558730650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.558730650
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3954927969
Short name T1109
Test name
Test status
Simulation time 90717219 ps
CPU time 1.76 seconds
Started Jul 20 05:29:46 PM PDT 24
Finished Jul 20 05:29:50 PM PDT 24
Peak memory 216088 kb
Host smart-d28ad3c1-5f31-49f3-95de-bcbcf25fc090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954927969 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3954927969
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.218428593
Short name T120
Test name
Test status
Simulation time 88398852 ps
CPU time 2.65 seconds
Started Jul 20 05:29:46 PM PDT 24
Finished Jul 20 05:29:50 PM PDT 24
Peak memory 207772 kb
Host smart-b3d0413b-b420-42b0-8e10-5ba37df607d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218428593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.218428593
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4055562036
Short name T1041
Test name
Test status
Simulation time 16333691 ps
CPU time 0.79 seconds
Started Jul 20 05:29:49 PM PDT 24
Finished Jul 20 05:29:51 PM PDT 24
Peak memory 204360 kb
Host smart-c582b9df-6d2a-489c-89b4-b25bbad20945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055562036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4055562036
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3093588569
Short name T1070
Test name
Test status
Simulation time 28141945 ps
CPU time 1.74 seconds
Started Jul 20 05:29:49 PM PDT 24
Finished Jul 20 05:29:52 PM PDT 24
Peak memory 215908 kb
Host smart-294abe6d-8984-4506-97ad-333e818bbd4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093588569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3093588569
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1729021989
Short name T1132
Test name
Test status
Simulation time 226684521 ps
CPU time 1.71 seconds
Started Jul 20 05:29:49 PM PDT 24
Finished Jul 20 05:29:52 PM PDT 24
Peak memory 216068 kb
Host smart-eeaa276c-42be-47ba-9072-a7b1a49b628e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729021989 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1729021989
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2951201722
Short name T151
Test name
Test status
Simulation time 53517935 ps
CPU time 1.39 seconds
Started Jul 20 05:29:45 PM PDT 24
Finished Jul 20 05:29:47 PM PDT 24
Peak memory 207824 kb
Host smart-2826d44c-240f-4c0a-8fe4-0b18a8274a60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951201722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2951201722
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.648849696
Short name T1084
Test name
Test status
Simulation time 14568315 ps
CPU time 0.74 seconds
Started Jul 20 05:29:48 PM PDT 24
Finished Jul 20 05:29:50 PM PDT 24
Peak memory 204708 kb
Host smart-37c9b49d-250b-4ca3-9012-1f9b8767bf8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648849696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.648849696
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2908968039
Short name T1043
Test name
Test status
Simulation time 461634916 ps
CPU time 3.03 seconds
Started Jul 20 05:29:49 PM PDT 24
Finished Jul 20 05:29:54 PM PDT 24
Peak memory 215820 kb
Host smart-bc272c0b-c5ca-4e8c-8590-08542a275e2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908968039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2908968039
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2188074516
Short name T1142
Test name
Test status
Simulation time 36022738 ps
CPU time 2.55 seconds
Started Jul 20 05:29:49 PM PDT 24
Finished Jul 20 05:29:53 PM PDT 24
Peak memory 216360 kb
Host smart-2a4a9e63-9cdc-4804-8bfd-9e6caa889649
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188074516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2188074516
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2308944224
Short name T1130
Test name
Test status
Simulation time 183065365 ps
CPU time 1.82 seconds
Started Jul 20 05:29:47 PM PDT 24
Finished Jul 20 05:29:50 PM PDT 24
Peak memory 216144 kb
Host smart-14067ad2-f70d-4653-a04e-489fc02482d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308944224 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2308944224
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3682391513
Short name T1083
Test name
Test status
Simulation time 49360148 ps
CPU time 1.43 seconds
Started Jul 20 05:29:48 PM PDT 24
Finished Jul 20 05:29:51 PM PDT 24
Peak memory 216012 kb
Host smart-74366f4f-0fe9-452d-b835-3b07088858dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682391513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3682391513
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1121991088
Short name T1136
Test name
Test status
Simulation time 11971472 ps
CPU time 0.76 seconds
Started Jul 20 05:29:49 PM PDT 24
Finished Jul 20 05:29:51 PM PDT 24
Peak memory 204808 kb
Host smart-c1175de7-c235-4a2e-9f70-9c1d79a497d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121991088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1121991088
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3118662736
Short name T1055
Test name
Test status
Simulation time 242072079 ps
CPU time 2.8 seconds
Started Jul 20 05:29:46 PM PDT 24
Finished Jul 20 05:29:50 PM PDT 24
Peak memory 215912 kb
Host smart-215d4092-904e-46ba-8199-8339527c888a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118662736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3118662736
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1370879311
Short name T111
Test name
Test status
Simulation time 97308055 ps
CPU time 1.96 seconds
Started Jul 20 05:29:49 PM PDT 24
Finished Jul 20 05:29:52 PM PDT 24
Peak memory 217208 kb
Host smart-161b57c1-81ae-422b-b7ae-6eea592adbaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370879311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1370879311
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3816617671
Short name T171
Test name
Test status
Simulation time 414552486 ps
CPU time 19.11 seconds
Started Jul 20 05:29:49 PM PDT 24
Finished Jul 20 05:30:09 PM PDT 24
Peak memory 216356 kb
Host smart-fe24abb5-8a76-41a8-a6d0-23186c5c51ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816617671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3816617671
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3677140451
Short name T114
Test name
Test status
Simulation time 231901595 ps
CPU time 2.92 seconds
Started Jul 20 05:29:54 PM PDT 24
Finished Jul 20 05:29:59 PM PDT 24
Peak memory 218956 kb
Host smart-6943dcc3-9d11-4dd8-9aa7-d0079fe5325b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677140451 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3677140451
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.348552547
Short name T1085
Test name
Test status
Simulation time 339727338 ps
CPU time 2.62 seconds
Started Jul 20 05:29:48 PM PDT 24
Finished Jul 20 05:29:52 PM PDT 24
Peak memory 216044 kb
Host smart-c2c462f0-24f3-41bd-a7a3-f90a287a648f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348552547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.348552547
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2542676261
Short name T1118
Test name
Test status
Simulation time 19790429 ps
CPU time 0.77 seconds
Started Jul 20 05:29:45 PM PDT 24
Finished Jul 20 05:29:46 PM PDT 24
Peak memory 204660 kb
Host smart-67ecb851-5e02-45db-b567-b7f82ea46cc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542676261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2542676261
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.244030353
Short name T1123
Test name
Test status
Simulation time 69964594 ps
CPU time 1.76 seconds
Started Jul 20 05:29:48 PM PDT 24
Finished Jul 20 05:29:51 PM PDT 24
Peak memory 215988 kb
Host smart-f9f8ee65-c576-4231-a1db-f38e6371ad42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244030353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.244030353
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3774410695
Short name T170
Test name
Test status
Simulation time 1735343024 ps
CPU time 24.13 seconds
Started Jul 20 05:29:46 PM PDT 24
Finished Jul 20 05:30:11 PM PDT 24
Peak memory 216084 kb
Host smart-476703b0-d701-4aec-a0ce-192f12663d01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774410695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3774410695
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.499758238
Short name T1067
Test name
Test status
Simulation time 393114237 ps
CPU time 8.76 seconds
Started Jul 20 05:29:19 PM PDT 24
Finished Jul 20 05:29:29 PM PDT 24
Peak memory 215840 kb
Host smart-831905ed-6693-40c1-a280-508f0eade508
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499758238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.499758238
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.749151301
Short name T129
Test name
Test status
Simulation time 9740689987 ps
CPU time 37.51 seconds
Started Jul 20 05:29:22 PM PDT 24
Finished Jul 20 05:30:01 PM PDT 24
Peak memory 207796 kb
Host smart-5ee3cd7a-58d7-4cac-9005-3048bb100f2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749151301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.749151301
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3730122652
Short name T1138
Test name
Test status
Simulation time 33483282 ps
CPU time 1.25 seconds
Started Jul 20 05:29:19 PM PDT 24
Finished Jul 20 05:29:21 PM PDT 24
Peak memory 207716 kb
Host smart-17480ec0-2636-439e-a78b-a292b7c2276e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730122652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3730122652
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.645898498
Short name T1092
Test name
Test status
Simulation time 166280651 ps
CPU time 3.47 seconds
Started Jul 20 05:29:32 PM PDT 24
Finished Jul 20 05:29:37 PM PDT 24
Peak memory 217844 kb
Host smart-bc1711e8-cab0-4915-ac46-0036b75ed2c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645898498 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.645898498
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2361873626
Short name T117
Test name
Test status
Simulation time 59883950 ps
CPU time 1.34 seconds
Started Jul 20 05:29:19 PM PDT 24
Finished Jul 20 05:29:21 PM PDT 24
Peak memory 207772 kb
Host smart-cf0fff9c-6c56-4f25-a2e3-a461febba4a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361873626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
361873626
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3803596219
Short name T1074
Test name
Test status
Simulation time 11772841 ps
CPU time 0.76 seconds
Started Jul 20 05:29:21 PM PDT 24
Finished Jul 20 05:29:23 PM PDT 24
Peak memory 204716 kb
Host smart-bc481a8e-5af6-4f9d-a3fd-abe26553142c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803596219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
803596219
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1324875639
Short name T1126
Test name
Test status
Simulation time 150560558 ps
CPU time 1.35 seconds
Started Jul 20 05:29:19 PM PDT 24
Finished Jul 20 05:29:21 PM PDT 24
Peak memory 216044 kb
Host smart-27cd9603-b059-46e3-aaba-1214aa07126a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324875639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1324875639
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1768397992
Short name T1093
Test name
Test status
Simulation time 19922252 ps
CPU time 0.68 seconds
Started Jul 20 05:29:20 PM PDT 24
Finished Jul 20 05:29:21 PM PDT 24
Peak memory 204480 kb
Host smart-90ce4075-1a85-4baa-aefc-d718ec3d0a7d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768397992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1768397992
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2504122758
Short name T1089
Test name
Test status
Simulation time 204149255 ps
CPU time 1.75 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:33 PM PDT 24
Peak memory 216348 kb
Host smart-049f38c6-9aa2-4c8c-9cb0-786d8263b0b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504122758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2504122758
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3175575103
Short name T1137
Test name
Test status
Simulation time 106112978 ps
CPU time 2.13 seconds
Started Jul 20 05:29:20 PM PDT 24
Finished Jul 20 05:29:23 PM PDT 24
Peak memory 216388 kb
Host smart-fed80709-c518-4a2c-b954-b79347c76dba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175575103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
175575103
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1355029289
Short name T177
Test name
Test status
Simulation time 107909425 ps
CPU time 7.1 seconds
Started Jul 20 05:29:20 PM PDT 24
Finished Jul 20 05:29:28 PM PDT 24
Peak memory 216096 kb
Host smart-2262337a-a2a4-4869-a10c-c69376e4a57f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355029289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1355029289
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3597722860
Short name T1054
Test name
Test status
Simulation time 13661337 ps
CPU time 0.73 seconds
Started Jul 20 05:29:57 PM PDT 24
Finished Jul 20 05:29:59 PM PDT 24
Peak memory 204460 kb
Host smart-780b45ff-be1d-40e1-a409-7c44af9cb054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597722860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3597722860
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2587026632
Short name T1077
Test name
Test status
Simulation time 11998090 ps
CPU time 0.78 seconds
Started Jul 20 05:29:54 PM PDT 24
Finished Jul 20 05:29:56 PM PDT 24
Peak memory 204448 kb
Host smart-cc3d4920-6e87-42e3-a4a1-fd26fa284dc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587026632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2587026632
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2699104346
Short name T1057
Test name
Test status
Simulation time 75329805 ps
CPU time 0.73 seconds
Started Jul 20 05:29:58 PM PDT 24
Finished Jul 20 05:30:00 PM PDT 24
Peak memory 204436 kb
Host smart-c2d18cdd-b202-4569-ad93-eb5c8b5edd3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699104346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2699104346
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2564856991
Short name T1131
Test name
Test status
Simulation time 11198626 ps
CPU time 0.76 seconds
Started Jul 20 05:29:54 PM PDT 24
Finished Jul 20 05:29:57 PM PDT 24
Peak memory 204476 kb
Host smart-6d089f24-5ea8-423f-8570-30d56335df1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564856991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2564856991
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1849935804
Short name T1076
Test name
Test status
Simulation time 15413715 ps
CPU time 0.78 seconds
Started Jul 20 05:29:53 PM PDT 24
Finished Jul 20 05:29:54 PM PDT 24
Peak memory 204452 kb
Host smart-9e168aaa-003c-4348-bf03-e82511593dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849935804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1849935804
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.269130206
Short name T1046
Test name
Test status
Simulation time 16762011 ps
CPU time 0.73 seconds
Started Jul 20 05:29:56 PM PDT 24
Finished Jul 20 05:29:58 PM PDT 24
Peak memory 204404 kb
Host smart-7f25e941-5186-401c-9a68-37c488bef9aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269130206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.269130206
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1439686273
Short name T1036
Test name
Test status
Simulation time 34385690 ps
CPU time 0.75 seconds
Started Jul 20 05:29:53 PM PDT 24
Finished Jul 20 05:29:55 PM PDT 24
Peak memory 204496 kb
Host smart-9ca868cb-6486-45d2-85a2-ef50a3f990ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439686273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1439686273
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3927894727
Short name T1049
Test name
Test status
Simulation time 35110369 ps
CPU time 0.74 seconds
Started Jul 20 05:29:57 PM PDT 24
Finished Jul 20 05:29:59 PM PDT 24
Peak memory 204784 kb
Host smart-c676edb3-4daf-4e3a-890e-b8681172c29a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927894727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3927894727
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.998125966
Short name T1094
Test name
Test status
Simulation time 95741361 ps
CPU time 0.74 seconds
Started Jul 20 05:29:55 PM PDT 24
Finished Jul 20 05:29:57 PM PDT 24
Peak memory 204332 kb
Host smart-00ead426-8b42-4418-a8d2-bd6b9f9406fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998125966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.998125966
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.970773391
Short name T1103
Test name
Test status
Simulation time 28736245 ps
CPU time 0.81 seconds
Started Jul 20 05:30:02 PM PDT 24
Finished Jul 20 05:30:04 PM PDT 24
Peak memory 204452 kb
Host smart-2d6e114b-54aa-48ed-9b74-77b824c9bb7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970773391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.970773391
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3995027571
Short name T152
Test name
Test status
Simulation time 4632974750 ps
CPU time 8.83 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 215964 kb
Host smart-a2d3f0f6-4fc8-47a5-a5bf-ddfcc887c92c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995027571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3995027571
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.548814783
Short name T1104
Test name
Test status
Simulation time 529743852 ps
CPU time 32.28 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:30:05 PM PDT 24
Peak memory 216232 kb
Host smart-9a177352-39a9-4e1a-8783-3b43419b8066
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548814783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.548814783
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2816072925
Short name T1114
Test name
Test status
Simulation time 17577997 ps
CPU time 1.18 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:29:35 PM PDT 24
Peak memory 207728 kb
Host smart-1420d7b8-de2c-45f8-8cec-4bb339e70b28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816072925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2816072925
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.546117481
Short name T1106
Test name
Test status
Simulation time 212171955 ps
CPU time 1.76 seconds
Started Jul 20 05:29:29 PM PDT 24
Finished Jul 20 05:29:31 PM PDT 24
Peak memory 217108 kb
Host smart-ebee3bd0-b235-4209-bfc0-0c2a5ffeaf45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546117481 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.546117481
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.451954164
Short name T122
Test name
Test status
Simulation time 746312498 ps
CPU time 2.67 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:34 PM PDT 24
Peak memory 216024 kb
Host smart-a288ab20-fc54-443c-8975-59723b6428bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451954164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.451954164
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2654792392
Short name T1047
Test name
Test status
Simulation time 16122333 ps
CPU time 0.72 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:29:34 PM PDT 24
Peak memory 204476 kb
Host smart-f5f4ce30-5e45-42a5-949b-22a304639c66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654792392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
654792392
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.424497775
Short name T123
Test name
Test status
Simulation time 124950464 ps
CPU time 1.35 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:29:35 PM PDT 24
Peak memory 215908 kb
Host smart-e7e724ea-32da-48ee-ad90-d82a4087e880
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424497775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.424497775
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1603786633
Short name T1073
Test name
Test status
Simulation time 10303151 ps
CPU time 0.77 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:32 PM PDT 24
Peak memory 204320 kb
Host smart-4f10f664-97b5-40ee-b5e2-a26fb84e6bc5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603786633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1603786633
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2422049500
Short name T1112
Test name
Test status
Simulation time 29480431 ps
CPU time 1.74 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:33 PM PDT 24
Peak memory 207712 kb
Host smart-e27fbb2d-67b6-4e44-bc04-127a3552f092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422049500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2422049500
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.223849779
Short name T115
Test name
Test status
Simulation time 319625026 ps
CPU time 4.43 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:36 PM PDT 24
Peak memory 217268 kb
Host smart-67741485-4ee8-455d-8c28-eec566343a67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223849779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.223849779
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3436467932
Short name T174
Test name
Test status
Simulation time 1780265195 ps
CPU time 23.22 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:54 PM PDT 24
Peak memory 216092 kb
Host smart-e736792f-d28c-4c99-a510-e86285a0ca92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436467932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3436467932
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.799440526
Short name T1038
Test name
Test status
Simulation time 16089036 ps
CPU time 0.72 seconds
Started Jul 20 05:29:56 PM PDT 24
Finished Jul 20 05:29:58 PM PDT 24
Peak memory 204464 kb
Host smart-8fafc5c9-800f-474a-9542-24f2c7906c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799440526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.799440526
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1072778168
Short name T1037
Test name
Test status
Simulation time 47250222 ps
CPU time 0.69 seconds
Started Jul 20 05:29:55 PM PDT 24
Finished Jul 20 05:29:57 PM PDT 24
Peak memory 204352 kb
Host smart-81392296-31f4-4773-aa04-36d80ec4dbe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072778168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1072778168
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.504448633
Short name T1117
Test name
Test status
Simulation time 61805282 ps
CPU time 0.84 seconds
Started Jul 20 05:29:53 PM PDT 24
Finished Jul 20 05:29:54 PM PDT 24
Peak memory 204424 kb
Host smart-e5fa77e6-86b7-4523-8075-09981239bea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504448633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.504448633
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2992924435
Short name T1035
Test name
Test status
Simulation time 32804664 ps
CPU time 0.71 seconds
Started Jul 20 05:29:55 PM PDT 24
Finished Jul 20 05:29:57 PM PDT 24
Peak memory 204472 kb
Host smart-07655973-653c-49f5-9769-e1d90d6f1cb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992924435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2992924435
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3521075023
Short name T1110
Test name
Test status
Simulation time 26851708 ps
CPU time 0.75 seconds
Started Jul 20 05:29:55 PM PDT 24
Finished Jul 20 05:29:58 PM PDT 24
Peak memory 204460 kb
Host smart-2859685e-4e7f-486b-aa37-03e09d360cb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521075023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3521075023
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3399032904
Short name T1079
Test name
Test status
Simulation time 10589389 ps
CPU time 0.73 seconds
Started Jul 20 05:29:54 PM PDT 24
Finished Jul 20 05:29:56 PM PDT 24
Peak memory 204464 kb
Host smart-ca564010-e113-44a8-9752-ae333c7046b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399032904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3399032904
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2164615134
Short name T1097
Test name
Test status
Simulation time 38464039 ps
CPU time 0.73 seconds
Started Jul 20 05:29:55 PM PDT 24
Finished Jul 20 05:29:58 PM PDT 24
Peak memory 204764 kb
Host smart-c98ee764-b64c-44f5-9828-2278bbfc2d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164615134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2164615134
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3028834599
Short name T1120
Test name
Test status
Simulation time 119772511 ps
CPU time 0.75 seconds
Started Jul 20 05:29:55 PM PDT 24
Finished Jul 20 05:29:57 PM PDT 24
Peak memory 204360 kb
Host smart-17168bfe-c421-49b6-a12b-f450dc633fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028834599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3028834599
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2541947886
Short name T1034
Test name
Test status
Simulation time 12460268 ps
CPU time 0.84 seconds
Started Jul 20 05:29:58 PM PDT 24
Finished Jul 20 05:30:00 PM PDT 24
Peak memory 204788 kb
Host smart-d601d47c-5d63-46f0-9f47-1b4ed6a25453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541947886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2541947886
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1185078278
Short name T1069
Test name
Test status
Simulation time 24262127 ps
CPU time 0.7 seconds
Started Jul 20 05:29:57 PM PDT 24
Finished Jul 20 05:29:59 PM PDT 24
Peak memory 204464 kb
Host smart-4adb3a94-17de-4305-8dba-83252d954377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185078278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1185078278
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3567064930
Short name T125
Test name
Test status
Simulation time 427531417 ps
CPU time 9.22 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:41 PM PDT 24
Peak memory 207752 kb
Host smart-be1c2579-2f1a-4d5c-9959-63068c785ee0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567064930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3567064930
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4108565333
Short name T1145
Test name
Test status
Simulation time 185974360 ps
CPU time 11.21 seconds
Started Jul 20 05:29:29 PM PDT 24
Finished Jul 20 05:29:41 PM PDT 24
Peak memory 207648 kb
Host smart-b297c881-b22b-492e-bed5-880817076017
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108565333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.4108565333
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1772307950
Short name T89
Test name
Test status
Simulation time 37137458 ps
CPU time 1.13 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:29:34 PM PDT 24
Peak memory 207792 kb
Host smart-5e03382a-34e5-41ba-8207-14f089e00433
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772307950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1772307950
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1703178069
Short name T1090
Test name
Test status
Simulation time 227792744 ps
CPU time 1.91 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:29:34 PM PDT 24
Peak memory 216248 kb
Host smart-60a58de0-c4b5-4d77-81b9-46e27cfbff17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703178069 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1703178069
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.473907014
Short name T1148
Test name
Test status
Simulation time 67291777 ps
CPU time 2.33 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:29:35 PM PDT 24
Peak memory 216184 kb
Host smart-7a4f43c9-427f-4061-ab75-da5602032c1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473907014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.473907014
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.711697751
Short name T1115
Test name
Test status
Simulation time 13143191 ps
CPU time 0.72 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:32 PM PDT 24
Peak memory 204432 kb
Host smart-42221539-7ed0-4dae-852c-158f98d36ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711697751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.711697751
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.520486499
Short name T1050
Test name
Test status
Simulation time 33148996 ps
CPU time 1.25 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:33 PM PDT 24
Peak memory 216016 kb
Host smart-53f2ca66-e0c2-4daa-8bf1-c6db6eb724d3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520486499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.520486499
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2686596848
Short name T1122
Test name
Test status
Simulation time 11423275 ps
CPU time 0.66 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:29:34 PM PDT 24
Peak memory 204292 kb
Host smart-4a7db03d-46cb-4997-8b39-8b5b5f37c546
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686596848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2686596848
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1651884411
Short name T1051
Test name
Test status
Simulation time 151811703 ps
CPU time 1.61 seconds
Started Jul 20 05:29:28 PM PDT 24
Finished Jul 20 05:29:30 PM PDT 24
Peak memory 215992 kb
Host smart-cd22ea44-f32f-4a4e-b067-cd6e115678bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651884411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1651884411
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1171026871
Short name T110
Test name
Test status
Simulation time 143097007 ps
CPU time 2.64 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:29:36 PM PDT 24
Peak memory 216376 kb
Host smart-35a00cc7-d9d6-4577-a419-987f75eee41c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171026871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
171026871
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.191025003
Short name T172
Test name
Test status
Simulation time 2024280252 ps
CPU time 21.44 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:29:54 PM PDT 24
Peak memory 216036 kb
Host smart-8b836629-466f-4736-b314-1ad05aca54bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191025003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.191025003
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3899788491
Short name T1065
Test name
Test status
Simulation time 14141535 ps
CPU time 0.72 seconds
Started Jul 20 05:29:54 PM PDT 24
Finished Jul 20 05:29:56 PM PDT 24
Peak memory 204772 kb
Host smart-29444ce7-8fd3-40b7-9a84-1338c9a56c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899788491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3899788491
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1908715324
Short name T1048
Test name
Test status
Simulation time 79460697 ps
CPU time 0.78 seconds
Started Jul 20 05:30:01 PM PDT 24
Finished Jul 20 05:30:02 PM PDT 24
Peak memory 204364 kb
Host smart-dda36111-73e0-4d86-b281-f76b94c5af6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908715324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1908715324
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1014148242
Short name T1127
Test name
Test status
Simulation time 32825919 ps
CPU time 0.76 seconds
Started Jul 20 05:30:01 PM PDT 24
Finished Jul 20 05:30:02 PM PDT 24
Peak memory 204748 kb
Host smart-218d2a88-6f18-4701-9a4c-0a25af63c87a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014148242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1014148242
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2166399642
Short name T1082
Test name
Test status
Simulation time 229519890 ps
CPU time 0.85 seconds
Started Jul 20 05:29:59 PM PDT 24
Finished Jul 20 05:30:01 PM PDT 24
Peak memory 204792 kb
Host smart-2ec5abc0-f69a-4810-94e7-a6fdeadd9e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166399642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2166399642
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1327898803
Short name T1075
Test name
Test status
Simulation time 120837578 ps
CPU time 0.74 seconds
Started Jul 20 05:29:58 PM PDT 24
Finished Jul 20 05:29:59 PM PDT 24
Peak memory 204460 kb
Host smart-e61f62c8-59b4-4b5d-889e-c9358e8fb881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327898803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1327898803
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1135425091
Short name T1040
Test name
Test status
Simulation time 14680926 ps
CPU time 0.77 seconds
Started Jul 20 05:29:54 PM PDT 24
Finished Jul 20 05:29:57 PM PDT 24
Peak memory 204376 kb
Host smart-91653dea-887b-44fd-9ffe-17e2087ac2a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135425091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1135425091
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.233765040
Short name T1147
Test name
Test status
Simulation time 65830539 ps
CPU time 0.76 seconds
Started Jul 20 05:29:56 PM PDT 24
Finished Jul 20 05:29:59 PM PDT 24
Peak memory 204792 kb
Host smart-2b6c22e1-5d5c-45ec-9282-a68717d73992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233765040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.233765040
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2071807144
Short name T1102
Test name
Test status
Simulation time 13685071 ps
CPU time 0.75 seconds
Started Jul 20 05:29:55 PM PDT 24
Finished Jul 20 05:29:58 PM PDT 24
Peak memory 204492 kb
Host smart-92ac48f4-4194-4690-a3bb-daad02265f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071807144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2071807144
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.524692948
Short name T1059
Test name
Test status
Simulation time 32245429 ps
CPU time 0.74 seconds
Started Jul 20 05:29:52 PM PDT 24
Finished Jul 20 05:29:53 PM PDT 24
Peak memory 204452 kb
Host smart-af6d77bc-77a8-4a61-9757-5b707e7b7eda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524692948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.524692948
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.754056176
Short name T1071
Test name
Test status
Simulation time 15941236 ps
CPU time 0.8 seconds
Started Jul 20 05:30:01 PM PDT 24
Finished Jul 20 05:30:02 PM PDT 24
Peak memory 204460 kb
Host smart-8564fe08-1c21-4b94-aed6-bbb7d1d357fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754056176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.754056176
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1280831861
Short name T1068
Test name
Test status
Simulation time 601385084 ps
CPU time 3.65 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:29:37 PM PDT 24
Peak memory 218056 kb
Host smart-316dd3c7-1d17-4085-b5ef-d30d569fccdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280831861 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1280831861
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1150258116
Short name T1121
Test name
Test status
Simulation time 161345873 ps
CPU time 2.38 seconds
Started Jul 20 05:29:29 PM PDT 24
Finished Jul 20 05:29:32 PM PDT 24
Peak memory 207732 kb
Host smart-b03ea002-1d34-4aaa-ae39-0d660a0b13e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150258116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
150258116
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4151677328
Short name T1101
Test name
Test status
Simulation time 17507276 ps
CPU time 0.8 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:32 PM PDT 24
Peak memory 204440 kb
Host smart-36bbc7a6-7ce9-4d8e-85e9-ccc3683253dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151677328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.4
151677328
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2024882756
Short name T1086
Test name
Test status
Simulation time 158950352 ps
CPU time 1.78 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:33 PM PDT 24
Peak memory 216020 kb
Host smart-a5c6ad18-6f83-433c-a0a5-b8c7a1c4af39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024882756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2024882756
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1510256163
Short name T109
Test name
Test status
Simulation time 239029574 ps
CPU time 2.17 seconds
Started Jul 20 05:29:29 PM PDT 24
Finished Jul 20 05:29:33 PM PDT 24
Peak memory 216164 kb
Host smart-bf51788f-ce1e-4bd5-82a9-56054dc43980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510256163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
510256163
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2760067340
Short name T179
Test name
Test status
Simulation time 946615501 ps
CPU time 22.17 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:53 PM PDT 24
Peak memory 216036 kb
Host smart-1e97bedf-8481-44bb-a4cd-4827faed15f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760067340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2760067340
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2639020335
Short name T1135
Test name
Test status
Simulation time 302983809 ps
CPU time 3.81 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:36 PM PDT 24
Peak memory 217956 kb
Host smart-04070882-f5bf-41a3-af19-f5bf2366cfcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639020335 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2639020335
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3809648939
Short name T160
Test name
Test status
Simulation time 1989678672 ps
CPU time 2.64 seconds
Started Jul 20 05:29:30 PM PDT 24
Finished Jul 20 05:29:35 PM PDT 24
Peak memory 216012 kb
Host smart-3a2df506-402f-466f-8b5c-0a76dca72bc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809648939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
809648939
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3291708025
Short name T1063
Test name
Test status
Simulation time 35227245 ps
CPU time 0.71 seconds
Started Jul 20 05:29:31 PM PDT 24
Finished Jul 20 05:29:34 PM PDT 24
Peak memory 204472 kb
Host smart-fd33367f-53af-46df-9510-1c895b9ea709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291708025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
291708025
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2417602521
Short name T1149
Test name
Test status
Simulation time 645835346 ps
CPU time 4.12 seconds
Started Jul 20 05:29:29 PM PDT 24
Finished Jul 20 05:29:33 PM PDT 24
Peak memory 215944 kb
Host smart-b48ad699-0df6-430e-b015-bf4af1180380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417602521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2417602521
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2565295720
Short name T105
Test name
Test status
Simulation time 128769519 ps
CPU time 3.13 seconds
Started Jul 20 05:29:29 PM PDT 24
Finished Jul 20 05:29:33 PM PDT 24
Peak memory 216180 kb
Host smart-f1be3cc7-88ba-4b19-b965-755f364f6ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565295720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
565295720
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4122833852
Short name T178
Test name
Test status
Simulation time 279418449 ps
CPU time 17.72 seconds
Started Jul 20 05:29:28 PM PDT 24
Finished Jul 20 05:29:46 PM PDT 24
Peak memory 216012 kb
Host smart-84881503-d31a-4179-8c24-4fbed297ebf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122833852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.4122833852
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1558866990
Short name T1107
Test name
Test status
Simulation time 102253488 ps
CPU time 3.49 seconds
Started Jul 20 05:29:36 PM PDT 24
Finished Jul 20 05:29:40 PM PDT 24
Peak memory 218844 kb
Host smart-aa390c10-971b-442f-bd00-fef08da09423
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558866990 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1558866990
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1760160778
Short name T121
Test name
Test status
Simulation time 77830341 ps
CPU time 1.29 seconds
Started Jul 20 05:29:39 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 216012 kb
Host smart-92595e34-a28e-4052-ad22-e56fca916cfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760160778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
760160778
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3891401507
Short name T1053
Test name
Test status
Simulation time 14848662 ps
CPU time 0.75 seconds
Started Jul 20 05:29:37 PM PDT 24
Finished Jul 20 05:29:38 PM PDT 24
Peak memory 204392 kb
Host smart-1ba3fe58-8932-4a32-9ca4-a6d016aec9d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891401507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
891401507
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.891954982
Short name T1058
Test name
Test status
Simulation time 136930686 ps
CPU time 1.96 seconds
Started Jul 20 05:29:38 PM PDT 24
Finished Jul 20 05:29:41 PM PDT 24
Peak memory 216024 kb
Host smart-9d33e35c-4843-4b75-b124-a5caba415590
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891954982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.891954982
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4077100824
Short name T108
Test name
Test status
Simulation time 90979374 ps
CPU time 1.56 seconds
Started Jul 20 05:29:29 PM PDT 24
Finished Jul 20 05:29:32 PM PDT 24
Peak memory 216304 kb
Host smart-fb44310d-c968-4c07-bba3-53fd43f5d0f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077100824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.4
077100824
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2888153596
Short name T176
Test name
Test status
Simulation time 1068284219 ps
CPU time 23.78 seconds
Started Jul 20 05:29:34 PM PDT 24
Finished Jul 20 05:29:58 PM PDT 24
Peak memory 215928 kb
Host smart-9733c99c-5d5a-4416-99f3-aef7c73842e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888153596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2888153596
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1193131896
Short name T1088
Test name
Test status
Simulation time 51229749 ps
CPU time 3.32 seconds
Started Jul 20 05:29:40 PM PDT 24
Finished Jul 20 05:29:46 PM PDT 24
Peak memory 218332 kb
Host smart-d9a09557-13a8-4701-8988-59e25f84f7d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193131896 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1193131896
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2268929788
Short name T1078
Test name
Test status
Simulation time 38337394 ps
CPU time 1.25 seconds
Started Jul 20 05:29:38 PM PDT 24
Finished Jul 20 05:29:40 PM PDT 24
Peak memory 207908 kb
Host smart-69a18445-ae8b-4457-a601-469045a3b5f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268929788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
268929788
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2547641989
Short name T1045
Test name
Test status
Simulation time 42292021 ps
CPU time 0.74 seconds
Started Jul 20 05:29:40 PM PDT 24
Finished Jul 20 05:29:44 PM PDT 24
Peak memory 204312 kb
Host smart-308a1249-206d-46bb-b857-914b188a5bdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547641989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
547641989
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.951673010
Short name T143
Test name
Test status
Simulation time 159289160 ps
CPU time 4.29 seconds
Started Jul 20 05:29:37 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 215968 kb
Host smart-46684b14-de41-4ca2-adc6-b57b16978910
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951673010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.951673010
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2359980024
Short name T106
Test name
Test status
Simulation time 35844823 ps
CPU time 2.18 seconds
Started Jul 20 05:29:37 PM PDT 24
Finished Jul 20 05:29:40 PM PDT 24
Peak memory 216180 kb
Host smart-c6462f64-07c2-4dab-93a5-d6cddc1dda21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359980024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
359980024
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1694770856
Short name T1108
Test name
Test status
Simulation time 791119530 ps
CPU time 20.14 seconds
Started Jul 20 05:29:38 PM PDT 24
Finished Jul 20 05:30:00 PM PDT 24
Peak memory 215952 kb
Host smart-dc13f6fd-86f6-44b0-a299-a725aa9b0a25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694770856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1694770856
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3360189773
Short name T100
Test name
Test status
Simulation time 29355282 ps
CPU time 1.84 seconds
Started Jul 20 05:29:39 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 216020 kb
Host smart-797ba42f-0b25-4c8a-b74d-b45eee7d331e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360189773 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3360189773
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.843451545
Short name T118
Test name
Test status
Simulation time 454851150 ps
CPU time 2.97 seconds
Started Jul 20 05:29:43 PM PDT 24
Finished Jul 20 05:29:47 PM PDT 24
Peak memory 215948 kb
Host smart-03cd355a-1b2a-41ce-87b8-5f13127b07ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843451545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.843451545
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4108500786
Short name T1042
Test name
Test status
Simulation time 45527764 ps
CPU time 0.74 seconds
Started Jul 20 05:29:40 PM PDT 24
Finished Jul 20 05:29:42 PM PDT 24
Peak memory 204772 kb
Host smart-c4d842b6-9343-49bb-a5b3-d315e051c03b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108500786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4
108500786
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3863438181
Short name T1098
Test name
Test status
Simulation time 245915902 ps
CPU time 1.82 seconds
Started Jul 20 05:29:42 PM PDT 24
Finished Jul 20 05:29:45 PM PDT 24
Peak memory 216024 kb
Host smart-7ad08fcb-79d4-4d82-9d58-95c14084ae4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863438181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3863438181
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3378212019
Short name T1116
Test name
Test status
Simulation time 191467472 ps
CPU time 2.59 seconds
Started Jul 20 05:29:40 PM PDT 24
Finished Jul 20 05:29:45 PM PDT 24
Peak memory 216052 kb
Host smart-3645f2d6-fc2c-4d32-9ed3-cb11407df1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378212019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
378212019
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1404132763
Short name T1134
Test name
Test status
Simulation time 437581457 ps
CPU time 6.99 seconds
Started Jul 20 05:29:37 PM PDT 24
Finished Jul 20 05:29:45 PM PDT 24
Peak memory 216068 kb
Host smart-9f75ca04-672b-4a31-a43a-6578603b8615
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404132763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1404132763
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3009370790
Short name T385
Test name
Test status
Simulation time 13885933 ps
CPU time 0.78 seconds
Started Jul 20 05:37:23 PM PDT 24
Finished Jul 20 05:37:25 PM PDT 24
Peak memory 205748 kb
Host smart-eccd73cf-2f03-44cb-ae2e-5460d1174772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009370790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
009370790
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2241729095
Short name T600
Test name
Test status
Simulation time 51829845 ps
CPU time 2.53 seconds
Started Jul 20 05:37:24 PM PDT 24
Finished Jul 20 05:37:28 PM PDT 24
Peak memory 224976 kb
Host smart-f2f6d301-c2ca-4726-b79f-eac5843d6801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241729095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2241729095
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.23953291
Short name T665
Test name
Test status
Simulation time 72038927 ps
CPU time 0.74 seconds
Started Jul 20 05:37:12 PM PDT 24
Finished Jul 20 05:37:13 PM PDT 24
Peak memory 206104 kb
Host smart-f2fe3048-2f6e-4146-872c-e9356e8a5eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23953291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.23953291
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1314242828
Short name T704
Test name
Test status
Simulation time 22539223753 ps
CPU time 160.1 seconds
Started Jul 20 05:37:24 PM PDT 24
Finished Jul 20 05:40:05 PM PDT 24
Peak memory 249620 kb
Host smart-28bb0f5a-11ba-49cb-ac4d-bda5bf18393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314242828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1314242828
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.709238515
Short name T65
Test name
Test status
Simulation time 96371984684 ps
CPU time 223.17 seconds
Started Jul 20 05:37:25 PM PDT 24
Finished Jul 20 05:41:08 PM PDT 24
Peak memory 255504 kb
Host smart-a7f9f67f-a200-4f91-ba41-fd39b2f3b7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709238515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.709238515
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1458065534
Short name T634
Test name
Test status
Simulation time 2917012822 ps
CPU time 40.81 seconds
Started Jul 20 05:37:23 PM PDT 24
Finished Jul 20 05:38:04 PM PDT 24
Peak memory 241424 kb
Host smart-dd78d280-c196-4735-a6c8-6d86e681ef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458065534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1458065534
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3288594409
Short name T1016
Test name
Test status
Simulation time 81880586 ps
CPU time 3.49 seconds
Started Jul 20 05:37:24 PM PDT 24
Finished Jul 20 05:37:28 PM PDT 24
Peak memory 233148 kb
Host smart-9ac1de93-c95a-4c38-8359-c18c5e5f296e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288594409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3288594409
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.917741498
Short name T696
Test name
Test status
Simulation time 30703779875 ps
CPU time 225.9 seconds
Started Jul 20 05:37:26 PM PDT 24
Finished Jul 20 05:41:12 PM PDT 24
Peak memory 251412 kb
Host smart-5eb6a2ae-5de1-4632-8da6-f712420f40f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917741498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
917741498
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3774135588
Short name T644
Test name
Test status
Simulation time 348077877 ps
CPU time 5.21 seconds
Started Jul 20 05:37:25 PM PDT 24
Finished Jul 20 05:37:31 PM PDT 24
Peak memory 233116 kb
Host smart-ed5702c7-ea31-4372-8b44-480bfdfbcbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774135588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3774135588
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4245757386
Short name T237
Test name
Test status
Simulation time 3608482119 ps
CPU time 13.36 seconds
Started Jul 20 05:37:22 PM PDT 24
Finished Jul 20 05:37:36 PM PDT 24
Peak memory 237764 kb
Host smart-68270d83-cd44-448f-b927-027cd04c9225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245757386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4245757386
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3832557503
Short name T731
Test name
Test status
Simulation time 205574609 ps
CPU time 1.01 seconds
Started Jul 20 05:37:15 PM PDT 24
Finished Jul 20 05:37:17 PM PDT 24
Peak memory 217128 kb
Host smart-b30b979b-91bb-438d-bf08-504499c68777
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832557503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3832557503
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4017235043
Short name T913
Test name
Test status
Simulation time 250037202 ps
CPU time 2.74 seconds
Started Jul 20 05:37:14 PM PDT 24
Finished Jul 20 05:37:17 PM PDT 24
Peak memory 224864 kb
Host smart-179d70d2-63e2-4700-a965-cb13fa0826ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017235043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4017235043
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4258250897
Short name T729
Test name
Test status
Simulation time 9891248609 ps
CPU time 15 seconds
Started Jul 20 05:37:15 PM PDT 24
Finished Jul 20 05:37:31 PM PDT 24
Peak memory 225048 kb
Host smart-baabe3f6-e008-47eb-a726-e0c8e5d52595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258250897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4258250897
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4190834837
Short name T150
Test name
Test status
Simulation time 165211906 ps
CPU time 4.28 seconds
Started Jul 20 05:37:28 PM PDT 24
Finished Jul 20 05:37:33 PM PDT 24
Peak memory 223556 kb
Host smart-8dc41742-f8c6-4346-85c7-8f4882f76f85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4190834837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4190834837
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2737152796
Short name T77
Test name
Test status
Simulation time 368468335 ps
CPU time 1.21 seconds
Started Jul 20 05:37:28 PM PDT 24
Finished Jul 20 05:37:30 PM PDT 24
Peak memory 235832 kb
Host smart-1a7b6685-a3e2-4b16-ae38-fd0784ad6b04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737152796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2737152796
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2352961739
Short name T36
Test name
Test status
Simulation time 945276843755 ps
CPU time 389.26 seconds
Started Jul 20 05:37:24 PM PDT 24
Finished Jul 20 05:43:54 PM PDT 24
Peak memory 249768 kb
Host smart-2fd8b629-9918-4596-a658-7b37059dbd09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352961739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2352961739
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4279437703
Short name T648
Test name
Test status
Simulation time 1580529821 ps
CPU time 6.41 seconds
Started Jul 20 05:37:14 PM PDT 24
Finished Jul 20 05:37:21 PM PDT 24
Peak memory 216696 kb
Host smart-81ba9b72-9b72-4e91-82bf-e65131ddc53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279437703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4279437703
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2117624588
Short name T406
Test name
Test status
Simulation time 46938942 ps
CPU time 0.86 seconds
Started Jul 20 05:37:12 PM PDT 24
Finished Jul 20 05:37:14 PM PDT 24
Peak memory 206300 kb
Host smart-d7c09755-2d02-4268-beb7-568071533349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117624588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2117624588
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1145163130
Short name T930
Test name
Test status
Simulation time 205458348 ps
CPU time 0.83 seconds
Started Jul 20 05:37:14 PM PDT 24
Finished Jul 20 05:37:15 PM PDT 24
Peak memory 206260 kb
Host smart-245b7c70-0ddb-4696-a4d2-e06b10208bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145163130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1145163130
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.4266446544
Short name T608
Test name
Test status
Simulation time 296620566 ps
CPU time 3.73 seconds
Started Jul 20 05:37:26 PM PDT 24
Finished Jul 20 05:37:30 PM PDT 24
Peak memory 224900 kb
Host smart-fe941f96-aa47-4671-bfc1-87e61150b3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266446544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4266446544
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4042434403
Short name T758
Test name
Test status
Simulation time 45927223 ps
CPU time 0.69 seconds
Started Jul 20 05:37:32 PM PDT 24
Finished Jul 20 05:37:33 PM PDT 24
Peak memory 205760 kb
Host smart-3a1e02d2-5b0e-4498-ac64-c05a6005b33a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042434403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
042434403
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1241031954
Short name T686
Test name
Test status
Simulation time 640863685 ps
CPU time 5.12 seconds
Started Jul 20 05:37:25 PM PDT 24
Finished Jul 20 05:37:31 PM PDT 24
Peak memory 233136 kb
Host smart-9d08d3ae-529c-4816-ad8a-cc1a377b256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241031954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1241031954
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2862368169
Short name T576
Test name
Test status
Simulation time 66343743 ps
CPU time 0.78 seconds
Started Jul 20 05:37:28 PM PDT 24
Finished Jul 20 05:37:30 PM PDT 24
Peak memory 206884 kb
Host smart-096cc3fc-4980-4d1e-b988-1e0e9ff449bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862368169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2862368169
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4146611069
Short name T691
Test name
Test status
Simulation time 8950819045 ps
CPU time 41.48 seconds
Started Jul 20 05:37:30 PM PDT 24
Finished Jul 20 05:38:13 PM PDT 24
Peak memory 249660 kb
Host smart-6b9416cb-fb14-46af-a395-cd39677d45eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146611069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4146611069
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3775910439
Short name T66
Test name
Test status
Simulation time 10878299021 ps
CPU time 154.48 seconds
Started Jul 20 05:37:30 PM PDT 24
Finished Jul 20 05:40:06 PM PDT 24
Peak memory 272232 kb
Host smart-d6d459ff-6cf6-43e4-862c-e822d2427a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775910439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3775910439
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1045949031
Short name T187
Test name
Test status
Simulation time 389203901097 ps
CPU time 573.69 seconds
Started Jul 20 05:37:32 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 268968 kb
Host smart-1b60523b-a749-43f4-8a16-22ef50b9954b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045949031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1045949031
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3955632020
Short name T921
Test name
Test status
Simulation time 1053016325 ps
CPU time 21.12 seconds
Started Jul 20 05:37:33 PM PDT 24
Finished Jul 20 05:37:55 PM PDT 24
Peak memory 249576 kb
Host smart-246f763e-6c74-499e-83e6-a11699bea43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955632020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3955632020
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.4039759581
Short name T964
Test name
Test status
Simulation time 4442263447 ps
CPU time 33.33 seconds
Started Jul 20 05:37:31 PM PDT 24
Finished Jul 20 05:38:06 PM PDT 24
Peak memory 249688 kb
Host smart-db28b080-68a2-4411-ba15-25bbb01fcaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039759581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.4039759581
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4152794161
Short name T764
Test name
Test status
Simulation time 677420003 ps
CPU time 3.62 seconds
Started Jul 20 05:37:23 PM PDT 24
Finished Jul 20 05:37:27 PM PDT 24
Peak memory 224916 kb
Host smart-4b1a4319-5adf-4b2c-9b3a-37662527a75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152794161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4152794161
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1318548032
Short name T133
Test name
Test status
Simulation time 141942519 ps
CPU time 2.27 seconds
Started Jul 20 05:37:26 PM PDT 24
Finished Jul 20 05:37:29 PM PDT 24
Peak memory 232888 kb
Host smart-cf9a8629-7be7-4edf-af7d-24edaa654823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318548032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1318548032
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1243249744
Short name T1006
Test name
Test status
Simulation time 3302563833 ps
CPU time 7.19 seconds
Started Jul 20 05:37:23 PM PDT 24
Finished Jul 20 05:37:31 PM PDT 24
Peak memory 233284 kb
Host smart-573b4df1-a51e-464d-8076-1c30da4ea944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243249744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1243249744
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3275397697
Short name T149
Test name
Test status
Simulation time 1715493605 ps
CPU time 8.14 seconds
Started Jul 20 05:37:34 PM PDT 24
Finished Jul 20 05:37:43 PM PDT 24
Peak memory 219660 kb
Host smart-7682a70a-faa1-46a4-a48e-a75be93797d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3275397697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3275397697
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1348708832
Short name T76
Test name
Test status
Simulation time 118504271 ps
CPU time 0.98 seconds
Started Jul 20 05:37:32 PM PDT 24
Finished Jul 20 05:37:34 PM PDT 24
Peak memory 235852 kb
Host smart-d2426a1d-e7eb-4126-8f2b-4452072e0c16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348708832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1348708832
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1002893420
Short name T391
Test name
Test status
Simulation time 48547708 ps
CPU time 0.98 seconds
Started Jul 20 05:37:32 PM PDT 24
Finished Jul 20 05:37:34 PM PDT 24
Peak memory 207876 kb
Host smart-f473c080-039c-4c11-a0e9-26b265ac56d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002893420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1002893420
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3100506042
Short name T326
Test name
Test status
Simulation time 1428109077 ps
CPU time 10.44 seconds
Started Jul 20 05:37:23 PM PDT 24
Finished Jul 20 05:37:35 PM PDT 24
Peak memory 216876 kb
Host smart-c5b7a60f-e174-48d6-a78b-36123d1905ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100506042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3100506042
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1461308380
Short name T500
Test name
Test status
Simulation time 1148207017 ps
CPU time 5.07 seconds
Started Jul 20 05:37:26 PM PDT 24
Finished Jul 20 05:37:32 PM PDT 24
Peak memory 216668 kb
Host smart-99ead4b1-f255-41f2-a14a-4a0bdc3a2e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461308380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1461308380
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1686371091
Short name T487
Test name
Test status
Simulation time 20999958 ps
CPU time 0.94 seconds
Started Jul 20 05:37:20 PM PDT 24
Finished Jul 20 05:37:22 PM PDT 24
Peak memory 206896 kb
Host smart-2c7393dc-59c2-4b13-b204-028913bb9200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686371091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1686371091
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1426268170
Short name T31
Test name
Test status
Simulation time 58251403 ps
CPU time 0.83 seconds
Started Jul 20 05:37:26 PM PDT 24
Finished Jul 20 05:37:27 PM PDT 24
Peak memory 206284 kb
Host smart-11879a30-4331-4359-ba10-cddad8f1a36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426268170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1426268170
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2397396677
Short name T250
Test name
Test status
Simulation time 1031516766 ps
CPU time 6.26 seconds
Started Jul 20 05:37:24 PM PDT 24
Finished Jul 20 05:37:31 PM PDT 24
Peak memory 233160 kb
Host smart-f59d4e53-09d8-42b0-82ad-bc375b5d0b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397396677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2397396677
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.436052673
Short name T808
Test name
Test status
Simulation time 14046250 ps
CPU time 0.75 seconds
Started Jul 20 05:38:26 PM PDT 24
Finished Jul 20 05:38:28 PM PDT 24
Peak memory 206072 kb
Host smart-3b501f0d-305f-4fe2-a300-ce88d29a61b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436052673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.436052673
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1026459799
Short name T333
Test name
Test status
Simulation time 2572826524 ps
CPU time 8.68 seconds
Started Jul 20 05:38:26 PM PDT 24
Finished Jul 20 05:38:35 PM PDT 24
Peak memory 225052 kb
Host smart-19dde56a-57e0-4214-b875-e51c8db400ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026459799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1026459799
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1851256563
Short name T624
Test name
Test status
Simulation time 20124004 ps
CPU time 0.82 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:38:38 PM PDT 24
Peak memory 206924 kb
Host smart-f577e0ed-c903-403e-ba50-c119752690fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851256563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1851256563
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2884546092
Short name T586
Test name
Test status
Simulation time 627731317591 ps
CPU time 212.37 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:42:09 PM PDT 24
Peak memory 256908 kb
Host smart-df1f51f7-81d2-4517-ad87-f39e5176d94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884546092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2884546092
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2640887769
Short name T168
Test name
Test status
Simulation time 10082352645 ps
CPU time 65.6 seconds
Started Jul 20 05:38:25 PM PDT 24
Finished Jul 20 05:39:31 PM PDT 24
Peak memory 250652 kb
Host smart-72650dbb-7f53-4fa0-8302-127796227f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640887769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2640887769
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.790926538
Short name T902
Test name
Test status
Simulation time 38528038707 ps
CPU time 132.94 seconds
Started Jul 20 05:38:27 PM PDT 24
Finished Jul 20 05:40:40 PM PDT 24
Peak memory 252152 kb
Host smart-082b0ec8-1f3e-4f29-8002-a6ff1ba3db9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790926538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.790926538
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.848914847
Short name T546
Test name
Test status
Simulation time 1590864368 ps
CPU time 33.18 seconds
Started Jul 20 05:38:34 PM PDT 24
Finished Jul 20 05:39:08 PM PDT 24
Peak memory 249568 kb
Host smart-4c393771-bb6c-494b-bceb-7dca092ee9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848914847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.848914847
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3624453460
Short name T534
Test name
Test status
Simulation time 2283199906 ps
CPU time 16.02 seconds
Started Jul 20 05:38:27 PM PDT 24
Finished Jul 20 05:38:44 PM PDT 24
Peak memory 219444 kb
Host smart-b482a811-c0dc-49d7-8d7c-470716a419ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624453460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3624453460
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3442542656
Short name T443
Test name
Test status
Simulation time 55686472 ps
CPU time 1.02 seconds
Started Jul 20 05:38:24 PM PDT 24
Finished Jul 20 05:38:25 PM PDT 24
Peak memory 217176 kb
Host smart-ea85bd58-c8c0-43fe-b00a-aa3e9ca302f5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442542656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3442542656
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1044567679
Short name T659
Test name
Test status
Simulation time 231899966 ps
CPU time 2.29 seconds
Started Jul 20 05:38:25 PM PDT 24
Finished Jul 20 05:38:28 PM PDT 24
Peak memory 224820 kb
Host smart-7f9ddad1-ee72-4283-8713-bc23df4ccc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044567679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1044567679
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1517295945
Short name T598
Test name
Test status
Simulation time 249911705 ps
CPU time 5.8 seconds
Started Jul 20 05:38:27 PM PDT 24
Finished Jul 20 05:38:34 PM PDT 24
Peak memory 223588 kb
Host smart-3424dce7-b583-4754-9895-d6e6c7f16b09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1517295945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1517295945
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2734777796
Short name T809
Test name
Test status
Simulation time 16201225 ps
CPU time 0.74 seconds
Started Jul 20 05:38:27 PM PDT 24
Finished Jul 20 05:38:28 PM PDT 24
Peak memory 206016 kb
Host smart-b62f60b0-86e0-4178-b896-497cf1731180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734777796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2734777796
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.503042875
Short name T577
Test name
Test status
Simulation time 3116678147 ps
CPU time 5.21 seconds
Started Jul 20 05:38:27 PM PDT 24
Finished Jul 20 05:38:33 PM PDT 24
Peak memory 216784 kb
Host smart-4a1c78ce-80a0-4154-bfff-6b272166d0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503042875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.503042875
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3551920586
Short name T615
Test name
Test status
Simulation time 52199768 ps
CPU time 0.82 seconds
Started Jul 20 05:38:27 PM PDT 24
Finished Jul 20 05:38:28 PM PDT 24
Peak memory 207136 kb
Host smart-dd6f464f-7861-4fb9-af5c-3082e87febae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551920586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3551920586
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2474288060
Short name T473
Test name
Test status
Simulation time 320451219 ps
CPU time 0.97 seconds
Started Jul 20 05:38:27 PM PDT 24
Finished Jul 20 05:38:29 PM PDT 24
Peak memory 206516 kb
Host smart-d27aae4b-32b8-4165-a0c7-bf33fc02550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474288060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2474288060
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2887106905
Short name T721
Test name
Test status
Simulation time 39000899352 ps
CPU time 32.12 seconds
Started Jul 20 05:38:26 PM PDT 24
Finished Jul 20 05:38:59 PM PDT 24
Peak memory 240008 kb
Host smart-e887427e-13da-41ea-a163-6be05d5faf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887106905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2887106905
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.53155704
Short name T450
Test name
Test status
Simulation time 29481054 ps
CPU time 0.71 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:38:37 PM PDT 24
Peak memory 205792 kb
Host smart-04ed695a-c35b-4e9a-b354-853738ae27ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53155704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.53155704
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3528456295
Short name T882
Test name
Test status
Simulation time 69655295 ps
CPU time 2.65 seconds
Started Jul 20 05:38:33 PM PDT 24
Finished Jul 20 05:38:36 PM PDT 24
Peak memory 224908 kb
Host smart-d104e07e-450e-4348-8002-672e117f0ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528456295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3528456295
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2049794409
Short name T429
Test name
Test status
Simulation time 37665660 ps
CPU time 0.79 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:38:37 PM PDT 24
Peak memory 206904 kb
Host smart-05f602a9-9446-4030-bc23-5d4c682853ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049794409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2049794409
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1322915563
Short name T310
Test name
Test status
Simulation time 256993659927 ps
CPU time 391.43 seconds
Started Jul 20 05:38:37 PM PDT 24
Finished Jul 20 05:45:09 PM PDT 24
Peak memory 257848 kb
Host smart-50650abb-2add-4881-adfd-72935527e3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322915563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1322915563
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1899800782
Short name T246
Test name
Test status
Simulation time 39994765455 ps
CPU time 63.49 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:39:39 PM PDT 24
Peak memory 249000 kb
Host smart-4fac2589-e5a6-495a-9f5b-bb3c52196d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899800782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1899800782
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2852609424
Short name T540
Test name
Test status
Simulation time 487124054 ps
CPU time 2.99 seconds
Started Jul 20 05:38:37 PM PDT 24
Finished Jul 20 05:38:41 PM PDT 24
Peak memory 218080 kb
Host smart-b5bd2f8f-0486-411f-9753-92c9b24cae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852609424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2852609424
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3458552669
Short name T739
Test name
Test status
Simulation time 3022105997 ps
CPU time 46.77 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:39:23 PM PDT 24
Peak memory 237936 kb
Host smart-07e02a2d-cf79-43c3-96e7-7bec08e47621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458552669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3458552669
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.914749058
Short name T191
Test name
Test status
Simulation time 28489366354 ps
CPU time 214.66 seconds
Started Jul 20 05:38:37 PM PDT 24
Finished Jul 20 05:42:13 PM PDT 24
Peak memory 257816 kb
Host smart-96ac678e-3ab5-4a2f-a7bb-79ad9a368b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914749058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.914749058
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1851760727
Short name T796
Test name
Test status
Simulation time 349233382 ps
CPU time 3.98 seconds
Started Jul 20 05:38:36 PM PDT 24
Finished Jul 20 05:38:41 PM PDT 24
Peak memory 224924 kb
Host smart-66b0a461-e2d9-4679-ae38-0c9e0bc4d0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851760727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1851760727
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1652883397
Short name T837
Test name
Test status
Simulation time 213178862 ps
CPU time 2.32 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:38:39 PM PDT 24
Peak memory 232792 kb
Host smart-a40ff2f4-777f-4b0e-bcfa-8ce0d6333edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652883397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1652883397
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2407172896
Short name T821
Test name
Test status
Simulation time 53496278 ps
CPU time 1.08 seconds
Started Jul 20 05:38:27 PM PDT 24
Finished Jul 20 05:38:29 PM PDT 24
Peak memory 217160 kb
Host smart-70850fec-e92f-47c7-b81a-b4326e1c022f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407172896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2407172896
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.962125333
Short name T55
Test name
Test status
Simulation time 2222533960 ps
CPU time 11.01 seconds
Started Jul 20 05:38:37 PM PDT 24
Finished Jul 20 05:38:49 PM PDT 24
Peak memory 233256 kb
Host smart-4aa6d3db-66f1-487b-957b-5703a8ffddc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962125333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.962125333
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3958857349
Short name T895
Test name
Test status
Simulation time 86634060 ps
CPU time 2.92 seconds
Started Jul 20 05:38:34 PM PDT 24
Finished Jul 20 05:38:38 PM PDT 24
Peak memory 233096 kb
Host smart-527e7f22-dec1-4961-8028-d806afb417fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958857349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3958857349
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3705266408
Short name T353
Test name
Test status
Simulation time 65249215 ps
CPU time 3.44 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:38:40 PM PDT 24
Peak memory 224008 kb
Host smart-7daf973f-819f-44c9-a0b0-0bfb0e455279
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3705266408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3705266408
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2405267681
Short name T468
Test name
Test status
Simulation time 95752465278 ps
CPU time 182.12 seconds
Started Jul 20 05:38:34 PM PDT 24
Finished Jul 20 05:41:36 PM PDT 24
Peak memory 257836 kb
Host smart-bca23268-acb0-4efa-9791-57c99a3d5ab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405267681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2405267681
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.669486854
Short name T822
Test name
Test status
Simulation time 23431245137 ps
CPU time 37.73 seconds
Started Jul 20 05:38:36 PM PDT 24
Finished Jul 20 05:39:15 PM PDT 24
Peak memory 216856 kb
Host smart-4c61103e-1d7e-47a7-a12a-59cba810a109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669486854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.669486854
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.519511752
Short name T440
Test name
Test status
Simulation time 27127559 ps
CPU time 0.7 seconds
Started Jul 20 05:38:36 PM PDT 24
Finished Jul 20 05:38:38 PM PDT 24
Peak memory 206012 kb
Host smart-0611b4e4-e71d-467a-8b35-444f5770c1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519511752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.519511752
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.651649380
Short name T431
Test name
Test status
Simulation time 81704182 ps
CPU time 0.97 seconds
Started Jul 20 05:38:38 PM PDT 24
Finished Jul 20 05:38:39 PM PDT 24
Peak memory 207684 kb
Host smart-514c1e36-7dd9-4651-a4d4-7795eb5e205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651649380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.651649380
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1509004952
Short name T477
Test name
Test status
Simulation time 212834404 ps
CPU time 0.89 seconds
Started Jul 20 05:38:34 PM PDT 24
Finished Jul 20 05:38:36 PM PDT 24
Peak memory 206272 kb
Host smart-06c505ca-26a1-462d-96d9-d1ab5d8d299f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509004952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1509004952
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4275652709
Short name T27
Test name
Test status
Simulation time 14217847345 ps
CPU time 22.53 seconds
Started Jul 20 05:38:33 PM PDT 24
Finished Jul 20 05:38:56 PM PDT 24
Peak memory 233160 kb
Host smart-0d4c20b9-ea13-4dae-9b2c-ee5833248150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275652709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4275652709
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.340236657
Short name T776
Test name
Test status
Simulation time 145210239 ps
CPU time 2.61 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:38:40 PM PDT 24
Peak memory 233108 kb
Host smart-d8e2311c-ac60-445a-9592-2f9fe5d9e9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340236657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.340236657
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.520574087
Short name T508
Test name
Test status
Simulation time 57631070 ps
CPU time 0.8 seconds
Started Jul 20 05:38:34 PM PDT 24
Finished Jul 20 05:38:35 PM PDT 24
Peak memory 206884 kb
Host smart-84ef4368-a434-4cbc-a3be-212633639027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520574087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.520574087
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1443114041
Short name T699
Test name
Test status
Simulation time 56004356761 ps
CPU time 85.36 seconds
Started Jul 20 05:38:50 PM PDT 24
Finished Jul 20 05:40:16 PM PDT 24
Peak memory 233280 kb
Host smart-0ad848f0-cad8-4826-a513-c51a10935db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443114041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1443114041
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3728513171
Short name T855
Test name
Test status
Simulation time 31984820936 ps
CPU time 153.86 seconds
Started Jul 20 05:38:46 PM PDT 24
Finished Jul 20 05:41:21 PM PDT 24
Peak memory 257188 kb
Host smart-a1a381d3-84d8-429e-8052-941ac2b8c584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728513171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3728513171
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.913632641
Short name T523
Test name
Test status
Simulation time 91354969891 ps
CPU time 445.93 seconds
Started Jul 20 05:38:45 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 266096 kb
Host smart-1dc9dad0-c391-48ec-9306-4c505448ca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913632641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.913632641
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1294836974
Short name T1009
Test name
Test status
Simulation time 9034698710 ps
CPU time 19.41 seconds
Started Jul 20 05:38:46 PM PDT 24
Finished Jul 20 05:39:06 PM PDT 24
Peak memory 225060 kb
Host smart-71057779-350d-463e-8cbb-b620685734dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294836974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1294836974
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1585345954
Short name T734
Test name
Test status
Simulation time 8980496970 ps
CPU time 43.74 seconds
Started Jul 20 05:38:46 PM PDT 24
Finished Jul 20 05:39:31 PM PDT 24
Peak memory 250108 kb
Host smart-0f64b354-fca5-4227-a9ca-292d631ca9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585345954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1585345954
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2683814780
Short name T345
Test name
Test status
Simulation time 29520036 ps
CPU time 2.13 seconds
Started Jul 20 05:38:34 PM PDT 24
Finished Jul 20 05:38:37 PM PDT 24
Peak memory 224140 kb
Host smart-af44b079-27d0-4f6d-8bfa-374dd4c318bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683814780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2683814780
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4073294765
Short name T463
Test name
Test status
Simulation time 13620474744 ps
CPU time 70.02 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:39:46 PM PDT 24
Peak memory 249592 kb
Host smart-99ac4f89-fdb5-4391-a94b-f70a32bd5403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073294765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4073294765
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.495224891
Short name T379
Test name
Test status
Simulation time 14716042 ps
CPU time 1.06 seconds
Started Jul 20 05:38:36 PM PDT 24
Finished Jul 20 05:38:38 PM PDT 24
Peak memory 217120 kb
Host smart-e841bbe6-8d53-4b20-9820-8f27b397fde4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495224891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.495224891
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2632877729
Short name T50
Test name
Test status
Simulation time 13179198083 ps
CPU time 12.41 seconds
Started Jul 20 05:38:34 PM PDT 24
Finished Jul 20 05:38:48 PM PDT 24
Peak memory 241060 kb
Host smart-08a684bc-a807-41ec-b1aa-9a108c7c8938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632877729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2632877729
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1257066577
Short name T240
Test name
Test status
Simulation time 1203962090 ps
CPU time 4.92 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:38:41 PM PDT 24
Peak memory 224956 kb
Host smart-9033e974-e16f-4f12-96c2-dec7a0d0cdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257066577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1257066577
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.357066246
Short name T724
Test name
Test status
Simulation time 105213874 ps
CPU time 3 seconds
Started Jul 20 05:38:46 PM PDT 24
Finished Jul 20 05:38:50 PM PDT 24
Peak memory 220568 kb
Host smart-8b9d4259-3044-4327-bc49-d3e655371846
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=357066246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.357066246
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3565741232
Short name T21
Test name
Test status
Simulation time 30135329697 ps
CPU time 300.07 seconds
Started Jul 20 05:38:44 PM PDT 24
Finished Jul 20 05:43:45 PM PDT 24
Peak memory 256908 kb
Host smart-a9feac1c-b150-4949-b283-a77b2954df1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565741232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3565741232
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.670675443
Short name T958
Test name
Test status
Simulation time 8095267730 ps
CPU time 20.59 seconds
Started Jul 20 05:38:33 PM PDT 24
Finished Jul 20 05:38:54 PM PDT 24
Peak memory 216848 kb
Host smart-b3d790fd-cea9-4682-aea6-edd96ebf23fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670675443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.670675443
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2820576125
Short name T823
Test name
Test status
Simulation time 2674303642 ps
CPU time 6.91 seconds
Started Jul 20 05:38:36 PM PDT 24
Finished Jul 20 05:38:44 PM PDT 24
Peak memory 216824 kb
Host smart-868a8a36-9ede-46e0-82c3-298f8e791625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820576125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2820576125
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.201747119
Short name T845
Test name
Test status
Simulation time 264261699 ps
CPU time 4.44 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:38:40 PM PDT 24
Peak memory 216604 kb
Host smart-b6909f5c-7064-4d2d-becb-948f8cbb8140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201747119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.201747119
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.126080774
Short name T35
Test name
Test status
Simulation time 220754821 ps
CPU time 0.81 seconds
Started Jul 20 05:38:35 PM PDT 24
Finished Jul 20 05:38:36 PM PDT 24
Peak memory 206252 kb
Host smart-f8171fa3-22fc-4925-b0e8-ec7c512ddb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126080774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.126080774
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1726945096
Short name T466
Test name
Test status
Simulation time 43374446917 ps
CPU time 35.55 seconds
Started Jul 20 05:38:38 PM PDT 24
Finished Jul 20 05:39:14 PM PDT 24
Peak memory 241396 kb
Host smart-e7a8e46b-64ce-4c3b-9fd7-15cc1e196107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726945096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1726945096
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3681360793
Short name T412
Test name
Test status
Simulation time 42972839 ps
CPU time 0.71 seconds
Started Jul 20 05:38:54 PM PDT 24
Finished Jul 20 05:38:56 PM PDT 24
Peak memory 205176 kb
Host smart-de8beeef-d9f0-4937-be63-34ed53b0c4f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681360793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3681360793
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1581875683
Short name T976
Test name
Test status
Simulation time 1540133424 ps
CPU time 3.36 seconds
Started Jul 20 05:38:49 PM PDT 24
Finished Jul 20 05:38:52 PM PDT 24
Peak memory 224912 kb
Host smart-2f39042c-f917-4d59-be46-441a621d3e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581875683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1581875683
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.272538722
Short name T525
Test name
Test status
Simulation time 61206156 ps
CPU time 0.77 seconds
Started Jul 20 05:38:45 PM PDT 24
Finished Jul 20 05:38:46 PM PDT 24
Peak memory 207208 kb
Host smart-ee94e390-b1ff-47f3-9734-69e3c7576919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272538722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.272538722
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4056781592
Short name T682
Test name
Test status
Simulation time 766984490 ps
CPU time 11.06 seconds
Started Jul 20 05:38:47 PM PDT 24
Finished Jul 20 05:38:59 PM PDT 24
Peak memory 235044 kb
Host smart-82276c96-ea92-4c96-8fcb-e13a015c7285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056781592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4056781592
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2662174014
Short name T593
Test name
Test status
Simulation time 74205911310 ps
CPU time 55.9 seconds
Started Jul 20 05:38:46 PM PDT 24
Finished Jul 20 05:39:42 PM PDT 24
Peak memory 234428 kb
Host smart-1972d8fe-238a-4d49-b429-f2cc099634c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662174014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2662174014
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1238947530
Short name T311
Test name
Test status
Simulation time 2717563537 ps
CPU time 39.68 seconds
Started Jul 20 05:38:46 PM PDT 24
Finished Jul 20 05:39:26 PM PDT 24
Peak memory 225052 kb
Host smart-b778775e-5f03-419c-b00c-2fc26f1b50fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238947530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1238947530
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.630813413
Short name T527
Test name
Test status
Simulation time 18561211376 ps
CPU time 39.36 seconds
Started Jul 20 05:38:44 PM PDT 24
Finished Jul 20 05:39:24 PM PDT 24
Peak memory 240136 kb
Host smart-cb1d7453-d775-41c0-a028-7d961ccfd0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630813413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.630813413
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4009830111
Short name T838
Test name
Test status
Simulation time 5841289420 ps
CPU time 12.9 seconds
Started Jul 20 05:38:47 PM PDT 24
Finished Jul 20 05:39:00 PM PDT 24
Peak memory 225036 kb
Host smart-8151bb7f-38f8-467a-9034-fb0333a47f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009830111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4009830111
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1725436488
Short name T247
Test name
Test status
Simulation time 2021555989 ps
CPU time 12.25 seconds
Started Jul 20 05:38:46 PM PDT 24
Finished Jul 20 05:38:59 PM PDT 24
Peak memory 233156 kb
Host smart-01e23f89-8096-4158-b239-545425610c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725436488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1725436488
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3299671076
Short name T646
Test name
Test status
Simulation time 199636375 ps
CPU time 1.02 seconds
Started Jul 20 05:38:45 PM PDT 24
Finished Jul 20 05:38:46 PM PDT 24
Peak memory 217164 kb
Host smart-b9af97f2-83a3-408f-a218-8268c95bcb08
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299671076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3299671076
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.287692499
Short name T278
Test name
Test status
Simulation time 123595259 ps
CPU time 2.31 seconds
Started Jul 20 05:38:46 PM PDT 24
Finished Jul 20 05:38:49 PM PDT 24
Peak memory 233116 kb
Host smart-cabff1fb-a217-4db3-afe4-f08d982487e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287692499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.287692499
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2094714974
Short name T455
Test name
Test status
Simulation time 123246943 ps
CPU time 2.1 seconds
Started Jul 20 05:38:45 PM PDT 24
Finished Jul 20 05:38:48 PM PDT 24
Peak memory 224872 kb
Host smart-f3171459-bfb6-436a-8259-2f8d90a86952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094714974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2094714974
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1317129434
Short name T491
Test name
Test status
Simulation time 788405633 ps
CPU time 8.19 seconds
Started Jul 20 05:38:46 PM PDT 24
Finished Jul 20 05:38:55 PM PDT 24
Peak memory 222896 kb
Host smart-07265e42-1665-405e-af1c-2f6cba4bf604
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1317129434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1317129434
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1524533901
Short name T37
Test name
Test status
Simulation time 187407408 ps
CPU time 0.99 seconds
Started Jul 20 05:38:53 PM PDT 24
Finished Jul 20 05:38:54 PM PDT 24
Peak memory 207660 kb
Host smart-449d6768-1280-4807-aaa0-baa6dc6cbcf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524533901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1524533901
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1853495920
Short name T416
Test name
Test status
Simulation time 1376787343 ps
CPU time 11.01 seconds
Started Jul 20 05:38:43 PM PDT 24
Finished Jul 20 05:38:54 PM PDT 24
Peak memory 219692 kb
Host smart-561368c8-2e7c-4617-9274-fe9d533d4eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853495920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1853495920
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.547346198
Short name T507
Test name
Test status
Simulation time 5338023517 ps
CPU time 13.67 seconds
Started Jul 20 05:38:46 PM PDT 24
Finished Jul 20 05:39:00 PM PDT 24
Peak memory 216796 kb
Host smart-1de8ca12-18d7-4003-8f1b-88e6de500e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547346198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.547346198
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.818262869
Short name T611
Test name
Test status
Simulation time 160649883 ps
CPU time 0.94 seconds
Started Jul 20 05:38:49 PM PDT 24
Finished Jul 20 05:38:50 PM PDT 24
Peak memory 207424 kb
Host smart-0046ecd2-d28c-489f-ba62-c97407d2223a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818262869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.818262869
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.925753801
Short name T782
Test name
Test status
Simulation time 36534388 ps
CPU time 0.87 seconds
Started Jul 20 05:38:47 PM PDT 24
Finished Jul 20 05:38:48 PM PDT 24
Peak memory 206252 kb
Host smart-f39e5692-52fe-49f0-b59f-694c396412b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925753801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.925753801
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4010825849
Short name T70
Test name
Test status
Simulation time 3370936706 ps
CPU time 11.2 seconds
Started Jul 20 05:38:44 PM PDT 24
Finished Jul 20 05:38:55 PM PDT 24
Peak memory 235940 kb
Host smart-6872b1cd-1827-43f5-8d4d-050ef1fd8600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010825849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4010825849
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2123133786
Short name T434
Test name
Test status
Simulation time 46489084 ps
CPU time 0.71 seconds
Started Jul 20 05:38:53 PM PDT 24
Finished Jul 20 05:38:55 PM PDT 24
Peak memory 206112 kb
Host smart-c2787357-637a-4ebd-badf-98235b4efefd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123133786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2123133786
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3303095954
Short name T257
Test name
Test status
Simulation time 1095552989 ps
CPU time 14.34 seconds
Started Jul 20 05:39:02 PM PDT 24
Finished Jul 20 05:39:18 PM PDT 24
Peak memory 224868 kb
Host smart-99feff7b-f48c-43af-ba8b-f8e9cfcadb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303095954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3303095954
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3455712835
Short name T632
Test name
Test status
Simulation time 32002994 ps
CPU time 0.75 seconds
Started Jul 20 05:38:53 PM PDT 24
Finished Jul 20 05:38:55 PM PDT 24
Peak memory 205872 kb
Host smart-80c49572-caaf-4dad-b672-9e2058713ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455712835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3455712835
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.918618499
Short name T1021
Test name
Test status
Simulation time 65036474388 ps
CPU time 158.52 seconds
Started Jul 20 05:38:55 PM PDT 24
Finished Jul 20 05:41:34 PM PDT 24
Peak memory 257788 kb
Host smart-fc94783f-4ab2-443a-a4e1-39d0a3525c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918618499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.918618499
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2647825155
Short name T971
Test name
Test status
Simulation time 11302060327 ps
CPU time 119.12 seconds
Started Jul 20 05:38:53 PM PDT 24
Finished Jul 20 05:40:53 PM PDT 24
Peak memory 252052 kb
Host smart-51c79d94-d0e8-4e20-b31e-2014afcb63ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647825155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2647825155
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1580368516
Short name T925
Test name
Test status
Simulation time 70013441 ps
CPU time 2.3 seconds
Started Jul 20 05:38:54 PM PDT 24
Finished Jul 20 05:38:57 PM PDT 24
Peak memory 224864 kb
Host smart-5d6d09e5-9c82-428d-b2c2-e892445b4afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580368516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1580368516
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3205997234
Short name T294
Test name
Test status
Simulation time 21714771851 ps
CPU time 75.88 seconds
Started Jul 20 05:38:58 PM PDT 24
Finished Jul 20 05:40:14 PM PDT 24
Peak memory 258136 kb
Host smart-2d1c9aec-ebfb-42b8-98cb-0e117f5c0826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205997234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3205997234
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.934766140
Short name T422
Test name
Test status
Simulation time 245485452 ps
CPU time 3.61 seconds
Started Jul 20 05:38:54 PM PDT 24
Finished Jul 20 05:38:59 PM PDT 24
Peak memory 224904 kb
Host smart-fa8f0a28-ec20-418b-9c17-148283381751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934766140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.934766140
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3491202124
Short name T1003
Test name
Test status
Simulation time 312409242 ps
CPU time 6.09 seconds
Started Jul 20 05:38:52 PM PDT 24
Finished Jul 20 05:38:59 PM PDT 24
Peak memory 224896 kb
Host smart-493f2cff-9d87-4c08-9db4-82ad38d3bcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491202124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3491202124
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.812377122
Short name T849
Test name
Test status
Simulation time 49152353 ps
CPU time 1.06 seconds
Started Jul 20 05:38:56 PM PDT 24
Finished Jul 20 05:38:58 PM PDT 24
Peak memory 218424 kb
Host smart-774d60ae-afd4-4507-a532-073dc3b8b1fd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812377122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.812377122
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.26340400
Short name T612
Test name
Test status
Simulation time 4517475275 ps
CPU time 9.8 seconds
Started Jul 20 05:38:54 PM PDT 24
Finished Jul 20 05:39:05 PM PDT 24
Peak memory 240332 kb
Host smart-56364171-ac3a-4c1f-a9c8-b2abd290c0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26340400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.26340400
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.94829536
Short name T755
Test name
Test status
Simulation time 166630348 ps
CPU time 3.04 seconds
Started Jul 20 05:38:53 PM PDT 24
Finished Jul 20 05:38:57 PM PDT 24
Peak memory 233200 kb
Host smart-0442a5bd-acfb-426f-8227-870ee10e0ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94829536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.94829536
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2547961971
Short name T789
Test name
Test status
Simulation time 166534848 ps
CPU time 3.81 seconds
Started Jul 20 05:38:53 PM PDT 24
Finished Jul 20 05:38:57 PM PDT 24
Peak memory 219244 kb
Host smart-aff3dc43-3d4d-4d5c-bf18-d77c848ab038
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2547961971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2547961971
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1088615740
Short name T158
Test name
Test status
Simulation time 5136033337 ps
CPU time 51.2 seconds
Started Jul 20 05:38:53 PM PDT 24
Finished Jul 20 05:39:45 PM PDT 24
Peak memory 225104 kb
Host smart-ae989a3a-247b-4be6-b905-bb7446f8aacc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088615740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1088615740
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2190292649
Short name T139
Test name
Test status
Simulation time 1574722447 ps
CPU time 12.41 seconds
Started Jul 20 05:38:52 PM PDT 24
Finished Jul 20 05:39:05 PM PDT 24
Peak memory 216684 kb
Host smart-30193de9-3f9e-4ee2-984d-3c314a01fd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190292649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2190292649
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.428364626
Short name T529
Test name
Test status
Simulation time 331269401 ps
CPU time 1.43 seconds
Started Jul 20 05:38:56 PM PDT 24
Finished Jul 20 05:38:58 PM PDT 24
Peak memory 208268 kb
Host smart-29ec2aa5-f7bf-42ae-9fc4-fc1e2b7c1586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428364626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.428364626
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1422726144
Short name T602
Test name
Test status
Simulation time 102561184 ps
CPU time 1.32 seconds
Started Jul 20 05:38:54 PM PDT 24
Finished Jul 20 05:38:56 PM PDT 24
Peak memory 216596 kb
Host smart-839b7a1b-7016-4102-82ed-c704f6546954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422726144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1422726144
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1221615590
Short name T787
Test name
Test status
Simulation time 142764875 ps
CPU time 0.98 seconds
Started Jul 20 05:38:54 PM PDT 24
Finished Jul 20 05:38:55 PM PDT 24
Peak memory 206320 kb
Host smart-5d289c89-4d52-4d87-ad1e-b784481d42d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221615590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1221615590
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4228197929
Short name T79
Test name
Test status
Simulation time 650626013 ps
CPU time 6.83 seconds
Started Jul 20 05:38:59 PM PDT 24
Finished Jul 20 05:39:07 PM PDT 24
Peak memory 241240 kb
Host smart-25df9441-b5dd-4c0e-b017-02a11e383976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228197929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4228197929
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.318049120
Short name T28
Test name
Test status
Simulation time 16063350 ps
CPU time 0.68 seconds
Started Jul 20 05:39:07 PM PDT 24
Finished Jul 20 05:39:08 PM PDT 24
Peak memory 205164 kb
Host smart-d63a0b33-1251-4f59-9df1-0503b35e1962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318049120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.318049120
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.80044072
Short name T584
Test name
Test status
Simulation time 528908778 ps
CPU time 2.98 seconds
Started Jul 20 05:39:07 PM PDT 24
Finished Jul 20 05:39:10 PM PDT 24
Peak memory 224604 kb
Host smart-2725d003-907f-413e-a4d1-27ab95d92756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80044072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.80044072
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3855752425
Short name T425
Test name
Test status
Simulation time 16052038 ps
CPU time 0.77 seconds
Started Jul 20 05:38:54 PM PDT 24
Finished Jul 20 05:38:56 PM PDT 24
Peak memory 205820 kb
Host smart-f2a822d1-9213-4d5f-9835-f9b023275bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855752425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3855752425
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3044640352
Short name T716
Test name
Test status
Simulation time 22223686 ps
CPU time 0.88 seconds
Started Jul 20 05:39:02 PM PDT 24
Finished Jul 20 05:39:04 PM PDT 24
Peak memory 216544 kb
Host smart-56cc2d04-5066-416a-bd3b-a078a370f841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044640352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3044640352
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3287518702
Short name T633
Test name
Test status
Simulation time 87655723354 ps
CPU time 222.12 seconds
Started Jul 20 05:39:04 PM PDT 24
Finished Jul 20 05:42:47 PM PDT 24
Peak memory 257044 kb
Host smart-447cadd5-93f7-454e-99fe-d7644c53ae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287518702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3287518702
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.524480837
Short name T896
Test name
Test status
Simulation time 1075282963 ps
CPU time 22.43 seconds
Started Jul 20 05:39:03 PM PDT 24
Finished Jul 20 05:39:26 PM PDT 24
Peak memory 237548 kb
Host smart-98e1ae09-056c-4937-8364-0bd1e9fb0678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524480837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.524480837
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3327483031
Short name T458
Test name
Test status
Simulation time 1315602118 ps
CPU time 28.58 seconds
Started Jul 20 05:39:05 PM PDT 24
Finished Jul 20 05:39:34 PM PDT 24
Peak memory 257332 kb
Host smart-491fdf83-5da5-4986-9dff-889c7f4ceebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327483031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3327483031
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1730744918
Short name T268
Test name
Test status
Simulation time 1235917268 ps
CPU time 10.61 seconds
Started Jul 20 05:38:58 PM PDT 24
Finished Jul 20 05:39:10 PM PDT 24
Peak memory 224844 kb
Host smart-0b2b4376-140c-4e5c-99ec-7f42215aa2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730744918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1730744918
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1413962896
Short name T728
Test name
Test status
Simulation time 47999166907 ps
CPU time 81.64 seconds
Started Jul 20 05:39:02 PM PDT 24
Finished Jul 20 05:40:25 PM PDT 24
Peak memory 233140 kb
Host smart-daeb5a15-3bf5-4820-a986-b1474c2d2811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413962896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1413962896
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3559024047
Short name T874
Test name
Test status
Simulation time 25002750 ps
CPU time 1.07 seconds
Started Jul 20 05:38:56 PM PDT 24
Finished Jul 20 05:38:58 PM PDT 24
Peak memory 217176 kb
Host smart-6d590402-65c5-4bae-a978-0e2cea4d73a4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559024047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3559024047
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1303233653
Short name T743
Test name
Test status
Simulation time 12627428490 ps
CPU time 19.23 seconds
Started Jul 20 05:38:56 PM PDT 24
Finished Jul 20 05:39:16 PM PDT 24
Peak memory 249504 kb
Host smart-9c26649a-c363-472e-abfc-84e5391828da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303233653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1303233653
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.480297647
Short name T619
Test name
Test status
Simulation time 458019974 ps
CPU time 2.72 seconds
Started Jul 20 05:38:57 PM PDT 24
Finished Jul 20 05:39:00 PM PDT 24
Peak memory 233116 kb
Host smart-a7efbf6e-a448-4508-b672-0ea3d8b10287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480297647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.480297647
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3165290771
Short name T791
Test name
Test status
Simulation time 520480594 ps
CPU time 3.92 seconds
Started Jul 20 05:39:04 PM PDT 24
Finished Jul 20 05:39:08 PM PDT 24
Peak memory 223356 kb
Host smart-b70a631d-d5b0-4ee4-ad71-5b7acbbdadff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3165290771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3165290771
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.862500011
Short name T154
Test name
Test status
Simulation time 514002745639 ps
CPU time 434.71 seconds
Started Jul 20 05:39:05 PM PDT 24
Finished Jul 20 05:46:21 PM PDT 24
Peak memory 257844 kb
Host smart-1de7d7a7-00bf-4105-be19-1d8180b2e2d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862500011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.862500011
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.46961442
Short name T875
Test name
Test status
Simulation time 342956189 ps
CPU time 6.89 seconds
Started Jul 20 05:38:54 PM PDT 24
Finished Jul 20 05:39:02 PM PDT 24
Peak memory 217028 kb
Host smart-224ad653-2d7c-47cc-97ca-0d29d6e570d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46961442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.46961442
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.808431590
Short name T851
Test name
Test status
Simulation time 2761266435 ps
CPU time 7.67 seconds
Started Jul 20 05:38:57 PM PDT 24
Finished Jul 20 05:39:05 PM PDT 24
Peak memory 216792 kb
Host smart-4168d656-ff74-4370-9216-c3db7cc79c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808431590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.808431590
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1250097834
Short name T908
Test name
Test status
Simulation time 53332867 ps
CPU time 2.11 seconds
Started Jul 20 05:38:52 PM PDT 24
Finished Jul 20 05:38:55 PM PDT 24
Peak memory 216636 kb
Host smart-ed7a0ecb-2ca7-4b26-b9eb-35f172e58263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250097834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1250097834
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2974560642
Short name T826
Test name
Test status
Simulation time 67982528 ps
CPU time 0.87 seconds
Started Jul 20 05:38:55 PM PDT 24
Finished Jul 20 05:38:57 PM PDT 24
Peak memory 206228 kb
Host smart-8dae92a2-8b1e-4376-9119-0e62d6105e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974560642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2974560642
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.528387749
Short name T214
Test name
Test status
Simulation time 37433479063 ps
CPU time 26.32 seconds
Started Jul 20 05:39:02 PM PDT 24
Finished Jul 20 05:39:30 PM PDT 24
Peak memory 233224 kb
Host smart-e85ba088-8f92-4927-bd7b-cfb689d40e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528387749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.528387749
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3545349434
Short name T684
Test name
Test status
Simulation time 14686217 ps
CPU time 0.73 seconds
Started Jul 20 05:39:05 PM PDT 24
Finished Jul 20 05:39:07 PM PDT 24
Peak memory 205108 kb
Host smart-1e19789b-6f14-4e96-be53-96e179739cfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545349434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3545349434
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2103209622
Short name T962
Test name
Test status
Simulation time 428280533 ps
CPU time 7.26 seconds
Started Jul 20 05:39:01 PM PDT 24
Finished Jul 20 05:39:09 PM PDT 24
Peak memory 233136 kb
Host smart-2eaea0be-3e4d-4ce2-89c2-2bb4bf6e3193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103209622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2103209622
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3750276217
Short name T594
Test name
Test status
Simulation time 21325744 ps
CPU time 0.82 seconds
Started Jul 20 05:39:01 PM PDT 24
Finished Jul 20 05:39:03 PM PDT 24
Peak memory 206876 kb
Host smart-338bb1c0-6c68-4cb7-93c6-83b734a995dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750276217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3750276217
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2149270914
Short name T655
Test name
Test status
Simulation time 2241706913 ps
CPU time 20.36 seconds
Started Jul 20 05:39:07 PM PDT 24
Finished Jul 20 05:39:28 PM PDT 24
Peak memory 241192 kb
Host smart-4450dd2d-f5bf-4255-85e6-856e61a29455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149270914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2149270914
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1722441282
Short name T664
Test name
Test status
Simulation time 24113670344 ps
CPU time 60.57 seconds
Started Jul 20 05:39:00 PM PDT 24
Finished Jul 20 05:40:02 PM PDT 24
Peak memory 249772 kb
Host smart-27a679e1-d24a-48b1-b56c-4ac4fe9f5af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722441282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1722441282
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3637688019
Short name T298
Test name
Test status
Simulation time 42161152752 ps
CPU time 169.6 seconds
Started Jul 20 05:39:00 PM PDT 24
Finished Jul 20 05:41:50 PM PDT 24
Peak memory 253960 kb
Host smart-e0c1b312-fce5-4ebb-93a8-2786539816d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637688019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3637688019
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.39263643
Short name T394
Test name
Test status
Simulation time 517861427 ps
CPU time 7.24 seconds
Started Jul 20 05:38:59 PM PDT 24
Finished Jul 20 05:39:07 PM PDT 24
Peak memory 233168 kb
Host smart-1419b6c5-b141-4492-80c0-1d5b3581c96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39263643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.39263643
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3384395007
Short name T309
Test name
Test status
Simulation time 47478789310 ps
CPU time 126.33 seconds
Started Jul 20 05:38:59 PM PDT 24
Finished Jul 20 05:41:06 PM PDT 24
Peak memory 263876 kb
Host smart-c92e1ac4-679e-4789-9aae-880d9c2218ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384395007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3384395007
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3804303768
Short name T201
Test name
Test status
Simulation time 490363838 ps
CPU time 6 seconds
Started Jul 20 05:39:01 PM PDT 24
Finished Jul 20 05:39:08 PM PDT 24
Peak memory 233156 kb
Host smart-cb44031c-f730-4fdf-ae11-e8c7712298a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804303768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3804303768
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1897882307
Short name T132
Test name
Test status
Simulation time 1203003110 ps
CPU time 6.81 seconds
Started Jul 20 05:39:02 PM PDT 24
Finished Jul 20 05:39:10 PM PDT 24
Peak memory 224900 kb
Host smart-727148d6-364a-4cd7-b7d9-2eff5ea74162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897882307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1897882307
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1152158215
Short name T737
Test name
Test status
Simulation time 26835382 ps
CPU time 1.03 seconds
Started Jul 20 05:39:03 PM PDT 24
Finished Jul 20 05:39:05 PM PDT 24
Peak memory 218380 kb
Host smart-9a682aaf-7acf-4ce6-812b-ffe2b0232e56
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152158215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1152158215
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1220256448
Short name T287
Test name
Test status
Simulation time 25608393547 ps
CPU time 20.31 seconds
Started Jul 20 05:39:02 PM PDT 24
Finished Jul 20 05:39:23 PM PDT 24
Peak memory 233276 kb
Host smart-a044c4d9-a679-44ca-b5c2-f4adbb9c642b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220256448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1220256448
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.864132506
Short name T666
Test name
Test status
Simulation time 33707388 ps
CPU time 2.52 seconds
Started Jul 20 05:39:07 PM PDT 24
Finished Jul 20 05:39:10 PM PDT 24
Peak memory 232856 kb
Host smart-bd81068c-50d6-4db5-9034-9638c9e5d9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864132506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.864132506
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3364599677
Short name T904
Test name
Test status
Simulation time 1102116432 ps
CPU time 10.89 seconds
Started Jul 20 05:39:01 PM PDT 24
Finished Jul 20 05:39:13 PM PDT 24
Peak memory 220872 kb
Host smart-338f371d-08d5-4fd9-81da-b5a3260db795
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3364599677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3364599677
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2223694695
Short name T872
Test name
Test status
Simulation time 42091340575 ps
CPU time 427.62 seconds
Started Jul 20 05:39:00 PM PDT 24
Finished Jul 20 05:46:08 PM PDT 24
Peak memory 265756 kb
Host smart-16e0f00a-ef59-4840-8b07-0c9d24bc4ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223694695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2223694695
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.767439627
Short name T321
Test name
Test status
Simulation time 6998599338 ps
CPU time 13.67 seconds
Started Jul 20 05:39:06 PM PDT 24
Finished Jul 20 05:39:21 PM PDT 24
Peak memory 217084 kb
Host smart-04f234ab-d97e-4413-985b-6ea8d6801ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767439627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.767439627
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2074033961
Short name T402
Test name
Test status
Simulation time 5410339287 ps
CPU time 4.68 seconds
Started Jul 20 05:39:05 PM PDT 24
Finished Jul 20 05:39:10 PM PDT 24
Peak memory 216824 kb
Host smart-71d5bee4-be2b-480a-982c-fd1b2d00d160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074033961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2074033961
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3001920022
Short name T879
Test name
Test status
Simulation time 517522033 ps
CPU time 3.84 seconds
Started Jul 20 05:39:02 PM PDT 24
Finished Jul 20 05:39:06 PM PDT 24
Peak memory 216632 kb
Host smart-5c31212a-5131-421a-83a6-77702236638c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001920022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3001920022
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1657072932
Short name T1023
Test name
Test status
Simulation time 27561109 ps
CPU time 0.68 seconds
Started Jul 20 05:39:01 PM PDT 24
Finished Jul 20 05:39:02 PM PDT 24
Peak memory 205940 kb
Host smart-af900d76-f2c1-4003-ba4f-28f147355adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657072932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1657072932
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1899349400
Short name T383
Test name
Test status
Simulation time 59179945 ps
CPU time 2.15 seconds
Started Jul 20 05:39:07 PM PDT 24
Finished Jul 20 05:39:09 PM PDT 24
Peak memory 224036 kb
Host smart-2dcaecd9-0171-478d-8e7d-49f580dbdbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899349400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1899349400
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2002311433
Short name T609
Test name
Test status
Simulation time 71281188 ps
CPU time 0.72 seconds
Started Jul 20 05:39:14 PM PDT 24
Finished Jul 20 05:39:15 PM PDT 24
Peak memory 205676 kb
Host smart-e855de8a-1a22-4b27-8881-79e64e1052c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002311433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2002311433
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4078482504
Short name T627
Test name
Test status
Simulation time 1054774731 ps
CPU time 8.42 seconds
Started Jul 20 05:39:04 PM PDT 24
Finished Jul 20 05:39:13 PM PDT 24
Peak memory 224912 kb
Host smart-a0470325-26cf-4c4c-8551-0cf974f28986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078482504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4078482504
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3517548657
Short name T480
Test name
Test status
Simulation time 28104027 ps
CPU time 0.79 seconds
Started Jul 20 05:39:01 PM PDT 24
Finished Jul 20 05:39:03 PM PDT 24
Peak memory 207188 kb
Host smart-a40f8172-7358-4955-8d75-4165b2b385fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517548657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3517548657
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2168584390
Short name T678
Test name
Test status
Simulation time 23090735731 ps
CPU time 102 seconds
Started Jul 20 05:39:11 PM PDT 24
Finished Jul 20 05:40:54 PM PDT 24
Peak memory 254864 kb
Host smart-f7ff346e-c8c5-4024-9fb3-cc01e4ed4c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168584390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2168584390
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1691451929
Short name T701
Test name
Test status
Simulation time 8556267091 ps
CPU time 72.42 seconds
Started Jul 20 05:39:08 PM PDT 24
Finished Jul 20 05:40:21 PM PDT 24
Peak memory 238568 kb
Host smart-dbcb2b88-1e7a-4e48-9c47-aee26f74629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691451929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1691451929
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1069069288
Short name T166
Test name
Test status
Simulation time 158067755376 ps
CPU time 175.6 seconds
Started Jul 20 05:39:14 PM PDT 24
Finished Jul 20 05:42:10 PM PDT 24
Peak memory 257852 kb
Host smart-1d37a44a-bc41-435c-b96d-1c3f5e7bedd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069069288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1069069288
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1777910377
Short name T315
Test name
Test status
Simulation time 549575979 ps
CPU time 13.08 seconds
Started Jul 20 05:39:05 PM PDT 24
Finished Jul 20 05:39:19 PM PDT 24
Peak memory 241340 kb
Host smart-85bedd62-e57d-4e53-b885-2922c254be07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777910377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1777910377
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3292179937
Short name T568
Test name
Test status
Simulation time 22992869927 ps
CPU time 184.58 seconds
Started Jul 20 05:39:08 PM PDT 24
Finished Jul 20 05:42:13 PM PDT 24
Peak memory 267820 kb
Host smart-4d1bede5-6a25-469e-8afb-556421df7187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292179937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3292179937
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3456921564
Short name T935
Test name
Test status
Simulation time 45839628 ps
CPU time 2.2 seconds
Started Jul 20 05:39:08 PM PDT 24
Finished Jul 20 05:39:11 PM PDT 24
Peak memory 224256 kb
Host smart-83ae72b0-a8ab-42ea-8ca4-ab312e02c9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456921564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3456921564
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1059160551
Short name T642
Test name
Test status
Simulation time 90649856 ps
CPU time 2.52 seconds
Started Jul 20 05:39:03 PM PDT 24
Finished Jul 20 05:39:06 PM PDT 24
Peak memory 224812 kb
Host smart-58b54eee-db0f-4ad2-9ef6-11e57045a7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059160551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1059160551
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2284369274
Short name T475
Test name
Test status
Simulation time 116112312 ps
CPU time 1.05 seconds
Started Jul 20 05:39:08 PM PDT 24
Finished Jul 20 05:39:10 PM PDT 24
Peak memory 217136 kb
Host smart-1f45966b-c863-4b95-b26c-055fb0151cad
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284369274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2284369274
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3046048056
Short name T297
Test name
Test status
Simulation time 21802187596 ps
CPU time 17.32 seconds
Started Jul 20 05:39:03 PM PDT 24
Finished Jul 20 05:39:21 PM PDT 24
Peak memory 233276 kb
Host smart-dd55f9c1-5b9e-4575-8499-be15500e20bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046048056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3046048056
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1165648866
Short name T618
Test name
Test status
Simulation time 12879628478 ps
CPU time 17.28 seconds
Started Jul 20 05:39:02 PM PDT 24
Finished Jul 20 05:39:20 PM PDT 24
Peak memory 225012 kb
Host smart-0108866e-8f30-4b15-b121-e56c7d611d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165648866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1165648866
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.158227317
Short name T49
Test name
Test status
Simulation time 4405635562 ps
CPU time 10.65 seconds
Started Jul 20 05:39:10 PM PDT 24
Finished Jul 20 05:39:22 PM PDT 24
Peak memory 222652 kb
Host smart-c62c2ebb-5082-4186-b91d-928ac34549b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=158227317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.158227317
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.969115984
Short name T232
Test name
Test status
Simulation time 91618013722 ps
CPU time 451.29 seconds
Started Jul 20 05:39:10 PM PDT 24
Finished Jul 20 05:46:42 PM PDT 24
Peak memory 257636 kb
Host smart-53cf0ba9-8988-425c-8087-aedf894807fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969115984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.969115984
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4272897400
Short name T854
Test name
Test status
Simulation time 6592927271 ps
CPU time 9.7 seconds
Started Jul 20 05:39:05 PM PDT 24
Finished Jul 20 05:39:16 PM PDT 24
Peak memory 218124 kb
Host smart-1527c8aa-4f2f-4b63-944a-d9c4d14423a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272897400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4272897400
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3546102009
Short name T967
Test name
Test status
Simulation time 2699953899 ps
CPU time 4.98 seconds
Started Jul 20 05:39:04 PM PDT 24
Finished Jul 20 05:39:09 PM PDT 24
Peak memory 216776 kb
Host smart-7c0b9d55-cb85-4a2a-944c-f8173175c872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546102009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3546102009
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1865159855
Short name T983
Test name
Test status
Simulation time 193328041 ps
CPU time 1.75 seconds
Started Jul 20 05:39:04 PM PDT 24
Finished Jul 20 05:39:06 PM PDT 24
Peak memory 216608 kb
Host smart-f45a7203-7bc2-4426-a28b-1e9a1ab107b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865159855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1865159855
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.542031793
Short name T23
Test name
Test status
Simulation time 44372041 ps
CPU time 0.91 seconds
Started Jul 20 05:39:08 PM PDT 24
Finished Jul 20 05:39:10 PM PDT 24
Peak memory 206260 kb
Host smart-d8fdee61-cb1e-4c05-b1c8-63d8416228ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542031793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.542031793
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.866969214
Short name T799
Test name
Test status
Simulation time 146078308 ps
CPU time 3.28 seconds
Started Jul 20 05:39:03 PM PDT 24
Finished Jul 20 05:39:07 PM PDT 24
Peak memory 233156 kb
Host smart-e674d562-581e-4049-bd1a-6e40c3d3657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866969214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.866969214
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1684690699
Short name T497
Test name
Test status
Simulation time 35548721 ps
CPU time 0.72 seconds
Started Jul 20 05:39:12 PM PDT 24
Finished Jul 20 05:39:14 PM PDT 24
Peak memory 206084 kb
Host smart-2d9e8bf2-4b51-4fb5-a302-a800d848f002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684690699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1684690699
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2661787856
Short name T842
Test name
Test status
Simulation time 49469829 ps
CPU time 2.54 seconds
Started Jul 20 05:39:11 PM PDT 24
Finished Jul 20 05:39:14 PM PDT 24
Peak memory 224928 kb
Host smart-e438b7f3-ed79-4e7b-9619-b19901c3c55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661787856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2661787856
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2831383903
Short name T381
Test name
Test status
Simulation time 36962788 ps
CPU time 0.8 seconds
Started Jul 20 05:39:10 PM PDT 24
Finished Jul 20 05:39:12 PM PDT 24
Peak memory 206856 kb
Host smart-0bbfd28c-2702-43a3-adf4-b3dd22c0c41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831383903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2831383903
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1432187887
Short name T245
Test name
Test status
Simulation time 21794538233 ps
CPU time 74.25 seconds
Started Jul 20 05:39:14 PM PDT 24
Finished Jul 20 05:40:29 PM PDT 24
Peak memory 272392 kb
Host smart-f41b0abc-232b-4d8a-8ff2-4c02cf3f3d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432187887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1432187887
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.624547055
Short name T917
Test name
Test status
Simulation time 91010515355 ps
CPU time 210.19 seconds
Started Jul 20 05:39:10 PM PDT 24
Finished Jul 20 05:42:41 PM PDT 24
Peak memory 257320 kb
Host smart-ee284f26-e8b7-40ab-af97-3b3758d3f8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624547055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.624547055
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1362820303
Short name T1012
Test name
Test status
Simulation time 89730819 ps
CPU time 2.69 seconds
Started Jul 20 05:39:10 PM PDT 24
Finished Jul 20 05:39:14 PM PDT 24
Peak memory 233164 kb
Host smart-6dca78ae-167d-45f9-b94e-6063c103b42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362820303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1362820303
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.4148870682
Short name T763
Test name
Test status
Simulation time 8730354333 ps
CPU time 54.87 seconds
Started Jul 20 05:39:09 PM PDT 24
Finished Jul 20 05:40:05 PM PDT 24
Peak memory 254464 kb
Host smart-238471e7-c8d3-4eb1-af03-a67b50dd35af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148870682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.4148870682
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.513772959
Short name T580
Test name
Test status
Simulation time 583802571 ps
CPU time 3.63 seconds
Started Jul 20 05:39:12 PM PDT 24
Finished Jul 20 05:39:16 PM PDT 24
Peak memory 233164 kb
Host smart-18bc992d-9673-400f-bc76-2f418353fdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513772959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.513772959
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.126631801
Short name T512
Test name
Test status
Simulation time 25428646425 ps
CPU time 83.83 seconds
Started Jul 20 05:39:14 PM PDT 24
Finished Jul 20 05:40:39 PM PDT 24
Peak memory 233264 kb
Host smart-14f307ed-6713-408b-ab3b-2870f437734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126631801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.126631801
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1958594573
Short name T495
Test name
Test status
Simulation time 17844307 ps
CPU time 0.98 seconds
Started Jul 20 05:39:16 PM PDT 24
Finished Jul 20 05:39:17 PM PDT 24
Peak memory 218388 kb
Host smart-d381984b-ab15-4029-a6c8-e74e6c6c0442
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958594573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1958594573
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1836926881
Short name T954
Test name
Test status
Simulation time 12589425934 ps
CPU time 9.21 seconds
Started Jul 20 05:39:12 PM PDT 24
Finished Jul 20 05:39:22 PM PDT 24
Peak memory 241048 kb
Host smart-d5527925-6246-4d60-8dc6-feb88d28c237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836926881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1836926881
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1778195463
Short name T164
Test name
Test status
Simulation time 235649327 ps
CPU time 3.68 seconds
Started Jul 20 05:39:10 PM PDT 24
Finished Jul 20 05:39:14 PM PDT 24
Peak memory 233120 kb
Host smart-04f6aae8-9423-4821-97f9-4b79b3ef45dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778195463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1778195463
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1725289398
Short name T557
Test name
Test status
Simulation time 739631485 ps
CPU time 3.74 seconds
Started Jul 20 05:39:11 PM PDT 24
Finished Jul 20 05:39:15 PM PDT 24
Peak memory 222952 kb
Host smart-b0ec8cda-fca5-4098-9087-016df9072bc4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1725289398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1725289398
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.840212889
Short name T377
Test name
Test status
Simulation time 626573604 ps
CPU time 7.15 seconds
Started Jul 20 05:39:10 PM PDT 24
Finished Jul 20 05:39:18 PM PDT 24
Peak memory 216748 kb
Host smart-5cb6674e-8912-4b19-a242-a524d0fc7a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840212889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.840212889
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.199028220
Short name T33
Test name
Test status
Simulation time 38224869776 ps
CPU time 14.29 seconds
Started Jul 20 05:39:12 PM PDT 24
Finished Jul 20 05:39:27 PM PDT 24
Peak memory 216792 kb
Host smart-57ea720a-6c50-4dec-b2c6-c10c38a8b904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199028220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.199028220
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2942107023
Short name T909
Test name
Test status
Simulation time 18222211 ps
CPU time 1.21 seconds
Started Jul 20 05:39:14 PM PDT 24
Finished Jul 20 05:39:16 PM PDT 24
Peak memory 208432 kb
Host smart-82f5c2c9-b41c-4662-8d6b-fa7309b9380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942107023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2942107023
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1311403208
Short name T973
Test name
Test status
Simulation time 31899479 ps
CPU time 0.88 seconds
Started Jul 20 05:39:11 PM PDT 24
Finished Jul 20 05:39:12 PM PDT 24
Peak memory 206252 kb
Host smart-27f8b3c4-9f03-495c-9649-3e581602479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311403208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1311403208
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.780058686
Short name T266
Test name
Test status
Simulation time 11380655984 ps
CPU time 17.01 seconds
Started Jul 20 05:39:14 PM PDT 24
Finished Jul 20 05:39:32 PM PDT 24
Peak memory 225032 kb
Host smart-ad17fd2c-7d44-47bb-a109-1b1408337c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780058686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.780058686
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1637283439
Short name T469
Test name
Test status
Simulation time 14589333 ps
CPU time 0.71 seconds
Started Jul 20 05:39:18 PM PDT 24
Finished Jul 20 05:39:19 PM PDT 24
Peak memory 205748 kb
Host smart-7bee77d9-6da4-4401-bb33-44fe9af9d573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637283439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1637283439
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2376089785
Short name T182
Test name
Test status
Simulation time 583163338 ps
CPU time 4.19 seconds
Started Jul 20 05:39:25 PM PDT 24
Finished Jul 20 05:39:30 PM PDT 24
Peak memory 233084 kb
Host smart-4923c299-7a83-498f-8a79-a6f2b88aef65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376089785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2376089785
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1585357215
Short name T389
Test name
Test status
Simulation time 79494995 ps
CPU time 0.77 seconds
Started Jul 20 05:39:12 PM PDT 24
Finished Jul 20 05:39:13 PM PDT 24
Peak memory 206872 kb
Host smart-5ab375f8-0754-466a-a0e8-36cea11bd823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585357215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1585357215
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.708739303
Short name T528
Test name
Test status
Simulation time 54150052029 ps
CPU time 55.8 seconds
Started Jul 20 05:39:21 PM PDT 24
Finished Jul 20 05:40:18 PM PDT 24
Peak memory 249636 kb
Host smart-f01de6b9-a091-4a6d-ba8d-8d5d4b8788e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708739303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.708739303
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3317045509
Short name T255
Test name
Test status
Simulation time 565922890 ps
CPU time 12 seconds
Started Jul 20 05:39:20 PM PDT 24
Finished Jul 20 05:39:33 PM PDT 24
Peak memory 235876 kb
Host smart-32b3086d-6745-4447-8df0-727fe5d75ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317045509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3317045509
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1046960628
Short name T1028
Test name
Test status
Simulation time 2435084582 ps
CPU time 34.74 seconds
Started Jul 20 05:39:19 PM PDT 24
Finished Jul 20 05:39:55 PM PDT 24
Peak memory 233044 kb
Host smart-8166706e-55d7-406d-b39d-ad610c2430ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046960628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1046960628
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.771552413
Short name T317
Test name
Test status
Simulation time 532143519 ps
CPU time 14.53 seconds
Started Jul 20 05:39:20 PM PDT 24
Finished Jul 20 05:39:35 PM PDT 24
Peak memory 224936 kb
Host smart-a4368ad7-0b08-4a45-b564-dd15d7284c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771552413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.771552413
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1227393773
Short name T961
Test name
Test status
Simulation time 14715514193 ps
CPU time 113.29 seconds
Started Jul 20 05:39:19 PM PDT 24
Finished Jul 20 05:41:13 PM PDT 24
Peak memory 256284 kb
Host smart-18d2eb50-054d-4038-8546-bd347070b928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227393773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1227393773
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.933886144
Short name T924
Test name
Test status
Simulation time 1941049949 ps
CPU time 7.3 seconds
Started Jul 20 05:39:20 PM PDT 24
Finished Jul 20 05:39:29 PM PDT 24
Peak memory 233088 kb
Host smart-75c9caaa-b5d8-4e10-b2b2-43f55b914b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933886144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.933886144
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2592949237
Short name T663
Test name
Test status
Simulation time 1835707901 ps
CPU time 20 seconds
Started Jul 20 05:39:23 PM PDT 24
Finished Jul 20 05:39:44 PM PDT 24
Peak memory 241184 kb
Host smart-401db473-5248-424a-ab4e-0df90b940bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592949237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2592949237
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1942864563
Short name T818
Test name
Test status
Simulation time 33104948 ps
CPU time 1.09 seconds
Started Jul 20 05:39:18 PM PDT 24
Finished Jul 20 05:39:20 PM PDT 24
Peak memory 217148 kb
Host smart-5fea626c-00d0-40b8-8276-3b3054744a2d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942864563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1942864563
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3974417593
Short name T828
Test name
Test status
Simulation time 10942576489 ps
CPU time 13.32 seconds
Started Jul 20 05:39:22 PM PDT 24
Finished Jul 20 05:39:36 PM PDT 24
Peak memory 241152 kb
Host smart-4e5d9f3c-7075-43a6-9b1d-bea44b29d695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974417593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3974417593
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.968922937
Short name T706
Test name
Test status
Simulation time 131757981 ps
CPU time 2.36 seconds
Started Jul 20 05:39:22 PM PDT 24
Finished Jul 20 05:39:26 PM PDT 24
Peak memory 232924 kb
Host smart-67b3406d-b285-4cbf-b22e-365e28e13ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968922937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.968922937
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1228884598
Short name T688
Test name
Test status
Simulation time 1184796391 ps
CPU time 13.08 seconds
Started Jul 20 05:39:25 PM PDT 24
Finished Jul 20 05:39:39 PM PDT 24
Peak memory 220724 kb
Host smart-f61ddd0a-b94c-467c-98ab-44244b0a14bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1228884598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1228884598
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2668744637
Short name T41
Test name
Test status
Simulation time 65973287319 ps
CPU time 469.45 seconds
Started Jul 20 05:39:23 PM PDT 24
Finished Jul 20 05:47:13 PM PDT 24
Peak memory 298876 kb
Host smart-e9900550-1c61-40a4-ba98-7aa79a10ff4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668744637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2668744637
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3075118016
Short name T718
Test name
Test status
Simulation time 14290421201 ps
CPU time 24.51 seconds
Started Jul 20 05:39:19 PM PDT 24
Finished Jul 20 05:39:45 PM PDT 24
Peak memory 216780 kb
Host smart-e2fbc573-4c7d-458d-b91c-d3a07bdfbdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075118016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3075118016
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1841039335
Short name T539
Test name
Test status
Simulation time 23871038837 ps
CPU time 12.63 seconds
Started Jul 20 05:39:18 PM PDT 24
Finished Jul 20 05:39:31 PM PDT 24
Peak memory 216808 kb
Host smart-f2c15671-8de1-4f06-b796-8dcd3f7f48ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841039335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1841039335
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2975628329
Short name T720
Test name
Test status
Simulation time 64304764 ps
CPU time 0.99 seconds
Started Jul 20 05:39:22 PM PDT 24
Finished Jul 20 05:39:24 PM PDT 24
Peak memory 207424 kb
Host smart-50527c81-5fed-4de5-bc53-997bdd583d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975628329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2975628329
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3239063813
Short name T397
Test name
Test status
Simulation time 153402135 ps
CPU time 0.89 seconds
Started Jul 20 05:39:19 PM PDT 24
Finished Jul 20 05:39:21 PM PDT 24
Peak memory 206260 kb
Host smart-43001007-4f73-4d88-98e0-88f995911ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239063813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3239063813
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.537258198
Short name T263
Test name
Test status
Simulation time 17944902955 ps
CPU time 14.09 seconds
Started Jul 20 05:39:23 PM PDT 24
Finished Jul 20 05:39:38 PM PDT 24
Peak memory 233216 kb
Host smart-094e41f2-82aa-49da-9db5-aa8dab307c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537258198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.537258198
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1704015865
Short name T885
Test name
Test status
Simulation time 10486965 ps
CPU time 0.7 seconds
Started Jul 20 05:37:39 PM PDT 24
Finished Jul 20 05:37:40 PM PDT 24
Peak memory 205748 kb
Host smart-92274ad8-53eb-413f-b210-e19445dc0a08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704015865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
704015865
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2287337009
Short name T1001
Test name
Test status
Simulation time 149495912 ps
CPU time 4.84 seconds
Started Jul 20 05:37:39 PM PDT 24
Finished Jul 20 05:37:45 PM PDT 24
Peak memory 224888 kb
Host smart-5b8f969a-a89f-435e-afea-15624ea46a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287337009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2287337009
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3271416161
Short name T621
Test name
Test status
Simulation time 35868082 ps
CPU time 0.79 seconds
Started Jul 20 05:37:32 PM PDT 24
Finished Jul 20 05:37:33 PM PDT 24
Peak memory 206864 kb
Host smart-eef93740-4c68-4f2e-9894-087163969fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271416161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3271416161
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1202393675
Short name T590
Test name
Test status
Simulation time 207520130405 ps
CPU time 303.02 seconds
Started Jul 20 05:37:41 PM PDT 24
Finished Jul 20 05:42:45 PM PDT 24
Peak memory 263300 kb
Host smart-c7128316-6a06-4561-b1ee-2f6f03e7e041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202393675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1202393675
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2490410847
Short name T966
Test name
Test status
Simulation time 953903670 ps
CPU time 7.39 seconds
Started Jul 20 05:37:41 PM PDT 24
Finished Jul 20 05:37:49 PM PDT 24
Peak memory 217856 kb
Host smart-19a6478f-d562-46c1-96b1-f1876bc52b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490410847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2490410847
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1795250817
Short name T47
Test name
Test status
Simulation time 5625819570 ps
CPU time 43.82 seconds
Started Jul 20 05:37:39 PM PDT 24
Finished Jul 20 05:38:23 PM PDT 24
Peak memory 241456 kb
Host smart-39fe343b-231f-43a8-87a8-807d901083a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795250817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1795250817
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4142038507
Short name T1017
Test name
Test status
Simulation time 719306926 ps
CPU time 14.64 seconds
Started Jul 20 05:37:39 PM PDT 24
Finished Jul 20 05:37:55 PM PDT 24
Peak memory 224928 kb
Host smart-773e0a67-da1c-4d6f-b230-effce78d53b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142038507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4142038507
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3421759731
Short name T794
Test name
Test status
Simulation time 1262612313 ps
CPU time 23.26 seconds
Started Jul 20 05:37:40 PM PDT 24
Finished Jul 20 05:38:04 PM PDT 24
Peak memory 240608 kb
Host smart-058108a1-e6d5-4970-a242-f3f90cc048a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421759731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3421759731
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.4120822144
Short name T774
Test name
Test status
Simulation time 87687845 ps
CPU time 3.5 seconds
Started Jul 20 05:37:38 PM PDT 24
Finished Jul 20 05:37:42 PM PDT 24
Peak memory 224960 kb
Host smart-4c0d8194-ccc8-4c08-8cb9-4982351fb2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120822144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4120822144
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2984304235
Short name T628
Test name
Test status
Simulation time 92686537784 ps
CPU time 58.82 seconds
Started Jul 20 05:37:39 PM PDT 24
Finished Jul 20 05:38:39 PM PDT 24
Peak memory 233224 kb
Host smart-43b32e7b-2e3c-4048-9e3f-ff521b2368e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984304235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2984304235
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2571309545
Short name T680
Test name
Test status
Simulation time 113309300 ps
CPU time 1.04 seconds
Started Jul 20 05:37:31 PM PDT 24
Finished Jul 20 05:37:33 PM PDT 24
Peak memory 218456 kb
Host smart-d32c88d3-8194-4b23-8028-031b5a595ff9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571309545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2571309545
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2417936400
Short name T230
Test name
Test status
Simulation time 556816472 ps
CPU time 3.14 seconds
Started Jul 20 05:37:30 PM PDT 24
Finished Jul 20 05:37:34 PM PDT 24
Peak memory 224916 kb
Host smart-d0dbc088-86a5-425b-bfc1-8b47d4229f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417936400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2417936400
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3528317184
Short name T284
Test name
Test status
Simulation time 861649424 ps
CPU time 2.65 seconds
Started Jul 20 05:37:31 PM PDT 24
Finished Jul 20 05:37:35 PM PDT 24
Peak memory 224932 kb
Host smart-61328b25-1f26-48ed-a0e7-f0d162cbc099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528317184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3528317184
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1425904804
Short name T629
Test name
Test status
Simulation time 9710178555 ps
CPU time 5.31 seconds
Started Jul 20 05:37:41 PM PDT 24
Finished Jul 20 05:37:47 PM PDT 24
Peak memory 219244 kb
Host smart-885e517e-5062-4631-95ea-8a1d3c7491c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1425904804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1425904804
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.8120178
Short name T78
Test name
Test status
Simulation time 91158603 ps
CPU time 1.09 seconds
Started Jul 20 05:37:38 PM PDT 24
Finished Jul 20 05:37:40 PM PDT 24
Peak memory 236180 kb
Host smart-1abaaee8-fcc5-44b7-8106-89e2cf094eb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8120178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.8120178
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2162359195
Short name T15
Test name
Test status
Simulation time 276053683 ps
CPU time 5.47 seconds
Started Jul 20 05:37:41 PM PDT 24
Finished Jul 20 05:37:47 PM PDT 24
Peak memory 233472 kb
Host smart-698e02b2-e1e8-4164-8bb9-637f9b1957c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162359195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2162359195
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.534928222
Short name T348
Test name
Test status
Simulation time 18748845 ps
CPU time 0.76 seconds
Started Jul 20 05:37:32 PM PDT 24
Finished Jul 20 05:37:34 PM PDT 24
Peak memory 205996 kb
Host smart-5d7035ab-a282-4c5a-8d71-14a38d0dc9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534928222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.534928222
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.38330057
Short name T649
Test name
Test status
Simulation time 4320442508 ps
CPU time 12.86 seconds
Started Jul 20 05:37:33 PM PDT 24
Finished Jul 20 05:37:47 PM PDT 24
Peak memory 216820 kb
Host smart-0f9aa322-3303-457d-8420-eb8ed512c3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38330057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.38330057
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1726308265
Short name T424
Test name
Test status
Simulation time 23350517 ps
CPU time 0.71 seconds
Started Jul 20 05:37:33 PM PDT 24
Finished Jul 20 05:37:34 PM PDT 24
Peak memory 205932 kb
Host smart-4d24ee95-393a-4c81-9999-893df8125375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726308265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1726308265
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3520268719
Short name T866
Test name
Test status
Simulation time 111388849 ps
CPU time 0.85 seconds
Started Jul 20 05:37:31 PM PDT 24
Finished Jul 20 05:37:33 PM PDT 24
Peak memory 206320 kb
Host smart-f499e414-a155-42d2-95e1-deb407a7145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520268719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3520268719
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.48844814
Short name T68
Test name
Test status
Simulation time 299581678 ps
CPU time 3.6 seconds
Started Jul 20 05:37:40 PM PDT 24
Finished Jul 20 05:37:44 PM PDT 24
Peak memory 224992 kb
Host smart-4d1de932-b543-4a13-81be-8bb47f501a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48844814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.48844814
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3660508567
Short name T452
Test name
Test status
Simulation time 11868257 ps
CPU time 0.72 seconds
Started Jul 20 05:39:21 PM PDT 24
Finished Jul 20 05:39:23 PM PDT 24
Peak memory 205748 kb
Host smart-a1f7e003-ac41-4e94-a78c-492df88c8361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660508567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3660508567
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3075248302
Short name T911
Test name
Test status
Simulation time 104591584 ps
CPU time 2.74 seconds
Started Jul 20 05:39:21 PM PDT 24
Finished Jul 20 05:39:26 PM PDT 24
Peak memory 233032 kb
Host smart-65be161b-3e9a-4f8d-9ade-a1435bc3bdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075248302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3075248302
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.131384267
Short name T620
Test name
Test status
Simulation time 15586951 ps
CPU time 0.83 seconds
Started Jul 20 05:39:20 PM PDT 24
Finished Jul 20 05:39:22 PM PDT 24
Peak memory 205876 kb
Host smart-57606bfc-051a-421f-b912-24fc34ebc491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131384267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.131384267
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2440667442
Short name T204
Test name
Test status
Simulation time 63979951318 ps
CPU time 234.06 seconds
Started Jul 20 05:39:21 PM PDT 24
Finished Jul 20 05:43:16 PM PDT 24
Peak memory 266072 kb
Host smart-b91ac0c1-0374-4b2c-ad23-f647ed76ef0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440667442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2440667442
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.439919710
Short name T231
Test name
Test status
Simulation time 5919917289 ps
CPU time 80 seconds
Started Jul 20 05:39:20 PM PDT 24
Finished Jul 20 05:40:41 PM PDT 24
Peak memory 250064 kb
Host smart-1c0b2f0f-cea1-4e0e-8390-f107ddb1aabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439919710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.439919710
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3069816680
Short name T235
Test name
Test status
Simulation time 78567068648 ps
CPU time 145.42 seconds
Started Jul 20 05:39:19 PM PDT 24
Finished Jul 20 05:41:45 PM PDT 24
Peak memory 254364 kb
Host smart-214377b2-a82e-4a7a-813f-2e30bd13d396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069816680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3069816680
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3832027033
Short name T601
Test name
Test status
Simulation time 296390588 ps
CPU time 4.63 seconds
Started Jul 20 05:39:19 PM PDT 24
Finished Jul 20 05:39:25 PM PDT 24
Peak memory 232852 kb
Host smart-5cd836f0-c46c-40aa-bbfe-0194eddd5a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832027033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3832027033
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.788096867
Short name T1005
Test name
Test status
Simulation time 356757508 ps
CPU time 8.35 seconds
Started Jul 20 05:39:19 PM PDT 24
Finished Jul 20 05:39:28 PM PDT 24
Peak memory 252460 kb
Host smart-466eee0e-0886-4684-9ba0-e68b1c2a6789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788096867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.788096867
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3657887833
Short name T840
Test name
Test status
Simulation time 581478951 ps
CPU time 3.39 seconds
Started Jul 20 05:39:22 PM PDT 24
Finished Jul 20 05:39:26 PM PDT 24
Peak memory 233060 kb
Host smart-b625b013-1730-4f2c-bc22-475a8e225241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657887833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3657887833
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2861844450
Short name T382
Test name
Test status
Simulation time 1173597336 ps
CPU time 3.06 seconds
Started Jul 20 05:39:20 PM PDT 24
Finished Jul 20 05:39:24 PM PDT 24
Peak memory 233144 kb
Host smart-41868d4d-5cfb-4dd6-98bc-b6ef6c949f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861844450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2861844450
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4180174683
Short name T359
Test name
Test status
Simulation time 225649434 ps
CPU time 6.02 seconds
Started Jul 20 05:39:25 PM PDT 24
Finished Jul 20 05:39:31 PM PDT 24
Peak memory 220916 kb
Host smart-573638ce-2782-4883-90c3-ad2d77e9d720
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4180174683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4180174683
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2999244274
Short name T556
Test name
Test status
Simulation time 148856510601 ps
CPU time 333.74 seconds
Started Jul 20 05:39:21 PM PDT 24
Finished Jul 20 05:44:56 PM PDT 24
Peak memory 250932 kb
Host smart-6b726c87-f7d3-4d3e-9596-06d076e64919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999244274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2999244274
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2600920830
Short name T952
Test name
Test status
Simulation time 3437279466 ps
CPU time 9.45 seconds
Started Jul 20 05:39:25 PM PDT 24
Finished Jul 20 05:39:36 PM PDT 24
Peak memory 217112 kb
Host smart-3f5b3057-da9c-42cb-880b-fcb56e7bff80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600920830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2600920830
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4278934761
Short name T393
Test name
Test status
Simulation time 2279113628 ps
CPU time 3.37 seconds
Started Jul 20 05:39:20 PM PDT 24
Finished Jul 20 05:39:24 PM PDT 24
Peak memory 216804 kb
Host smart-3cd76488-4dad-41ff-929b-3a9c0bd2904a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278934761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4278934761
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.277986472
Short name T993
Test name
Test status
Simulation time 20450795 ps
CPU time 1 seconds
Started Jul 20 05:39:26 PM PDT 24
Finished Jul 20 05:39:28 PM PDT 24
Peak memory 207524 kb
Host smart-1a4e0774-ba5a-40d7-b226-7e467307a7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277986472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.277986472
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3721185456
Short name T713
Test name
Test status
Simulation time 28508204 ps
CPU time 0.69 seconds
Started Jul 20 05:39:20 PM PDT 24
Finished Jul 20 05:39:23 PM PDT 24
Peak memory 205880 kb
Host smart-29d10021-3ea5-4d3c-900c-45120697904a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721185456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3721185456
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3120096667
Short name T893
Test name
Test status
Simulation time 2809482637 ps
CPU time 10.56 seconds
Started Jul 20 05:39:19 PM PDT 24
Finished Jul 20 05:39:30 PM PDT 24
Peak memory 225064 kb
Host smart-c592d49c-7e3a-4e62-8e11-e1ebcc653af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120096667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3120096667
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3315740900
Short name T398
Test name
Test status
Simulation time 80050882 ps
CPU time 0.74 seconds
Started Jul 20 05:39:30 PM PDT 24
Finished Jul 20 05:39:31 PM PDT 24
Peak memory 205116 kb
Host smart-bcdc7732-1374-43de-92f7-3ac462e4109f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315740900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3315740900
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3186727035
Short name T745
Test name
Test status
Simulation time 1856069488 ps
CPU time 9.67 seconds
Started Jul 20 05:39:30 PM PDT 24
Finished Jul 20 05:39:41 PM PDT 24
Peak memory 224916 kb
Host smart-4dde2d87-17fc-4fa1-a436-7e2f39cae43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186727035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3186727035
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2440138606
Short name T69
Test name
Test status
Simulation time 20985438 ps
CPU time 0.83 seconds
Started Jul 20 05:39:23 PM PDT 24
Finished Jul 20 05:39:25 PM PDT 24
Peak memory 207184 kb
Host smart-d20629ed-a500-44d8-bb9c-c9d7a6397347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440138606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2440138606
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2320934307
Short name T565
Test name
Test status
Simulation time 100475223812 ps
CPU time 192.66 seconds
Started Jul 20 05:39:35 PM PDT 24
Finished Jul 20 05:42:48 PM PDT 24
Peak memory 262736 kb
Host smart-57920c75-aa94-44b7-91ff-724d191528a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320934307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2320934307
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1094575544
Short name T10
Test name
Test status
Simulation time 1212504074 ps
CPU time 4.01 seconds
Started Jul 20 05:39:30 PM PDT 24
Finished Jul 20 05:39:35 PM PDT 24
Peak memory 224964 kb
Host smart-503a871d-5ba0-4ad0-895a-b089ceade052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094575544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1094575544
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4062409367
Short name T308
Test name
Test status
Simulation time 54814290505 ps
CPU time 132.51 seconds
Started Jul 20 05:39:29 PM PDT 24
Finished Jul 20 05:41:42 PM PDT 24
Peak memory 263436 kb
Host smart-5980aac1-63d8-43bd-ad71-7fcb81f6180f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062409367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4062409367
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1551521229
Short name T697
Test name
Test status
Simulation time 111579268 ps
CPU time 2.63 seconds
Started Jul 20 05:39:30 PM PDT 24
Finished Jul 20 05:39:33 PM PDT 24
Peak memory 224932 kb
Host smart-bc3b0242-a76e-42e2-b782-0cd8bc47ffab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551521229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1551521229
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3437872120
Short name T654
Test name
Test status
Simulation time 16975169953 ps
CPU time 57.32 seconds
Started Jul 20 05:39:27 PM PDT 24
Finished Jul 20 05:40:24 PM PDT 24
Peak memory 239012 kb
Host smart-9fc49bdc-bcea-408d-b4f8-10a6a060f2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437872120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3437872120
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4041742248
Short name T258
Test name
Test status
Simulation time 1023578059 ps
CPU time 11.5 seconds
Started Jul 20 05:39:30 PM PDT 24
Finished Jul 20 05:39:43 PM PDT 24
Peak memory 232992 kb
Host smart-2b75ce4b-0768-4f53-af14-7b9f2b7d7c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041742248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4041742248
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1572210614
Short name T4
Test name
Test status
Simulation time 137092706359 ps
CPU time 60.06 seconds
Started Jul 20 05:39:35 PM PDT 24
Finished Jul 20 05:40:35 PM PDT 24
Peak memory 233144 kb
Host smart-23901789-9da8-41c1-8b16-cc7d28b06f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572210614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1572210614
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1463761443
Short name T545
Test name
Test status
Simulation time 5788574450 ps
CPU time 18.66 seconds
Started Jul 20 05:39:29 PM PDT 24
Finished Jul 20 05:39:48 PM PDT 24
Peak memory 233280 kb
Host smart-ee2690e1-52b0-409a-a54e-595d0190b56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463761443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1463761443
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3600115357
Short name T375
Test name
Test status
Simulation time 59850802 ps
CPU time 2.61 seconds
Started Jul 20 05:39:27 PM PDT 24
Finished Jul 20 05:39:30 PM PDT 24
Peak memory 232968 kb
Host smart-950c0695-ea40-4932-aea9-91bd24332bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600115357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3600115357
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.615147639
Short name T824
Test name
Test status
Simulation time 610082604 ps
CPU time 4.91 seconds
Started Jul 20 05:39:33 PM PDT 24
Finished Jul 20 05:39:39 PM PDT 24
Peak memory 220368 kb
Host smart-ca9bd553-a581-4a0b-87a3-ac2a7a220410
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=615147639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.615147639
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1027326758
Short name T157
Test name
Test status
Simulation time 8735465768 ps
CPU time 172.56 seconds
Started Jul 20 05:39:29 PM PDT 24
Finished Jul 20 05:42:23 PM PDT 24
Peak memory 262860 kb
Host smart-f64a6213-77e1-480e-aa8c-c5e6c6703788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027326758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1027326758
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1984734735
Short name T906
Test name
Test status
Simulation time 6119050686 ps
CPU time 32.96 seconds
Started Jul 20 05:39:33 PM PDT 24
Finished Jul 20 05:40:07 PM PDT 24
Peak memory 216824 kb
Host smart-2d9d8565-a1bc-4365-b936-fe894def2d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984734735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1984734735
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.4116112826
Short name T652
Test name
Test status
Simulation time 1660522859 ps
CPU time 2.67 seconds
Started Jul 20 05:39:21 PM PDT 24
Finished Jul 20 05:39:25 PM PDT 24
Peak memory 216632 kb
Host smart-cc6364e2-92a1-4e4a-b8a2-d57473287712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116112826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4116112826
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2677716935
Short name T585
Test name
Test status
Simulation time 382936057 ps
CPU time 2.07 seconds
Started Jul 20 05:39:28 PM PDT 24
Finished Jul 20 05:39:30 PM PDT 24
Peak memory 216620 kb
Host smart-87d662d7-5f76-43af-98bb-3fda27fe3088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677716935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2677716935
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2702539090
Short name T753
Test name
Test status
Simulation time 631965011 ps
CPU time 0.97 seconds
Started Jul 20 05:39:31 PM PDT 24
Finished Jul 20 05:39:33 PM PDT 24
Peak memory 207292 kb
Host smart-4ee52cd5-b013-4807-8e69-4f56037915f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702539090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2702539090
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.613554682
Short name T988
Test name
Test status
Simulation time 41037458022 ps
CPU time 26.8 seconds
Started Jul 20 05:39:26 PM PDT 24
Finished Jul 20 05:39:53 PM PDT 24
Peak memory 233300 kb
Host smart-c2303bd9-0eb4-4fde-b26a-35d5a89bb411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613554682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.613554682
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2189259953
Short name T349
Test name
Test status
Simulation time 44176419 ps
CPU time 0.7 seconds
Started Jul 20 05:39:50 PM PDT 24
Finished Jul 20 05:39:52 PM PDT 24
Peak memory 205168 kb
Host smart-3aece4ea-f123-4ac2-8b4e-17e303884d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189259953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2189259953
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2034043819
Short name T670
Test name
Test status
Simulation time 447003571 ps
CPU time 5.35 seconds
Started Jul 20 05:39:30 PM PDT 24
Finished Jul 20 05:39:36 PM PDT 24
Peak memory 224888 kb
Host smart-872ae892-967a-4dcb-b915-5076a0d4254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034043819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2034043819
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1598742368
Short name T835
Test name
Test status
Simulation time 18232725 ps
CPU time 0.76 seconds
Started Jul 20 05:39:29 PM PDT 24
Finished Jul 20 05:39:31 PM PDT 24
Peak memory 205840 kb
Host smart-0884cc08-2d27-4b08-8970-4bcb57909364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598742368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1598742368
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2746510531
Short name T209
Test name
Test status
Simulation time 212166752539 ps
CPU time 387.21 seconds
Started Jul 20 05:39:39 PM PDT 24
Finished Jul 20 05:46:07 PM PDT 24
Peak memory 255800 kb
Host smart-590adaa8-4b4c-4b7e-9040-b9d9519b964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746510531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2746510531
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3882324347
Short name T329
Test name
Test status
Simulation time 4673008915 ps
CPU time 26.5 seconds
Started Jul 20 05:39:38 PM PDT 24
Finished Jul 20 05:40:06 PM PDT 24
Peak memory 218144 kb
Host smart-04582bce-f614-4490-80a6-94bb082eb404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882324347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3882324347
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3279120871
Short name T946
Test name
Test status
Simulation time 4187567847 ps
CPU time 76.32 seconds
Started Jul 20 05:39:36 PM PDT 24
Finished Jul 20 05:40:53 PM PDT 24
Peak memory 249752 kb
Host smart-fc32d29c-e1aa-4f66-911b-d131e634af96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279120871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3279120871
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2609626263
Short name T770
Test name
Test status
Simulation time 1268843521 ps
CPU time 11.86 seconds
Started Jul 20 05:39:29 PM PDT 24
Finished Jul 20 05:39:41 PM PDT 24
Peak memory 224948 kb
Host smart-1059f873-c2a7-4abf-a87b-07f1760482c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609626263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2609626263
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.541535894
Short name T752
Test name
Test status
Simulation time 38595910 ps
CPU time 0.77 seconds
Started Jul 20 05:39:38 PM PDT 24
Finished Jul 20 05:39:40 PM PDT 24
Peak memory 216328 kb
Host smart-d31ee718-4fb0-453b-82eb-dbd848c990b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541535894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.541535894
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2635521977
Short name T889
Test name
Test status
Simulation time 2956837052 ps
CPU time 10.49 seconds
Started Jul 20 05:39:34 PM PDT 24
Finished Jul 20 05:39:45 PM PDT 24
Peak memory 224936 kb
Host smart-632a7e1d-a487-4d7d-a19d-30f800bf4526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635521977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2635521977
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3275079745
Short name T530
Test name
Test status
Simulation time 22332858147 ps
CPU time 99.77 seconds
Started Jul 20 05:39:29 PM PDT 24
Finished Jul 20 05:41:09 PM PDT 24
Peak memory 249168 kb
Host smart-38129a43-a78f-426c-893f-d88924f6f13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275079745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3275079745
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1752903994
Short name T974
Test name
Test status
Simulation time 10253193406 ps
CPU time 30.45 seconds
Started Jul 20 05:39:29 PM PDT 24
Finished Jul 20 05:40:01 PM PDT 24
Peak memory 225076 kb
Host smart-31f14533-fb1e-491c-8c0b-e178a5ce1af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752903994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1752903994
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2202788659
Short name T248
Test name
Test status
Simulation time 4425366273 ps
CPU time 15.28 seconds
Started Jul 20 05:39:36 PM PDT 24
Finished Jul 20 05:39:52 PM PDT 24
Peak memory 241300 kb
Host smart-fd1ba442-f231-46b6-8c50-9baaeac0e62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202788659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2202788659
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1570726148
Short name T901
Test name
Test status
Simulation time 66824281 ps
CPU time 3.49 seconds
Started Jul 20 05:39:39 PM PDT 24
Finished Jul 20 05:39:44 PM PDT 24
Peak memory 222980 kb
Host smart-61132650-8b7c-4acb-99d3-94d8797f9df7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1570726148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1570726148
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3270131778
Short name T929
Test name
Test status
Simulation time 150481674447 ps
CPU time 286.41 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:44:25 PM PDT 24
Peak memory 252864 kb
Host smart-6344a91d-1543-4553-af25-d96c8efeb5d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270131778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3270131778
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2045408785
Short name T324
Test name
Test status
Simulation time 1580139841 ps
CPU time 14.46 seconds
Started Jul 20 05:39:29 PM PDT 24
Finished Jul 20 05:39:44 PM PDT 24
Peak memory 216824 kb
Host smart-a9a4c6c1-950d-4e13-822c-d5375e79f4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045408785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2045408785
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3350806071
Short name T934
Test name
Test status
Simulation time 4271755635 ps
CPU time 14.26 seconds
Started Jul 20 05:39:30 PM PDT 24
Finished Jul 20 05:39:45 PM PDT 24
Peak memory 216672 kb
Host smart-66dd2166-1833-4152-a0fa-d218ece5f38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350806071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3350806071
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.123442663
Short name T421
Test name
Test status
Simulation time 75443266 ps
CPU time 1.46 seconds
Started Jul 20 05:39:27 PM PDT 24
Finished Jul 20 05:39:30 PM PDT 24
Peak memory 216700 kb
Host smart-f29a0c3c-4fc4-4215-9811-66742e7d0fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123442663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.123442663
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2415011321
Short name T813
Test name
Test status
Simulation time 58139856 ps
CPU time 0.7 seconds
Started Jul 20 05:39:31 PM PDT 24
Finished Jul 20 05:39:33 PM PDT 24
Peak memory 205916 kb
Host smart-a22f4f0f-89d8-4d5c-baf7-dbc8d3c5f824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415011321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2415011321
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1419727135
Short name T265
Test name
Test status
Simulation time 278343606 ps
CPU time 6.21 seconds
Started Jul 20 05:39:33 PM PDT 24
Finished Jul 20 05:39:39 PM PDT 24
Peak memory 224948 kb
Host smart-083cd727-d677-43a3-927c-5d94c76c0e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419727135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1419727135
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3115463684
Short name T979
Test name
Test status
Simulation time 13754793 ps
CPU time 0.69 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:39:39 PM PDT 24
Peak memory 205148 kb
Host smart-53791f27-d805-4c94-9437-d3f1c70e26ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115463684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3115463684
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2442697243
Short name T492
Test name
Test status
Simulation time 178919004 ps
CPU time 3.13 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:39:41 PM PDT 24
Peak memory 224860 kb
Host smart-acf1720a-2db8-4e6b-94b5-b2c2e35cdd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442697243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2442697243
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1389615501
Short name T366
Test name
Test status
Simulation time 26898180 ps
CPU time 0.77 seconds
Started Jul 20 05:39:52 PM PDT 24
Finished Jul 20 05:39:54 PM PDT 24
Peak memory 205632 kb
Host smart-8a275031-c03b-4a1b-8a9e-16d64ac68e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389615501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1389615501
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2418999029
Short name T196
Test name
Test status
Simulation time 6422099616 ps
CPU time 79.18 seconds
Started Jul 20 05:39:36 PM PDT 24
Finished Jul 20 05:40:56 PM PDT 24
Peak memory 260976 kb
Host smart-df4b1aa3-89c6-47ef-80fe-fb64115eda14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418999029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2418999029
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1746445998
Short name T639
Test name
Test status
Simulation time 3027620652 ps
CPU time 39.75 seconds
Started Jul 20 05:39:51 PM PDT 24
Finished Jul 20 05:40:32 PM PDT 24
Peak memory 249680 kb
Host smart-e5ab8252-39ea-45e5-a326-384d9758b9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746445998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1746445998
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1708481492
Short name T328
Test name
Test status
Simulation time 13472184368 ps
CPU time 6.56 seconds
Started Jul 20 05:39:36 PM PDT 24
Finished Jul 20 05:39:43 PM PDT 24
Peak memory 218168 kb
Host smart-f3262b29-d7d7-4a01-9e34-cd30c0bb9236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708481492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1708481492
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1337061338
Short name T319
Test name
Test status
Simulation time 2469681554 ps
CPU time 22.14 seconds
Started Jul 20 05:39:38 PM PDT 24
Finished Jul 20 05:40:01 PM PDT 24
Peak memory 235440 kb
Host smart-0cf42bd9-fb91-4d6b-95d9-a94de95c8fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337061338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1337061338
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1347609649
Short name T71
Test name
Test status
Simulation time 28994150733 ps
CPU time 138.56 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:41:57 PM PDT 24
Peak memory 252196 kb
Host smart-14a1bea5-ea49-4fd7-a0e6-7c8292308158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347609649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1347609649
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1583355647
Short name T39
Test name
Test status
Simulation time 204284166 ps
CPU time 4.85 seconds
Started Jul 20 05:39:38 PM PDT 24
Finished Jul 20 05:39:44 PM PDT 24
Peak memory 233124 kb
Host smart-224e3e44-57e9-4860-9ad1-5addf8bb51a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583355647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1583355647
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1247344691
Short name T998
Test name
Test status
Simulation time 935375324 ps
CPU time 15.19 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:39:54 PM PDT 24
Peak memory 241340 kb
Host smart-741cd10f-9c91-42dc-9793-47db1bbe5f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247344691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1247344691
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.4036359920
Short name T848
Test name
Test status
Simulation time 48269128096 ps
CPU time 37.56 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:40:15 PM PDT 24
Peak memory 249476 kb
Host smart-86eead86-cdc0-4224-bec5-d43432de6026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036359920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.4036359920
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.927188603
Short name T555
Test name
Test status
Simulation time 1274285254 ps
CPU time 8.09 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:39:46 PM PDT 24
Peak memory 233068 kb
Host smart-bbf0fe6b-8970-4c9f-b7b6-d0c9cc72935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927188603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.927188603
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.31057283
Short name T531
Test name
Test status
Simulation time 299627464 ps
CPU time 3.52 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:39:41 PM PDT 24
Peak memory 220784 kb
Host smart-317e1668-fd6a-4d6e-91e8-2ca3d5d89b1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=31057283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direc
t.31057283
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2407136293
Short name T850
Test name
Test status
Simulation time 2613318588 ps
CPU time 25.03 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:40:03 PM PDT 24
Peak memory 216824 kb
Host smart-4b6f1e4f-99aa-4990-afeb-9307af7d59b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407136293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2407136293
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.627795393
Short name T614
Test name
Test status
Simulation time 661516616 ps
CPU time 3.25 seconds
Started Jul 20 05:39:39 PM PDT 24
Finished Jul 20 05:39:43 PM PDT 24
Peak memory 216452 kb
Host smart-a4bcc385-bcac-4dd4-a331-94c157149cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627795393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.627795393
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1070852942
Short name T535
Test name
Test status
Simulation time 244445877 ps
CPU time 0.95 seconds
Started Jul 20 05:39:51 PM PDT 24
Finished Jul 20 05:39:53 PM PDT 24
Peak memory 207280 kb
Host smart-e509b2fd-fa1b-4643-adbd-b19d7826afc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070852942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1070852942
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3217405371
Short name T362
Test name
Test status
Simulation time 57088092 ps
CPU time 0.79 seconds
Started Jul 20 05:39:38 PM PDT 24
Finished Jul 20 05:39:40 PM PDT 24
Peak memory 206292 kb
Host smart-0c1a1d48-fd89-42f3-af48-44cc9873d86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217405371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3217405371
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3781404304
Short name T254
Test name
Test status
Simulation time 21303335569 ps
CPU time 20.19 seconds
Started Jul 20 05:39:35 PM PDT 24
Finished Jul 20 05:39:56 PM PDT 24
Peak memory 237728 kb
Host smart-769790b4-8cb0-49b9-af9f-160df9cc2fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781404304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3781404304
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2255804680
Short name T707
Test name
Test status
Simulation time 44126261 ps
CPU time 0.72 seconds
Started Jul 20 05:39:36 PM PDT 24
Finished Jul 20 05:39:37 PM PDT 24
Peak memory 205120 kb
Host smart-51e0e27f-9c6b-40da-9704-ef90f482c126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255804680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2255804680
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1751491737
Short name T478
Test name
Test status
Simulation time 107277058 ps
CPU time 2.23 seconds
Started Jul 20 05:39:50 PM PDT 24
Finished Jul 20 05:39:53 PM PDT 24
Peak memory 224928 kb
Host smart-28e60f72-8326-46b9-b237-9951c7a7328d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751491737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1751491737
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2914833647
Short name T811
Test name
Test status
Simulation time 151338789 ps
CPU time 0.75 seconds
Started Jul 20 05:39:51 PM PDT 24
Finished Jul 20 05:39:53 PM PDT 24
Peak memory 205832 kb
Host smart-2d1081c9-1947-4d45-b2ea-118902b1dc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914833647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2914833647
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1209505688
Short name T53
Test name
Test status
Simulation time 20987204146 ps
CPU time 52.8 seconds
Started Jul 20 05:39:51 PM PDT 24
Finished Jul 20 05:40:46 PM PDT 24
Peak memory 249664 kb
Host smart-9024c35f-6d91-4c29-9aae-79b9329f2a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209505688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1209505688
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2917303082
Short name T205
Test name
Test status
Simulation time 180665996781 ps
CPU time 427.96 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:46:46 PM PDT 24
Peak memory 267404 kb
Host smart-457cfad0-0af9-4bd8-9640-97fcdf6cbd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917303082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2917303082
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1775893876
Short name T839
Test name
Test status
Simulation time 160387632872 ps
CPU time 342.73 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:45:20 PM PDT 24
Peak memory 255948 kb
Host smart-5ebd94d6-2f0a-4737-ba7a-3e8c44c68f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775893876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1775893876
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3489406464
Short name T709
Test name
Test status
Simulation time 15688029167 ps
CPU time 39.05 seconds
Started Jul 20 05:39:40 PM PDT 24
Finished Jul 20 05:40:20 PM PDT 24
Peak memory 233256 kb
Host smart-2e5f0d96-80f7-4ed9-a228-d77d716e7ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489406464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3489406464
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2719451879
Short name T671
Test name
Test status
Simulation time 4254391592 ps
CPU time 34.17 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:40:13 PM PDT 24
Peak memory 251224 kb
Host smart-fe9967ff-4855-443f-a879-ae63db0e9504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719451879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2719451879
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.784520968
Short name T134
Test name
Test status
Simulation time 249826213 ps
CPU time 4.86 seconds
Started Jul 20 05:39:35 PM PDT 24
Finished Jul 20 05:39:41 PM PDT 24
Peak memory 224888 kb
Host smart-7970e6c1-43a7-406f-9d6e-d24c6051e227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784520968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.784520968
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3216872918
Short name T339
Test name
Test status
Simulation time 2174781946 ps
CPU time 14.23 seconds
Started Jul 20 05:39:39 PM PDT 24
Finished Jul 20 05:39:54 PM PDT 24
Peak memory 225012 kb
Host smart-285a613f-d72d-44bd-929a-1cb36c2d33b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216872918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3216872918
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4025759486
Short name T923
Test name
Test status
Simulation time 13066083277 ps
CPU time 13.97 seconds
Started Jul 20 05:39:40 PM PDT 24
Finished Jul 20 05:39:54 PM PDT 24
Peak memory 233248 kb
Host smart-5fb99e02-ae77-4d21-9206-aae614af8477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025759486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4025759486
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.94518268
Short name T560
Test name
Test status
Simulation time 6917520745 ps
CPU time 18.14 seconds
Started Jul 20 05:39:52 PM PDT 24
Finished Jul 20 05:40:11 PM PDT 24
Peak memory 233088 kb
Host smart-9a14f2ac-85e5-487e-8d9c-67450b5a7de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94518268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.94518268
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.905898367
Short name T661
Test name
Test status
Simulation time 145040608 ps
CPU time 3.76 seconds
Started Jul 20 05:39:36 PM PDT 24
Finished Jul 20 05:39:40 PM PDT 24
Peak memory 220728 kb
Host smart-0265f2b8-6c3c-4d24-8bcb-807958a19c82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=905898367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.905898367
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2378820506
Short name T301
Test name
Test status
Simulation time 274953830409 ps
CPU time 346.82 seconds
Started Jul 20 05:39:39 PM PDT 24
Finished Jul 20 05:45:27 PM PDT 24
Peak memory 253076 kb
Host smart-7b5c353e-7d1e-4bd3-a80f-756dc4fd16e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378820506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2378820506
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1773821025
Short name T819
Test name
Test status
Simulation time 43480013684 ps
CPU time 36.14 seconds
Started Jul 20 05:39:38 PM PDT 24
Finished Jul 20 05:40:16 PM PDT 24
Peak memory 216844 kb
Host smart-c4588518-aebd-491c-909b-2b5e6591f74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773821025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1773821025
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.331688627
Short name T918
Test name
Test status
Simulation time 22344051528 ps
CPU time 7.53 seconds
Started Jul 20 05:39:37 PM PDT 24
Finished Jul 20 05:39:46 PM PDT 24
Peak memory 216784 kb
Host smart-42940408-2f1b-4d6f-bcd0-ad960f305565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331688627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.331688627
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3821908963
Short name T496
Test name
Test status
Simulation time 68566917 ps
CPU time 0.95 seconds
Started Jul 20 05:39:38 PM PDT 24
Finished Jul 20 05:39:40 PM PDT 24
Peak memory 207292 kb
Host smart-33ba99d9-bb34-477e-885d-8e2182ef42de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821908963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3821908963
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.299525262
Short name T569
Test name
Test status
Simulation time 69501954 ps
CPU time 0.92 seconds
Started Jul 20 05:39:39 PM PDT 24
Finished Jul 20 05:39:41 PM PDT 24
Peak memory 207252 kb
Host smart-d3e596dc-8842-49f2-b928-65df0545ee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299525262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.299525262
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1938771209
Short name T829
Test name
Test status
Simulation time 12698268 ps
CPU time 0.72 seconds
Started Jul 20 05:39:46 PM PDT 24
Finished Jul 20 05:39:49 PM PDT 24
Peak memory 205184 kb
Host smart-e1c1ab95-ac0a-4346-9817-15ba17561868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938771209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1938771209
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.811568932
Short name T437
Test name
Test status
Simulation time 2511809387 ps
CPU time 18.86 seconds
Started Jul 20 05:39:47 PM PDT 24
Finished Jul 20 05:40:08 PM PDT 24
Peak memory 225036 kb
Host smart-df4a3410-2dae-4a97-97e7-6c692be77b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811568932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.811568932
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.476150338
Short name T344
Test name
Test status
Simulation time 16207021 ps
CPU time 0.79 seconds
Started Jul 20 05:39:38 PM PDT 24
Finished Jul 20 05:39:40 PM PDT 24
Peak memory 207204 kb
Host smart-621b154f-99ae-4f77-a78a-2e58cb99b028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476150338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.476150338
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3247180929
Short name T188
Test name
Test status
Simulation time 23332210486 ps
CPU time 76.47 seconds
Started Jul 20 05:39:49 PM PDT 24
Finished Jul 20 05:41:07 PM PDT 24
Peak memory 255188 kb
Host smart-99ec371e-a4fd-4a3e-9b36-0f4e39135e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247180929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3247180929
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.976410125
Short name T462
Test name
Test status
Simulation time 64533416328 ps
CPU time 312.15 seconds
Started Jul 20 05:39:45 PM PDT 24
Finished Jul 20 05:44:59 PM PDT 24
Peak memory 265616 kb
Host smart-7f02d1a6-a2c6-47a5-99a2-6ad8fc189815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976410125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.976410125
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1887388709
Short name T732
Test name
Test status
Simulation time 16969005194 ps
CPU time 78.24 seconds
Started Jul 20 05:39:48 PM PDT 24
Finished Jul 20 05:41:08 PM PDT 24
Peak memory 250980 kb
Host smart-47bfaa81-a6bb-4ac7-9dfa-bb51ef295487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887388709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1887388709
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.220572303
Short name T635
Test name
Test status
Simulation time 391577294 ps
CPU time 5.24 seconds
Started Jul 20 05:39:47 PM PDT 24
Finished Jul 20 05:39:55 PM PDT 24
Peak memory 233164 kb
Host smart-95215911-523c-455c-bc7e-1fef1556cff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220572303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.220572303
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2017255897
Short name T651
Test name
Test status
Simulation time 33663768299 ps
CPU time 23.17 seconds
Started Jul 20 05:39:46 PM PDT 24
Finished Jul 20 05:40:11 PM PDT 24
Peak memory 236736 kb
Host smart-c3da1c45-4d20-43ec-82e6-789becb56c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017255897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2017255897
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3025440018
Short name T542
Test name
Test status
Simulation time 236900868 ps
CPU time 2.35 seconds
Started Jul 20 05:39:44 PM PDT 24
Finished Jul 20 05:39:47 PM PDT 24
Peak memory 232828 kb
Host smart-a2f8a5e8-58c9-416c-8da6-3aec533ba9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025440018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3025440018
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3081348729
Short name T616
Test name
Test status
Simulation time 665668490 ps
CPU time 11.54 seconds
Started Jul 20 05:39:46 PM PDT 24
Finished Jul 20 05:39:59 PM PDT 24
Peak memory 241224 kb
Host smart-0e6b45ac-1c44-42d8-8106-6cabac00dff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081348729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3081348729
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1883599466
Short name T815
Test name
Test status
Simulation time 21818404538 ps
CPU time 16.3 seconds
Started Jul 20 05:39:44 PM PDT 24
Finished Jul 20 05:40:01 PM PDT 24
Peak memory 233260 kb
Host smart-df158b36-34fb-4033-a792-57e3fd654cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883599466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1883599466
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1217087741
Short name T827
Test name
Test status
Simulation time 4513528273 ps
CPU time 5.03 seconds
Started Jul 20 05:39:48 PM PDT 24
Finished Jul 20 05:39:55 PM PDT 24
Peak memory 225068 kb
Host smart-9a4d502e-798f-4385-863d-cc2cf9275e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217087741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1217087741
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1041271525
Short name T900
Test name
Test status
Simulation time 199408162 ps
CPU time 4.72 seconds
Started Jul 20 05:39:50 PM PDT 24
Finished Jul 20 05:39:56 PM PDT 24
Peak memory 219652 kb
Host smart-91a43b8e-b68f-4b29-91a3-0f2dad17c613
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1041271525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1041271525
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.852664674
Short name T446
Test name
Test status
Simulation time 130632293 ps
CPU time 0.97 seconds
Started Jul 20 05:39:46 PM PDT 24
Finished Jul 20 05:39:49 PM PDT 24
Peak memory 207792 kb
Host smart-45372236-bd07-4d45-a2ae-93031c2fe030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852664674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.852664674
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2110504259
Short name T26
Test name
Test status
Simulation time 17625132864 ps
CPU time 30.98 seconds
Started Jul 20 05:39:46 PM PDT 24
Finished Jul 20 05:40:19 PM PDT 24
Peak memory 216780 kb
Host smart-eb4a1ddc-5107-4ee5-a9d9-77122a23e630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110504259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2110504259
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.41035386
Short name T401
Test name
Test status
Simulation time 1046009827 ps
CPU time 4.98 seconds
Started Jul 20 05:39:51 PM PDT 24
Finished Jul 20 05:39:58 PM PDT 24
Peak memory 216616 kb
Host smart-78da1025-1ded-4a3c-9cc2-157def5b80cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41035386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.41035386
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3278166980
Short name T695
Test name
Test status
Simulation time 21053173 ps
CPU time 1.08 seconds
Started Jul 20 05:39:49 PM PDT 24
Finished Jul 20 05:39:52 PM PDT 24
Peak memory 208240 kb
Host smart-4a443003-0e7d-4b44-8085-654adf088f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278166980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3278166980
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1734663008
Short name T499
Test name
Test status
Simulation time 39906339 ps
CPU time 0.75 seconds
Started Jul 20 05:39:51 PM PDT 24
Finished Jul 20 05:39:53 PM PDT 24
Peak memory 206180 kb
Host smart-eac549ab-f8fb-4334-9478-ed7728386ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734663008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1734663008
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.204271040
Short name T933
Test name
Test status
Simulation time 7167092756 ps
CPU time 20.43 seconds
Started Jul 20 05:39:50 PM PDT 24
Finished Jul 20 05:40:11 PM PDT 24
Peak memory 224988 kb
Host smart-f68d3281-bbd8-4bfc-958b-2f7a5bcc7a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204271040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.204271040
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3883862003
Short name T777
Test name
Test status
Simulation time 14022076 ps
CPU time 0.71 seconds
Started Jul 20 05:39:46 PM PDT 24
Finished Jul 20 05:39:49 PM PDT 24
Peak memory 206104 kb
Host smart-022f61c9-95e5-41e9-908d-6fad354370c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883862003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3883862003
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3306562225
Short name T968
Test name
Test status
Simulation time 67339754 ps
CPU time 2.8 seconds
Started Jul 20 05:39:46 PM PDT 24
Finished Jul 20 05:39:51 PM PDT 24
Peak memory 233188 kb
Host smart-f7cfce35-c1cb-404e-8015-9c6d521e113c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306562225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3306562225
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2913268229
Short name T564
Test name
Test status
Simulation time 46654803 ps
CPU time 0.75 seconds
Started Jul 20 05:39:44 PM PDT 24
Finished Jul 20 05:39:46 PM PDT 24
Peak memory 206004 kb
Host smart-bbbb66ab-2f17-4ab0-b2ae-9a3f22f557b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913268229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2913268229
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1010837794
Short name T853
Test name
Test status
Simulation time 6646751575 ps
CPU time 89.33 seconds
Started Jul 20 05:39:49 PM PDT 24
Finished Jul 20 05:41:20 PM PDT 24
Peak memory 256192 kb
Host smart-7b128115-37fe-4c6b-bd98-ad629b7de67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010837794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1010837794
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1203448226
Short name T190
Test name
Test status
Simulation time 90536275933 ps
CPU time 606.6 seconds
Started Jul 20 05:39:47 PM PDT 24
Finished Jul 20 05:49:56 PM PDT 24
Peak memory 268216 kb
Host smart-0c522d00-0a7f-48d9-8525-bb71b05bc857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203448226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1203448226
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.537448832
Short name T888
Test name
Test status
Simulation time 142240599707 ps
CPU time 411.98 seconds
Started Jul 20 05:39:45 PM PDT 24
Finished Jul 20 05:46:38 PM PDT 24
Peak memory 273680 kb
Host smart-3d045796-6575-4123-a841-c85538f055f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537448832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.537448832
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.238382749
Short name T80
Test name
Test status
Simulation time 931538046 ps
CPU time 2.99 seconds
Started Jul 20 05:39:48 PM PDT 24
Finished Jul 20 05:39:53 PM PDT 24
Peak memory 224900 kb
Host smart-c4d19561-8008-4b1b-b2fa-c7d5a5ac6cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238382749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.238382749
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2149286993
Short name T228
Test name
Test status
Simulation time 2071351794 ps
CPU time 28.59 seconds
Started Jul 20 05:39:47 PM PDT 24
Finished Jul 20 05:40:18 PM PDT 24
Peak memory 241268 kb
Host smart-21298826-c5c9-4a51-a34f-a8c05be85d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149286993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2149286993
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2463205584
Short name T945
Test name
Test status
Simulation time 74278487 ps
CPU time 2.28 seconds
Started Jul 20 05:39:47 PM PDT 24
Finished Jul 20 05:39:52 PM PDT 24
Peak memory 224184 kb
Host smart-80ce429e-c80f-49bd-b958-c2b802cad875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463205584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2463205584
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1090105166
Short name T798
Test name
Test status
Simulation time 1695172115 ps
CPU time 9.43 seconds
Started Jul 20 05:39:45 PM PDT 24
Finished Jul 20 05:39:55 PM PDT 24
Peak memory 224936 kb
Host smart-dd34bd68-5a0e-4c47-a60f-975b00d81c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090105166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1090105166
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2983999627
Short name T403
Test name
Test status
Simulation time 447041236 ps
CPU time 2.6 seconds
Started Jul 20 05:39:47 PM PDT 24
Finished Jul 20 05:39:52 PM PDT 24
Peak memory 233136 kb
Host smart-db510107-c678-4a9b-864e-28ddea766e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983999627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2983999627
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3431996645
Short name T532
Test name
Test status
Simulation time 6996949730 ps
CPU time 9.99 seconds
Started Jul 20 05:39:45 PM PDT 24
Finished Jul 20 05:39:56 PM PDT 24
Peak memory 240328 kb
Host smart-e9fcc9b3-5bb4-4d72-abf5-13b87b781c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431996645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3431996645
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3770250001
Short name T878
Test name
Test status
Simulation time 874529145 ps
CPU time 4.71 seconds
Started Jul 20 05:39:47 PM PDT 24
Finished Jul 20 05:39:53 PM PDT 24
Peak memory 223468 kb
Host smart-ad5b45e0-1fb2-478c-9556-a7eadabe3546
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3770250001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3770250001
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3114789374
Short name T159
Test name
Test status
Simulation time 27093099060 ps
CPU time 64.84 seconds
Started Jul 20 05:39:46 PM PDT 24
Finished Jul 20 05:40:52 PM PDT 24
Peak memory 265436 kb
Host smart-a6353da2-4fea-425c-a85b-5772dee621f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114789374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3114789374
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1004213957
Short name T647
Test name
Test status
Simulation time 4131854720 ps
CPU time 12.09 seconds
Started Jul 20 05:39:46 PM PDT 24
Finished Jul 20 05:39:59 PM PDT 24
Peak memory 216944 kb
Host smart-562f158d-63a7-45a1-b3f7-31f79860478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004213957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1004213957
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1283325381
Short name T29
Test name
Test status
Simulation time 19997454 ps
CPU time 1.22 seconds
Started Jul 20 05:39:48 PM PDT 24
Finished Jul 20 05:39:51 PM PDT 24
Peak memory 216376 kb
Host smart-3c1d2b48-d37a-4c93-b06d-c8319c572ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283325381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1283325381
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4186704674
Short name T453
Test name
Test status
Simulation time 77410505 ps
CPU time 0.85 seconds
Started Jul 20 05:39:47 PM PDT 24
Finished Jul 20 05:39:50 PM PDT 24
Peak memory 206272 kb
Host smart-2c92f25e-a1ca-48a0-b87f-67cf38b60448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186704674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4186704674
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1627025956
Short name T975
Test name
Test status
Simulation time 5621340568 ps
CPU time 6.31 seconds
Started Jul 20 05:39:45 PM PDT 24
Finished Jul 20 05:39:53 PM PDT 24
Peak memory 225040 kb
Host smart-3a957eac-6052-42d5-adc1-772115b71a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627025956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1627025956
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3946029570
Short name T963
Test name
Test status
Simulation time 45069963 ps
CPU time 0.74 seconds
Started Jul 20 05:40:02 PM PDT 24
Finished Jul 20 05:40:04 PM PDT 24
Peak memory 205768 kb
Host smart-4c4258d5-476b-406f-a047-7bb2029a868a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946029570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3946029570
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2604546036
Short name T862
Test name
Test status
Simulation time 811306988 ps
CPU time 4.27 seconds
Started Jul 20 05:39:43 PM PDT 24
Finished Jul 20 05:39:48 PM PDT 24
Peak memory 224960 kb
Host smart-5b6f8dda-f36a-489d-8a44-b07dc9bd7524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604546036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2604546036
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2313317927
Short name T448
Test name
Test status
Simulation time 21513323 ps
CPU time 0.75 seconds
Started Jul 20 05:39:48 PM PDT 24
Finished Jul 20 05:39:51 PM PDT 24
Peak memory 207232 kb
Host smart-a8ff4b4b-39a9-461a-931b-dea2821f4c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313317927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2313317927
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3208981972
Short name T914
Test name
Test status
Simulation time 25040472027 ps
CPU time 199.37 seconds
Started Jul 20 05:39:58 PM PDT 24
Finished Jul 20 05:43:18 PM PDT 24
Peak memory 257096 kb
Host smart-ade4b54f-f512-4aa6-84f9-6190d6eebfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208981972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3208981972
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3493981061
Short name T63
Test name
Test status
Simulation time 37418953567 ps
CPU time 323.83 seconds
Started Jul 20 05:40:03 PM PDT 24
Finished Jul 20 05:45:28 PM PDT 24
Peak memory 249692 kb
Host smart-a426caaa-761b-4d75-8c45-4a785f5522dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493981061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3493981061
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.884985057
Short name T226
Test name
Test status
Simulation time 1078393887 ps
CPU time 13.09 seconds
Started Jul 20 05:40:01 PM PDT 24
Finished Jul 20 05:40:16 PM PDT 24
Peak memory 237168 kb
Host smart-34fbd7aa-1219-4caf-8414-87cd53eefd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884985057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.884985057
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3253871540
Short name T778
Test name
Test status
Simulation time 1168061773 ps
CPU time 3.51 seconds
Started Jul 20 05:40:02 PM PDT 24
Finished Jul 20 05:40:07 PM PDT 24
Peak memory 224924 kb
Host smart-a8f51194-101a-45e1-92c7-a7aedd505851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253871540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3253871540
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1191459422
Short name T982
Test name
Test status
Simulation time 27400689 ps
CPU time 0.73 seconds
Started Jul 20 05:39:58 PM PDT 24
Finished Jul 20 05:40:00 PM PDT 24
Peak memory 208028 kb
Host smart-9c837171-14cf-4285-b80c-7cac8c1be379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191459422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1191459422
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.190060673
Short name T802
Test name
Test status
Simulation time 283904150 ps
CPU time 6.67 seconds
Started Jul 20 05:39:46 PM PDT 24
Finished Jul 20 05:39:55 PM PDT 24
Peak memory 224956 kb
Host smart-3accc996-b60d-43e3-b407-c115ca8ef9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190060673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.190060673
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.530732467
Short name T591
Test name
Test status
Simulation time 2245185087 ps
CPU time 4.43 seconds
Started Jul 20 05:39:48 PM PDT 24
Finished Jul 20 05:39:54 PM PDT 24
Peak memory 233304 kb
Host smart-37a50753-c289-4df5-a9cd-e52df78f2db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530732467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.530732467
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3032613440
Short name T887
Test name
Test status
Simulation time 10049836883 ps
CPU time 18.71 seconds
Started Jul 20 05:39:46 PM PDT 24
Finished Jul 20 05:40:06 PM PDT 24
Peak memory 241468 kb
Host smart-d9607afb-57db-433d-bf9b-c66bdad8026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032613440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3032613440
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4627073
Short name T710
Test name
Test status
Simulation time 6270134010 ps
CPU time 19.88 seconds
Started Jul 20 05:39:48 PM PDT 24
Finished Jul 20 05:40:10 PM PDT 24
Peak memory 236948 kb
Host smart-6fd64001-de5b-48d4-9cbf-c0f0ee6428e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4627073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4627073
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.421899871
Short name T689
Test name
Test status
Simulation time 445346633 ps
CPU time 6.1 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:07 PM PDT 24
Peak memory 219616 kb
Host smart-1f385e8b-8952-4fc0-9cad-39155717b02b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=421899871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.421899871
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4224937682
Short name T623
Test name
Test status
Simulation time 92967158 ps
CPU time 1.04 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:03 PM PDT 24
Peak memory 207400 kb
Host smart-38055bd2-979b-4992-a6a0-88e9b3bba509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224937682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4224937682
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.807754012
Short name T482
Test name
Test status
Simulation time 2991904099 ps
CPU time 8.46 seconds
Started Jul 20 05:39:47 PM PDT 24
Finished Jul 20 05:39:58 PM PDT 24
Peak memory 216788 kb
Host smart-40d25f79-e176-4d60-9f72-e42d8bb50b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807754012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.807754012
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.412762643
Short name T919
Test name
Test status
Simulation time 24241002378 ps
CPU time 10.65 seconds
Started Jul 20 05:39:48 PM PDT 24
Finished Jul 20 05:40:01 PM PDT 24
Peak memory 216560 kb
Host smart-750fd5f7-23ab-4f86-b667-fa04202ea774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412762643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.412762643
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4114319164
Short name T604
Test name
Test status
Simulation time 13763455 ps
CPU time 0.75 seconds
Started Jul 20 05:39:45 PM PDT 24
Finished Jul 20 05:39:48 PM PDT 24
Peak memory 205916 kb
Host smart-4d6c4f7c-ae35-4513-8da5-3e8227a9d03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114319164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4114319164
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2591981959
Short name T722
Test name
Test status
Simulation time 22062658 ps
CPU time 0.78 seconds
Started Jul 20 05:39:46 PM PDT 24
Finished Jul 20 05:39:48 PM PDT 24
Peak memory 206292 kb
Host smart-4534c755-a92f-4d66-a5e0-5e1a612f8fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591981959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2591981959
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1046766185
Short name T489
Test name
Test status
Simulation time 7389026685 ps
CPU time 22.37 seconds
Started Jul 20 05:39:44 PM PDT 24
Finished Jul 20 05:40:07 PM PDT 24
Peak memory 233172 kb
Host smart-73070148-378b-4595-abe5-cd726c85c141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046766185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1046766185
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2873247733
Short name T46
Test name
Test status
Simulation time 13987898 ps
CPU time 0.76 seconds
Started Jul 20 05:40:01 PM PDT 24
Finished Jul 20 05:40:03 PM PDT 24
Peak memory 206088 kb
Host smart-31515b03-60c9-408e-a9c0-a84f835d7035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873247733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2873247733
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2496486435
Short name T832
Test name
Test status
Simulation time 434591086 ps
CPU time 3.89 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:05 PM PDT 24
Peak memory 233156 kb
Host smart-9ee338b1-46d9-4795-b0ec-9f4f529630ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496486435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2496486435
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1843108104
Short name T1011
Test name
Test status
Simulation time 60784884 ps
CPU time 0.84 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:03 PM PDT 24
Peak memory 206920 kb
Host smart-770532fe-1e10-4084-8d9d-b5efe4d1e6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843108104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1843108104
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3935749755
Short name T206
Test name
Test status
Simulation time 9112205083 ps
CPU time 87.13 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:41:29 PM PDT 24
Peak memory 249692 kb
Host smart-26bc82b6-9082-4b25-9d5c-919df088e368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935749755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3935749755
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1409145668
Short name T643
Test name
Test status
Simulation time 15475467987 ps
CPU time 30.75 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:32 PM PDT 24
Peak memory 218164 kb
Host smart-43ef178e-5a0c-4571-ad5c-f9cc6cd5b2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409145668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1409145668
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3210838900
Short name T916
Test name
Test status
Simulation time 13795786157 ps
CPU time 113.42 seconds
Started Jul 20 05:40:03 PM PDT 24
Finished Jul 20 05:41:57 PM PDT 24
Peak memory 256844 kb
Host smart-b515b4a0-9939-4240-87ce-61a0ea56343e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210838900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3210838900
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3814716917
Short name T347
Test name
Test status
Simulation time 846676623 ps
CPU time 4.79 seconds
Started Jul 20 05:39:59 PM PDT 24
Finished Jul 20 05:40:05 PM PDT 24
Peak memory 224932 kb
Host smart-0a928194-8bc6-4903-9c61-36ea92a85d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814716917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3814716917
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3740670944
Short name T365
Test name
Test status
Simulation time 2505907941 ps
CPU time 18.12 seconds
Started Jul 20 05:40:03 PM PDT 24
Finished Jul 20 05:40:22 PM PDT 24
Peak memory 225076 kb
Host smart-8d0c4890-aeee-4623-b325-4e8382a4109e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740670944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3740670944
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3440537421
Short name T280
Test name
Test status
Simulation time 17358892632 ps
CPU time 16.24 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:18 PM PDT 24
Peak memory 240944 kb
Host smart-bbf4634e-654b-4a9d-87d1-04bf9e386e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440537421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3440537421
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3921971156
Short name T84
Test name
Test status
Simulation time 861567821 ps
CPU time 3.41 seconds
Started Jul 20 05:40:02 PM PDT 24
Finished Jul 20 05:40:07 PM PDT 24
Peak memory 233132 kb
Host smart-04e9e5d4-30cb-4455-bf54-5177af197375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921971156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3921971156
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3820775944
Short name T456
Test name
Test status
Simulation time 514708534 ps
CPU time 3.75 seconds
Started Jul 20 05:40:01 PM PDT 24
Finished Jul 20 05:40:07 PM PDT 24
Peak memory 219076 kb
Host smart-a8142a9a-a5c6-42c3-a8f3-05392746f7a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3820775944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3820775944
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.495962033
Short name T1022
Test name
Test status
Simulation time 8328188038 ps
CPU time 40.96 seconds
Started Jul 20 05:40:01 PM PDT 24
Finished Jul 20 05:40:44 PM PDT 24
Peak memory 216796 kb
Host smart-0bc02886-5d3c-48d2-bfef-4348984b4055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495962033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.495962033
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4053740172
Short name T493
Test name
Test status
Simulation time 2780377141 ps
CPU time 5.41 seconds
Started Jul 20 05:40:02 PM PDT 24
Finished Jul 20 05:40:09 PM PDT 24
Peak memory 216780 kb
Host smart-f12cb2ae-ced8-4dd6-9129-c47702607825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053740172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4053740172
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1532896826
Short name T883
Test name
Test status
Simulation time 170002657 ps
CPU time 1.34 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:04 PM PDT 24
Peak memory 216656 kb
Host smart-a7bd9511-6b80-4fcd-8bb9-1d2e65d28d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532896826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1532896826
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3037506455
Short name T392
Test name
Test status
Simulation time 24726874 ps
CPU time 0.79 seconds
Started Jul 20 05:40:01 PM PDT 24
Finished Jul 20 05:40:04 PM PDT 24
Peak memory 206264 kb
Host smart-490ddd22-5713-4e08-86ba-fb5f4d0acacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037506455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3037506455
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.503028035
Short name T554
Test name
Test status
Simulation time 191599328 ps
CPU time 3.83 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:06 PM PDT 24
Peak memory 233092 kb
Host smart-597f775b-4b6d-4b8b-a520-77b3a8c729ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503028035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.503028035
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1319656286
Short name T667
Test name
Test status
Simulation time 21385859 ps
CPU time 0.75 seconds
Started Jul 20 05:40:06 PM PDT 24
Finished Jul 20 05:40:07 PM PDT 24
Peak memory 205316 kb
Host smart-1e3d4ee2-e4a7-4100-9eb7-65ce28c59ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319656286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1319656286
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2810852498
Short name T91
Test name
Test status
Simulation time 438945458 ps
CPU time 8.08 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:10 PM PDT 24
Peak memory 233080 kb
Host smart-142335a0-0833-429c-890b-eed65bbfdacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810852498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2810852498
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1565908543
Short name T34
Test name
Test status
Simulation time 19210433 ps
CPU time 0.8 seconds
Started Jul 20 05:40:03 PM PDT 24
Finished Jul 20 05:40:05 PM PDT 24
Peak memory 206900 kb
Host smart-5af85544-261d-4f80-9ed5-dff128b41abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565908543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1565908543
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1087092716
Short name T14
Test name
Test status
Simulation time 103676273015 ps
CPU time 125.11 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:42:07 PM PDT 24
Peak memory 241400 kb
Host smart-f53e5cfe-4060-481e-a14a-ae209c9ad068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087092716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1087092716
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1984493520
Short name T953
Test name
Test status
Simulation time 4328052463 ps
CPU time 76.49 seconds
Started Jul 20 05:40:11 PM PDT 24
Finished Jul 20 05:41:30 PM PDT 24
Peak memory 273316 kb
Host smart-5f68affb-502d-455c-a4c8-012470d35c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984493520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1984493520
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.734711622
Short name T677
Test name
Test status
Simulation time 19837311997 ps
CPU time 60.88 seconds
Started Jul 20 05:40:03 PM PDT 24
Finished Jul 20 05:41:05 PM PDT 24
Peak memory 241400 kb
Host smart-b652a56c-e7d7-4703-81b0-22e40ab6f53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734711622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.734711622
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3104447945
Short name T341
Test name
Test status
Simulation time 84708623 ps
CPU time 3.31 seconds
Started Jul 20 05:39:59 PM PDT 24
Finished Jul 20 05:40:03 PM PDT 24
Peak memory 233180 kb
Host smart-35b34225-23dc-4c0e-8351-8be879cbeccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104447945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3104447945
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2859238600
Short name T58
Test name
Test status
Simulation time 6408193686 ps
CPU time 11.17 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:13 PM PDT 24
Peak memory 225032 kb
Host smart-339a759b-fb8f-4d9c-a337-2baca301c28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859238600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2859238600
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.956449430
Short name T886
Test name
Test status
Simulation time 1696443571 ps
CPU time 4.88 seconds
Started Jul 20 05:40:02 PM PDT 24
Finished Jul 20 05:40:08 PM PDT 24
Peak memory 224920 kb
Host smart-b305baeb-87c8-40ff-a9f4-ef62f690a751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956449430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.956449430
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2587129804
Short name T610
Test name
Test status
Simulation time 5758560613 ps
CPU time 13.77 seconds
Started Jul 20 05:40:01 PM PDT 24
Finished Jul 20 05:40:17 PM PDT 24
Peak memory 233036 kb
Host smart-f886a78b-ddc8-453b-96b1-6fb5933845ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587129804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2587129804
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1890251967
Short name T668
Test name
Test status
Simulation time 364751792 ps
CPU time 8.43 seconds
Started Jul 20 05:40:01 PM PDT 24
Finished Jul 20 05:40:11 PM PDT 24
Peak memory 220420 kb
Host smart-4d723cf6-029f-489e-b6d3-ef7732667fcb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1890251967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1890251967
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3339009185
Short name T541
Test name
Test status
Simulation time 4613622005 ps
CPU time 28.44 seconds
Started Jul 20 05:40:09 PM PDT 24
Finished Jul 20 05:40:38 PM PDT 24
Peak memory 251828 kb
Host smart-25d75d30-3417-494b-b963-1bd8e79e7eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339009185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3339009185
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4134766097
Short name T62
Test name
Test status
Simulation time 2655092442 ps
CPU time 22.08 seconds
Started Jul 20 05:40:04 PM PDT 24
Finished Jul 20 05:40:27 PM PDT 24
Peak memory 220824 kb
Host smart-b0c5340c-f37b-4bc8-880d-59ab29d996e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134766097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4134766097
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1798590592
Short name T783
Test name
Test status
Simulation time 678738536 ps
CPU time 3.16 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:05 PM PDT 24
Peak memory 216664 kb
Host smart-d9769d69-013a-4066-8c05-d17ae5cc4bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798590592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1798590592
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.4269645211
Short name T435
Test name
Test status
Simulation time 90276638 ps
CPU time 1.51 seconds
Started Jul 20 05:40:00 PM PDT 24
Finished Jul 20 05:40:03 PM PDT 24
Peak memory 216628 kb
Host smart-b6b780c9-e534-47f4-9b23-2626809e574a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269645211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.4269645211
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3239417921
Short name T631
Test name
Test status
Simulation time 115785532 ps
CPU time 0.76 seconds
Started Jul 20 05:40:03 PM PDT 24
Finished Jul 20 05:40:05 PM PDT 24
Peak memory 206256 kb
Host smart-4103396e-c98d-41a2-a74f-60326e4b45e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239417921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3239417921
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1018097755
Short name T8
Test name
Test status
Simulation time 2903896734 ps
CPU time 11.17 seconds
Started Jul 20 05:40:01 PM PDT 24
Finished Jul 20 05:40:14 PM PDT 24
Peak memory 225096 kb
Host smart-f6cd5516-e9be-448c-b371-e98d955708a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018097755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1018097755
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2267515289
Short name T1030
Test name
Test status
Simulation time 33137442 ps
CPU time 0.73 seconds
Started Jul 20 05:37:50 PM PDT 24
Finished Jul 20 05:37:52 PM PDT 24
Peak memory 205712 kb
Host smart-a79415e7-a75f-430d-8ddb-0efea63bd619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267515289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
267515289
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2476973552
Short name T948
Test name
Test status
Simulation time 92220569 ps
CPU time 3.09 seconds
Started Jul 20 05:37:51 PM PDT 24
Finished Jul 20 05:37:55 PM PDT 24
Peak memory 233120 kb
Host smart-77800213-0379-4074-a7d2-9d889dff0c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476973552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2476973552
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3262829393
Short name T719
Test name
Test status
Simulation time 38310587 ps
CPU time 0.81 seconds
Started Jul 20 05:37:40 PM PDT 24
Finished Jul 20 05:37:41 PM PDT 24
Peak memory 206848 kb
Host smart-22649a80-b2c6-43d0-8f34-49dcdc85afb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262829393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3262829393
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2326827431
Short name T223
Test name
Test status
Simulation time 207113434475 ps
CPU time 354.6 seconds
Started Jul 20 05:37:51 PM PDT 24
Finished Jul 20 05:43:47 PM PDT 24
Peak memory 252796 kb
Host smart-41c2abee-3e8f-4803-a6f0-e2d94696c263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326827431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2326827431
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3750840660
Short name T679
Test name
Test status
Simulation time 100582725843 ps
CPU time 172.69 seconds
Started Jul 20 05:37:50 PM PDT 24
Finished Jul 20 05:40:45 PM PDT 24
Peak memory 225108 kb
Host smart-1979a23d-e514-45a5-b47a-6e46a941e904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750840660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3750840660
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2758144476
Short name T449
Test name
Test status
Simulation time 3973823741 ps
CPU time 21.9 seconds
Started Jul 20 05:37:54 PM PDT 24
Finished Jul 20 05:38:16 PM PDT 24
Peak memory 218188 kb
Host smart-66515175-2165-4d62-9782-44c4a1430462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758144476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2758144476
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.626663715
Short name T746
Test name
Test status
Simulation time 1201000123 ps
CPU time 10.55 seconds
Started Jul 20 05:37:50 PM PDT 24
Finished Jul 20 05:38:03 PM PDT 24
Peak memory 234160 kb
Host smart-61f3ae37-24f4-4b1a-a7d1-63b739a2f2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626663715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.626663715
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2176524586
Short name T12
Test name
Test status
Simulation time 31539888428 ps
CPU time 90.06 seconds
Started Jul 20 05:37:51 PM PDT 24
Finished Jul 20 05:39:22 PM PDT 24
Peak memory 249620 kb
Host smart-1a104b78-f894-45c8-8d1a-57b4a363034f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176524586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2176524586
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1484918244
Short name T926
Test name
Test status
Simulation time 219894797 ps
CPU time 3.19 seconds
Started Jul 20 05:37:50 PM PDT 24
Finished Jul 20 05:37:55 PM PDT 24
Peak memory 224912 kb
Host smart-d0a0c03f-1305-44c7-8f63-85f26032d1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484918244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1484918244
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3143710499
Short name T980
Test name
Test status
Simulation time 3813678933 ps
CPU time 40.44 seconds
Started Jul 20 05:37:50 PM PDT 24
Finished Jul 20 05:38:33 PM PDT 24
Peak memory 233188 kb
Host smart-95099822-c23f-495e-8a9a-723bcdad3a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143710499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3143710499
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2207782396
Short name T420
Test name
Test status
Simulation time 223517872 ps
CPU time 1.05 seconds
Started Jul 20 05:37:40 PM PDT 24
Finished Jul 20 05:37:42 PM PDT 24
Peak memory 217120 kb
Host smart-74aab66f-e2e0-45fe-a803-8c7db68c40f3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207782396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2207782396
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3616298658
Short name T219
Test name
Test status
Simulation time 332966427 ps
CPU time 5.26 seconds
Started Jul 20 05:37:40 PM PDT 24
Finished Jul 20 05:37:46 PM PDT 24
Peak memory 224932 kb
Host smart-d7c357bb-a720-4540-97bf-00f15620cf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616298658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3616298658
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3384214842
Short name T636
Test name
Test status
Simulation time 807507095 ps
CPU time 8.36 seconds
Started Jul 20 05:37:46 PM PDT 24
Finished Jul 20 05:37:55 PM PDT 24
Peak memory 233148 kb
Host smart-e2107e4a-db31-4b63-a29c-baf296bda0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384214842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3384214842
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3275773951
Short name T82
Test name
Test status
Simulation time 265490786 ps
CPU time 3.69 seconds
Started Jul 20 05:37:51 PM PDT 24
Finished Jul 20 05:37:56 PM PDT 24
Peak memory 220348 kb
Host smart-7d68478b-6fe0-4a85-8732-c8b08a44475d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3275773951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3275773951
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3144710767
Short name T955
Test name
Test status
Simulation time 4394498941 ps
CPU time 12.85 seconds
Started Jul 20 05:37:41 PM PDT 24
Finished Jul 20 05:37:55 PM PDT 24
Peak memory 216784 kb
Host smart-5a7c5ddf-dd2d-4095-ba6e-4dbba8e1db6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144710767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3144710767
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1189765685
Short name T1015
Test name
Test status
Simulation time 35649102785 ps
CPU time 11.64 seconds
Started Jul 20 05:37:40 PM PDT 24
Finished Jul 20 05:37:52 PM PDT 24
Peak memory 217976 kb
Host smart-befae093-e61b-4304-bb00-d8efd2d19b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189765685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1189765685
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2393226325
Short name T404
Test name
Test status
Simulation time 29114963 ps
CPU time 0.65 seconds
Started Jul 20 05:37:39 PM PDT 24
Finished Jul 20 05:37:40 PM PDT 24
Peak memory 205904 kb
Host smart-f05079f8-5a49-4191-8672-065df8cd325a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393226325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2393226325
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1346518776
Short name T474
Test name
Test status
Simulation time 73095567 ps
CPU time 0.78 seconds
Started Jul 20 05:37:39 PM PDT 24
Finished Jul 20 05:37:40 PM PDT 24
Peak memory 206216 kb
Host smart-4c6b5bf7-0f1f-4e5c-b2d6-3790d0b66f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346518776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1346518776
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1296583423
Short name T374
Test name
Test status
Simulation time 82183792 ps
CPU time 2.14 seconds
Started Jul 20 05:37:50 PM PDT 24
Finished Jul 20 05:37:54 PM PDT 24
Peak memory 224660 kb
Host smart-17aa1f86-676f-4d67-bf84-68f379b58eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296583423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1296583423
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4277732668
Short name T367
Test name
Test status
Simulation time 16046819 ps
CPU time 0.74 seconds
Started Jul 20 05:40:16 PM PDT 24
Finished Jul 20 05:40:17 PM PDT 24
Peak memory 206104 kb
Host smart-ccfac17e-e685-4750-aa04-e5dcf1039c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277732668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4277732668
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.995662616
Short name T656
Test name
Test status
Simulation time 1269416624 ps
CPU time 4.31 seconds
Started Jul 20 05:40:14 PM PDT 24
Finished Jul 20 05:40:20 PM PDT 24
Peak memory 224912 kb
Host smart-a376c01f-4282-4851-b4cd-d604a9c80023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995662616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.995662616
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1095258449
Short name T32
Test name
Test status
Simulation time 28193583 ps
CPU time 0.78 seconds
Started Jul 20 05:40:07 PM PDT 24
Finished Jul 20 05:40:08 PM PDT 24
Peak memory 207240 kb
Host smart-e004bf87-c7a8-4133-b029-c14a2f09ad92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095258449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1095258449
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3890026753
Short name T992
Test name
Test status
Simulation time 36329781895 ps
CPU time 29.43 seconds
Started Jul 20 05:40:06 PM PDT 24
Finished Jul 20 05:40:36 PM PDT 24
Peak memory 238624 kb
Host smart-0e72d768-d42d-4821-9bc4-961ceaf2e8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890026753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3890026753
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1528449077
Short name T805
Test name
Test status
Simulation time 5479236744 ps
CPU time 59.2 seconds
Started Jul 20 05:40:16 PM PDT 24
Finished Jul 20 05:41:16 PM PDT 24
Peak memory 251960 kb
Host smart-96fad906-73c3-4574-ac9d-cf58b01a29bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528449077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1528449077
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2424925732
Short name T1008
Test name
Test status
Simulation time 464282842 ps
CPU time 12.18 seconds
Started Jul 20 05:40:15 PM PDT 24
Finished Jul 20 05:40:28 PM PDT 24
Peak memory 235068 kb
Host smart-fcf470de-c590-44b1-89dd-b1e363be6c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424925732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2424925732
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1897279995
Short name T852
Test name
Test status
Simulation time 62688146 ps
CPU time 0.8 seconds
Started Jul 20 05:40:10 PM PDT 24
Finished Jul 20 05:40:13 PM PDT 24
Peak memory 216232 kb
Host smart-c0fc5b6b-41bc-4e40-b7c4-227835e1b213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897279995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1897279995
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2147256503
Short name T264
Test name
Test status
Simulation time 567490545 ps
CPU time 5.86 seconds
Started Jul 20 05:40:11 PM PDT 24
Finished Jul 20 05:40:18 PM PDT 24
Peak memory 220112 kb
Host smart-45f53292-fb47-4263-9ffe-20b6e896722d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147256503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2147256503
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3548054553
Short name T986
Test name
Test status
Simulation time 489992980 ps
CPU time 12.42 seconds
Started Jul 20 05:40:10 PM PDT 24
Finished Jul 20 05:40:24 PM PDT 24
Peak memory 224888 kb
Host smart-fcf92f29-878b-4548-9f01-cc8d76d2c35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548054553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3548054553
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3263266804
Short name T951
Test name
Test status
Simulation time 17644349100 ps
CPU time 14.53 seconds
Started Jul 20 05:40:08 PM PDT 24
Finished Jul 20 05:40:23 PM PDT 24
Peak memory 241428 kb
Host smart-1f74224a-abff-43f0-9a39-4189886373cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263266804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3263266804
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3100173362
Short name T272
Test name
Test status
Simulation time 1009635030 ps
CPU time 7.68 seconds
Started Jul 20 05:40:08 PM PDT 24
Finished Jul 20 05:40:16 PM PDT 24
Peak memory 233156 kb
Host smart-5dc41ecd-25fe-4e11-8887-bbf3f842faf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100173362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3100173362
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3166351622
Short name T526
Test name
Test status
Simulation time 4618997836 ps
CPU time 10.18 seconds
Started Jul 20 05:40:06 PM PDT 24
Finished Jul 20 05:40:17 PM PDT 24
Peak memory 221072 kb
Host smart-533e1bda-6591-49c7-8ec2-3cabd1c4b1e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3166351622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3166351622
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1656059506
Short name T582
Test name
Test status
Simulation time 7282906623 ps
CPU time 89.63 seconds
Started Jul 20 05:40:17 PM PDT 24
Finished Jul 20 05:41:48 PM PDT 24
Peak memory 253816 kb
Host smart-274c2e3b-c3cc-4348-b231-99b93cde4041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656059506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1656059506
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4261992290
Short name T400
Test name
Test status
Simulation time 1396194544 ps
CPU time 10.27 seconds
Started Jul 20 05:40:08 PM PDT 24
Finished Jul 20 05:40:19 PM PDT 24
Peak memory 216704 kb
Host smart-8beb7339-d984-4917-8487-6579a2e0510d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261992290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4261992290
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2687825343
Short name T140
Test name
Test status
Simulation time 1311267996 ps
CPU time 8.43 seconds
Started Jul 20 05:40:13 PM PDT 24
Finished Jul 20 05:40:23 PM PDT 24
Peak memory 216624 kb
Host smart-a9a239ea-39fa-4802-a3e9-57256445f5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687825343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2687825343
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1404484758
Short name T494
Test name
Test status
Simulation time 173821817 ps
CPU time 1.22 seconds
Started Jul 20 05:40:12 PM PDT 24
Finished Jul 20 05:40:15 PM PDT 24
Peak memory 207176 kb
Host smart-d00e9f19-ae76-44d9-90e0-26e6f796e53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404484758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1404484758
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.827766312
Short name T972
Test name
Test status
Simulation time 12785513 ps
CPU time 0.7 seconds
Started Jul 20 05:40:10 PM PDT 24
Finished Jul 20 05:40:13 PM PDT 24
Peak memory 205900 kb
Host smart-f99f0848-403c-4e30-bfb7-df64ae3e6219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827766312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.827766312
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1541337272
Short name T772
Test name
Test status
Simulation time 715615412 ps
CPU time 5.84 seconds
Started Jul 20 05:40:08 PM PDT 24
Finished Jul 20 05:40:14 PM PDT 24
Peak memory 224864 kb
Host smart-e5aa58eb-bfad-463f-a63c-070996c32340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541337272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1541337272
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4269409153
Short name T549
Test name
Test status
Simulation time 22150563 ps
CPU time 0.7 seconds
Started Jul 20 05:40:09 PM PDT 24
Finished Jul 20 05:40:11 PM PDT 24
Peak memory 205112 kb
Host smart-b672fd7e-ee6e-4bc3-a743-69bfa43e1181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269409153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4269409153
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1540687221
Short name T51
Test name
Test status
Simulation time 1098957709 ps
CPU time 7.33 seconds
Started Jul 20 05:40:10 PM PDT 24
Finished Jul 20 05:40:18 PM PDT 24
Peak memory 224792 kb
Host smart-8a524eff-1107-43f4-adfd-3f2e9b447fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540687221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1540687221
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.681513640
Short name T513
Test name
Test status
Simulation time 57803054 ps
CPU time 0.77 seconds
Started Jul 20 05:40:07 PM PDT 24
Finished Jul 20 05:40:09 PM PDT 24
Peak memory 205876 kb
Host smart-5adbec7b-a63a-48cd-82f7-f57ba6dd69c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681513640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.681513640
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3470624657
Short name T286
Test name
Test status
Simulation time 37138200514 ps
CPU time 96.38 seconds
Started Jul 20 05:40:15 PM PDT 24
Finished Jul 20 05:41:53 PM PDT 24
Peak memory 255320 kb
Host smart-eb1ab32c-133d-4e90-8f27-ee7b7466c2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470624657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3470624657
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.740814605
Short name T142
Test name
Test status
Simulation time 264090107109 ps
CPU time 404.18 seconds
Started Jul 20 05:40:11 PM PDT 24
Finished Jul 20 05:46:57 PM PDT 24
Peak memory 265008 kb
Host smart-0a14fa53-4870-4217-9477-0f63ee3c2a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740814605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.740814605
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3496550812
Short name T167
Test name
Test status
Simulation time 13010176044 ps
CPU time 107.95 seconds
Started Jul 20 05:40:13 PM PDT 24
Finished Jul 20 05:42:03 PM PDT 24
Peak memory 262568 kb
Host smart-171b6e6c-4114-419d-b8c1-3696578b4f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496550812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3496550812
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1802207623
Short name T419
Test name
Test status
Simulation time 343778756 ps
CPU time 6.84 seconds
Started Jul 20 05:40:13 PM PDT 24
Finished Jul 20 05:40:22 PM PDT 24
Peak memory 224884 kb
Host smart-8eb99636-afde-40c4-a7b6-62fc4fc8f4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802207623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1802207623
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.538396873
Short name T54
Test name
Test status
Simulation time 97208770293 ps
CPU time 195.39 seconds
Started Jul 20 05:40:11 PM PDT 24
Finished Jul 20 05:43:28 PM PDT 24
Peak memory 251700 kb
Host smart-e432f7a4-df8a-4c89-85ea-a0976900c167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538396873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.538396873
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3706891707
Short name T599
Test name
Test status
Simulation time 6415713553 ps
CPU time 16.68 seconds
Started Jul 20 05:40:11 PM PDT 24
Finished Jul 20 05:40:29 PM PDT 24
Peak memory 233240 kb
Host smart-49607a96-d4f1-42fc-86d7-35ee6e8f09a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706891707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3706891707
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.215887857
Short name T735
Test name
Test status
Simulation time 946714924 ps
CPU time 7.29 seconds
Started Jul 20 05:40:12 PM PDT 24
Finished Jul 20 05:40:22 PM PDT 24
Peak memory 241244 kb
Host smart-3884cd3f-e5f5-4472-aa69-8778e7c2285e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215887857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.215887857
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1272219000
Short name T292
Test name
Test status
Simulation time 1340589410 ps
CPU time 9.82 seconds
Started Jul 20 05:40:11 PM PDT 24
Finished Jul 20 05:40:22 PM PDT 24
Peak memory 240744 kb
Host smart-fca7cee2-34ac-459a-a9db-1dffff6312da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272219000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1272219000
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1332347605
Short name T396
Test name
Test status
Simulation time 6216085862 ps
CPU time 6.66 seconds
Started Jul 20 05:40:11 PM PDT 24
Finished Jul 20 05:40:19 PM PDT 24
Peak memory 232592 kb
Host smart-a1c925c4-baa4-4538-b930-1dd7a702b80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332347605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1332347605
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1091289755
Short name T138
Test name
Test status
Simulation time 25799263970 ps
CPU time 17.28 seconds
Started Jul 20 05:40:17 PM PDT 24
Finished Jul 20 05:40:36 PM PDT 24
Peak memory 223640 kb
Host smart-83aeb0e4-a4d0-428b-bc8c-fc64ded09543
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1091289755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1091289755
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3600518036
Short name T293
Test name
Test status
Simulation time 117164111132 ps
CPU time 339.78 seconds
Started Jul 20 05:40:12 PM PDT 24
Finished Jul 20 05:45:54 PM PDT 24
Peak memory 278752 kb
Host smart-2c56d4bb-c69a-4a3d-9cc2-fc6e53b3c002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600518036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3600518036
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4187823597
Short name T876
Test name
Test status
Simulation time 12514869541 ps
CPU time 25.63 seconds
Started Jul 20 05:40:17 PM PDT 24
Finished Jul 20 05:40:44 PM PDT 24
Peak memory 216788 kb
Host smart-80e4e87e-22a8-4060-9051-c82b97750556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187823597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4187823597
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1969714416
Short name T338
Test name
Test status
Simulation time 474848878 ps
CPU time 3.8 seconds
Started Jul 20 05:40:12 PM PDT 24
Finished Jul 20 05:40:18 PM PDT 24
Peak memory 216648 kb
Host smart-1c79f122-2d71-452f-b7a8-a5e3e05d1a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969714416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1969714416
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1935944911
Short name T905
Test name
Test status
Simulation time 867577335 ps
CPU time 7.58 seconds
Started Jul 20 05:40:08 PM PDT 24
Finished Jul 20 05:40:16 PM PDT 24
Peak memory 216600 kb
Host smart-2eeec686-a5ad-4ef1-82f3-e9b094225dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935944911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1935944911
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3709490238
Short name T559
Test name
Test status
Simulation time 275053648 ps
CPU time 0.84 seconds
Started Jul 20 05:40:13 PM PDT 24
Finished Jul 20 05:40:16 PM PDT 24
Peak memory 206288 kb
Host smart-32d4bf48-22db-445b-b8e0-36abaf027213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709490238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3709490238
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2006423534
Short name T754
Test name
Test status
Simulation time 70942673379 ps
CPU time 30.52 seconds
Started Jul 20 05:40:12 PM PDT 24
Finished Jul 20 05:40:45 PM PDT 24
Peak memory 225068 kb
Host smart-fc9e20e9-526c-405f-b3c3-5e31697f559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006423534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2006423534
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1135489788
Short name T73
Test name
Test status
Simulation time 19382834 ps
CPU time 0.71 seconds
Started Jul 20 05:40:09 PM PDT 24
Finished Jul 20 05:40:10 PM PDT 24
Peak memory 205732 kb
Host smart-a80d7986-5fca-4429-8a2e-65984402e291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135489788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1135489788
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3618164051
Short name T994
Test name
Test status
Simulation time 176987904 ps
CPU time 2.25 seconds
Started Jul 20 05:40:11 PM PDT 24
Finished Jul 20 05:40:15 PM PDT 24
Peak memory 224880 kb
Host smart-1a31270f-8e08-4506-b9ff-185294798d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618164051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3618164051
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1111981014
Short name T857
Test name
Test status
Simulation time 23894925 ps
CPU time 0.88 seconds
Started Jul 20 05:40:10 PM PDT 24
Finished Jul 20 05:40:12 PM PDT 24
Peak memory 206852 kb
Host smart-96f75184-76dc-43eb-a81f-33283211be9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111981014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1111981014
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3907864925
Short name T506
Test name
Test status
Simulation time 14010048307 ps
CPU time 90.38 seconds
Started Jul 20 05:40:09 PM PDT 24
Finished Jul 20 05:41:40 PM PDT 24
Peak memory 236708 kb
Host smart-b7261c53-3340-4abb-93fc-175d9df18ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907864925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3907864925
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.375184374
Short name T860
Test name
Test status
Simulation time 7731622004 ps
CPU time 20.99 seconds
Started Jul 20 05:40:12 PM PDT 24
Finished Jul 20 05:40:35 PM PDT 24
Peak memory 220340 kb
Host smart-e788bb07-2833-4d59-a628-2796c33363f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375184374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.375184374
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.614467065
Short name T775
Test name
Test status
Simulation time 45183882826 ps
CPU time 316.49 seconds
Started Jul 20 05:40:12 PM PDT 24
Finished Jul 20 05:45:31 PM PDT 24
Peak memory 261616 kb
Host smart-8a964724-71e2-4318-a0c6-0952f7ebf1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614467065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.614467065
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1734136432
Short name T1029
Test name
Test status
Simulation time 1080966342 ps
CPU time 5.47 seconds
Started Jul 20 05:40:11 PM PDT 24
Finished Jul 20 05:40:17 PM PDT 24
Peak memory 224892 kb
Host smart-a44fb5e6-b18e-4f4c-93c6-99a593732618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734136432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1734136432
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.4040845482
Short name T881
Test name
Test status
Simulation time 11096321847 ps
CPU time 53.26 seconds
Started Jul 20 05:40:07 PM PDT 24
Finished Jul 20 05:41:01 PM PDT 24
Peak memory 245768 kb
Host smart-f3c7bd99-338c-48a4-aa9e-1861bde51907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040845482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.4040845482
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1094208856
Short name T498
Test name
Test status
Simulation time 959928186 ps
CPU time 2.6 seconds
Started Jul 20 05:40:16 PM PDT 24
Finished Jul 20 05:40:19 PM PDT 24
Peak memory 224948 kb
Host smart-8a98783f-c369-46f4-92c8-6820ab35fd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094208856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1094208856
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1862368408
Short name T221
Test name
Test status
Simulation time 206380000 ps
CPU time 4.58 seconds
Started Jul 20 05:40:13 PM PDT 24
Finished Jul 20 05:40:19 PM PDT 24
Peak memory 224956 kb
Host smart-a5f136e1-b75e-47ee-893e-b7540926a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862368408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1862368408
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.74169597
Short name T981
Test name
Test status
Simulation time 4664289257 ps
CPU time 15.16 seconds
Started Jul 20 05:40:10 PM PDT 24
Finished Jul 20 05:40:26 PM PDT 24
Peak memory 233252 kb
Host smart-b1412dd6-0a65-48f9-87bf-675adb6802c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74169597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.74169597
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2401909103
Short name T436
Test name
Test status
Simulation time 583526607 ps
CPU time 5.2 seconds
Started Jul 20 05:40:11 PM PDT 24
Finished Jul 20 05:40:18 PM PDT 24
Peak memory 233076 kb
Host smart-1858828f-be8f-40f8-bd81-76ae768ff76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401909103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2401909103
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4048993112
Short name T622
Test name
Test status
Simulation time 501654754 ps
CPU time 5.42 seconds
Started Jul 20 05:40:13 PM PDT 24
Finished Jul 20 05:40:20 PM PDT 24
Peak memory 223504 kb
Host smart-69ef2921-c30f-49e7-bfef-608beb566b1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4048993112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4048993112
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2939277671
Short name T155
Test name
Test status
Simulation time 56571738005 ps
CPU time 519 seconds
Started Jul 20 05:40:13 PM PDT 24
Finished Jul 20 05:48:54 PM PDT 24
Peak memory 257500 kb
Host smart-110129c1-cf26-4f15-956b-04bf5abd5440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939277671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2939277671
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.115211142
Short name T417
Test name
Test status
Simulation time 2884917258 ps
CPU time 10.48 seconds
Started Jul 20 05:40:17 PM PDT 24
Finished Jul 20 05:40:29 PM PDT 24
Peak memory 216760 kb
Host smart-0dc9af9a-b35d-4c6b-b292-b7b299a372e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115211142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.115211142
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.403943350
Short name T950
Test name
Test status
Simulation time 5045192070 ps
CPU time 14.03 seconds
Started Jul 20 05:40:13 PM PDT 24
Finished Jul 20 05:40:29 PM PDT 24
Peak memory 216612 kb
Host smart-f2110d23-1055-4157-8bc2-3b584f0c0df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403943350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.403943350
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3923880288
Short name T640
Test name
Test status
Simulation time 93194265 ps
CPU time 0.94 seconds
Started Jul 20 05:40:11 PM PDT 24
Finished Jul 20 05:40:14 PM PDT 24
Peak memory 207536 kb
Host smart-4ec0ee08-d1bc-4edf-9a31-e6ab4dd8cc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923880288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3923880288
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.778200838
Short name T856
Test name
Test status
Simulation time 20870277 ps
CPU time 0.79 seconds
Started Jul 20 05:40:10 PM PDT 24
Finished Jul 20 05:40:12 PM PDT 24
Peak memory 206148 kb
Host smart-00e764c5-be5f-4392-b901-814873e337ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778200838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.778200838
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.41907865
Short name T275
Test name
Test status
Simulation time 135403469 ps
CPU time 2.32 seconds
Started Jul 20 05:40:11 PM PDT 24
Finished Jul 20 05:40:15 PM PDT 24
Peak memory 224876 kb
Host smart-442ce320-adc6-4776-b4d2-1ed4654d6aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41907865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.41907865
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2714313729
Short name T773
Test name
Test status
Simulation time 25869244 ps
CPU time 0.69 seconds
Started Jul 20 05:40:16 PM PDT 24
Finished Jul 20 05:40:18 PM PDT 24
Peak memory 205692 kb
Host smart-0f9113d6-cb74-4762-b65f-d446aedebcc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714313729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2714313729
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2494504039
Short name T267
Test name
Test status
Simulation time 24736101426 ps
CPU time 11.63 seconds
Started Jul 20 05:40:24 PM PDT 24
Finished Jul 20 05:40:37 PM PDT 24
Peak memory 225080 kb
Host smart-1a1a4532-747d-42ea-9d5f-d077ccf5ac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494504039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2494504039
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1767494587
Short name T834
Test name
Test status
Simulation time 19080936 ps
CPU time 0.81 seconds
Started Jul 20 05:40:12 PM PDT 24
Finished Jul 20 05:40:15 PM PDT 24
Peak memory 207236 kb
Host smart-f8ec1a09-39fe-4cd9-aa3f-6328794ceb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767494587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1767494587
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3533434883
Short name T222
Test name
Test status
Simulation time 1970566882 ps
CPU time 45.89 seconds
Started Jul 20 05:40:25 PM PDT 24
Finished Jul 20 05:41:13 PM PDT 24
Peak memory 249500 kb
Host smart-0a453d44-8fef-4649-a1ff-96bac813811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533434883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3533434883
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4228720162
Short name T423
Test name
Test status
Simulation time 15413145415 ps
CPU time 51.12 seconds
Started Jul 20 05:40:19 PM PDT 24
Finished Jul 20 05:41:11 PM PDT 24
Peak memory 250032 kb
Host smart-270c7a26-5e7f-4e8a-957e-5f5ee7af0571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228720162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4228720162
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3321601803
Short name T807
Test name
Test status
Simulation time 12175527064 ps
CPU time 57.03 seconds
Started Jul 20 05:40:18 PM PDT 24
Finished Jul 20 05:41:16 PM PDT 24
Peak memory 249660 kb
Host smart-f50a485f-5ba3-4663-876c-c78e38a6f2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321601803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3321601803
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1230583909
Short name T672
Test name
Test status
Simulation time 112560027 ps
CPU time 3.64 seconds
Started Jul 20 05:40:24 PM PDT 24
Finished Jul 20 05:40:29 PM PDT 24
Peak memory 233520 kb
Host smart-5ecea404-80d3-4b84-8023-2eb30160c43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230583909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1230583909
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.644429040
Short name T444
Test name
Test status
Simulation time 473938678 ps
CPU time 4.53 seconds
Started Jul 20 05:40:19 PM PDT 24
Finished Jul 20 05:40:24 PM PDT 24
Peak memory 224928 kb
Host smart-9de42b46-37d8-4051-9e69-466a10ec98be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644429040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.644429040
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3463421243
Short name T467
Test name
Test status
Simulation time 167772661 ps
CPU time 5.06 seconds
Started Jul 20 05:40:10 PM PDT 24
Finished Jul 20 05:40:17 PM PDT 24
Peak memory 233064 kb
Host smart-d929cb6b-fe70-4992-b1e8-969402dd2ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463421243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3463421243
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.792748739
Short name T233
Test name
Test status
Simulation time 694469799 ps
CPU time 8.9 seconds
Started Jul 20 05:40:15 PM PDT 24
Finished Jul 20 05:40:25 PM PDT 24
Peak memory 232872 kb
Host smart-c0c8cae5-393b-4667-b6ad-386b3f7d616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792748739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.792748739
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2636703382
Short name T445
Test name
Test status
Simulation time 1389047344 ps
CPU time 7.77 seconds
Started Jul 20 05:40:12 PM PDT 24
Finished Jul 20 05:40:22 PM PDT 24
Peak memory 233088 kb
Host smart-8e062322-634d-4099-9a4b-f1da4bfc44c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636703382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2636703382
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1774661031
Short name T804
Test name
Test status
Simulation time 2651876110 ps
CPU time 5.39 seconds
Started Jul 20 05:40:13 PM PDT 24
Finished Jul 20 05:40:20 PM PDT 24
Peak memory 225052 kb
Host smart-3d1ffd9f-58bf-4f3f-8a15-c96a371fab6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774661031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1774661031
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1856379782
Short name T730
Test name
Test status
Simulation time 932329722 ps
CPU time 11.75 seconds
Started Jul 20 05:40:17 PM PDT 24
Finished Jul 20 05:40:30 PM PDT 24
Peak memory 219252 kb
Host smart-461216e9-45ea-4fb9-a6ec-b39d08d14dec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1856379782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1856379782
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.616423610
Short name T153
Test name
Test status
Simulation time 44795624053 ps
CPU time 153.61 seconds
Started Jul 20 05:40:15 PM PDT 24
Finished Jul 20 05:42:50 PM PDT 24
Peak memory 263332 kb
Host smart-15bbb821-8ff5-4e6c-9400-1ac5622b69f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616423610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.616423610
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3882602624
Short name T322
Test name
Test status
Simulation time 2667610986 ps
CPU time 14.82 seconds
Started Jul 20 05:40:17 PM PDT 24
Finished Jul 20 05:40:33 PM PDT 24
Peak memory 216836 kb
Host smart-fd022757-0d97-41f9-aefb-7b9bafd04854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882602624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3882602624
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1586498852
Short name T350
Test name
Test status
Simulation time 469848253 ps
CPU time 3.22 seconds
Started Jul 20 05:40:13 PM PDT 24
Finished Jul 20 05:40:18 PM PDT 24
Peak memory 216580 kb
Host smart-9819698b-ade1-432d-b8be-0f12c6c55800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586498852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1586498852
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1035219639
Short name T884
Test name
Test status
Simulation time 1442428989 ps
CPU time 2.65 seconds
Started Jul 20 05:40:10 PM PDT 24
Finished Jul 20 05:40:14 PM PDT 24
Peak memory 216620 kb
Host smart-d23cfa0d-216e-4449-bf00-133dcb93cf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035219639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1035219639
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2215818108
Short name T24
Test name
Test status
Simulation time 81579548 ps
CPU time 0.78 seconds
Started Jul 20 05:40:12 PM PDT 24
Finished Jul 20 05:40:15 PM PDT 24
Peak memory 206212 kb
Host smart-dae8209b-9ac5-4a46-8f1c-711f7324c050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215818108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2215818108
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3083146807
Short name T698
Test name
Test status
Simulation time 14421402088 ps
CPU time 14.13 seconds
Started Jul 20 05:40:15 PM PDT 24
Finished Jul 20 05:40:30 PM PDT 24
Peak memory 233280 kb
Host smart-49d4dc83-aac3-411f-a8d7-c0646fed56fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083146807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3083146807
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4242587431
Short name T742
Test name
Test status
Simulation time 40192512 ps
CPU time 0.71 seconds
Started Jul 20 05:40:17 PM PDT 24
Finished Jul 20 05:40:18 PM PDT 24
Peak memory 206088 kb
Host smart-1d65e9a4-8f23-4703-be9c-b55746fd4fcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242587431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4242587431
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.180316864
Short name T617
Test name
Test status
Simulation time 62909265 ps
CPU time 2.5 seconds
Started Jul 20 05:40:18 PM PDT 24
Finished Jul 20 05:40:22 PM PDT 24
Peak memory 232856 kb
Host smart-6c31160d-caa4-406d-831c-8ffec7c24be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180316864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.180316864
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1612486590
Short name T405
Test name
Test status
Simulation time 100119851 ps
CPU time 0.8 seconds
Started Jul 20 05:40:17 PM PDT 24
Finished Jul 20 05:40:19 PM PDT 24
Peak memory 207212 kb
Host smart-7e2afc5b-53ad-4337-b476-4c0fe5d95d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612486590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1612486590
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.82507953
Short name T806
Test name
Test status
Simulation time 75591878140 ps
CPU time 182.33 seconds
Started Jul 20 05:40:24 PM PDT 24
Finished Jul 20 05:43:27 PM PDT 24
Peak memory 255072 kb
Host smart-8d679aef-6210-4df7-94ae-cb530d37a14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82507953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.82507953
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4259395814
Short name T64
Test name
Test status
Simulation time 439765096 ps
CPU time 10.68 seconds
Started Jul 20 05:40:25 PM PDT 24
Finished Jul 20 05:40:37 PM PDT 24
Peak memory 224920 kb
Host smart-b3954f5d-1122-4771-87f0-742b7b51c484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259395814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4259395814
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3018305260
Short name T738
Test name
Test status
Simulation time 6031072481 ps
CPU time 20.05 seconds
Started Jul 20 05:40:17 PM PDT 24
Finished Jul 20 05:40:38 PM PDT 24
Peak memory 225076 kb
Host smart-aa77e7ce-affa-4561-abb7-3990f369a728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018305260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3018305260
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3220342178
Short name T457
Test name
Test status
Simulation time 1032010643 ps
CPU time 9.93 seconds
Started Jul 20 05:40:18 PM PDT 24
Finished Jul 20 05:40:29 PM PDT 24
Peak memory 235412 kb
Host smart-c3b13576-675c-4500-97b8-cb7fcd11ccd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220342178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3220342178
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2748370231
Short name T725
Test name
Test status
Simulation time 5260169804 ps
CPU time 11.25 seconds
Started Jul 20 05:40:18 PM PDT 24
Finished Jul 20 05:40:30 PM PDT 24
Peak memory 233252 kb
Host smart-74f6c60e-f458-43a4-83d5-103aab2b4dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748370231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2748370231
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3673221515
Short name T779
Test name
Test status
Simulation time 162365116 ps
CPU time 2.9 seconds
Started Jul 20 05:40:25 PM PDT 24
Finished Jul 20 05:40:30 PM PDT 24
Peak memory 233108 kb
Host smart-e1ce9848-5e02-4337-b1c9-fddfa09bf0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673221515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3673221515
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2710169839
Short name T800
Test name
Test status
Simulation time 4646279003 ps
CPU time 10.09 seconds
Started Jul 20 05:40:24 PM PDT 24
Finished Jul 20 05:40:35 PM PDT 24
Peak memory 225068 kb
Host smart-f9d651dc-92b9-4471-ba1e-d1755c850f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710169839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2710169839
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1254823980
Short name T211
Test name
Test status
Simulation time 2227400116 ps
CPU time 6.39 seconds
Started Jul 20 05:40:17 PM PDT 24
Finished Jul 20 05:40:24 PM PDT 24
Peak memory 233196 kb
Host smart-2675561a-3cac-495f-b818-8cf27491aaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254823980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1254823980
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1399463906
Short name T390
Test name
Test status
Simulation time 5299264998 ps
CPU time 16.48 seconds
Started Jul 20 05:40:19 PM PDT 24
Finished Jul 20 05:40:37 PM PDT 24
Peak memory 219356 kb
Host smart-f633e26a-b8fa-4e61-b2ea-d686e547a851
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1399463906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1399463906
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1966360943
Short name T430
Test name
Test status
Simulation time 20730447 ps
CPU time 0.72 seconds
Started Jul 20 05:40:25 PM PDT 24
Finished Jul 20 05:40:27 PM PDT 24
Peak memory 205920 kb
Host smart-503dffb4-3960-456c-8ad8-6fa46860ed07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966360943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1966360943
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3618267387
Short name T759
Test name
Test status
Simulation time 6008003975 ps
CPU time 9.62 seconds
Started Jul 20 05:40:25 PM PDT 24
Finished Jul 20 05:40:36 PM PDT 24
Peak memory 216716 kb
Host smart-7fb1b0f9-8200-46e0-9be5-41fdc096dad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618267387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3618267387
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.604149696
Short name T60
Test name
Test status
Simulation time 320650824 ps
CPU time 6.24 seconds
Started Jul 20 05:40:18 PM PDT 24
Finished Jul 20 05:40:26 PM PDT 24
Peak memory 216648 kb
Host smart-0b8b778d-ade5-4f50-8018-0a84740c3828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604149696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.604149696
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1544964561
Short name T544
Test name
Test status
Simulation time 93343790 ps
CPU time 1.04 seconds
Started Jul 20 05:40:19 PM PDT 24
Finished Jul 20 05:40:21 PM PDT 24
Peak memory 206508 kb
Host smart-61176ac0-35c8-4c77-a686-ff31ee08435b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544964561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1544964561
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1471491504
Short name T376
Test name
Test status
Simulation time 1328408689 ps
CPU time 10.54 seconds
Started Jul 20 05:40:20 PM PDT 24
Finished Jul 20 05:40:31 PM PDT 24
Peak memory 233128 kb
Host smart-dd550b51-f891-485b-b068-d3971fe592b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471491504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1471491504
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2556276184
Short name T74
Test name
Test status
Simulation time 12189187 ps
CPU time 0.73 seconds
Started Jul 20 05:40:30 PM PDT 24
Finished Jul 20 05:40:32 PM PDT 24
Peak memory 206016 kb
Host smart-02184518-761d-4fb8-8ebe-b0ec4633b19f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556276184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2556276184
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4271995253
Short name T581
Test name
Test status
Simulation time 878211138 ps
CPU time 11.51 seconds
Started Jul 20 05:40:23 PM PDT 24
Finished Jul 20 05:40:35 PM PDT 24
Peak memory 233124 kb
Host smart-c3d1a0e9-7374-448c-b0c7-8391bd434231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271995253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4271995253
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.4233171876
Short name T343
Test name
Test status
Simulation time 16954245 ps
CPU time 0.83 seconds
Started Jul 20 05:40:25 PM PDT 24
Finished Jul 20 05:40:28 PM PDT 24
Peak memory 206860 kb
Host smart-daf3b695-7d6f-4dbe-b61f-5b12b9fab0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233171876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4233171876
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3664573621
Short name T270
Test name
Test status
Simulation time 3420473918 ps
CPU time 85.02 seconds
Started Jul 20 05:40:28 PM PDT 24
Finished Jul 20 05:41:54 PM PDT 24
Peak memory 254616 kb
Host smart-9122e812-0d2c-435e-8a20-a948b310afee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664573621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3664573621
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1499622683
Short name T183
Test name
Test status
Simulation time 6415629189 ps
CPU time 43.79 seconds
Started Jul 20 05:40:29 PM PDT 24
Finished Jul 20 05:41:14 PM PDT 24
Peak memory 249724 kb
Host smart-fe74405f-2680-44ab-8b15-7f33d866fe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499622683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1499622683
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.895307880
Short name T700
Test name
Test status
Simulation time 503627604 ps
CPU time 6.45 seconds
Started Jul 20 05:40:25 PM PDT 24
Finished Jul 20 05:40:32 PM PDT 24
Peak memory 233064 kb
Host smart-2b3417e6-cadf-4629-ad15-af6d65e8cfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895307880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.895307880
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2017101998
Short name T520
Test name
Test status
Simulation time 1052517112 ps
CPU time 4.65 seconds
Started Jul 20 05:40:28 PM PDT 24
Finished Jul 20 05:40:34 PM PDT 24
Peak memory 224932 kb
Host smart-86242a01-3a84-4849-811c-97de4cc40840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017101998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2017101998
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1604429437
Short name T762
Test name
Test status
Simulation time 188441706 ps
CPU time 5.6 seconds
Started Jul 20 05:40:26 PM PDT 24
Finished Jul 20 05:40:33 PM PDT 24
Peak memory 224932 kb
Host smart-e7233b5e-7e20-45f0-b809-c5ca39d2e9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604429437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1604429437
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2603822722
Short name T279
Test name
Test status
Simulation time 1266325366 ps
CPU time 9.89 seconds
Started Jul 20 05:40:27 PM PDT 24
Finished Jul 20 05:40:38 PM PDT 24
Peak memory 233220 kb
Host smart-c85a8dc0-d137-42a3-aab4-3f309042edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603822722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2603822722
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3183498771
Short name T207
Test name
Test status
Simulation time 13668872513 ps
CPU time 12.56 seconds
Started Jul 20 05:40:28 PM PDT 24
Finished Jul 20 05:40:41 PM PDT 24
Peak memory 241056 kb
Host smart-975c8da0-c28d-43b3-b99a-3e611f90a7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183498771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3183498771
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1354816640
Short name T575
Test name
Test status
Simulation time 1593256427 ps
CPU time 12.66 seconds
Started Jul 20 05:40:26 PM PDT 24
Finished Jul 20 05:40:41 PM PDT 24
Peak memory 219256 kb
Host smart-46375a00-fc96-4bdf-ae91-1bdaa19f6ef1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1354816640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1354816640
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1436527154
Short name T242
Test name
Test status
Simulation time 34382748514 ps
CPU time 340.38 seconds
Started Jul 20 05:40:29 PM PDT 24
Finished Jul 20 05:46:10 PM PDT 24
Peak memory 267836 kb
Host smart-b28dc838-435a-4341-a053-35691b279838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436527154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1436527154
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2282267638
Short name T399
Test name
Test status
Simulation time 815599889 ps
CPU time 8.08 seconds
Started Jul 20 05:40:25 PM PDT 24
Finished Jul 20 05:40:34 PM PDT 24
Peak memory 216664 kb
Host smart-98b2dc91-3c8e-42d6-bb2e-78b189cd0ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282267638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2282267638
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.200858647
Short name T538
Test name
Test status
Simulation time 1597410757 ps
CPU time 3.85 seconds
Started Jul 20 05:40:26 PM PDT 24
Finished Jul 20 05:40:31 PM PDT 24
Peak memory 216648 kb
Host smart-1344b98f-24c3-40b1-83e4-d7a08cbccc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200858647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.200858647
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2338184461
Short name T1031
Test name
Test status
Simulation time 63330557 ps
CPU time 0.99 seconds
Started Jul 20 05:40:26 PM PDT 24
Finished Jul 20 05:40:29 PM PDT 24
Peak memory 207580 kb
Host smart-7f414e17-1677-4e14-aa76-a61e2bd3e752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338184461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2338184461
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.335186163
Short name T471
Test name
Test status
Simulation time 53542547 ps
CPU time 0.84 seconds
Started Jul 20 05:40:28 PM PDT 24
Finished Jul 20 05:40:30 PM PDT 24
Peak memory 206260 kb
Host smart-fee1ce61-d4d5-4964-81c7-74c47370d878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335186163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.335186163
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.585589921
Short name T202
Test name
Test status
Simulation time 5405982767 ps
CPU time 9.49 seconds
Started Jul 20 05:40:25 PM PDT 24
Finished Jul 20 05:40:36 PM PDT 24
Peak memory 225004 kb
Host smart-a2077943-eef5-477b-a65f-2c09dbe93656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585589921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.585589921
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3914801293
Short name T847
Test name
Test status
Simulation time 31915324 ps
CPU time 0.71 seconds
Started Jul 20 05:40:34 PM PDT 24
Finished Jul 20 05:40:36 PM PDT 24
Peak memory 205768 kb
Host smart-1ab47a77-3559-4d57-818d-53a03828429f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914801293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3914801293
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.4071548290
Short name T395
Test name
Test status
Simulation time 9877362366 ps
CPU time 6.35 seconds
Started Jul 20 05:40:30 PM PDT 24
Finished Jul 20 05:40:38 PM PDT 24
Peak memory 224984 kb
Host smart-3241bda2-4dfa-4bc2-96e8-e0d7f71d88cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071548290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.4071548290
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1233436878
Short name T915
Test name
Test status
Simulation time 20484112 ps
CPU time 0.79 seconds
Started Jul 20 05:40:28 PM PDT 24
Finished Jul 20 05:40:30 PM PDT 24
Peak memory 206912 kb
Host smart-3923a909-5e74-4737-a426-898be0b12a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233436878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1233436878
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1161400045
Short name T596
Test name
Test status
Simulation time 1348801529 ps
CPU time 28.31 seconds
Started Jul 20 05:40:29 PM PDT 24
Finished Jul 20 05:40:58 PM PDT 24
Peak memory 241376 kb
Host smart-02740bf3-d633-445a-b35d-06e65009c0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161400045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1161400045
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3634245388
Short name T509
Test name
Test status
Simulation time 4958346014 ps
CPU time 28.65 seconds
Started Jul 20 05:40:35 PM PDT 24
Finished Jul 20 05:41:05 PM PDT 24
Peak memory 248968 kb
Host smart-5106d5e9-fe40-4915-a097-0464babd70e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634245388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3634245388
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3880739663
Short name T131
Test name
Test status
Simulation time 164505403720 ps
CPU time 437.21 seconds
Started Jul 20 05:40:34 PM PDT 24
Finished Jul 20 05:47:53 PM PDT 24
Peak memory 256520 kb
Host smart-3095e086-6415-41da-b195-a081995070d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880739663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3880739663
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1912789255
Short name T318
Test name
Test status
Simulation time 20107459040 ps
CPU time 23.73 seconds
Started Jul 20 05:40:28 PM PDT 24
Finished Jul 20 05:40:53 PM PDT 24
Peak memory 247060 kb
Host smart-3f231983-05f8-401d-a100-4857ac06bbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912789255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1912789255
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.218094360
Short name T503
Test name
Test status
Simulation time 236936208382 ps
CPU time 135.82 seconds
Started Jul 20 05:40:26 PM PDT 24
Finished Jul 20 05:42:43 PM PDT 24
Peak memory 249676 kb
Host smart-7492d871-12c8-4842-b0f7-8a0ba3813646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218094360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.218094360
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3858294710
Short name T67
Test name
Test status
Simulation time 661638463 ps
CPU time 6.49 seconds
Started Jul 20 05:40:30 PM PDT 24
Finished Jul 20 05:40:38 PM PDT 24
Peak memory 233068 kb
Host smart-ee425f5b-8b26-49ed-b229-ee3a83f2d808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858294710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3858294710
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.596990116
Short name T461
Test name
Test status
Simulation time 8127905856 ps
CPU time 46.68 seconds
Started Jul 20 05:40:26 PM PDT 24
Finished Jul 20 05:41:14 PM PDT 24
Peak memory 233316 kb
Host smart-b8c9623f-6106-4df7-8dbd-4fc1e0bee94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596990116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.596990116
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.951146607
Short name T871
Test name
Test status
Simulation time 8734221242 ps
CPU time 7.36 seconds
Started Jul 20 05:40:30 PM PDT 24
Finished Jul 20 05:40:39 PM PDT 24
Peak memory 234236 kb
Host smart-4c07bf0b-2261-4675-b970-c9ca2273b591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951146607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.951146607
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3495198736
Short name T81
Test name
Test status
Simulation time 929370180 ps
CPU time 6.97 seconds
Started Jul 20 05:40:30 PM PDT 24
Finished Jul 20 05:40:38 PM PDT 24
Peak memory 233140 kb
Host smart-35389d12-59f1-4baa-99b7-3c6e5ca4420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495198736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3495198736
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2259996760
Short name T351
Test name
Test status
Simulation time 4903490813 ps
CPU time 10.45 seconds
Started Jul 20 05:40:26 PM PDT 24
Finished Jul 20 05:40:37 PM PDT 24
Peak memory 219756 kb
Host smart-6788cdb1-c864-405d-b069-92eb346ec825
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2259996760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2259996760
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3603658990
Short name T985
Test name
Test status
Simulation time 19476138890 ps
CPU time 48.97 seconds
Started Jul 20 05:40:26 PM PDT 24
Finished Jul 20 05:41:16 PM PDT 24
Peak memory 216780 kb
Host smart-be460157-a022-4a43-8032-e77da5971a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603658990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3603658990
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1391463683
Short name T378
Test name
Test status
Simulation time 6318896016 ps
CPU time 15.8 seconds
Started Jul 20 05:40:28 PM PDT 24
Finished Jul 20 05:40:45 PM PDT 24
Peak memory 216776 kb
Host smart-7a4e0bab-52a7-427f-8f3b-7b69bcaf2a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391463683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1391463683
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1961173619
Short name T486
Test name
Test status
Simulation time 38787665 ps
CPU time 1.25 seconds
Started Jul 20 05:40:28 PM PDT 24
Finished Jul 20 05:40:31 PM PDT 24
Peak memory 216700 kb
Host smart-213293f8-0058-4756-b5ea-57d2ffbdb1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961173619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1961173619
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.58223563
Short name T380
Test name
Test status
Simulation time 72131444 ps
CPU time 0.76 seconds
Started Jul 20 05:40:26 PM PDT 24
Finished Jul 20 05:40:28 PM PDT 24
Peak memory 206260 kb
Host smart-799cb9fc-c8e9-4de5-ad62-ec48c0d67b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58223563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.58223563
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1293871933
Short name T1010
Test name
Test status
Simulation time 100779469 ps
CPU time 2.38 seconds
Started Jul 20 05:40:26 PM PDT 24
Finished Jul 20 05:40:30 PM PDT 24
Peak memory 224932 kb
Host smart-3b35f14a-6f6a-4653-930c-ee078fe2d91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293871933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1293871933
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3271974835
Short name T844
Test name
Test status
Simulation time 35244029 ps
CPU time 0.75 seconds
Started Jul 20 05:40:39 PM PDT 24
Finished Jul 20 05:40:40 PM PDT 24
Peak memory 205780 kb
Host smart-0415036a-4429-49d7-b9bb-6672d008ebef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271974835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3271974835
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.41348410
Short name T370
Test name
Test status
Simulation time 142666167 ps
CPU time 1.93 seconds
Started Jul 20 05:40:34 PM PDT 24
Finished Jul 20 05:40:36 PM PDT 24
Peak memory 223536 kb
Host smart-1ffd2aeb-09b8-4a79-9c1a-5ea2e8ca795b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41348410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.41348410
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.373051579
Short name T358
Test name
Test status
Simulation time 62255187 ps
CPU time 0.77 seconds
Started Jul 20 05:40:33 PM PDT 24
Finished Jul 20 05:40:35 PM PDT 24
Peak memory 206832 kb
Host smart-2f17ded9-4018-4820-8646-6c105bebe2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373051579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.373051579
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2146493957
Short name T997
Test name
Test status
Simulation time 27113443 ps
CPU time 0.75 seconds
Started Jul 20 05:40:33 PM PDT 24
Finished Jul 20 05:40:35 PM PDT 24
Peak memory 216188 kb
Host smart-fc18f87c-b276-468a-9e08-4b706f1c2913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146493957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2146493957
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.30395305
Short name T514
Test name
Test status
Simulation time 7637514726 ps
CPU time 14.33 seconds
Started Jul 20 05:40:35 PM PDT 24
Finished Jul 20 05:40:51 PM PDT 24
Peak memory 218216 kb
Host smart-80d48b9b-d35b-4b39-8f85-82c29bca4c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30395305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.30395305
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.818689406
Short name T928
Test name
Test status
Simulation time 69787391768 ps
CPU time 174.26 seconds
Started Jul 20 05:40:33 PM PDT 24
Finished Jul 20 05:43:27 PM PDT 24
Peak memory 254020 kb
Host smart-f81c4371-3089-4cda-b7c3-25de78b8b227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818689406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.818689406
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.127531199
Short name T313
Test name
Test status
Simulation time 2014809736 ps
CPU time 9.01 seconds
Started Jul 20 05:40:35 PM PDT 24
Finished Jul 20 05:40:46 PM PDT 24
Peak memory 224952 kb
Host smart-c4530f06-17ba-4768-aa5b-69f806116cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127531199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.127531199
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2238475050
Short name T236
Test name
Test status
Simulation time 40202767644 ps
CPU time 271.92 seconds
Started Jul 20 05:40:32 PM PDT 24
Finished Jul 20 05:45:05 PM PDT 24
Peak memory 250084 kb
Host smart-7dd396fe-ce3d-498d-b0cb-d5d1bb3a3faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238475050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2238475050
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3098007846
Short name T932
Test name
Test status
Simulation time 5257431606 ps
CPU time 28.49 seconds
Started Jul 20 05:40:35 PM PDT 24
Finished Jul 20 05:41:04 PM PDT 24
Peak memory 233292 kb
Host smart-c0cb8a99-8ddb-4c3f-b9a8-caeaa238f3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098007846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3098007846
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3394780
Short name T515
Test name
Test status
Simulation time 8290160617 ps
CPU time 41.73 seconds
Started Jul 20 05:40:36 PM PDT 24
Finished Jul 20 05:41:18 PM PDT 24
Peak memory 233276 kb
Host smart-f3997f95-ab6b-4d32-94f4-14b0ea7b56bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3394780
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1592248979
Short name T836
Test name
Test status
Simulation time 429216606 ps
CPU time 5.35 seconds
Started Jul 20 05:40:35 PM PDT 24
Finished Jul 20 05:40:42 PM PDT 24
Peak memory 224892 kb
Host smart-1e12b0d3-07a4-4324-87d0-7cab0751180d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592248979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1592248979
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.13625099
Short name T225
Test name
Test status
Simulation time 7808943935 ps
CPU time 9.08 seconds
Started Jul 20 05:40:32 PM PDT 24
Finished Jul 20 05:40:41 PM PDT 24
Peak memory 233380 kb
Host smart-05eb74ee-695f-4840-bce6-4a794b30f486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13625099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.13625099
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1937023497
Short name T460
Test name
Test status
Simulation time 1997482065 ps
CPU time 8.14 seconds
Started Jul 20 05:40:39 PM PDT 24
Finished Jul 20 05:40:48 PM PDT 24
Peak memory 221528 kb
Host smart-23d67a05-189e-4c5b-9bba-6dd3e2a0118f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1937023497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1937023497
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1444729367
Short name T476
Test name
Test status
Simulation time 13764139459 ps
CPU time 27.97 seconds
Started Jul 20 05:40:35 PM PDT 24
Finished Jul 20 05:41:04 PM PDT 24
Peak memory 233240 kb
Host smart-c7c9af8d-b2cc-4d0e-9a9f-4e9de87b9b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444729367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1444729367
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.971653595
Short name T325
Test name
Test status
Simulation time 4349685141 ps
CPU time 23.22 seconds
Started Jul 20 05:40:34 PM PDT 24
Finished Jul 20 05:40:59 PM PDT 24
Peak memory 216788 kb
Host smart-a8428f78-891c-4ba5-ab48-4aac6312afe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971653595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.971653595
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1692930691
Short name T356
Test name
Test status
Simulation time 4672247134 ps
CPU time 12.12 seconds
Started Jul 20 05:40:33 PM PDT 24
Finished Jul 20 05:40:46 PM PDT 24
Peak memory 216788 kb
Host smart-68e404ad-290a-47d9-87fd-fa189b633512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692930691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1692930691
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1753502165
Short name T85
Test name
Test status
Simulation time 10860078 ps
CPU time 0.68 seconds
Started Jul 20 05:40:35 PM PDT 24
Finished Jul 20 05:40:37 PM PDT 24
Peak memory 205876 kb
Host smart-5c9a6943-85fc-40b4-8e4e-7a3ce1e56a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753502165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1753502165
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1438865533
Short name T766
Test name
Test status
Simulation time 596522592 ps
CPU time 0.96 seconds
Started Jul 20 05:40:34 PM PDT 24
Finished Jul 20 05:40:36 PM PDT 24
Peak memory 207296 kb
Host smart-6a3572c8-2d56-44b5-9976-035b606744f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438865533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1438865533
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.964666469
Short name T274
Test name
Test status
Simulation time 153227186 ps
CPU time 2.95 seconds
Started Jul 20 05:40:35 PM PDT 24
Finished Jul 20 05:40:39 PM PDT 24
Peak memory 233064 kb
Host smart-aeaf3e61-7e64-4e25-ad7f-5fc9c0044959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964666469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.964666469
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3548252353
Short name T795
Test name
Test status
Simulation time 33603914 ps
CPU time 0.72 seconds
Started Jul 20 05:40:45 PM PDT 24
Finished Jul 20 05:40:47 PM PDT 24
Peak memory 206080 kb
Host smart-f087ef27-7765-4f6f-90e1-a37bef9a091e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548252353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3548252353
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1905721814
Short name T583
Test name
Test status
Simulation time 66997460 ps
CPU time 2.63 seconds
Started Jul 20 05:40:33 PM PDT 24
Finished Jul 20 05:40:36 PM PDT 24
Peak memory 233156 kb
Host smart-19889f48-1c74-4897-8977-cb9ae56014c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905721814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1905721814
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4144365867
Short name T960
Test name
Test status
Simulation time 24159677 ps
CPU time 0.79 seconds
Started Jul 20 05:40:36 PM PDT 24
Finished Jul 20 05:40:38 PM PDT 24
Peak memory 206872 kb
Host smart-bf38a47f-3725-4385-b5a0-bdc0c63d95c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144365867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4144365867
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3008434523
Short name T447
Test name
Test status
Simulation time 33917191535 ps
CPU time 44.39 seconds
Started Jul 20 05:40:45 PM PDT 24
Finished Jul 20 05:41:31 PM PDT 24
Peak memory 233212 kb
Host smart-60e59feb-cb6c-43ce-9f94-9a7bc2bd327d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008434523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3008434523
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1537292105
Short name T295
Test name
Test status
Simulation time 265159633892 ps
CPU time 253.7 seconds
Started Jul 20 05:40:44 PM PDT 24
Finished Jul 20 05:44:59 PM PDT 24
Peak memory 253780 kb
Host smart-54289376-8f28-4d0b-804f-4dfc50a3280e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537292105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1537292105
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2069888819
Short name T984
Test name
Test status
Simulation time 413788556 ps
CPU time 9.83 seconds
Started Jul 20 05:40:45 PM PDT 24
Finished Jul 20 05:40:55 PM PDT 24
Peak memory 237540 kb
Host smart-1f2b7ac1-0cd1-40cf-b830-30440019b89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069888819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2069888819
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3043902447
Short name T218
Test name
Test status
Simulation time 17692005879 ps
CPU time 116.18 seconds
Started Jul 20 05:40:44 PM PDT 24
Finished Jul 20 05:42:41 PM PDT 24
Peak memory 266104 kb
Host smart-9fa7e17d-e696-4665-a8dd-45101e01514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043902447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3043902447
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.469514492
Short name T185
Test name
Test status
Simulation time 1460797388 ps
CPU time 11.18 seconds
Started Jul 20 05:40:34 PM PDT 24
Finished Jul 20 05:40:47 PM PDT 24
Peak memory 224888 kb
Host smart-a60f6d65-b240-4484-800b-903f70e5468f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469514492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.469514492
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3684488348
Short name T890
Test name
Test status
Simulation time 815595181 ps
CPU time 3.92 seconds
Started Jul 20 05:40:34 PM PDT 24
Finished Jul 20 05:40:38 PM PDT 24
Peak memory 233148 kb
Host smart-7e93169e-d10d-4e14-a0bc-4a606e13994f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684488348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3684488348
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4176288595
Short name T524
Test name
Test status
Simulation time 2519861887 ps
CPU time 5.58 seconds
Started Jul 20 05:40:35 PM PDT 24
Finished Jul 20 05:40:42 PM PDT 24
Peak memory 233096 kb
Host smart-c1e58b22-e61a-4421-9117-4ea036203a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176288595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.4176288595
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2424252372
Short name T251
Test name
Test status
Simulation time 232980052 ps
CPU time 2.95 seconds
Started Jul 20 05:40:36 PM PDT 24
Finished Jul 20 05:40:40 PM PDT 24
Peak memory 233020 kb
Host smart-5ea0cae2-ab35-4833-b81f-6fc2f89a1df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424252372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2424252372
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1159545273
Short name T558
Test name
Test status
Simulation time 384611660 ps
CPU time 3.97 seconds
Started Jul 20 05:40:46 PM PDT 24
Finished Jul 20 05:40:50 PM PDT 24
Peak memory 223476 kb
Host smart-aad8bb6b-0bfd-4e6a-84fe-c4d47cd16426
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1159545273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1159545273
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.757220366
Short name T216
Test name
Test status
Simulation time 132093743539 ps
CPU time 347.62 seconds
Started Jul 20 05:40:47 PM PDT 24
Finished Jul 20 05:46:35 PM PDT 24
Peak memory 263424 kb
Host smart-52fe8891-2c88-44ba-a42c-a5e491233a26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757220366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.757220366
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1512464671
Short name T912
Test name
Test status
Simulation time 27092462119 ps
CPU time 30.65 seconds
Started Jul 20 05:40:34 PM PDT 24
Finished Jul 20 05:41:06 PM PDT 24
Peak memory 216788 kb
Host smart-16215bbc-b639-4360-91a1-0d71c47fb885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512464671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1512464671
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1378061321
Short name T880
Test name
Test status
Simulation time 1015304593 ps
CPU time 2.95 seconds
Started Jul 20 05:40:33 PM PDT 24
Finished Jul 20 05:40:37 PM PDT 24
Peak memory 216416 kb
Host smart-41627ad0-821f-42e3-9210-a9e58d4f0a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378061321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1378061321
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1871002124
Short name T708
Test name
Test status
Simulation time 81663548 ps
CPU time 2.04 seconds
Started Jul 20 05:40:32 PM PDT 24
Finished Jul 20 05:40:35 PM PDT 24
Peak memory 216752 kb
Host smart-3230d1f2-55c6-45f0-a44b-017fa4ceafb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871002124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1871002124
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3184746447
Short name T830
Test name
Test status
Simulation time 66479545 ps
CPU time 0.8 seconds
Started Jul 20 05:40:33 PM PDT 24
Finished Jul 20 05:40:35 PM PDT 24
Peak memory 206208 kb
Host smart-82926523-6555-4ab3-9229-5860cb3e9f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184746447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3184746447
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.315781922
Short name T479
Test name
Test status
Simulation time 339064882 ps
CPU time 3.01 seconds
Started Jul 20 05:40:37 PM PDT 24
Finished Jul 20 05:40:40 PM PDT 24
Peak memory 236700 kb
Host smart-279dec87-0200-42db-b4e7-133d8f735ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315781922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.315781922
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.413594786
Short name T780
Test name
Test status
Simulation time 127911642 ps
CPU time 0.72 seconds
Started Jul 20 05:40:45 PM PDT 24
Finished Jul 20 05:40:46 PM PDT 24
Peak memory 205764 kb
Host smart-9960f4c1-0ea8-4b69-b8cf-46c42a89867b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413594786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.413594786
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2096008315
Short name T943
Test name
Test status
Simulation time 3878677726 ps
CPU time 6.48 seconds
Started Jul 20 05:40:44 PM PDT 24
Finished Jul 20 05:40:51 PM PDT 24
Peak memory 233216 kb
Host smart-dd02fab9-d1e4-49c5-8e34-9e9541e6f786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096008315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2096008315
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4290560852
Short name T72
Test name
Test status
Simulation time 283980059 ps
CPU time 0.8 seconds
Started Jul 20 05:40:45 PM PDT 24
Finished Jul 20 05:40:47 PM PDT 24
Peak memory 206828 kb
Host smart-8b04401e-8b07-4711-aecb-2965b066e3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290560852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4290560852
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3075521806
Short name T810
Test name
Test status
Simulation time 4714899179 ps
CPU time 62.55 seconds
Started Jul 20 05:40:46 PM PDT 24
Finished Jul 20 05:41:49 PM PDT 24
Peak memory 251596 kb
Host smart-320dd7ab-3653-419f-a5dc-3047e36b8e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075521806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3075521806
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3127444203
Short name T281
Test name
Test status
Simulation time 46123605379 ps
CPU time 114.4 seconds
Started Jul 20 05:40:46 PM PDT 24
Finished Jul 20 05:42:41 PM PDT 24
Peak memory 251208 kb
Host smart-baf94d2e-b79b-4873-9e87-472455a61757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127444203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3127444203
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.434217549
Short name T987
Test name
Test status
Simulation time 19848471440 ps
CPU time 213.93 seconds
Started Jul 20 05:40:41 PM PDT 24
Finished Jul 20 05:44:16 PM PDT 24
Peak memory 268244 kb
Host smart-9b6ba844-d5ed-41af-a368-676e2e5d1422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434217549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.434217549
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2613457800
Short name T320
Test name
Test status
Simulation time 2079802588 ps
CPU time 19.63 seconds
Started Jul 20 05:40:44 PM PDT 24
Finished Jul 20 05:41:05 PM PDT 24
Peak memory 224892 kb
Host smart-ba1d04e8-081f-464d-8e2d-327b4624e0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613457800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2613457800
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3553778132
Short name T413
Test name
Test status
Simulation time 4776182285 ps
CPU time 34.48 seconds
Started Jul 20 05:40:48 PM PDT 24
Finished Jul 20 05:41:22 PM PDT 24
Peak memory 249696 kb
Host smart-20cda17c-17fc-4320-9fb8-62b41a2ca708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553778132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3553778132
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1949514644
Short name T533
Test name
Test status
Simulation time 215977036 ps
CPU time 2.25 seconds
Started Jul 20 05:40:44 PM PDT 24
Finished Jul 20 05:40:47 PM PDT 24
Peak memory 223568 kb
Host smart-de2287f2-ff26-49d2-9996-0b85b0d3bbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949514644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1949514644
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.34521579
Short name T282
Test name
Test status
Simulation time 2438113915 ps
CPU time 33.41 seconds
Started Jul 20 05:40:45 PM PDT 24
Finished Jul 20 05:41:19 PM PDT 24
Peak memory 239616 kb
Host smart-00461fa8-af15-45db-8d29-878ff8db53dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34521579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.34521579
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2142060799
Short name T213
Test name
Test status
Simulation time 8200118211 ps
CPU time 10.65 seconds
Started Jul 20 05:40:42 PM PDT 24
Finished Jul 20 05:40:54 PM PDT 24
Peak memory 233352 kb
Host smart-228fa263-4802-4437-847e-c22544f1f6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142060799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2142060799
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3280398795
Short name T685
Test name
Test status
Simulation time 3643847470 ps
CPU time 6.93 seconds
Started Jul 20 05:40:43 PM PDT 24
Finished Jul 20 05:40:51 PM PDT 24
Peak memory 225060 kb
Host smart-0a9e5bc3-fb36-4d37-a271-ac7cb58fbeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280398795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3280398795
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.852862182
Short name T6
Test name
Test status
Simulation time 461172611 ps
CPU time 6.86 seconds
Started Jul 20 05:40:44 PM PDT 24
Finished Jul 20 05:40:52 PM PDT 24
Peak memory 221936 kb
Host smart-e79065a8-7094-4d6b-a48f-98ca208dcd85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=852862182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.852862182
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2604169437
Short name T521
Test name
Test status
Simulation time 5464390800 ps
CPU time 13.1 seconds
Started Jul 20 05:40:47 PM PDT 24
Finished Jul 20 05:41:01 PM PDT 24
Peak memory 216828 kb
Host smart-6b872e56-28e7-4df6-8218-b2a4a4a8931f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604169437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2604169437
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3268629504
Short name T372
Test name
Test status
Simulation time 3110041256 ps
CPU time 1.96 seconds
Started Jul 20 05:40:44 PM PDT 24
Finished Jul 20 05:40:47 PM PDT 24
Peak memory 208372 kb
Host smart-70cf1bf6-dc8d-4be7-8138-4a3c8eedaff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268629504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3268629504
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3913167513
Short name T693
Test name
Test status
Simulation time 267384940 ps
CPU time 1.94 seconds
Started Jul 20 05:40:45 PM PDT 24
Finished Jul 20 05:40:48 PM PDT 24
Peak memory 216632 kb
Host smart-886ef3f0-6155-4931-a6d6-a722801d7fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913167513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3913167513
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.100629414
Short name T814
Test name
Test status
Simulation time 99129266 ps
CPU time 0.92 seconds
Started Jul 20 05:40:46 PM PDT 24
Finished Jul 20 05:40:48 PM PDT 24
Peak memory 206280 kb
Host smart-28e1c23e-d74e-4f21-8cc4-e09e3553d206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100629414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.100629414
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2429687471
Short name T517
Test name
Test status
Simulation time 2812139175 ps
CPU time 4.05 seconds
Started Jul 20 05:40:45 PM PDT 24
Finished Jul 20 05:40:50 PM PDT 24
Peak memory 224944 kb
Host smart-953171a1-855a-430b-ad07-0bd1e48aeecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429687471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2429687471
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.875331388
Short name T797
Test name
Test status
Simulation time 20544465 ps
CPU time 0.76 seconds
Started Jul 20 05:38:02 PM PDT 24
Finished Jul 20 05:38:04 PM PDT 24
Peak memory 205756 kb
Host smart-3be7dff1-1012-47cf-b3ff-9aa54121a260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875331388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.875331388
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2024191779
Short name T942
Test name
Test status
Simulation time 138597127 ps
CPU time 2.79 seconds
Started Jul 20 05:38:02 PM PDT 24
Finished Jul 20 05:38:07 PM PDT 24
Peak memory 224888 kb
Host smart-ed3238c5-c0a6-46b6-90b8-0c9803cbf9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024191779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2024191779
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.711339765
Short name T595
Test name
Test status
Simulation time 65706571 ps
CPU time 0.78 seconds
Started Jul 20 05:37:50 PM PDT 24
Finished Jul 20 05:37:53 PM PDT 24
Peak memory 205796 kb
Host smart-31d6ef0a-0425-416e-a98e-ce214b9fa133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711339765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.711339765
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3287365345
Short name T472
Test name
Test status
Simulation time 82085330398 ps
CPU time 170.29 seconds
Started Jul 20 05:38:01 PM PDT 24
Finished Jul 20 05:40:52 PM PDT 24
Peak memory 256412 kb
Host smart-c1a0f6bf-c218-47fd-815c-449ff5edb9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287365345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3287365345
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.604817552
Short name T299
Test name
Test status
Simulation time 14024019070 ps
CPU time 186.75 seconds
Started Jul 20 05:38:03 PM PDT 24
Finished Jul 20 05:41:12 PM PDT 24
Peak memory 264972 kb
Host smart-322c6b2a-38ad-496e-9bb1-b42893600794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604817552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.604817552
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1643262421
Short name T193
Test name
Test status
Simulation time 18010828304 ps
CPU time 144.93 seconds
Started Jul 20 05:38:02 PM PDT 24
Finished Jul 20 05:40:28 PM PDT 24
Peak memory 250928 kb
Host smart-c3344e0b-9d08-43a7-a003-36e879a2d53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643262421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1643262421
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2481975865
Short name T522
Test name
Test status
Simulation time 863949238 ps
CPU time 15.02 seconds
Started Jul 20 05:38:03 PM PDT 24
Finished Jul 20 05:38:20 PM PDT 24
Peak memory 234496 kb
Host smart-0733a1f8-fffb-4c38-afbf-833ddac69f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481975865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2481975865
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2453600770
Short name T369
Test name
Test status
Simulation time 444780859 ps
CPU time 8.74 seconds
Started Jul 20 05:38:02 PM PDT 24
Finished Jul 20 05:38:13 PM PDT 24
Peak memory 233060 kb
Host smart-0edaadeb-842a-4cf8-85a8-59a2d9f1ed00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453600770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2453600770
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.301102701
Short name T938
Test name
Test status
Simulation time 5443733029 ps
CPU time 13.41 seconds
Started Jul 20 05:38:02 PM PDT 24
Finished Jul 20 05:38:17 PM PDT 24
Peak memory 233212 kb
Host smart-b2b124cc-0963-4e68-8e77-3e0eb9a4f81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301102701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.301102701
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.862764661
Short name T936
Test name
Test status
Simulation time 12710068400 ps
CPU time 53.74 seconds
Started Jul 20 05:38:04 PM PDT 24
Finished Jul 20 05:39:00 PM PDT 24
Peak memory 225024 kb
Host smart-98878d3b-31f4-40d1-8918-7cc52efd4dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862764661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.862764661
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.716075415
Short name T44
Test name
Test status
Simulation time 17950661 ps
CPU time 1.02 seconds
Started Jul 20 05:37:50 PM PDT 24
Finished Jul 20 05:37:52 PM PDT 24
Peak memory 218404 kb
Host smart-9cdec76c-fe8d-4892-9db8-19e0c56c22c7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716075415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.716075415
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.210460020
Short name T277
Test name
Test status
Simulation time 4345426544 ps
CPU time 5.65 seconds
Started Jul 20 05:38:00 PM PDT 24
Finished Jul 20 05:38:07 PM PDT 24
Peak memory 225008 kb
Host smart-55bf3984-327b-425e-8e9d-96c6b3ca24d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210460020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
210460020
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2052541194
Short name T812
Test name
Test status
Simulation time 7783919625 ps
CPU time 16.58 seconds
Started Jul 20 05:38:02 PM PDT 24
Finished Jul 20 05:38:21 PM PDT 24
Peak memory 236636 kb
Host smart-edd36495-eb3b-42a7-af33-4f36da44b722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052541194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2052541194
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3664537185
Short name T148
Test name
Test status
Simulation time 131076455 ps
CPU time 4 seconds
Started Jul 20 05:38:00 PM PDT 24
Finished Jul 20 05:38:04 PM PDT 24
Peak memory 219748 kb
Host smart-93808afb-d54d-4065-9b3f-0fd4bae6fede
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3664537185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3664537185
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3738046748
Short name T19
Test name
Test status
Simulation time 61388401 ps
CPU time 1.04 seconds
Started Jul 20 05:38:01 PM PDT 24
Finished Jul 20 05:38:03 PM PDT 24
Peak memory 235800 kb
Host smart-4e4c4759-b2fb-490d-af1f-c15f4c80fcf2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738046748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3738046748
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.270974452
Short name T873
Test name
Test status
Simulation time 962743764 ps
CPU time 9.13 seconds
Started Jul 20 05:37:51 PM PDT 24
Finished Jul 20 05:38:02 PM PDT 24
Peak memory 216672 kb
Host smart-8d43f4ee-d0c8-41f7-9838-6a2a72a289da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270974452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.270974452
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3140375775
Short name T927
Test name
Test status
Simulation time 189741112 ps
CPU time 1 seconds
Started Jul 20 05:37:50 PM PDT 24
Finished Jul 20 05:37:53 PM PDT 24
Peak memory 207084 kb
Host smart-2439aa8e-8bbf-47e4-addb-dedbaf7fb300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140375775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3140375775
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.529742894
Short name T786
Test name
Test status
Simulation time 45161646 ps
CPU time 0.75 seconds
Started Jul 20 05:38:03 PM PDT 24
Finished Jul 20 05:38:06 PM PDT 24
Peak memory 206284 kb
Host smart-006dc4bf-24f3-4c33-9b52-cac98bfea156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529742894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.529742894
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3933971899
Short name T970
Test name
Test status
Simulation time 81585701 ps
CPU time 0.85 seconds
Started Jul 20 05:37:51 PM PDT 24
Finished Jul 20 05:37:53 PM PDT 24
Peak memory 206228 kb
Host smart-8f41e826-4ccc-4e29-8b23-c1c2ce4f532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933971899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3933971899
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.290014662
Short name T244
Test name
Test status
Simulation time 581541427 ps
CPU time 5.47 seconds
Started Jul 20 05:38:01 PM PDT 24
Finished Jul 20 05:38:07 PM PDT 24
Peak memory 234920 kb
Host smart-19a897c6-27ee-46f3-9cd6-e5ed6205549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290014662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.290014662
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.620623620
Short name T334
Test name
Test status
Simulation time 35987679 ps
CPU time 0.72 seconds
Started Jul 20 05:40:52 PM PDT 24
Finished Jul 20 05:40:54 PM PDT 24
Peak memory 205172 kb
Host smart-bb7857d9-1431-4e78-833b-fca9a81f9a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620623620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.620623620
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3793946221
Short name T261
Test name
Test status
Simulation time 428002735 ps
CPU time 2.46 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:40:58 PM PDT 24
Peak memory 224960 kb
Host smart-aae9fb26-1846-4afe-9b1c-5864d005685b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793946221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3793946221
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2900564552
Short name T439
Test name
Test status
Simulation time 48973480 ps
CPU time 0.83 seconds
Started Jul 20 05:40:45 PM PDT 24
Finished Jul 20 05:40:47 PM PDT 24
Peak memory 206828 kb
Host smart-35cc7d0d-ecea-4aa3-8d9d-c0a80f31b846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900564552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2900564552
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1383380608
Short name T536
Test name
Test status
Simulation time 11363627947 ps
CPU time 60.71 seconds
Started Jul 20 05:40:55 PM PDT 24
Finished Jul 20 05:41:57 PM PDT 24
Peak memory 251528 kb
Host smart-53cc716c-4400-4e31-95d5-8a1f0ed8da8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383380608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1383380608
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.587976898
Short name T653
Test name
Test status
Simulation time 3198360967 ps
CPU time 41.92 seconds
Started Jul 20 05:40:54 PM PDT 24
Finished Jul 20 05:41:38 PM PDT 24
Peak memory 241504 kb
Host smart-e46caef7-6afd-4bf7-8f50-164841e3e2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587976898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.587976898
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1834000174
Short name T1033
Test name
Test status
Simulation time 2832023365 ps
CPU time 72.43 seconds
Started Jul 20 05:40:56 PM PDT 24
Finished Jul 20 05:42:10 PM PDT 24
Peak memory 266080 kb
Host smart-8e1a2281-dca5-495e-91f1-f0ea96bf324d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834000174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1834000174
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1639418280
Short name T944
Test name
Test status
Simulation time 4914546107 ps
CPU time 20.06 seconds
Started Jul 20 05:40:52 PM PDT 24
Finished Jul 20 05:41:13 PM PDT 24
Peak memory 233284 kb
Host smart-093ad20b-e62a-47c6-a41a-db92f2388ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639418280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1639418280
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3752848806
Short name T165
Test name
Test status
Simulation time 1881660503 ps
CPU time 44.77 seconds
Started Jul 20 05:40:52 PM PDT 24
Finished Jul 20 05:41:38 PM PDT 24
Peak memory 256392 kb
Host smart-d2400e15-54d6-4bbb-a8e6-ff5819382ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752848806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3752848806
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4246723983
Short name T454
Test name
Test status
Simulation time 1106011205 ps
CPU time 6.25 seconds
Started Jul 20 05:40:47 PM PDT 24
Finished Jul 20 05:40:54 PM PDT 24
Peak memory 224552 kb
Host smart-14b81bc9-275f-47cc-b708-13e0b20da36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246723983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4246723983
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2022158421
Short name T388
Test name
Test status
Simulation time 2913824147 ps
CPU time 31.12 seconds
Started Jul 20 05:40:47 PM PDT 24
Finished Jul 20 05:41:19 PM PDT 24
Peak memory 240740 kb
Host smart-356f6831-b5c5-40fe-9895-328b756232ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022158421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2022158421
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4292730130
Short name T300
Test name
Test status
Simulation time 86855079258 ps
CPU time 19.52 seconds
Started Jul 20 05:40:45 PM PDT 24
Finished Jul 20 05:41:06 PM PDT 24
Peak memory 233252 kb
Host smart-5e9ce800-99ad-462e-9144-3367cc56aa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292730130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4292730130
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.686333197
Short name T427
Test name
Test status
Simulation time 1135013127 ps
CPU time 7.29 seconds
Started Jul 20 05:40:43 PM PDT 24
Finished Jul 20 05:40:51 PM PDT 24
Peak memory 241372 kb
Host smart-e84e3d39-d0d1-475c-9f7b-4619de1bea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686333197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.686333197
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3694285448
Short name T1000
Test name
Test status
Simulation time 11117407037 ps
CPU time 11.86 seconds
Started Jul 20 05:40:54 PM PDT 24
Finished Jul 20 05:41:08 PM PDT 24
Peak memory 223104 kb
Host smart-fbc414fd-1acc-4d35-9d59-f442bc606608
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3694285448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3694285448
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1640969777
Short name T910
Test name
Test status
Simulation time 86152221 ps
CPU time 0.93 seconds
Started Jul 20 05:40:54 PM PDT 24
Finished Jul 20 05:40:57 PM PDT 24
Peak memory 206892 kb
Host smart-78dacd9b-1e56-4215-9563-4af370a62819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640969777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1640969777
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3653023292
Short name T335
Test name
Test status
Simulation time 83137961 ps
CPU time 0.77 seconds
Started Jul 20 05:40:42 PM PDT 24
Finished Jul 20 05:40:44 PM PDT 24
Peak memory 206024 kb
Host smart-d2ecb1c4-17c1-4bd9-8f28-522f27b4a17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653023292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3653023292
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3513645577
Short name T384
Test name
Test status
Simulation time 82476594479 ps
CPU time 12.01 seconds
Started Jul 20 05:40:44 PM PDT 24
Finished Jul 20 05:40:56 PM PDT 24
Peak memory 217924 kb
Host smart-2f60fd41-2ce3-4a54-b6f7-0621f52da1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513645577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3513645577
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.213977363
Short name T363
Test name
Test status
Simulation time 106790146 ps
CPU time 1.1 seconds
Started Jul 20 05:40:45 PM PDT 24
Finished Jul 20 05:40:47 PM PDT 24
Peak memory 207620 kb
Host smart-cb4c7e79-ec2d-449f-be03-822a4c55a1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213977363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.213977363
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.854180194
Short name T1018
Test name
Test status
Simulation time 16171901 ps
CPU time 0.69 seconds
Started Jul 20 05:40:43 PM PDT 24
Finished Jul 20 05:40:44 PM PDT 24
Peak memory 205904 kb
Host smart-126c0082-f048-4130-ba52-cd8add496235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854180194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.854180194
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1728163875
Short name T768
Test name
Test status
Simulation time 470627212 ps
CPU time 4.46 seconds
Started Jul 20 05:40:52 PM PDT 24
Finished Jul 20 05:40:57 PM PDT 24
Peak memory 224860 kb
Host smart-29d7c28a-ecb8-49a1-936b-5827add15086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728163875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1728163875
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1623890579
Short name T841
Test name
Test status
Simulation time 43930182 ps
CPU time 0.73 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:40:56 PM PDT 24
Peak memory 205776 kb
Host smart-6e649b3e-deec-4ed2-91dc-b3b674026c08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623890579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1623890579
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2076909879
Short name T820
Test name
Test status
Simulation time 553075795 ps
CPU time 4.33 seconds
Started Jul 20 05:40:50 PM PDT 24
Finished Jul 20 05:40:54 PM PDT 24
Peak memory 233200 kb
Host smart-24ea2089-309e-4277-b686-4d0d3088ea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076909879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2076909879
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2363002520
Short name T340
Test name
Test status
Simulation time 33176192 ps
CPU time 0.78 seconds
Started Jul 20 05:40:52 PM PDT 24
Finished Jul 20 05:40:54 PM PDT 24
Peak memory 206840 kb
Host smart-73ed50a5-af9c-4a10-9c97-f4d9d65a71b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363002520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2363002520
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1836786741
Short name T863
Test name
Test status
Simulation time 38214167879 ps
CPU time 251.08 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:45:06 PM PDT 24
Peak memory 252012 kb
Host smart-8c0576b4-d166-42f3-8541-4d0633968042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836786741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1836786741
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.450235893
Short name T715
Test name
Test status
Simulation time 21714987059 ps
CPU time 60.93 seconds
Started Jul 20 05:40:55 PM PDT 24
Finished Jul 20 05:41:58 PM PDT 24
Peak memory 249320 kb
Host smart-3aa7c9c3-f7b2-43ac-a176-7900e0322b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450235893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.450235893
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1283575896
Short name T289
Test name
Test status
Simulation time 37632235008 ps
CPU time 394.18 seconds
Started Jul 20 05:40:54 PM PDT 24
Finished Jul 20 05:47:31 PM PDT 24
Peak memory 263160 kb
Host smart-7fb0e439-f282-49ea-b23f-3af50778759f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283575896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1283575896
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1429551723
Short name T760
Test name
Test status
Simulation time 169017626 ps
CPU time 6.85 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:41:02 PM PDT 24
Peak memory 249520 kb
Host smart-521a6b34-2ea3-4aa9-af9f-ec6f18d95eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429551723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1429551723
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2251418230
Short name T892
Test name
Test status
Simulation time 110277499 ps
CPU time 3.05 seconds
Started Jul 20 05:40:55 PM PDT 24
Finished Jul 20 05:41:00 PM PDT 24
Peak memory 233112 kb
Host smart-da58ccb8-a18e-4974-8491-991a1b89fae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251418230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2251418230
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2290686162
Short name T625
Test name
Test status
Simulation time 2052245343 ps
CPU time 12.25 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:41:07 PM PDT 24
Peak memory 240504 kb
Host smart-a53d0a15-549b-45b8-b39a-fc90b89036f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290686162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2290686162
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2952482035
Short name T52
Test name
Test status
Simulation time 1815813683 ps
CPU time 8.25 seconds
Started Jul 20 05:40:51 PM PDT 24
Finished Jul 20 05:41:00 PM PDT 24
Peak memory 233092 kb
Host smart-f66b5477-2ec7-4de8-ad77-630dfd6d3e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952482035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2952482035
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2670403618
Short name T337
Test name
Test status
Simulation time 352737917 ps
CPU time 2.21 seconds
Started Jul 20 05:40:55 PM PDT 24
Finished Jul 20 05:40:59 PM PDT 24
Peak memory 223620 kb
Host smart-73f73bf5-7412-4fce-920f-44eb6a086c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670403618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2670403618
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2165903472
Short name T364
Test name
Test status
Simulation time 1599658948 ps
CPU time 11.44 seconds
Started Jul 20 05:40:52 PM PDT 24
Finished Jul 20 05:41:05 PM PDT 24
Peak memory 219196 kb
Host smart-6ae12c1c-ad40-4dd9-b169-84284a8c09c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2165903472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2165903472
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3306087383
Short name T740
Test name
Test status
Simulation time 13799220994 ps
CPU time 51.78 seconds
Started Jul 20 05:40:51 PM PDT 24
Finished Jul 20 05:41:43 PM PDT 24
Peak memory 239484 kb
Host smart-1f07814b-4287-485a-a462-870f2693749d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306087383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3306087383
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1626477251
Short name T327
Test name
Test status
Simulation time 2222233940 ps
CPU time 3.83 seconds
Started Jul 20 05:40:55 PM PDT 24
Finished Jul 20 05:41:01 PM PDT 24
Peak memory 216756 kb
Host smart-cf1276fd-4146-43e9-b7b4-ffd6d7aa91d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626477251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1626477251
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2400997932
Short name T561
Test name
Test status
Simulation time 3321510090 ps
CPU time 4.62 seconds
Started Jul 20 05:40:54 PM PDT 24
Finished Jul 20 05:41:00 PM PDT 24
Peak memory 216784 kb
Host smart-8f49956a-c032-4fa1-af62-72e55fa699dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400997932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2400997932
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.209952483
Short name T562
Test name
Test status
Simulation time 498815907 ps
CPU time 1.45 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:40:57 PM PDT 24
Peak memory 216596 kb
Host smart-d99fead0-2e83-4610-a955-07964822ae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209952483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.209952483
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1247376001
Short name T485
Test name
Test status
Simulation time 17122647 ps
CPU time 0.74 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:40:56 PM PDT 24
Peak memory 205944 kb
Host smart-f7e0771e-6e49-4518-88d4-14973541542e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247376001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1247376001
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2034369553
Short name T761
Test name
Test status
Simulation time 21031653713 ps
CPU time 35.44 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:41:31 PM PDT 24
Peak memory 240484 kb
Host smart-4f467265-1c1a-45fe-83a5-5d24c727e5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034369553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2034369553
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1852982324
Short name T373
Test name
Test status
Simulation time 47910072 ps
CPU time 0.76 seconds
Started Jul 20 05:40:54 PM PDT 24
Finished Jul 20 05:40:56 PM PDT 24
Peak memory 205180 kb
Host smart-77cc3935-fa03-426b-8067-84a4cd28195c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852982324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1852982324
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2376908210
Short name T563
Test name
Test status
Simulation time 191199702 ps
CPU time 4.05 seconds
Started Jul 20 05:40:54 PM PDT 24
Finished Jul 20 05:41:00 PM PDT 24
Peak memory 224896 kb
Host smart-aace9be8-12fc-489d-a042-a6068d22c5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376908210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2376908210
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2643204457
Short name T843
Test name
Test status
Simulation time 28886137 ps
CPU time 0.79 seconds
Started Jul 20 05:40:51 PM PDT 24
Finished Jul 20 05:40:52 PM PDT 24
Peak memory 205912 kb
Host smart-431b3273-bd28-46b9-9fe1-53c818a75e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643204457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2643204457
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.215231492
Short name T432
Test name
Test status
Simulation time 14848429 ps
CPU time 0.77 seconds
Started Jul 20 05:40:54 PM PDT 24
Finished Jul 20 05:40:57 PM PDT 24
Peak memory 216232 kb
Host smart-7df9a0ff-1aaa-4dab-805a-1975b8e281d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215231492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.215231492
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1351599903
Short name T705
Test name
Test status
Simulation time 31369186343 ps
CPU time 60.96 seconds
Started Jul 20 05:40:54 PM PDT 24
Finished Jul 20 05:41:58 PM PDT 24
Peak memory 254912 kb
Host smart-535dd73b-8ef4-4b3c-988f-d83f88d7d843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351599903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1351599903
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1777014458
Short name T220
Test name
Test status
Simulation time 6066907283 ps
CPU time 73.68 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:42:09 PM PDT 24
Peak memory 255740 kb
Host smart-ba7ec57f-1be1-430e-8eda-ec80edc0d043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777014458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1777014458
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.4054587010
Short name T1026
Test name
Test status
Simulation time 22807007686 ps
CPU time 24.84 seconds
Started Jul 20 05:40:52 PM PDT 24
Finished Jul 20 05:41:18 PM PDT 24
Peak memory 240012 kb
Host smart-1498d70e-e472-403d-82cc-494d4d0964b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054587010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4054587010
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.535361214
Short name T2
Test name
Test status
Simulation time 1662522722 ps
CPU time 22.5 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:41:16 PM PDT 24
Peak memory 235396 kb
Host smart-fa667726-6058-4da7-858c-49b33875cfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535361214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.535361214
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.75157195
Short name T749
Test name
Test status
Simulation time 790187433 ps
CPU time 5.6 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:41:01 PM PDT 24
Peak memory 233116 kb
Host smart-038c70b5-b477-410d-b2ed-9346b9375604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75157195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.75157195
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.632612921
Short name T210
Test name
Test status
Simulation time 5530887366 ps
CPU time 18.76 seconds
Started Jul 20 05:40:56 PM PDT 24
Finished Jul 20 05:41:16 PM PDT 24
Peak memory 235080 kb
Host smart-6e4410ba-165a-4261-b19d-5042de171cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632612921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.632612921
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1634871113
Short name T771
Test name
Test status
Simulation time 1608038941 ps
CPU time 10.64 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:41:05 PM PDT 24
Peak memory 236532 kb
Host smart-f6006abf-f7c5-49a5-bbcf-67c0b8091f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634871113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1634871113
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3908346099
Short name T956
Test name
Test status
Simulation time 15071840993 ps
CPU time 17.54 seconds
Started Jul 20 05:40:55 PM PDT 24
Finished Jul 20 05:41:15 PM PDT 24
Peak memory 233212 kb
Host smart-b58c1d4e-adc8-478f-b891-459b799f69a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908346099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3908346099
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1438825402
Short name T408
Test name
Test status
Simulation time 1181375676 ps
CPU time 4.1 seconds
Started Jul 20 05:40:54 PM PDT 24
Finished Jul 20 05:41:00 PM PDT 24
Peak memory 220660 kb
Host smart-261e2ebf-4064-4ac1-a047-bfad5c2dc3b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1438825402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1438825402
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4110468944
Short name T42
Test name
Test status
Simulation time 49514475466 ps
CPU time 141.51 seconds
Started Jul 20 05:40:52 PM PDT 24
Finished Jul 20 05:43:14 PM PDT 24
Peak memory 265728 kb
Host smart-601f0e70-f445-42f3-a6e6-18b6ddf80d3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110468944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4110468944
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3321365552
Short name T736
Test name
Test status
Simulation time 6907356125 ps
CPU time 14.6 seconds
Started Jul 20 05:40:56 PM PDT 24
Finished Jul 20 05:41:12 PM PDT 24
Peak memory 216772 kb
Host smart-a11be0ab-da46-4a0c-81c5-f0a1d47ffe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321365552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3321365552
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.276305706
Short name T518
Test name
Test status
Simulation time 1462382624 ps
CPU time 5 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:40:59 PM PDT 24
Peak memory 216612 kb
Host smart-671dc675-ca76-4ae1-bc1e-87fb341b020e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276305706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.276305706
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2045900995
Short name T578
Test name
Test status
Simulation time 280783639 ps
CPU time 1.72 seconds
Started Jul 20 05:40:54 PM PDT 24
Finished Jul 20 05:40:58 PM PDT 24
Peak memory 216520 kb
Host smart-c7f51c67-b319-4121-9d80-896918a0f603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045900995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2045900995
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2354651892
Short name T831
Test name
Test status
Simulation time 45781974 ps
CPU time 0.77 seconds
Started Jul 20 05:40:56 PM PDT 24
Finished Jul 20 05:40:58 PM PDT 24
Peak memory 206256 kb
Host smart-fb4fbe1a-b93f-4a71-882d-9e5a7f812d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354651892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2354651892
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.4263560034
Short name T253
Test name
Test status
Simulation time 503780089 ps
CPU time 6.6 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:41:02 PM PDT 24
Peak memory 233164 kb
Host smart-c581368b-b4e0-459e-8812-2541d577a572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263560034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.4263560034
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2419310481
Short name T694
Test name
Test status
Simulation time 39267274 ps
CPU time 0.76 seconds
Started Jul 20 05:41:09 PM PDT 24
Finished Jul 20 05:41:11 PM PDT 24
Peak memory 205124 kb
Host smart-dacc8d26-a25c-44b3-807c-db3c1ce03f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419310481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2419310481
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.320158825
Short name T1025
Test name
Test status
Simulation time 3163755233 ps
CPU time 18.38 seconds
Started Jul 20 05:40:58 PM PDT 24
Finished Jul 20 05:41:17 PM PDT 24
Peak memory 225076 kb
Host smart-e2e91d22-7b06-4002-bc6a-25eb1cb5a50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320158825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.320158825
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3975572202
Short name T136
Test name
Test status
Simulation time 56531374 ps
CPU time 0.8 seconds
Started Jul 20 05:40:55 PM PDT 24
Finished Jul 20 05:40:58 PM PDT 24
Peak memory 206856 kb
Host smart-02653727-e684-4df9-973d-39d7a13923f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975572202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3975572202
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3187997005
Short name T765
Test name
Test status
Simulation time 19377076254 ps
CPU time 79.67 seconds
Started Jul 20 05:41:06 PM PDT 24
Finished Jul 20 05:42:27 PM PDT 24
Peak memory 262552 kb
Host smart-2badaded-dcbb-4bf1-9c4a-638b5c85834f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187997005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3187997005
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4042204287
Short name T464
Test name
Test status
Simulation time 88308657911 ps
CPU time 91.33 seconds
Started Jul 20 05:41:09 PM PDT 24
Finished Jul 20 05:42:41 PM PDT 24
Peak memory 249860 kb
Host smart-6df1f583-a8de-462b-826f-563d4400d892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042204287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4042204287
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3637029155
Short name T316
Test name
Test status
Simulation time 158916937 ps
CPU time 11.08 seconds
Started Jul 20 05:41:09 PM PDT 24
Finished Jul 20 05:41:21 PM PDT 24
Peak memory 233088 kb
Host smart-57c56a59-d1ce-426c-8e1e-d812fc40baa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637029155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3637029155
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2717943004
Short name T302
Test name
Test status
Simulation time 4717200413 ps
CPU time 57.5 seconds
Started Jul 20 05:41:02 PM PDT 24
Finished Jul 20 05:42:01 PM PDT 24
Peak memory 266048 kb
Host smart-95b0ed24-d51f-47a5-9dd0-e7d046f18dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717943004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2717943004
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2489261805
Short name T727
Test name
Test status
Simulation time 2365197290 ps
CPU time 11.7 seconds
Started Jul 20 05:41:03 PM PDT 24
Finished Jul 20 05:41:16 PM PDT 24
Peak memory 225040 kb
Host smart-cb42472e-b1f1-43b4-a883-5339f7e707e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489261805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2489261805
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3135529922
Short name T784
Test name
Test status
Simulation time 14458089056 ps
CPU time 40.55 seconds
Started Jul 20 05:41:03 PM PDT 24
Finished Jul 20 05:41:44 PM PDT 24
Peak memory 249448 kb
Host smart-c5c70f3e-ee7c-4808-bb32-4a6d7a12e8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135529922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3135529922
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3985941367
Short name T570
Test name
Test status
Simulation time 13731696308 ps
CPU time 14.95 seconds
Started Jul 20 05:41:00 PM PDT 24
Finished Jul 20 05:41:15 PM PDT 24
Peak memory 233220 kb
Host smart-5d0e24c4-a2ac-4482-b837-71fcad09c265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985941367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3985941367
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3998652438
Short name T501
Test name
Test status
Simulation time 6578148781 ps
CPU time 12.16 seconds
Started Jul 20 05:40:54 PM PDT 24
Finished Jul 20 05:41:09 PM PDT 24
Peak memory 233172 kb
Host smart-e4707f0e-bac6-417f-b8b4-b91df6d770da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998652438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3998652438
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2930403605
Short name T147
Test name
Test status
Simulation time 294916911 ps
CPU time 4.54 seconds
Started Jul 20 05:41:08 PM PDT 24
Finished Jul 20 05:41:14 PM PDT 24
Peak memory 222708 kb
Host smart-df158d4b-46f3-49f0-83e2-17a9d6042c27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2930403605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2930403605
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3889412372
Short name T1014
Test name
Test status
Simulation time 234702832 ps
CPU time 1.05 seconds
Started Jul 20 05:41:01 PM PDT 24
Finished Jul 20 05:41:03 PM PDT 24
Peak memory 208048 kb
Host smart-45da04af-d645-4466-a72b-3a610a1b998b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889412372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3889412372
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.92640520
Short name T587
Test name
Test status
Simulation time 116021819836 ps
CPU time 47.73 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:41:43 PM PDT 24
Peak memory 216784 kb
Host smart-47eee7e5-d053-43e2-b891-c67da5e196c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92640520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.92640520
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2444355857
Short name T7
Test name
Test status
Simulation time 5954576387 ps
CPU time 9.14 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:41:04 PM PDT 24
Peak memory 216716 kb
Host smart-58b2ec18-065d-458e-ac5c-bfadf9fec71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444355857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2444355857
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2971913584
Short name T999
Test name
Test status
Simulation time 61268195 ps
CPU time 1.14 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:40:55 PM PDT 24
Peak memory 216416 kb
Host smart-66139614-ced1-43a4-b9d7-00dfff0c42b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971913584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2971913584
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4029376300
Short name T505
Test name
Test status
Simulation time 61512720 ps
CPU time 0.8 seconds
Started Jul 20 05:40:53 PM PDT 24
Finished Jul 20 05:40:55 PM PDT 24
Peak memory 206208 kb
Host smart-3e39ad3d-c7e0-46f6-86b0-d9ea52f44585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029376300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4029376300
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.761588893
Short name T1024
Test name
Test status
Simulation time 24688572440 ps
CPU time 17.21 seconds
Started Jul 20 05:41:09 PM PDT 24
Finished Jul 20 05:41:27 PM PDT 24
Peak memory 225080 kb
Host smart-1863d414-e3f6-4cff-9585-8179fa86de2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761588893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.761588893
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4002042014
Short name T355
Test name
Test status
Simulation time 12306378 ps
CPU time 0.76 seconds
Started Jul 20 05:41:11 PM PDT 24
Finished Jul 20 05:41:13 PM PDT 24
Peak memory 204948 kb
Host smart-0a687b76-8438-4de0-8ede-c258ef7b8280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002042014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4002042014
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3822074999
Short name T368
Test name
Test status
Simulation time 122479661 ps
CPU time 3.53 seconds
Started Jul 20 05:41:09 PM PDT 24
Finished Jul 20 05:41:13 PM PDT 24
Peak memory 233016 kb
Host smart-4edabcdb-48ce-4e3d-8c21-f6b3e6602ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822074999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3822074999
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1330696393
Short name T567
Test name
Test status
Simulation time 65542485 ps
CPU time 0.82 seconds
Started Jul 20 05:41:11 PM PDT 24
Finished Jul 20 05:41:13 PM PDT 24
Peak memory 206720 kb
Host smart-292074eb-4d3e-4238-9241-f1d0a6b5afe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330696393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1330696393
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.766869449
Short name T606
Test name
Test status
Simulation time 58856098 ps
CPU time 0.97 seconds
Started Jul 20 05:41:07 PM PDT 24
Finished Jul 20 05:41:09 PM PDT 24
Peak memory 216512 kb
Host smart-33c09a9c-95bb-406c-991e-9a6a4b9c4b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766869449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.766869449
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2096193169
Short name T217
Test name
Test status
Simulation time 200478829033 ps
CPU time 187.43 seconds
Started Jul 20 05:41:11 PM PDT 24
Finished Jul 20 05:44:20 PM PDT 24
Peak memory 255572 kb
Host smart-bdc17ba9-c902-4576-8d64-7e4c8c818d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096193169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2096193169
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2549672318
Short name T747
Test name
Test status
Simulation time 26746180355 ps
CPU time 135.04 seconds
Started Jul 20 05:41:09 PM PDT 24
Finished Jul 20 05:43:25 PM PDT 24
Peak memory 247896 kb
Host smart-ab1dd60d-d84e-4a51-9322-f47d1760d7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549672318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2549672318
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.505174227
Short name T662
Test name
Test status
Simulation time 124220779 ps
CPU time 2.72 seconds
Started Jul 20 05:41:08 PM PDT 24
Finished Jul 20 05:41:12 PM PDT 24
Peak memory 233120 kb
Host smart-f68f053b-5f92-4827-89fa-b647c958c227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505174227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.505174227
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.4115431088
Short name T90
Test name
Test status
Simulation time 12976266366 ps
CPU time 39.31 seconds
Started Jul 20 05:41:04 PM PDT 24
Finished Jul 20 05:41:44 PM PDT 24
Peak memory 250796 kb
Host smart-6190402d-069f-41fb-839b-d648e54ef71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115431088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.4115431088
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3621663459
Short name T726
Test name
Test status
Simulation time 150809341 ps
CPU time 2.4 seconds
Started Jul 20 05:41:00 PM PDT 24
Finished Jul 20 05:41:03 PM PDT 24
Peak memory 233164 kb
Host smart-74b06e4b-38ea-459b-84b7-9a78114dbc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621663459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3621663459
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.460080720
Short name T899
Test name
Test status
Simulation time 11126009298 ps
CPU time 10.86 seconds
Started Jul 20 05:41:02 PM PDT 24
Finished Jul 20 05:41:14 PM PDT 24
Peak memory 241200 kb
Host smart-4be8437c-530e-4ee8-b6de-9e0c13bc939f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460080720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.460080720
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3346348450
Short name T94
Test name
Test status
Simulation time 3509552171 ps
CPU time 9.92 seconds
Started Jul 20 05:41:08 PM PDT 24
Finished Jul 20 05:41:19 PM PDT 24
Peak memory 233240 kb
Host smart-a1c48b96-0b63-40ee-a44b-bd8d2dc473ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346348450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3346348450
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1348613698
Short name T276
Test name
Test status
Simulation time 4752019901 ps
CPU time 18.47 seconds
Started Jul 20 05:41:03 PM PDT 24
Finished Jul 20 05:41:22 PM PDT 24
Peak memory 240028 kb
Host smart-ea0c7335-0f59-414c-ac16-5bc145ac0357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348613698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1348613698
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.4162515940
Short name T669
Test name
Test status
Simulation time 1989491757 ps
CPU time 6.18 seconds
Started Jul 20 05:41:02 PM PDT 24
Finished Jul 20 05:41:08 PM PDT 24
Peak memory 222420 kb
Host smart-0d090f58-884b-41a7-bfba-9f7ef1c1d761
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4162515940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.4162515940
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2828638641
Short name T269
Test name
Test status
Simulation time 19002167821 ps
CPU time 141.62 seconds
Started Jul 20 05:41:02 PM PDT 24
Finished Jul 20 05:43:24 PM PDT 24
Peak memory 257836 kb
Host smart-2515ccd5-dad3-482c-aba7-73001a1a4f75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828638641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2828638641
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1798976927
Short name T61
Test name
Test status
Simulation time 828131527 ps
CPU time 2.96 seconds
Started Jul 20 05:41:02 PM PDT 24
Finished Jul 20 05:41:06 PM PDT 24
Peak memory 217684 kb
Host smart-bf8ea87e-f08d-4b15-9ce9-a25ad2aefa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798976927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1798976927
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.413838306
Short name T415
Test name
Test status
Simulation time 522053809 ps
CPU time 3.75 seconds
Started Jul 20 05:41:08 PM PDT 24
Finished Jul 20 05:41:13 PM PDT 24
Peak memory 216676 kb
Host smart-d2713489-ccf8-45c8-b235-467361968c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413838306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.413838306
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1881742303
Short name T548
Test name
Test status
Simulation time 21587622 ps
CPU time 1.01 seconds
Started Jul 20 05:41:02 PM PDT 24
Finished Jul 20 05:41:04 PM PDT 24
Peak memory 207820 kb
Host smart-46139c55-512c-4d8b-8948-9e221de1616b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881742303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1881742303
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1671183050
Short name T989
Test name
Test status
Simulation time 18633593 ps
CPU time 0.76 seconds
Started Jul 20 05:41:08 PM PDT 24
Finished Jul 20 05:41:09 PM PDT 24
Peak memory 206252 kb
Host smart-384d8839-1b39-4cf7-b86d-277fc43944a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671183050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1671183050
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3870723483
Short name T861
Test name
Test status
Simulation time 291278984 ps
CPU time 2.68 seconds
Started Jul 20 05:41:09 PM PDT 24
Finished Jul 20 05:41:13 PM PDT 24
Peak memory 233128 kb
Host smart-14e5803c-d6da-4bd1-ba0d-4064fa76984e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870723483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3870723483
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2776538312
Short name T551
Test name
Test status
Simulation time 40355307 ps
CPU time 0.7 seconds
Started Jul 20 05:41:19 PM PDT 24
Finished Jul 20 05:41:21 PM PDT 24
Peak memory 206088 kb
Host smart-74b760c6-73d2-457f-913f-842d95e07536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776538312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2776538312
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.545840080
Short name T332
Test name
Test status
Simulation time 133952356 ps
CPU time 2.09 seconds
Started Jul 20 05:41:11 PM PDT 24
Finished Jul 20 05:41:14 PM PDT 24
Peak memory 224432 kb
Host smart-71b1fa58-a20c-457e-a073-40ce0fb648cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545840080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.545840080
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2112977174
Short name T626
Test name
Test status
Simulation time 15320106 ps
CPU time 0.86 seconds
Started Jul 20 05:41:07 PM PDT 24
Finished Jul 20 05:41:08 PM PDT 24
Peak memory 207220 kb
Host smart-bf921841-8d49-4a1e-81df-eb347ca517d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112977174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2112977174
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.555739703
Short name T641
Test name
Test status
Simulation time 13265016 ps
CPU time 0.77 seconds
Started Jul 20 05:41:17 PM PDT 24
Finished Jul 20 05:41:18 PM PDT 24
Peak memory 216284 kb
Host smart-b0296a44-574e-4aa9-86b4-1018db162ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555739703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.555739703
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1014414701
Short name T947
Test name
Test status
Simulation time 106613553535 ps
CPU time 462.45 seconds
Started Jul 20 05:41:09 PM PDT 24
Finished Jul 20 05:48:52 PM PDT 24
Peak memory 257900 kb
Host smart-3b1d5b18-faf6-41eb-b7cf-35b2caff9b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014414701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1014414701
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3661213806
Short name T817
Test name
Test status
Simulation time 13752399710 ps
CPU time 121.44 seconds
Started Jul 20 05:41:14 PM PDT 24
Finished Jul 20 05:43:16 PM PDT 24
Peak memory 238840 kb
Host smart-2098694b-559f-497a-818e-30a6f4bac878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661213806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3661213806
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2166822566
Short name T1019
Test name
Test status
Simulation time 1154860358 ps
CPU time 22.49 seconds
Started Jul 20 05:41:11 PM PDT 24
Finished Jul 20 05:41:35 PM PDT 24
Peak memory 241308 kb
Host smart-23a25f7e-ff0e-4472-ad32-88543b593559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166822566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2166822566
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2385828554
Short name T959
Test name
Test status
Simulation time 23281210927 ps
CPU time 144.94 seconds
Started Jul 20 05:41:12 PM PDT 24
Finished Jul 20 05:43:38 PM PDT 24
Peak memory 253484 kb
Host smart-87b9735e-0edf-44e8-a8b9-62b1148de534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385828554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2385828554
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.866098392
Short name T941
Test name
Test status
Simulation time 647701128 ps
CPU time 7.85 seconds
Started Jul 20 05:41:10 PM PDT 24
Finished Jul 20 05:41:19 PM PDT 24
Peak memory 233116 kb
Host smart-61a80684-6d30-422c-8a61-c19074d1af63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866098392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.866098392
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2403583086
Short name T703
Test name
Test status
Simulation time 88954940 ps
CPU time 3.18 seconds
Started Jul 20 05:41:09 PM PDT 24
Finished Jul 20 05:41:14 PM PDT 24
Peak memory 233144 kb
Host smart-d299b0e8-d736-4ab4-9751-b3f3e07dbad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403583086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2403583086
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.236556556
Short name T459
Test name
Test status
Simulation time 490527610 ps
CPU time 7.17 seconds
Started Jul 20 05:41:03 PM PDT 24
Finished Jul 20 05:41:10 PM PDT 24
Peak memory 233112 kb
Host smart-db2927a5-c715-4e23-b2ff-e4dec83be2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236556556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.236556556
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3419305250
Short name T229
Test name
Test status
Simulation time 4099854174 ps
CPU time 7.42 seconds
Started Jul 20 05:41:01 PM PDT 24
Finished Jul 20 05:41:09 PM PDT 24
Peak memory 225044 kb
Host smart-d641e164-8a5e-4812-8fa1-6f751b9d6ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419305250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3419305250
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1378581125
Short name T386
Test name
Test status
Simulation time 154576832 ps
CPU time 3.52 seconds
Started Jul 20 05:41:17 PM PDT 24
Finished Jul 20 05:41:21 PM PDT 24
Peak memory 220752 kb
Host smart-13e1a0f4-2b0c-45a7-aaac-817a26f61c16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1378581125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1378581125
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2747891103
Short name T1013
Test name
Test status
Simulation time 49782605 ps
CPU time 0.98 seconds
Started Jul 20 05:41:11 PM PDT 24
Finished Jul 20 05:41:13 PM PDT 24
Peak memory 207140 kb
Host smart-e9d30853-33a6-4f14-a728-eebcc0d01d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747891103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2747891103
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2085346439
Short name T516
Test name
Test status
Simulation time 29995628558 ps
CPU time 25.53 seconds
Started Jul 20 05:41:01 PM PDT 24
Finished Jul 20 05:41:27 PM PDT 24
Peak memory 216872 kb
Host smart-3ce3ad12-0f29-498b-bb54-fb3be5aa53fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085346439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2085346439
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3180733523
Short name T712
Test name
Test status
Simulation time 13256223975 ps
CPU time 10.21 seconds
Started Jul 20 05:41:03 PM PDT 24
Finished Jul 20 05:41:14 PM PDT 24
Peak memory 216812 kb
Host smart-c50a6bf0-5d39-422f-993f-34487868a6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180733523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3180733523
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3230838773
Short name T717
Test name
Test status
Simulation time 74660680 ps
CPU time 1.32 seconds
Started Jul 20 05:41:08 PM PDT 24
Finished Jul 20 05:41:09 PM PDT 24
Peak memory 216676 kb
Host smart-3e9a445d-b5e8-48bc-8116-ce2fb667adea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230838773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3230838773
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3203136103
Short name T1002
Test name
Test status
Simulation time 33750796 ps
CPU time 0.69 seconds
Started Jul 20 05:41:01 PM PDT 24
Finished Jul 20 05:41:02 PM PDT 24
Peak memory 205932 kb
Host smart-5e19a1f8-1fd3-4f7c-9e00-ef6efa08dc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203136103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3203136103
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.804387326
Short name T907
Test name
Test status
Simulation time 1392063189 ps
CPU time 6.8 seconds
Started Jul 20 05:41:10 PM PDT 24
Finished Jul 20 05:41:18 PM PDT 24
Peak memory 224908 kb
Host smart-6108168b-2937-4280-856c-05b3010aebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804387326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.804387326
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.599314817
Short name T433
Test name
Test status
Simulation time 42859928 ps
CPU time 0.74 seconds
Started Jul 20 05:41:11 PM PDT 24
Finished Jul 20 05:41:13 PM PDT 24
Peak memory 206012 kb
Host smart-0755042a-e979-4754-b8a5-356dd91b1e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599314817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.599314817
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4130617180
Short name T504
Test name
Test status
Simulation time 14045712506 ps
CPU time 17.11 seconds
Started Jul 20 05:41:11 PM PDT 24
Finished Jul 20 05:41:29 PM PDT 24
Peak memory 233188 kb
Host smart-42dc6f0c-9b40-4aa3-a2db-d21212b10abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130617180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4130617180
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2705281009
Short name T571
Test name
Test status
Simulation time 178470998 ps
CPU time 0.73 seconds
Started Jul 20 05:41:11 PM PDT 24
Finished Jul 20 05:41:13 PM PDT 24
Peak memory 205840 kb
Host smart-a4cbe4c3-202d-4ac6-949d-ceb9d6d50fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705281009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2705281009
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3591105953
Short name T192
Test name
Test status
Simulation time 36077093511 ps
CPU time 129.67 seconds
Started Jul 20 05:41:12 PM PDT 24
Finished Jul 20 05:43:22 PM PDT 24
Peak memory 249648 kb
Host smart-09524b92-e37b-496a-b572-734aef87c154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591105953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3591105953
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3380206516
Short name T409
Test name
Test status
Simulation time 3457026948 ps
CPU time 39.93 seconds
Started Jul 20 05:41:18 PM PDT 24
Finished Jul 20 05:41:59 PM PDT 24
Peak memory 250716 kb
Host smart-1ede50a3-36ea-45c0-af28-2991a1264297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380206516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3380206516
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2118993843
Short name T922
Test name
Test status
Simulation time 8932249151 ps
CPU time 99.29 seconds
Started Jul 20 05:41:12 PM PDT 24
Finished Jul 20 05:42:52 PM PDT 24
Peak memory 256668 kb
Host smart-aaeb674b-de66-4483-9e49-d9ea764daed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118993843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2118993843
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.941929872
Short name T239
Test name
Test status
Simulation time 1885088885 ps
CPU time 5.84 seconds
Started Jul 20 05:41:14 PM PDT 24
Finished Jul 20 05:41:21 PM PDT 24
Peak memory 241336 kb
Host smart-265f71f4-6992-421a-8469-1a0ead49ff61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941929872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.941929872
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4048786984
Short name T592
Test name
Test status
Simulation time 16234513826 ps
CPU time 41.62 seconds
Started Jul 20 05:41:14 PM PDT 24
Finished Jul 20 05:41:56 PM PDT 24
Peak memory 241440 kb
Host smart-50f90047-7528-4297-8aa1-48e81ff20c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048786984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4048786984
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.841271514
Short name T867
Test name
Test status
Simulation time 24533982177 ps
CPU time 11.57 seconds
Started Jul 20 05:41:11 PM PDT 24
Finished Jul 20 05:41:24 PM PDT 24
Peak memory 233264 kb
Host smart-3d5a24a7-48af-4fe5-bd4b-95519e02ad81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841271514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.841271514
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2212439121
Short name T733
Test name
Test status
Simulation time 2311758857 ps
CPU time 15.64 seconds
Started Jul 20 05:41:19 PM PDT 24
Finished Jul 20 05:41:36 PM PDT 24
Peak memory 233220 kb
Host smart-0b58593c-ba3b-4127-a4c4-589ff068aa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212439121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2212439121
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1128696813
Short name T674
Test name
Test status
Simulation time 863203728 ps
CPU time 8.22 seconds
Started Jul 20 05:41:10 PM PDT 24
Finished Jul 20 05:41:19 PM PDT 24
Peak memory 241168 kb
Host smart-30ec59f9-95fc-4c68-9e76-603f8d995b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128696813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1128696813
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.144531841
Short name T510
Test name
Test status
Simulation time 22257461140 ps
CPU time 18.81 seconds
Started Jul 20 05:41:17 PM PDT 24
Finished Jul 20 05:41:37 PM PDT 24
Peak memory 233240 kb
Host smart-c8954988-fa58-4b03-8215-94de36b10090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144531841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.144531841
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1470440538
Short name T426
Test name
Test status
Simulation time 1068169377 ps
CPU time 10.53 seconds
Started Jul 20 05:41:12 PM PDT 24
Finished Jul 20 05:41:23 PM PDT 24
Peak memory 221964 kb
Host smart-26a2be0a-bd72-4a16-a3b0-ba44a508c0bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1470440538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1470440538
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3482021124
Short name T336
Test name
Test status
Simulation time 25885292 ps
CPU time 0.72 seconds
Started Jul 20 05:41:10 PM PDT 24
Finished Jul 20 05:41:11 PM PDT 24
Peak memory 206008 kb
Host smart-61511f0b-f3fe-4960-9265-a960db99760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482021124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3482021124
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2954634894
Short name T995
Test name
Test status
Simulation time 156889817 ps
CPU time 1.69 seconds
Started Jul 20 05:41:12 PM PDT 24
Finished Jul 20 05:41:15 PM PDT 24
Peak memory 208244 kb
Host smart-8aa06a9b-9222-40ec-a945-13c0a0c620d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954634894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2954634894
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1547874224
Short name T346
Test name
Test status
Simulation time 19470459 ps
CPU time 0.77 seconds
Started Jul 20 05:41:09 PM PDT 24
Finished Jul 20 05:41:11 PM PDT 24
Peak memory 206556 kb
Host smart-ebc0348c-bf3e-452f-941e-6e3ecd5e783b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547874224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1547874224
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3584032812
Short name T588
Test name
Test status
Simulation time 99652788 ps
CPU time 0.78 seconds
Started Jul 20 05:41:14 PM PDT 24
Finished Jul 20 05:41:15 PM PDT 24
Peak memory 206272 kb
Host smart-0273f1c1-6838-4bde-a4b3-a56a6e14e56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584032812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3584032812
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2188897150
Short name T465
Test name
Test status
Simulation time 262429798 ps
CPU time 3.96 seconds
Started Jul 20 05:41:18 PM PDT 24
Finished Jul 20 05:41:22 PM PDT 24
Peak memory 224936 kb
Host smart-616e57de-0d45-4a12-94e6-8c93b97f9959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188897150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2188897150
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1993069168
Short name T411
Test name
Test status
Simulation time 30935031 ps
CPU time 0.77 seconds
Started Jul 20 05:41:20 PM PDT 24
Finished Jul 20 05:41:23 PM PDT 24
Peak memory 205168 kb
Host smart-ced744b2-1c30-4144-bbb1-11a5ae93167f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993069168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1993069168
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1846583313
Short name T869
Test name
Test status
Simulation time 722257482 ps
CPU time 5.03 seconds
Started Jul 20 05:41:19 PM PDT 24
Finished Jul 20 05:41:25 PM PDT 24
Peak memory 224952 kb
Host smart-aa99d9f2-7f8d-4ee3-b0e3-4fb1382bd437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846583313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1846583313
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1236031038
Short name T502
Test name
Test status
Simulation time 15436844 ps
CPU time 0.75 seconds
Started Jul 20 05:41:11 PM PDT 24
Finished Jul 20 05:41:12 PM PDT 24
Peak memory 207224 kb
Host smart-3ca61752-d11c-450d-a3ae-578363cd0531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236031038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1236031038
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2965529657
Short name T227
Test name
Test status
Simulation time 5855234569 ps
CPU time 77.97 seconds
Started Jul 20 05:41:19 PM PDT 24
Finished Jul 20 05:42:38 PM PDT 24
Peak memory 253020 kb
Host smart-6f91a587-ca79-4570-9804-64007a28c47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965529657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2965529657
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1183266726
Short name T751
Test name
Test status
Simulation time 17109432820 ps
CPU time 142.21 seconds
Started Jul 20 05:41:23 PM PDT 24
Finished Jul 20 05:43:47 PM PDT 24
Peak memory 256464 kb
Host smart-e138030e-2d5e-4325-8e4d-5292912b538b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183266726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1183266726
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4195947297
Short name T483
Test name
Test status
Simulation time 78419399255 ps
CPU time 191.26 seconds
Started Jul 20 05:41:21 PM PDT 24
Finished Jul 20 05:44:35 PM PDT 24
Peak memory 253288 kb
Host smart-cd057f61-68da-49c6-86bf-ca89fd2b19a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195947297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4195947297
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2781747253
Short name T687
Test name
Test status
Simulation time 58185231 ps
CPU time 2.58 seconds
Started Jul 20 05:41:22 PM PDT 24
Finished Jul 20 05:41:27 PM PDT 24
Peak memory 233160 kb
Host smart-50398616-e58f-46b2-9c3a-fc4202c13b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781747253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2781747253
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2306476047
Short name T769
Test name
Test status
Simulation time 21172117399 ps
CPU time 69.01 seconds
Started Jul 20 05:41:21 PM PDT 24
Finished Jul 20 05:42:32 PM PDT 24
Peak memory 249676 kb
Host smart-55e49ecf-98f2-4d97-ba60-f8b65cf04c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306476047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2306476047
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2258205744
Short name T271
Test name
Test status
Simulation time 2122227056 ps
CPU time 8.48 seconds
Started Jul 20 05:41:08 PM PDT 24
Finished Jul 20 05:41:18 PM PDT 24
Peak memory 233152 kb
Host smart-6e815c85-bc32-4f73-bd63-c14c032ce631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258205744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2258205744
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1161042632
Short name T470
Test name
Test status
Simulation time 7181302378 ps
CPU time 22.95 seconds
Started Jul 20 05:41:14 PM PDT 24
Finished Jul 20 05:41:38 PM PDT 24
Peak memory 225032 kb
Host smart-89bbc254-ef32-40df-8335-3edceef3382a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161042632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1161042632
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1332235061
Short name T603
Test name
Test status
Simulation time 6116909501 ps
CPU time 6.86 seconds
Started Jul 20 05:41:14 PM PDT 24
Finished Jul 20 05:41:21 PM PDT 24
Peak memory 225052 kb
Host smart-bd746743-82a5-4bfa-817a-1318815814cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332235061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1332235061
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1880092751
Short name T750
Test name
Test status
Simulation time 1127310662 ps
CPU time 7.37 seconds
Started Jul 20 05:41:15 PM PDT 24
Finished Jul 20 05:41:22 PM PDT 24
Peak memory 241300 kb
Host smart-0ee4643a-c2f6-47d1-9e22-229eb9615b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880092751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1880092751
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2205521369
Short name T146
Test name
Test status
Simulation time 1052254254 ps
CPU time 7.82 seconds
Started Jul 20 05:41:17 PM PDT 24
Finished Jul 20 05:41:26 PM PDT 24
Peak memory 219392 kb
Host smart-a753efd6-ea09-4aac-9b21-022ae983450a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2205521369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2205521369
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1358258791
Short name T238
Test name
Test status
Simulation time 57770608815 ps
CPU time 515.66 seconds
Started Jul 20 05:41:20 PM PDT 24
Finished Jul 20 05:49:58 PM PDT 24
Peak memory 300720 kb
Host smart-34756991-090b-4732-945f-e2468b1992ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358258791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1358258791
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2364287695
Short name T657
Test name
Test status
Simulation time 14779899227 ps
CPU time 15.74 seconds
Started Jul 20 05:41:14 PM PDT 24
Finished Jul 20 05:41:31 PM PDT 24
Peak memory 216760 kb
Host smart-8a22fe09-b307-4ae4-a4e5-5135a3cf8375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364287695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2364287695
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.11672894
Short name T543
Test name
Test status
Simulation time 8713267284 ps
CPU time 21.42 seconds
Started Jul 20 05:41:10 PM PDT 24
Finished Jul 20 05:41:33 PM PDT 24
Peak memory 216812 kb
Host smart-55e497e1-d8f2-40b8-b496-f9f2f46176fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11672894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.11672894
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3335544460
Short name T637
Test name
Test status
Simulation time 44744455 ps
CPU time 1.05 seconds
Started Jul 20 05:41:12 PM PDT 24
Finished Jul 20 05:41:14 PM PDT 24
Peak memory 208256 kb
Host smart-beb11722-b05c-462e-aaf5-5bcd19c12a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335544460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3335544460
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2032322818
Short name T996
Test name
Test status
Simulation time 130295757 ps
CPU time 0.98 seconds
Started Jul 20 05:41:19 PM PDT 24
Finished Jul 20 05:41:21 PM PDT 24
Peak memory 206256 kb
Host smart-860ee4ca-96aa-4e84-b35c-7277c66e027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032322818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2032322818
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1358031395
Short name T816
Test name
Test status
Simulation time 4665270848 ps
CPU time 15.8 seconds
Started Jul 20 05:41:13 PM PDT 24
Finished Jul 20 05:41:29 PM PDT 24
Peak memory 233272 kb
Host smart-efd609cc-f3c6-408d-880f-7701c0a25b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358031395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1358031395
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.637476598
Short name T481
Test name
Test status
Simulation time 37163096 ps
CPU time 0.69 seconds
Started Jul 20 05:41:17 PM PDT 24
Finished Jul 20 05:41:18 PM PDT 24
Peak memory 205864 kb
Host smart-c5c56969-29d6-4fd5-90b7-53fde07705e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637476598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.637476598
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.617138280
Short name T969
Test name
Test status
Simulation time 100388500 ps
CPU time 2.52 seconds
Started Jul 20 05:41:20 PM PDT 24
Finished Jul 20 05:41:25 PM PDT 24
Peak memory 233052 kb
Host smart-ba8697cf-1410-434c-9b00-86a5e9996203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617138280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.617138280
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3755496423
Short name T891
Test name
Test status
Simulation time 16307611 ps
CPU time 0.76 seconds
Started Jul 20 05:41:22 PM PDT 24
Finished Jul 20 05:41:25 PM PDT 24
Peak memory 206204 kb
Host smart-5a0360dd-3227-42b3-b819-81ecbdd85dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755496423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3755496423
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3058364452
Short name T212
Test name
Test status
Simulation time 19543050625 ps
CPU time 120.43 seconds
Started Jul 20 05:41:20 PM PDT 24
Finished Jul 20 05:43:23 PM PDT 24
Peak memory 249740 kb
Host smart-f5510721-e1f9-4ded-8163-64040ef87232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058364452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3058364452
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3489276801
Short name T290
Test name
Test status
Simulation time 70126056846 ps
CPU time 546.67 seconds
Started Jul 20 05:41:22 PM PDT 24
Finished Jul 20 05:50:30 PM PDT 24
Peak memory 267504 kb
Host smart-f220cb35-ae70-4bcb-859e-b241643fb472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489276801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3489276801
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1583406476
Short name T939
Test name
Test status
Simulation time 1885741401 ps
CPU time 9.56 seconds
Started Jul 20 05:41:22 PM PDT 24
Finished Jul 20 05:41:34 PM PDT 24
Peak memory 224924 kb
Host smart-02e76dd5-1b45-47da-96dc-5d456a05a07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583406476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1583406476
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2248942800
Short name T1020
Test name
Test status
Simulation time 3495614534 ps
CPU time 45.78 seconds
Started Jul 20 05:41:20 PM PDT 24
Finished Jul 20 05:42:07 PM PDT 24
Peak memory 249680 kb
Host smart-e6ab1db4-7e1e-410c-a771-f0cf76d5774e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248942800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2248942800
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.4031171839
Short name T785
Test name
Test status
Simulation time 3008359545 ps
CPU time 7.73 seconds
Started Jul 20 05:41:23 PM PDT 24
Finished Jul 20 05:41:32 PM PDT 24
Peak memory 224940 kb
Host smart-f4f48765-2187-4b4a-9e99-5416f0ac874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031171839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.4031171839
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2150641584
Short name T283
Test name
Test status
Simulation time 23918377227 ps
CPU time 40.73 seconds
Started Jul 20 05:41:19 PM PDT 24
Finished Jul 20 05:42:01 PM PDT 24
Peak memory 236880 kb
Host smart-0629f34d-682b-471a-a531-15ffc8d83415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150641584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2150641584
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2128400817
Short name T903
Test name
Test status
Simulation time 10305751238 ps
CPU time 10.66 seconds
Started Jul 20 05:41:21 PM PDT 24
Finished Jul 20 05:41:34 PM PDT 24
Peak memory 233248 kb
Host smart-f0ac20ae-44c7-472d-8c3b-8e7786fe8932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128400817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2128400817
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.228806298
Short name T990
Test name
Test status
Simulation time 934759429 ps
CPU time 8.33 seconds
Started Jul 20 05:41:20 PM PDT 24
Finished Jul 20 05:41:31 PM PDT 24
Peak memory 232884 kb
Host smart-9936bf8e-9ea9-4757-b117-d4a27a2aa741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228806298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.228806298
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3340156791
Short name T484
Test name
Test status
Simulation time 962460982 ps
CPU time 10.93 seconds
Started Jul 20 05:41:22 PM PDT 24
Finished Jul 20 05:41:35 PM PDT 24
Peak memory 221000 kb
Host smart-ca0764f2-e451-456a-b989-ce0cebd2caa4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3340156791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3340156791
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.4241080428
Short name T579
Test name
Test status
Simulation time 19837830008 ps
CPU time 101.06 seconds
Started Jul 20 05:41:20 PM PDT 24
Finished Jul 20 05:43:03 PM PDT 24
Peak memory 252172 kb
Host smart-8fb8760e-c1a4-44b2-b314-eca604bf4d3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241080428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4241080428
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3486964586
Short name T410
Test name
Test status
Simulation time 10600886048 ps
CPU time 9.8 seconds
Started Jul 20 05:41:20 PM PDT 24
Finished Jul 20 05:41:31 PM PDT 24
Peak memory 216848 kb
Host smart-39e48d07-6f8b-4c71-aca7-eafd47ae498c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486964586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3486964586
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3503995059
Short name T360
Test name
Test status
Simulation time 2767976839 ps
CPU time 5.09 seconds
Started Jul 20 05:41:19 PM PDT 24
Finished Jul 20 05:41:25 PM PDT 24
Peak memory 216824 kb
Host smart-ddbac61d-7378-42f6-ad6c-6e49ad3ad27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503995059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3503995059
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.941487692
Short name T675
Test name
Test status
Simulation time 20969434 ps
CPU time 0.91 seconds
Started Jul 20 05:41:23 PM PDT 24
Finished Jul 20 05:41:26 PM PDT 24
Peak memory 208060 kb
Host smart-d8409766-18c6-4ddd-aa36-1a2d2781091e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941487692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.941487692
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3690685830
Short name T859
Test name
Test status
Simulation time 92578444 ps
CPU time 0.93 seconds
Started Jul 20 05:41:17 PM PDT 24
Finished Jul 20 05:41:19 PM PDT 24
Peak memory 206716 kb
Host smart-81059625-8c8d-4cdf-9f4b-636966f24abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690685830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3690685830
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2024135322
Short name T940
Test name
Test status
Simulation time 17596574600 ps
CPU time 12.41 seconds
Started Jul 20 05:41:17 PM PDT 24
Finished Jul 20 05:41:31 PM PDT 24
Peak memory 225080 kb
Host smart-2b13bab4-0abe-45c6-83ce-7f584d6f3e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024135322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2024135322
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.548608710
Short name T605
Test name
Test status
Simulation time 37257391 ps
CPU time 0.73 seconds
Started Jul 20 05:41:21 PM PDT 24
Finished Jul 20 05:41:23 PM PDT 24
Peak memory 205692 kb
Host smart-4b1c66ae-865d-4717-be4e-87a38c44284e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548608710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.548608710
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.936883466
Short name T702
Test name
Test status
Simulation time 1693515247 ps
CPU time 6.01 seconds
Started Jul 20 05:41:20 PM PDT 24
Finished Jul 20 05:41:27 PM PDT 24
Peak memory 233124 kb
Host smart-367943b6-a452-4ae7-996e-1ec96c9c729c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936883466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.936883466
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3276652812
Short name T949
Test name
Test status
Simulation time 62259250 ps
CPU time 0.87 seconds
Started Jul 20 05:41:21 PM PDT 24
Finished Jul 20 05:41:24 PM PDT 24
Peak memory 207220 kb
Host smart-97a893e5-c87c-451e-8828-46bf1c304688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276652812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3276652812
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1304836836
Short name T262
Test name
Test status
Simulation time 4281110691 ps
CPU time 26.3 seconds
Started Jul 20 05:41:17 PM PDT 24
Finished Jul 20 05:41:43 PM PDT 24
Peak memory 237064 kb
Host smart-13754a24-9707-4193-8c2a-4aa65ee618bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304836836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1304836836
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3705856988
Short name T249
Test name
Test status
Simulation time 24613566267 ps
CPU time 227.97 seconds
Started Jul 20 05:41:23 PM PDT 24
Finished Jul 20 05:45:13 PM PDT 24
Peak memory 252800 kb
Host smart-d3f5f86c-0e35-47c8-9d09-9486abd148c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705856988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3705856988
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.925731186
Short name T547
Test name
Test status
Simulation time 8226650011 ps
CPU time 28 seconds
Started Jul 20 05:41:22 PM PDT 24
Finished Jul 20 05:41:52 PM PDT 24
Peak memory 241516 kb
Host smart-19434d5d-2e8e-4f61-8e6d-20d501448bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925731186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.925731186
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.569935655
Short name T354
Test name
Test status
Simulation time 707965733 ps
CPU time 3.49 seconds
Started Jul 20 05:41:21 PM PDT 24
Finished Jul 20 05:41:27 PM PDT 24
Peak memory 233160 kb
Host smart-21c625dc-269b-45aa-b233-9b15fda37f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569935655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.569935655
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1674116797
Short name T194
Test name
Test status
Simulation time 45233275300 ps
CPU time 151.18 seconds
Started Jul 20 05:41:23 PM PDT 24
Finished Jul 20 05:43:56 PM PDT 24
Peak memory 249608 kb
Host smart-5e79f3ed-3db1-40a5-843f-f19d269ab88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674116797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1674116797
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.687743449
Short name T83
Test name
Test status
Simulation time 10396009835 ps
CPU time 18.61 seconds
Started Jul 20 05:41:20 PM PDT 24
Finished Jul 20 05:41:41 PM PDT 24
Peak memory 225008 kb
Host smart-36affb5d-0ae2-4717-ad3a-eb06d4eef0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687743449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.687743449
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2657807290
Short name T991
Test name
Test status
Simulation time 438163767 ps
CPU time 10.56 seconds
Started Jul 20 05:41:18 PM PDT 24
Finished Jul 20 05:41:30 PM PDT 24
Peak memory 235700 kb
Host smart-44e5ca94-dc03-4a22-a138-f660fab87f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657807290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2657807290
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.176577893
Short name T920
Test name
Test status
Simulation time 4130673661 ps
CPU time 4.98 seconds
Started Jul 20 05:41:22 PM PDT 24
Finished Jul 20 05:41:29 PM PDT 24
Peak memory 225052 kb
Host smart-3cd6c062-0795-4a7a-9019-6603bceec641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176577893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.176577893
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.505403070
Short name T285
Test name
Test status
Simulation time 2031768029 ps
CPU time 6.89 seconds
Started Jul 20 05:41:22 PM PDT 24
Finished Jul 20 05:41:31 PM PDT 24
Peak memory 233144 kb
Host smart-57c69608-857c-4ffb-b2b0-c1128282cd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505403070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.505403070
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3738875243
Short name T573
Test name
Test status
Simulation time 1211203180 ps
CPU time 8.67 seconds
Started Jul 20 05:41:20 PM PDT 24
Finished Jul 20 05:41:31 PM PDT 24
Peak memory 219536 kb
Host smart-f2a02a4e-7590-4c8a-b960-9e3205ed1944
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3738875243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3738875243
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4198135939
Short name T451
Test name
Test status
Simulation time 125957339 ps
CPU time 1.24 seconds
Started Jul 20 05:41:18 PM PDT 24
Finished Jul 20 05:41:21 PM PDT 24
Peak memory 207588 kb
Host smart-7222afc6-7516-480b-a07a-5af436fb80ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198135939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4198135939
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.876882233
Short name T323
Test name
Test status
Simulation time 6704038701 ps
CPU time 26.85 seconds
Started Jul 20 05:41:22 PM PDT 24
Finished Jul 20 05:41:51 PM PDT 24
Peak memory 216788 kb
Host smart-4406d152-6152-46fb-8b9c-a091d06eb8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876882233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.876882233
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2563157741
Short name T692
Test name
Test status
Simulation time 890761042 ps
CPU time 6.39 seconds
Started Jul 20 05:41:22 PM PDT 24
Finished Jul 20 05:41:30 PM PDT 24
Peak memory 216692 kb
Host smart-f62c5527-4b09-4b8e-b2c7-3f29d168461a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563157741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2563157741
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1074629103
Short name T957
Test name
Test status
Simulation time 282223282 ps
CPU time 1.84 seconds
Started Jul 20 05:41:22 PM PDT 24
Finished Jul 20 05:41:26 PM PDT 24
Peak memory 216640 kb
Host smart-76e552ff-4bce-409f-9505-878187c75fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074629103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1074629103
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2430593439
Short name T741
Test name
Test status
Simulation time 75541001 ps
CPU time 0.79 seconds
Started Jul 20 05:41:19 PM PDT 24
Finished Jul 20 05:41:21 PM PDT 24
Peak memory 206304 kb
Host smart-32332021-35f4-4833-b90d-7eed930c67e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430593439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2430593439
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4148554358
Short name T5
Test name
Test status
Simulation time 22296265718 ps
CPU time 35.4 seconds
Started Jul 20 05:41:20 PM PDT 24
Finished Jul 20 05:41:57 PM PDT 24
Peak memory 233264 kb
Host smart-9920a041-9814-4d75-b013-8be94cc2f573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148554358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4148554358
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3361216094
Short name T638
Test name
Test status
Simulation time 13761763 ps
CPU time 0.72 seconds
Started Jul 20 05:38:02 PM PDT 24
Finished Jul 20 05:38:04 PM PDT 24
Peak memory 205168 kb
Host smart-2b27e4e2-958d-4d1d-8ad5-22f58c69082c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361216094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
361216094
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.671924773
Short name T553
Test name
Test status
Simulation time 5237528072 ps
CPU time 21.67 seconds
Started Jul 20 05:38:01 PM PDT 24
Finished Jul 20 05:38:25 PM PDT 24
Peak memory 225064 kb
Host smart-c984e926-eee7-4ad4-81ca-87b76686175d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671924773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.671924773
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3994840841
Short name T572
Test name
Test status
Simulation time 21610910 ps
CPU time 0.76 seconds
Started Jul 20 05:37:59 PM PDT 24
Finished Jul 20 05:38:01 PM PDT 24
Peak memory 207196 kb
Host smart-bee4dba1-9d8b-40f3-9fab-9d2d2aaeb6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994840841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3994840841
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2771151111
Short name T203
Test name
Test status
Simulation time 14466830337 ps
CPU time 130.38 seconds
Started Jul 20 05:38:01 PM PDT 24
Finished Jul 20 05:40:12 PM PDT 24
Peak memory 270036 kb
Host smart-a3341d20-325a-4ff3-8edf-a20f1fcfbff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771151111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2771151111
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4290544315
Short name T198
Test name
Test status
Simulation time 45447891520 ps
CPU time 149.62 seconds
Started Jul 20 05:38:01 PM PDT 24
Finished Jul 20 05:40:32 PM PDT 24
Peak memory 273220 kb
Host smart-eb6e2643-b152-4192-9671-9810f05c3476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290544315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4290544315
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1272692436
Short name T414
Test name
Test status
Simulation time 47644487682 ps
CPU time 141.98 seconds
Started Jul 20 05:38:02 PM PDT 24
Finished Jul 20 05:40:25 PM PDT 24
Peak memory 249672 kb
Host smart-7ba59733-8497-4bfd-8ac7-8f01ac28b58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272692436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1272692436
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3359677883
Short name T574
Test name
Test status
Simulation time 1040689918 ps
CPU time 7.8 seconds
Started Jul 20 05:38:03 PM PDT 24
Finished Jul 20 05:38:13 PM PDT 24
Peak memory 224916 kb
Host smart-ffb90936-062f-46f6-9964-af36ea3c3d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359677883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3359677883
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2104627351
Short name T442
Test name
Test status
Simulation time 22861856208 ps
CPU time 151.06 seconds
Started Jul 20 05:38:01 PM PDT 24
Finished Jul 20 05:40:33 PM PDT 24
Peak memory 251460 kb
Host smart-7f00a2f6-2880-4bd8-890a-a9c241a59f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104627351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2104627351
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3872570394
Short name T714
Test name
Test status
Simulation time 1310928704 ps
CPU time 7.12 seconds
Started Jul 20 05:38:02 PM PDT 24
Finished Jul 20 05:38:10 PM PDT 24
Peak memory 233116 kb
Host smart-85354840-3a1b-496d-b467-f117671b91b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872570394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3872570394
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3687660983
Short name T260
Test name
Test status
Simulation time 30679168047 ps
CPU time 71.07 seconds
Started Jul 20 05:38:01 PM PDT 24
Finished Jul 20 05:39:14 PM PDT 24
Peak memory 233288 kb
Host smart-3f46b139-0a52-4634-b65c-13e3421e2419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687660983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3687660983
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1138198152
Short name T676
Test name
Test status
Simulation time 26264837 ps
CPU time 1 seconds
Started Jul 20 05:38:02 PM PDT 24
Finished Jul 20 05:38:05 PM PDT 24
Peak memory 217172 kb
Host smart-bd13b323-71e0-4977-ad4c-0b63949a55b2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138198152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1138198152
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1868613030
Short name T937
Test name
Test status
Simulation time 3354956073 ps
CPU time 7.11 seconds
Started Jul 20 05:38:03 PM PDT 24
Finished Jul 20 05:38:12 PM PDT 24
Peak memory 233252 kb
Host smart-aeb13053-26e0-4a2f-b999-37611db217dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868613030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1868613030
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2766906403
Short name T273
Test name
Test status
Simulation time 161585745 ps
CPU time 3.9 seconds
Started Jul 20 05:38:03 PM PDT 24
Finished Jul 20 05:38:09 PM PDT 24
Peak memory 224956 kb
Host smart-8e9c5409-b7e1-4735-9ae4-578dc7ffb1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766906403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2766906403
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.184403060
Short name T40
Test name
Test status
Simulation time 659993821 ps
CPU time 3.63 seconds
Started Jul 20 05:38:03 PM PDT 24
Finished Jul 20 05:38:09 PM PDT 24
Peak memory 221408 kb
Host smart-17015b53-047e-4161-a27a-a2e9e19c4d2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=184403060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.184403060
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3396430322
Short name T660
Test name
Test status
Simulation time 67719337 ps
CPU time 0.93 seconds
Started Jul 20 05:38:04 PM PDT 24
Finished Jul 20 05:38:07 PM PDT 24
Peak memory 206860 kb
Host smart-39526819-ce6b-4878-8661-250f675981ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396430322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3396430322
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3748952999
Short name T868
Test name
Test status
Simulation time 3698203992 ps
CPU time 6.21 seconds
Started Jul 20 05:38:03 PM PDT 24
Finished Jul 20 05:38:11 PM PDT 24
Peak memory 220288 kb
Host smart-8b59123b-84bb-4923-9d1e-ded61f494813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748952999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3748952999
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3728458315
Short name T418
Test name
Test status
Simulation time 5599995878 ps
CPU time 17.02 seconds
Started Jul 20 05:38:00 PM PDT 24
Finished Jul 20 05:38:17 PM PDT 24
Peak memory 216748 kb
Host smart-611321cf-cf70-4b03-ae74-21dd6c756de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728458315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3728458315
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3178435639
Short name T550
Test name
Test status
Simulation time 796522858 ps
CPU time 2.25 seconds
Started Jul 20 05:38:01 PM PDT 24
Finished Jul 20 05:38:04 PM PDT 24
Peak memory 216700 kb
Host smart-8be5c301-bdf5-4896-9921-90f41fcb6bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178435639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3178435639
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2861194163
Short name T352
Test name
Test status
Simulation time 43340000 ps
CPU time 0.86 seconds
Started Jul 20 05:38:00 PM PDT 24
Finished Jul 20 05:38:01 PM PDT 24
Peak memory 206308 kb
Host smart-f8a45eff-fd2b-4b93-86e1-a37d4265afdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861194163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2861194163
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3931396744
Short name T137
Test name
Test status
Simulation time 7987866278 ps
CPU time 27.96 seconds
Started Jul 20 05:38:03 PM PDT 24
Finished Jul 20 05:38:33 PM PDT 24
Peak memory 233256 kb
Host smart-80a9e6f1-4675-41f4-a5da-37d2a8bce104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931396744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3931396744
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.210954776
Short name T589
Test name
Test status
Simulation time 14345466 ps
CPU time 0.69 seconds
Started Jul 20 05:38:10 PM PDT 24
Finished Jul 20 05:38:12 PM PDT 24
Peak memory 205168 kb
Host smart-2d2abf89-c6c4-4c5f-b5f7-214298e3a565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210954776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.210954776
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.4097634246
Short name T537
Test name
Test status
Simulation time 294386073 ps
CPU time 3.88 seconds
Started Jul 20 05:38:09 PM PDT 24
Finished Jul 20 05:38:13 PM PDT 24
Peak memory 224884 kb
Host smart-5110fa12-612f-4af1-bc44-2de4bd621430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097634246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.4097634246
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3724343305
Short name T331
Test name
Test status
Simulation time 29500398 ps
CPU time 0.73 seconds
Started Jul 20 05:38:02 PM PDT 24
Finished Jul 20 05:38:04 PM PDT 24
Peak memory 206160 kb
Host smart-fe8bd997-cadd-4386-ac7c-4db3ab85675f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724343305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3724343305
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.905520027
Short name T428
Test name
Test status
Simulation time 15456640856 ps
CPU time 54.32 seconds
Started Jul 20 05:38:10 PM PDT 24
Finished Jul 20 05:39:05 PM PDT 24
Peak memory 241468 kb
Host smart-73eb1116-acc7-4bd4-9bcf-408415ee1d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905520027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.905520027
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3334922694
Short name T224
Test name
Test status
Simulation time 5811861302 ps
CPU time 83.17 seconds
Started Jul 20 05:38:09 PM PDT 24
Finished Jul 20 05:39:33 PM PDT 24
Peak memory 254896 kb
Host smart-bc7b8480-4be6-49c8-921f-60608d5376fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334922694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3334922694
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.875293833
Short name T552
Test name
Test status
Simulation time 141738145810 ps
CPU time 88.32 seconds
Started Jul 20 05:38:10 PM PDT 24
Finished Jul 20 05:39:39 PM PDT 24
Peak memory 240384 kb
Host smart-4808f43c-ff19-4edf-bad5-9b72dfe7c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875293833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
875293833
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3044487602
Short name T711
Test name
Test status
Simulation time 68373855 ps
CPU time 3.41 seconds
Started Jul 20 05:38:12 PM PDT 24
Finished Jul 20 05:38:16 PM PDT 24
Peak memory 233148 kb
Host smart-0e4ecee3-91b2-4ad3-9b9c-2c928468337a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044487602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3044487602
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.4076207011
Short name T252
Test name
Test status
Simulation time 7965456853 ps
CPU time 25.21 seconds
Started Jul 20 05:38:10 PM PDT 24
Finished Jul 20 05:38:36 PM PDT 24
Peak memory 237356 kb
Host smart-ff6b52be-5ec4-42e6-96bd-395cb9ce31d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076207011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.4076207011
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2198289873
Short name T135
Test name
Test status
Simulation time 175839802 ps
CPU time 2.67 seconds
Started Jul 20 05:38:12 PM PDT 24
Finished Jul 20 05:38:16 PM PDT 24
Peak memory 224860 kb
Host smart-bea5b4d9-09d7-43f4-bd27-693929b2c215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198289873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2198289873
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.4144136136
Short name T977
Test name
Test status
Simulation time 11356925136 ps
CPU time 42.46 seconds
Started Jul 20 05:38:10 PM PDT 24
Finished Jul 20 05:38:53 PM PDT 24
Peak memory 241504 kb
Host smart-a1cba012-d7d9-4347-87b1-2a512457e57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144136136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4144136136
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1076289584
Short name T767
Test name
Test status
Simulation time 21198561 ps
CPU time 1.01 seconds
Started Jul 20 05:38:05 PM PDT 24
Finished Jul 20 05:38:07 PM PDT 24
Peak memory 217168 kb
Host smart-eb705933-8425-4fa0-aa94-5c72b788f8a3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076289584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1076289584
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.54456956
Short name T803
Test name
Test status
Simulation time 2035231786 ps
CPU time 3.66 seconds
Started Jul 20 05:38:08 PM PDT 24
Finished Jul 20 05:38:13 PM PDT 24
Peak memory 224736 kb
Host smart-ed2ed485-fc8c-4d76-9257-0bac4181c635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54456956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.54456956
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.484605639
Short name T208
Test name
Test status
Simulation time 685107862 ps
CPU time 4.99 seconds
Started Jul 20 05:38:03 PM PDT 24
Finished Jul 20 05:38:10 PM PDT 24
Peak memory 233104 kb
Host smart-80976977-a4cd-4695-b6c0-4c033c16b328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484605639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.484605639
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2697357356
Short name T825
Test name
Test status
Simulation time 2263332821 ps
CPU time 7.57 seconds
Started Jul 20 05:38:12 PM PDT 24
Finished Jul 20 05:38:20 PM PDT 24
Peak memory 222952 kb
Host smart-858ce590-20f5-43dd-b8c2-c0cf456d7c9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2697357356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2697357356
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3143630171
Short name T156
Test name
Test status
Simulation time 239450762 ps
CPU time 1.04 seconds
Started Jul 20 05:38:10 PM PDT 24
Finished Jul 20 05:38:12 PM PDT 24
Peak memory 207112 kb
Host smart-76e2db27-225d-4c56-8379-67d46c4fdf22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143630171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3143630171
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3125835113
Short name T650
Test name
Test status
Simulation time 2308490038 ps
CPU time 4.31 seconds
Started Jul 20 05:37:59 PM PDT 24
Finished Jul 20 05:38:04 PM PDT 24
Peak memory 216896 kb
Host smart-da8631d7-16fb-47d5-b03f-5ca07540cc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125835113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3125835113
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1676311250
Short name T965
Test name
Test status
Simulation time 28030806005 ps
CPU time 20.86 seconds
Started Jul 20 05:38:00 PM PDT 24
Finished Jul 20 05:38:22 PM PDT 24
Peak memory 217888 kb
Host smart-a9ffd882-19a7-4ff3-87fa-05594a58cb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676311250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1676311250
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2275383169
Short name T681
Test name
Test status
Simulation time 29199337 ps
CPU time 1.17 seconds
Started Jul 20 05:38:01 PM PDT 24
Finished Jul 20 05:38:03 PM PDT 24
Peak memory 207748 kb
Host smart-27cb5e05-4cfe-492f-a6a7-16c260a8b483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275383169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2275383169
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2535931227
Short name T744
Test name
Test status
Simulation time 16636045 ps
CPU time 0.72 seconds
Started Jul 20 05:38:11 PM PDT 24
Finished Jul 20 05:38:13 PM PDT 24
Peak memory 205912 kb
Host smart-54aa35e9-4dde-482b-a80b-790f3a32d86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535931227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2535931227
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.654543985
Short name T181
Test name
Test status
Simulation time 926240264 ps
CPU time 3.51 seconds
Started Jul 20 05:38:09 PM PDT 24
Finished Jul 20 05:38:14 PM PDT 24
Peak memory 233176 kb
Host smart-e53c22e1-6978-41ab-a41b-7b67d8a6a1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654543985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.654543985
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1864830298
Short name T361
Test name
Test status
Simulation time 13914522 ps
CPU time 0.74 seconds
Started Jul 20 05:38:19 PM PDT 24
Finished Jul 20 05:38:20 PM PDT 24
Peak memory 205704 kb
Host smart-81ba17f7-19d4-456b-a256-b9da01fbc71d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864830298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
864830298
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.319520551
Short name T59
Test name
Test status
Simulation time 375795298 ps
CPU time 6 seconds
Started Jul 20 05:38:10 PM PDT 24
Finished Jul 20 05:38:17 PM PDT 24
Peak memory 233068 kb
Host smart-a6f5c284-6afd-4b36-834e-a46b05eb7c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319520551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.319520551
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4177883734
Short name T723
Test name
Test status
Simulation time 22120361 ps
CPU time 0.77 seconds
Started Jul 20 05:38:08 PM PDT 24
Finished Jul 20 05:38:09 PM PDT 24
Peak memory 207192 kb
Host smart-0bde659e-4148-4fa6-ac92-a9832ce7dbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177883734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4177883734
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2217649258
Short name T306
Test name
Test status
Simulation time 2567949524 ps
CPU time 15.27 seconds
Started Jul 20 05:38:12 PM PDT 24
Finished Jul 20 05:38:28 PM PDT 24
Peak memory 236064 kb
Host smart-4be66b96-32da-4ee4-a1fa-a3ab86477014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217649258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2217649258
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3519342544
Short name T788
Test name
Test status
Simulation time 16022897372 ps
CPU time 19.33 seconds
Started Jul 20 05:38:11 PM PDT 24
Finished Jul 20 05:38:31 PM PDT 24
Peak memory 218024 kb
Host smart-1654cab8-40b7-411c-a97a-f17c0bfa2aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519342544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3519342544
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3717560140
Short name T511
Test name
Test status
Simulation time 24738429214 ps
CPU time 241.51 seconds
Started Jul 20 05:38:08 PM PDT 24
Finished Jul 20 05:42:10 PM PDT 24
Peak memory 265068 kb
Host smart-1bbfdefb-c2ce-48f7-8dc1-84445e7f2de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717560140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3717560140
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1125931608
Short name T566
Test name
Test status
Simulation time 45265624 ps
CPU time 3.2 seconds
Started Jul 20 05:38:08 PM PDT 24
Finished Jul 20 05:38:12 PM PDT 24
Peak memory 233160 kb
Host smart-c61fe7af-69cc-442f-9df6-407daa1f6181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125931608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1125931608
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1377087299
Short name T441
Test name
Test status
Simulation time 2702817400 ps
CPU time 39.03 seconds
Started Jul 20 05:38:10 PM PDT 24
Finished Jul 20 05:38:50 PM PDT 24
Peak memory 249628 kb
Host smart-b2869102-8594-4943-b7a8-27b7426d3f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377087299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1377087299
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1391204146
Short name T597
Test name
Test status
Simulation time 1015314883 ps
CPU time 9.75 seconds
Started Jul 20 05:38:11 PM PDT 24
Finished Jul 20 05:38:22 PM PDT 24
Peak memory 233048 kb
Host smart-f3153e5e-1922-4c0e-b1a7-ef50a965d501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391204146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1391204146
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1585124910
Short name T259
Test name
Test status
Simulation time 29859417639 ps
CPU time 16.55 seconds
Started Jul 20 05:38:09 PM PDT 24
Finished Jul 20 05:38:26 PM PDT 24
Peak memory 239220 kb
Host smart-fe5fd516-a4a1-47d6-9957-58ec2e9c1006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585124910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1585124910
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.416907674
Short name T45
Test name
Test status
Simulation time 121955025 ps
CPU time 1.05 seconds
Started Jul 20 05:38:08 PM PDT 24
Finished Jul 20 05:38:10 PM PDT 24
Peak memory 217132 kb
Host smart-ea263560-43d1-48f7-86f2-b8ded9c562cc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416907674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.416907674
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.790227241
Short name T658
Test name
Test status
Simulation time 275017905 ps
CPU time 5.1 seconds
Started Jul 20 05:38:10 PM PDT 24
Finished Jul 20 05:38:16 PM PDT 24
Peak memory 233088 kb
Host smart-449d9015-43ab-4f89-872d-fc8f7d69a490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790227241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
790227241
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.496444648
Short name T243
Test name
Test status
Simulation time 586944951 ps
CPU time 8.77 seconds
Started Jul 20 05:38:10 PM PDT 24
Finished Jul 20 05:38:19 PM PDT 24
Peak memory 224956 kb
Host smart-58c03d76-86bc-423d-a571-631f6e1529e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496444648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.496444648
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4044967578
Short name T357
Test name
Test status
Simulation time 2866647667 ps
CPU time 9.62 seconds
Started Jul 20 05:38:09 PM PDT 24
Finished Jul 20 05:38:19 PM PDT 24
Peak memory 223316 kb
Host smart-c437ff4b-b6ae-445e-a090-b56daa5e0f39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4044967578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4044967578
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2993292669
Short name T978
Test name
Test status
Simulation time 5156363870 ps
CPU time 13.78 seconds
Started Jul 20 05:38:12 PM PDT 24
Finished Jul 20 05:38:26 PM PDT 24
Peak memory 216820 kb
Host smart-07a3646a-84ae-4e43-8296-638cb18d3d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993292669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2993292669
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3019129532
Short name T757
Test name
Test status
Simulation time 1778601607 ps
CPU time 4.77 seconds
Started Jul 20 05:38:10 PM PDT 24
Finished Jul 20 05:38:16 PM PDT 24
Peak memory 216648 kb
Host smart-5f317ded-4fdb-4b94-ae50-11c9f948a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019129532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3019129532
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4112485523
Short name T387
Test name
Test status
Simulation time 353571695 ps
CPU time 1.35 seconds
Started Jul 20 05:38:09 PM PDT 24
Finished Jul 20 05:38:11 PM PDT 24
Peak memory 216696 kb
Host smart-8224b85c-494d-443b-8fb6-d508b9922cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112485523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4112485523
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3338091403
Short name T30
Test name
Test status
Simulation time 360440315 ps
CPU time 0.93 seconds
Started Jul 20 05:38:09 PM PDT 24
Finished Jul 20 05:38:10 PM PDT 24
Peak memory 206292 kb
Host smart-a54cf2c4-f3ff-482a-be78-51cdd328917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338091403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3338091403
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1535522068
Short name T645
Test name
Test status
Simulation time 1477837996 ps
CPU time 5.29 seconds
Started Jul 20 05:38:11 PM PDT 24
Finished Jul 20 05:38:17 PM PDT 24
Peak memory 241284 kb
Host smart-b307d7d5-21ae-495c-ac77-818ff26c79c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535522068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1535522068
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.453878219
Short name T630
Test name
Test status
Simulation time 134103641 ps
CPU time 0.72 seconds
Started Jul 20 05:38:19 PM PDT 24
Finished Jul 20 05:38:20 PM PDT 24
Peak memory 205784 kb
Host smart-f4a9b946-de98-4af3-ad79-73fc9eecb9c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453878219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.453878219
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.551400498
Short name T898
Test name
Test status
Simulation time 740475170 ps
CPU time 8.58 seconds
Started Jul 20 05:38:16 PM PDT 24
Finished Jul 20 05:38:25 PM PDT 24
Peak memory 224812 kb
Host smart-eba9609d-c9f0-46f2-90f7-14f9dc33ddd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551400498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.551400498
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2022102144
Short name T490
Test name
Test status
Simulation time 21361712 ps
CPU time 0.77 seconds
Started Jul 20 05:38:18 PM PDT 24
Finished Jul 20 05:38:19 PM PDT 24
Peak memory 207192 kb
Host smart-02c06579-a981-46d6-8f69-bd3197a47400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022102144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2022102144
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1777219477
Short name T781
Test name
Test status
Simulation time 467087065522 ps
CPU time 168.21 seconds
Started Jul 20 05:38:18 PM PDT 24
Finished Jul 20 05:41:07 PM PDT 24
Peak memory 255948 kb
Host smart-4bc086fd-a28a-4ae4-96ae-abf49dbd6328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777219477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1777219477
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1845958803
Short name T931
Test name
Test status
Simulation time 25583236298 ps
CPU time 240.88 seconds
Started Jul 20 05:38:17 PM PDT 24
Finished Jul 20 05:42:18 PM PDT 24
Peak memory 257924 kb
Host smart-881d23f8-31b2-4f94-85f0-35b4169f867f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845958803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1845958803
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2017140128
Short name T519
Test name
Test status
Simulation time 1480537782 ps
CPU time 29.22 seconds
Started Jul 20 05:38:21 PM PDT 24
Finished Jul 20 05:38:50 PM PDT 24
Peak memory 250336 kb
Host smart-bc46ca16-780b-4cd6-a318-471247aecbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017140128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2017140128
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3491453416
Short name T314
Test name
Test status
Simulation time 5754293056 ps
CPU time 47.24 seconds
Started Jul 20 05:38:17 PM PDT 24
Finished Jul 20 05:39:05 PM PDT 24
Peak memory 240624 kb
Host smart-351a933e-5f33-4eec-b2ec-0cdf035ef591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491453416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3491453416
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1688281984
Short name T1004
Test name
Test status
Simulation time 32667020406 ps
CPU time 36.74 seconds
Started Jul 20 05:38:18 PM PDT 24
Finished Jul 20 05:38:56 PM PDT 24
Peak memory 253592 kb
Host smart-1f455230-3af1-49b4-a5ba-cfecf9636de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688281984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1688281984
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4095119319
Short name T748
Test name
Test status
Simulation time 966416475 ps
CPU time 4.55 seconds
Started Jul 20 05:38:18 PM PDT 24
Finished Jul 20 05:38:23 PM PDT 24
Peak memory 233192 kb
Host smart-4cf7d8b8-e7d3-4e4a-86bd-51ac4d0e0bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095119319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4095119319
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2214982778
Short name T93
Test name
Test status
Simulation time 3982878246 ps
CPU time 15.28 seconds
Started Jul 20 05:38:20 PM PDT 24
Finished Jul 20 05:38:36 PM PDT 24
Peak memory 249508 kb
Host smart-efe58370-bad2-48fd-8008-14152395c427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214982778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2214982778
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3126424712
Short name T673
Test name
Test status
Simulation time 68166022 ps
CPU time 1.08 seconds
Started Jul 20 05:38:19 PM PDT 24
Finished Jul 20 05:38:21 PM PDT 24
Peak memory 217152 kb
Host smart-98125d6f-1e68-4566-a28b-6f0ddf2fe13f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126424712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3126424712
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2715083227
Short name T57
Test name
Test status
Simulation time 9860529921 ps
CPU time 18.08 seconds
Started Jul 20 05:38:19 PM PDT 24
Finished Jul 20 05:38:38 PM PDT 24
Peak memory 241452 kb
Host smart-8811cd0d-d221-4e75-bff6-460f963f9527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715083227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2715083227
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1416035496
Short name T690
Test name
Test status
Simulation time 1647336668 ps
CPU time 5.61 seconds
Started Jul 20 05:38:16 PM PDT 24
Finished Jul 20 05:38:23 PM PDT 24
Peak memory 224968 kb
Host smart-93e3cc5e-b94e-4711-8851-c2f09e8064b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416035496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1416035496
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3991494461
Short name T858
Test name
Test status
Simulation time 530264169 ps
CPU time 5.89 seconds
Started Jul 20 05:38:19 PM PDT 24
Finished Jul 20 05:38:25 PM PDT 24
Peak memory 223508 kb
Host smart-0b8595f7-72cd-4a9d-ac21-eb79fdd0e0ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3991494461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3991494461
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.332784538
Short name T1032
Test name
Test status
Simulation time 52352738002 ps
CPU time 144.72 seconds
Started Jul 20 05:38:18 PM PDT 24
Finished Jul 20 05:40:43 PM PDT 24
Peak memory 253116 kb
Host smart-a46780b5-3089-4f73-b765-19a96706bcd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332784538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.332784538
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.995786051
Short name T1027
Test name
Test status
Simulation time 10559862850 ps
CPU time 17.34 seconds
Started Jul 20 05:38:20 PM PDT 24
Finished Jul 20 05:38:38 PM PDT 24
Peak memory 216872 kb
Host smart-c5384abd-ae62-43c8-903c-c67b662c7604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995786051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.995786051
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3267858176
Short name T488
Test name
Test status
Simulation time 20421865837 ps
CPU time 15.25 seconds
Started Jul 20 05:38:19 PM PDT 24
Finished Jul 20 05:38:35 PM PDT 24
Peak memory 216824 kb
Host smart-cb8c8b0b-f263-4d94-8d11-933eeceea607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267858176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3267858176
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2747940238
Short name T756
Test name
Test status
Simulation time 287414648 ps
CPU time 1.77 seconds
Started Jul 20 05:38:20 PM PDT 24
Finished Jul 20 05:38:22 PM PDT 24
Peak memory 216592 kb
Host smart-959259c7-8138-4941-bf49-ee2c7838db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747940238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2747940238
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1481129986
Short name T833
Test name
Test status
Simulation time 203996781 ps
CPU time 0.74 seconds
Started Jul 20 05:38:17 PM PDT 24
Finished Jul 20 05:38:18 PM PDT 24
Peak memory 206276 kb
Host smart-9f6685ba-b00c-460d-9cf6-4d0a5d40b066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481129986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1481129986
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2873684586
Short name T256
Test name
Test status
Simulation time 5487865282 ps
CPU time 16.23 seconds
Started Jul 20 05:38:21 PM PDT 24
Finished Jul 20 05:38:38 PM PDT 24
Peak memory 225076 kb
Host smart-74e89f4d-8b6f-4b71-92eb-cb476f4b3db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873684586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2873684586
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.10588154
Short name T865
Test name
Test status
Simulation time 55495058 ps
CPU time 0.71 seconds
Started Jul 20 05:38:26 PM PDT 24
Finished Jul 20 05:38:27 PM PDT 24
Peak memory 205188 kb
Host smart-32a285d7-c290-44f8-b1cd-b64940f3efde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10588154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.10588154
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.715356754
Short name T683
Test name
Test status
Simulation time 390901980 ps
CPU time 6.89 seconds
Started Jul 20 05:38:28 PM PDT 24
Finished Jul 20 05:38:36 PM PDT 24
Peak memory 233048 kb
Host smart-c2b9c72a-0ec8-4541-856b-b9d47a336db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715356754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.715356754
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.720149628
Short name T407
Test name
Test status
Simulation time 45167008 ps
CPU time 0.74 seconds
Started Jul 20 05:38:16 PM PDT 24
Finished Jul 20 05:38:17 PM PDT 24
Peak memory 205860 kb
Host smart-2da5d9b9-515d-46df-910b-75a398f813cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720149628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.720149628
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3493680317
Short name T288
Test name
Test status
Simulation time 70833457707 ps
CPU time 490.46 seconds
Started Jul 20 05:38:26 PM PDT 24
Finished Jul 20 05:46:37 PM PDT 24
Peak memory 268708 kb
Host smart-6574ded8-2a8b-4cfc-88a2-cbdbf4c831e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493680317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3493680317
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.73086340
Short name T870
Test name
Test status
Simulation time 3443701534 ps
CPU time 39.72 seconds
Started Jul 20 05:38:26 PM PDT 24
Finished Jul 20 05:39:06 PM PDT 24
Peak memory 236852 kb
Host smart-7c6cea5a-0eca-4f6c-b9b8-cf62cb9cee33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73086340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.73086340
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3079135544
Short name T1007
Test name
Test status
Simulation time 1327156010 ps
CPU time 10.27 seconds
Started Jul 20 05:38:27 PM PDT 24
Finished Jul 20 05:38:38 PM PDT 24
Peak memory 249564 kb
Host smart-4b68ecd5-0ff5-4747-9472-f27a31d28c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079135544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3079135544
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1636215303
Short name T307
Test name
Test status
Simulation time 84656269841 ps
CPU time 303.12 seconds
Started Jul 20 05:38:34 PM PDT 24
Finished Jul 20 05:43:38 PM PDT 24
Peak memory 265972 kb
Host smart-3209eb74-f7d9-49fa-a1c2-56c89d3084f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636215303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1636215303
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.226043410
Short name T197
Test name
Test status
Simulation time 4112898939 ps
CPU time 4.72 seconds
Started Jul 20 05:38:20 PM PDT 24
Finished Jul 20 05:38:25 PM PDT 24
Peak memory 233208 kb
Host smart-2f7d5845-19cc-4e77-91dd-a59340649a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226043410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.226043410
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4225134608
Short name T790
Test name
Test status
Simulation time 164652843 ps
CPU time 4.7 seconds
Started Jul 20 05:38:17 PM PDT 24
Finished Jul 20 05:38:22 PM PDT 24
Peak memory 224884 kb
Host smart-d7a76a4b-33e5-4b69-9eb7-6da9d466df9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225134608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4225134608
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3674376058
Short name T877
Test name
Test status
Simulation time 177282469 ps
CPU time 1.02 seconds
Started Jul 20 05:38:15 PM PDT 24
Finished Jul 20 05:38:17 PM PDT 24
Peak memory 218396 kb
Host smart-e47e7f27-9c84-4fe4-8499-a31372574cf0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674376058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3674376058
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1749062270
Short name T846
Test name
Test status
Simulation time 720546425 ps
CPU time 5.43 seconds
Started Jul 20 05:38:18 PM PDT 24
Finished Jul 20 05:38:24 PM PDT 24
Peak memory 224892 kb
Host smart-351bfdb4-1208-4183-b7ec-8ecceab84724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749062270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1749062270
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2480625557
Short name T792
Test name
Test status
Simulation time 2249350552 ps
CPU time 7.83 seconds
Started Jul 20 05:38:21 PM PDT 24
Finished Jul 20 05:38:29 PM PDT 24
Peak memory 225044 kb
Host smart-10a07609-cae5-490f-86c0-429958206518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480625557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2480625557
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.835558955
Short name T897
Test name
Test status
Simulation time 805334793 ps
CPU time 4.87 seconds
Started Jul 20 05:38:27 PM PDT 24
Finished Jul 20 05:38:33 PM PDT 24
Peak memory 222796 kb
Host smart-293a7191-4747-4b0f-a364-16d1c1292d9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=835558955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.835558955
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1705687339
Short name T161
Test name
Test status
Simulation time 14943101981 ps
CPU time 21.76 seconds
Started Jul 20 05:38:29 PM PDT 24
Finished Jul 20 05:38:51 PM PDT 24
Peak memory 219700 kb
Host smart-16fe6647-8e80-4db2-a635-a09f5a5861cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705687339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1705687339
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3878356080
Short name T38
Test name
Test status
Simulation time 4821556368 ps
CPU time 34.47 seconds
Started Jul 20 05:38:17 PM PDT 24
Finished Jul 20 05:38:53 PM PDT 24
Peak memory 216616 kb
Host smart-fb1e4f44-68f7-4d54-88ed-2e323b96b8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878356080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3878356080
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.692658663
Short name T342
Test name
Test status
Simulation time 36496793 ps
CPU time 0.69 seconds
Started Jul 20 05:38:17 PM PDT 24
Finished Jul 20 05:38:18 PM PDT 24
Peak memory 205996 kb
Host smart-2649500b-5ee2-4ae0-a924-30ac60df61f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692658663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.692658663
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.468161883
Short name T438
Test name
Test status
Simulation time 135758034 ps
CPU time 1.42 seconds
Started Jul 20 05:38:20 PM PDT 24
Finished Jul 20 05:38:22 PM PDT 24
Peak memory 216660 kb
Host smart-999932d8-a944-43e6-9ff6-536e91cf45be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468161883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.468161883
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3409949075
Short name T894
Test name
Test status
Simulation time 22968445 ps
CPU time 0.78 seconds
Started Jul 20 05:38:21 PM PDT 24
Finished Jul 20 05:38:23 PM PDT 24
Peak memory 206284 kb
Host smart-938b094e-8561-4c87-a084-06b39de00f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409949075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3409949075
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.650565130
Short name T793
Test name
Test status
Simulation time 2262666884 ps
CPU time 10.42 seconds
Started Jul 20 05:38:18 PM PDT 24
Finished Jul 20 05:38:29 PM PDT 24
Peak memory 233204 kb
Host smart-b62fe222-d6cb-4fcd-b44e-8a35499c242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650565130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.650565130
Directory /workspace/9.spi_device_upload/latest
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