Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3230963	1			T1	1		T2	1		T3	1
all_values[1]	3230963	1			T1	1		T2	1		T3	1
all_values[2]	3230963	1			T1	1		T2	1		T3	1
all_values[3]	3230963	1			T1	1		T2	1		T3	1
all_values[4]	3230963	1			T1	1		T2	1		T3	1
all_values[5]	3230963	1			T1	1		T2	1		T3	1
all_values[6]	3230963	1			T1	1		T2	1		T3	1
all_values[7]	3230963	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25598946

1

T1

8

T2

8

T3

8

auto[1]

248758

1

T12

44

T17

12991

T18

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25819119

1

T1

8

T2

8

T3

8

auto[1]

28585

1

T12

169

T13

30

T17

97

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3173873	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	13804	1			T12	111		T13	30		T17	2
all_values[0]	auto[1]	auto[0]	42783	1			T12	6		T17	2556		T18	2
all_values[0]	auto[1]	auto[1]	503	1			T12	1		T17	39		T18	3
all_values[1]	auto[0]	auto[0]	3194361	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	8612	1			T12	32		T17	1		T28	236
all_values[1]	auto[1]	auto[0]	27609	1			T12	4		T17	2572		T18	5
all_values[1]	auto[1]	auto[1]	381	1			T12	2		T17	20		T18	5
all_values[2]	auto[0]	auto[0]	3204639	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3311	1			T12	2		T17	2		T28	91
all_values[2]	auto[1]	auto[0]	22754	1			T12	5		T17	6		T18	2
all_values[2]	auto[1]	auto[1]	259	1			T12	1		T17	1		T18	3
all_values[3]	auto[0]	auto[0]	3186748	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	184	1			T12	1		T17	3		T18	4
all_values[3]	auto[1]	auto[0]	43859	1			T12	3		T17	2588		T18	3
all_values[3]	auto[1]	auto[1]	172	1			T17	2		T20	6		T21	2
all_values[4]	auto[0]	auto[0]	3218129	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	152	1			T12	2		T17	2		T20	2
all_values[4]	auto[1]	auto[0]	12485	1			T12	5		T17	2592		T18	5
all_values[4]	auto[1]	auto[1]	197	1			T12	2		T17	1		T20	4
all_values[5]	auto[0]	auto[0]	3191784	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	158	1			T12	3		T17	5		T18	2
all_values[5]	auto[1]	auto[0]	38858	1			T12	7		T17	2589		T18	6
all_values[5]	auto[1]	auto[1]	163	1			T12	1		T17	6		T18	2
all_values[6]	auto[0]	auto[0]	3196041	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	156	1			T12	2		T17	2		T18	1
all_values[6]	auto[1]	auto[0]	34573	1			T12	1		T17	8		T20	6
all_values[6]	auto[1]	auto[1]	193	1			T12	2		T17	4		T18	4
all_values[7]	auto[0]	auto[0]	3206814	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	180	1			T12	5		T17	5		T18	4
all_values[7]	auto[1]	auto[0]	23809	1			T12	2		T17	5		T18	2
all_values[7]	auto[1]	auto[1]	160	1			T12	2		T17	2		T18	1