Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	39222	1			T2	2		T3	4		T8	14
auto[SpiFlashAddrCfg]	8387	1			T11	6		T12	60		T13	23
auto[SpiFlashAddr3b]	9930	1			T11	8		T12	52		T13	21
auto[SpiFlashAddr4b]	8012	1			T8	6		T12	42		T13	20

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36695

1

T3

4

T8

20

T12

383

auto[1]

28856

1

T2

2

T11

16

T12

223

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34895

1

T8

20

T11

8

T12

439

auto[1]

30656

1

T2

2

T3

4

T11

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	44223	1			T3	4		T8	14		T11	6
values[1]	1240	1			T2	2		T12	4		T13	6
values[2]	1577	1			T12	3		T13	6		T14	4
values[3]	1631	1			T12	11		T13	2		T14	3
values[4]	1539	1			T11	4		T12	6		T13	6
values[5]	1527	1			T12	11		T13	3		T14	3
values[6]	1583	1			T12	4		T13	5		T14	3
values[7]	1680	1			T11	2		T12	17		T13	2
values[8]	10551	1			T8	6		T11	4		T12	65

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34482

1

T2

2

T3

4

T8

20

auto[1]

31069

1

T12

606

T13

157

T17

50

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

61947

1

T2

2

T3

4

T8

20

write

3604

1

T11

2

T12

28

T13

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20815

1

T8

20

T11

8

T12

132

valids[0x1]

44736

1

T2

2

T3

4

T11

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1730	1			T12	15		T13	7		T14	4
internal_process_ops[0x5a]	1661	1			T11	2		T12	12		T13	3
internal_process_ops[0x05]	24158	1			T12	340		T13	44		T14	6
internal_process_ops[0x35]	1730	1			T11	2		T12	8		T13	4
internal_process_ops[0x15]	1686	1			T3	4		T12	21		T13	5
internal_process_ops[0x03]	1138	1			T11	2		T12	1		T13	1
internal_process_ops[0x0b]	1077	1			T12	5		T14	3		T16	2
internal_process_ops[0x3b]	1124	1			T12	2		T13	2		T14	2
internal_process_ops[0x6b]	1166	1			T13	2		T14	6		T16	2
internal_process_ops[0xbb]	1125	1			T11	2		T12	7		T13	1
internal_process_ops[0xeb]	1192	1			T11	2		T12	2		T14	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63772

1

T2

2

T3

4

T8

20

auto[1]

1779

1

T11

2

T12

13

T13

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62899

1

T2

2

T3

4

T8

20

auto[1]

2652

1

T12

22

T13

6

T14

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11377

1

T3

4

T8

14

T14

21

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7557

1

T2

2

T11

2

T14

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2331

1

T14

8

T16

2

T39

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2107

1

T11

4

T14

14

T15

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2751

1

T14

5

T39

11

T45

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2413

1

T11

8

T14

8

T39

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2136

1

T8

6

T14

17

T16

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2012

1

T14

13

T39

7

T28

23

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

116

1

T16

2

T49

1

T50

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

90

1

T39

1

T28

2

T20

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

106

1

T39

1

T28

2

T20

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

125

1

T47

1

T152

1

T153

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

123

1

T14

1

T20

7

T80

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

98

1

T28

3

T20

1

T21

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

83

1

T39

1

T28

1

T20

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

128

1

T11

2

T20

1

T21

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

119

1

T20

2

T47

4

T49

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

123

1

T14

2

T28

3

T20

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

114

1

T20

5

T49

2

T50

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

101

1

T39

1

T20

1

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

156

1

T39

1

T28

3

T125

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

107

1

T28

3

T20

1

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

106

1

T39

2

T28

6

T20

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

103

1

T14

1

T28

1

T20

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11210

1

T12

301

T13

36

T17

12

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8221

1

T12

142

T13

57

T17

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1584

1

T12

24

T13

11

T17

5

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1480

1

T12

27

T13

12

T17

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2018

1

T12

26

T13

6

T17

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1828

1

T12

22

T13

13

T17

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1445

1

T12

18

T13

7

T17

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1477

1

T12

18

T13

9

T17

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

94

1

T12

1

T154

1

T155

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

96

1

T12

2

T40

4

T127

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

103

1

T12

2

T17

1

T21

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

127

1

T12

4

T40

4

T21

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

107

1

T12

3

T40

2

T21

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

116

1

T12

3

T71

4

T79

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

122

1

T12

3

T17

2

T40

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

108

1

T79

1

T156

3

T157

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

132

1

T12

1

T21

2

T71

7

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

118

1

T12

2

T40

1

T79

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

106

1

T40

3

T154

1

T158

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

107

1

T12

1

T13

2

T17

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

110

1

T12

2

T13

2

T40

6

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

138

1

T13

1

T19

2

T21

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

128

1

T12

3

T13

1

T17

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

94

1

T12

1

T154

3

T155

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4378	1			T8	14		T14	21		T32	8
auto[0]	values[0]	valids[0x1]	17680	1			T3	4		T11	6		T14	22
auto[0]	values[1]	valids[0x1]	675	1			T2	2		T14	4		T39	4
auto[0]	values[2]	valids[0x0]	577	1			T14	4		T39	3		T28	4
auto[0]	values[2]	valids[0x1]	341	1			T16	2		T28	1		T20	1
auto[0]	values[3]	valids[0x0]	587	1			T14	1		T28	6		T159	2
auto[0]	values[3]	valids[0x1]	343	1			T14	2		T28	3		T20	2
auto[0]	values[4]	valids[0x0]	585	1			T11	4		T14	12		T39	3
auto[0]	values[4]	valids[0x1]	332	1			T39	6		T28	3		T20	7
auto[0]	values[5]	valids[0x0]	593	1			T14	2		T45	3		T28	5
auto[0]	values[5]	valids[0x1]	325	1			T14	1		T20	5		T21	2
auto[0]	values[6]	valids[0x0]	582	1			T14	1		T16	2		T39	2
auto[0]	values[6]	valids[0x1]	311	1			T14	2		T28	4		T21	2
auto[0]	values[7]	valids[0x0]	661	1			T11	2		T14	2		T39	3
auto[0]	values[7]	valids[0x1]	363	1			T14	2		T39	1		T28	2
auto[0]	values[8]	valids[0x0]	3889	1			T8	6		T11	2		T14	19
auto[0]	values[8]	valids[0x1]	2260	1			T11	2		T14	5		T43	2
auto[1]	values[0]	valids[0x0]	4041	1			T12	60		T13	25		T17	7
auto[1]	values[0]	valids[0x1]	18124	1			T12	425		T13	76		T17	22
auto[1]	values[1]	valids[0x1]	565	1			T12	4		T13	6		T17	1
auto[1]	values[2]	valids[0x0]	413	1			T12	3		T13	3		T17	2
auto[1]	values[2]	valids[0x1]	246	1			T13	3		T17	2		T40	2
auto[1]	values[3]	valids[0x0]	393	1			T12	5		T13	1		T40	4
auto[1]	values[3]	valids[0x1]	308	1			T12	6		T13	1		T17	2
auto[1]	values[4]	valids[0x0]	362	1			T12	2		T13	5		T17	3
auto[1]	values[4]	valids[0x1]	260	1			T12	4		T13	1		T17	1
auto[1]	values[5]	valids[0x0]	343	1			T12	6		T13	3		T26	2
auto[1]	values[5]	valids[0x1]	266	1			T12	5		T40	5		T71	3
auto[1]	values[6]	valids[0x0]	427	1			T12	3		T13	1		T40	5
auto[1]	values[6]	valids[0x1]	263	1			T12	1		T13	4		T40	4
auto[1]	values[7]	valids[0x0]	400	1			T12	9		T13	2		T40	5
auto[1]	values[7]	valids[0x1]	256	1			T12	8		T19	1		T71	6
auto[1]	values[8]	valids[0x0]	2584	1			T12	44		T13	16		T17	7
auto[1]	values[8]	valids[0x1]	1818	1			T12	21		T13	10		T17	3