Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3757614

1

T2

1

T3

496

T8

818

auto[1]

33448

1

T12

326

T13

37

T14

14

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000722

1

T2

1

T3

36

T8

818

auto[1]

2790340

1

T3

460

T12

14282

T13

7484

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	789518	1			T2	1		T8	3		T11	1
auto[524288:1048575]	497051	1			T8	290		T12	2582		T13	2981
auto[1048576:1572863]	416330	1			T8	9		T12	2958		T13	2226
auto[1572864:2097151]	418096	1			T12	3904		T14	533		T17	1203
auto[2097152:2621439]	427577	1			T3	273		T8	254		T12	1204
auto[2621440:3145727]	453669	1			T8	12		T13	1137		T14	17
auto[3145728:3670015]	392005	1			T3	223		T8	14		T12	1174
auto[3670016:4194303]	396816	1			T8	236		T12	501		T13	1

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2827057

1

T2

1

T3

464

T8

27

auto[1]

964005

1

T3

32

T8

791

T12

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3282374

1

T2

1

T3

496

T8

818

auto[1]

508688

1

T12

5913

T13

515

T14

18

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	254738	1			T2	1		T8	3		T11	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	470902	1			T12	1678		T13	906		T14	649
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	158948	1			T8	290		T12	7		T13	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	266589	1			T12	1433		T13	2980		T39	259
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	108284	1			T8	9		T12	11		T13	12
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	245200	1			T12	1549		T13	2210		T39	128
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	103054	1			T12	3		T14	9		T17	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	249744	1			T12	1926		T14	512		T17	1193
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	93829	1			T3	17		T8	254		T12	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	254690	1			T3	256		T12	1091		T13	231
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	99322	1			T8	12		T13	2		T14	8
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	288790	1			T13	614		T14	5		T40	920
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	89271	1			T3	19		T8	14		T12	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	233893	1			T3	204		T12	2		T14	4692
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	77387	1			T8	236		T12	1		T13	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	259356	1			T12	500		T39	256		T28	1270
auto[0]	auto[1]	auto[0:524287]	auto[0]	2494	1			T12	5		T14	2		T39	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	55888	1			T12	310		T20	1603		T21	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2113	1			T32	9		T40	21		T45	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	65243	1			T12	1131		T28	2317		T20	1029
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	593	1			T12	3		T39	2		T40	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	58322	1			T12	1281		T19	2661		T47	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1789	1			T12	4		T14	9		T40	18
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	59831	1			T12	1926		T28	2		T46	7441
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1814	1			T12	3		T40	40		T21	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	72514	1			T12	3		T40	2342		T20	533
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	881	1			T13	2		T14	4		T17	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	60036	1			T13	512		T17	256		T40	802
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	688	1			T13	1		T32	9		T39	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	64992	1			T12	1148		T39	2985		T40	128
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1163	1			T40	9		T28	1		T20	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	55256	1			T71	128		T47	512		T79	1624
auto[1]	auto[0]	auto[0:524287]	auto[0]	586	1			T12	2		T13	4		T14	9
auto[1]	auto[0]	auto[0:524287]	auto[1]	4218	1			T12	35		T13	22		T14	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	434	1			T12	3		T40	3		T28	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3200	1			T12	8		T28	6		T20	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	439	1			T12	3		T13	1		T28	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2883	1			T12	111		T13	3		T28	8
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	395	1			T12	3		T17	3		T40	11
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2677	1			T12	23		T17	2		T28	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	490	1			T12	2		T17	2		T19	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3575	1			T12	16		T17	3		T20	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	466	1			T13	1		T28	3		T19	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3524	1			T13	6		T28	1		T19	9
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	383	1			T12	1		T40	8		T20	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2230	1			T12	20		T40	16		T20	67
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	409	1			T40	3		T28	2		T21	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2468	1			T28	7		T21	2		T46	15
auto[1]	auto[1]	auto[0:524287]	auto[0]	115	1			T40	10		T21	1		T71	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	577	1			T71	1		T79	3		T49	9
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	76	1			T40	6		T28	4		T20	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	448	1			T28	6		T20	7		T79	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	89	1			T47	1		T152	1		T127	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	520	1			T47	44		T152	4		T127	5
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	110	1			T12	5		T14	3		T40	6
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	496	1			T12	14		T28	5		T187	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	88	1			T12	3		T21	2		T79	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	577	1			T12	77		T21	17		T79	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	96	1			T48	1		T158	1		T182	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	554	1			T48	50		T158	4		T182	16
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	83	1			T40	4		T28	2		T31	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	465	1			T28	6		T31	3		T201	18
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	95	1			T188	1		T127	1		T187	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	682	1			T188	19		T127	3		T187	6

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2297200	1			T2	1		T3	464		T8	27
auto[0]	auto[0]	auto[1]	956797	1			T3	32		T8	791		T13	3
auto[0]	auto[1]	auto[0]	497146	1			T12	5814		T13	515		T14	15
auto[0]	auto[1]	auto[1]	6471	1			T32	6		T28	1		T85	12
auto[1]	auto[0]	auto[0]	27757	1			T12	225		T13	34		T14	9
auto[1]	auto[0]	auto[1]	620	1			T12	2		T13	3		T14	2
auto[1]	auto[1]	auto[0]	4954	1			T12	99		T14	3		T40	20
auto[1]	auto[1]	auto[1]	117	1			T40	6		T21	2		T79	2