Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3230963	1			T1	1		T2	1		T3	1
all_pins[1]	3230963	1			T1	1		T2	1		T3	1
all_pins[2]	3230963	1			T1	1		T2	1		T3	1
all_pins[3]	3230963	1			T1	1		T2	1		T3	1
all_pins[4]	3230963	1			T1	1		T2	1		T3	1
all_pins[5]	3230963	1			T1	1		T2	1		T3	1
all_pins[6]	3230963	1			T1	1		T2	1		T3	1
all_pins[7]	3230963	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	25810283	1			T1	8		T2	8		T3	8
values[0x1]	37421	1			T12	11		T17	312		T18	18
transitions[0x0=>0x1]	36568	1			T12	10		T17	286		T18	14
transitions[0x1=>0x0]	36581	1			T12	10		T17	287		T18	14

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3230397	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	566	1			T12	1		T17	44		T18	3
all_pins[0]	transitions[0x0=>0x1]	368	1			T12	1		T17	23		T18	2
all_pins[0]	transitions[0x1=>0x0]	221	1			T12	2		T17	3		T18	4
all_pins[1]	values[0x0]	3230544	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	419	1			T12	2		T17	24		T18	5
all_pins[1]	transitions[0x0=>0x1]	333	1			T12	2		T17	23		T18	4
all_pins[1]	transitions[0x1=>0x0]	185	1			T12	1		T18	2		T20	3
all_pins[2]	values[0x0]	3230692	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	271	1			T12	1		T17	1		T18	3
all_pins[2]	transitions[0x0=>0x1]	227	1			T12	1		T17	1		T18	3
all_pins[2]	transitions[0x1=>0x0]	128	1			T17	2		T20	3		T21	1
all_pins[3]	values[0x0]	3230791	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	172	1			T17	2		T20	6		T21	2
all_pins[3]	transitions[0x0=>0x1]	116	1			T17	2		T20	5		T21	1
all_pins[3]	transitions[0x1=>0x0]	141	1			T12	2		T17	1		T20	3
all_pins[4]	values[0x0]	3230766	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	197	1			T12	2		T17	1		T20	4
all_pins[4]	transitions[0x0=>0x1]	149	1			T12	1		T20	3		T21	4
all_pins[4]	transitions[0x1=>0x0]	1153	1			T17	233		T18	2		T20	1
all_pins[5]	values[0x0]	3229762	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1201	1			T12	1		T17	234		T18	2
all_pins[5]	transitions[0x0=>0x1]	857	1			T12	1		T17	232		T18	1
all_pins[5]	transitions[0x1=>0x0]	34091	1			T12	2		T17	2		T18	3
all_pins[6]	values[0x0]	3196528	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	34435	1			T12	2		T17	4		T18	4
all_pins[6]	transitions[0x0=>0x1]	34399	1			T12	2		T17	4		T18	3
all_pins[6]	transitions[0x1=>0x0]	124	1			T12	2		T17	2		T20	3
all_pins[7]	values[0x0]	3230803	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	160	1			T12	2		T17	2		T18	1
all_pins[7]	transitions[0x0=>0x1]	119	1			T12	2		T17	1		T18	1
all_pins[7]	transitions[0x1=>0x0]	538	1			T12	1		T17	44		T18	3