Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19527

1

T3

4

T8

20

T14

54

auto[1]

14955

1

T2

2

T11

16

T14

46

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4796	1			T14	20		T159	26		T20	47
values[1]	3867	1			T16	15		T28	21		T20	40
values[2]	4438	1			T14	20		T39	20		T28	30
values[3]	4305	1			T14	20		T32	8		T43	2
values[4]	4860	1			T8	20		T44	4		T28	24
values[5]	4070	1			T11	16		T14	40		T15	4
values[6]	3733	1			T2	2		T28	41		T214	2
values[7]	4413	1			T3	4		T39	57		T91	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4433	1			T14	40		T39	30		T90	4
values[1]	5011	1			T11	16		T15	4		T28	90
values[2]	4593	1			T91	10		T44	4		T28	87
values[3]	3576	1			T8	20		T14	20		T39	20
values[4]	4414	1			T3	4		T16	15		T28	57
values[5]	3934	1			T2	2		T14	20		T39	20
values[6]	4429	1			T14	20		T32	8		T39	47
values[7]	4092	1			T43	2		T20	20		T21	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	221	1			T14	15		T20	10		T47	10
auto[0]	values[0]	values[1]	630	1			T20	14		T47	208		T215	8
auto[0]	values[0]	values[2]	439	1			T159	26		T216	16		T217	13
auto[0]	values[0]	values[3]	295	1			T21	22		T80	27		T218	4
auto[0]	values[0]	values[4]	306	1			T126	10		T31	14		T196	10
auto[0]	values[0]	values[5]	382	1			T78	16		T48	16		T33	15
auto[0]	values[0]	values[6]	328	1			T49	33		T219	4		T211	44
auto[0]	values[0]	values[7]	164	1			T21	8		T50	20		T187	6
auto[0]	values[1]	values[0]	216	1			T28	9		T127	12		T220	2
auto[0]	values[1]	values[1]	188	1			T152	11		T80	8		T221	24
auto[0]	values[1]	values[2]	341	1			T20	13		T21	15		T34	8
auto[0]	values[1]	values[3]	330	1			T185	15		T145	8		T201	9
auto[0]	values[1]	values[4]	427	1			T16	15		T49	10		T182	46
auto[0]	values[1]	values[5]	271	1			T20	11		T179	20		T33	16
auto[0]	values[1]	values[6]	334	1			T21	11		T80	87		T182	8
auto[0]	values[1]	values[7]	325	1			T145	39		T171	14		T59	46
auto[0]	values[2]	values[0]	529	1			T47	14		T49	13		T50	6
auto[0]	values[2]	values[1]	452	1			T28	18		T20	9		T191	4
auto[0]	values[2]	values[2]	266	1			T47	11		T50	5		T152	14
auto[0]	values[2]	values[3]	235	1			T46	13		T222	8		T182	15
auto[0]	values[2]	values[4]	247	1			T50	13		T200	141		T223	8
auto[0]	values[2]	values[5]	389	1			T14	8		T39	8		T46	14
auto[0]	values[2]	values[6]	212	1			T20	7		T217	11		T196	26
auto[0]	values[2]	values[7]	268	1			T207	20		T224	9		T225	41
auto[0]	values[3]	values[0]	271	1			T90	4		T183	11		T190	13
auto[0]	values[3]	values[1]	263	1			T28	7		T20	12		T21	9
auto[0]	values[3]	values[2]	288	1			T21	48		T183	11		T213	4
auto[0]	values[3]	values[3]	206	1			T39	9		T46	26		T49	11
auto[0]	values[3]	values[4]	293	1			T152	66		T187	13		T179	14
auto[0]	values[3]	values[5]	483	1			T28	18		T20	10		T21	6
auto[0]	values[3]	values[6]	254	1			T14	12		T32	8		T195	6
auto[0]	values[3]	values[7]	387	1			T43	2		T20	12		T192	89
auto[0]	values[4]	values[0]	269	1			T28	12		T20	14		T50	15
auto[0]	values[4]	values[1]	505	1			T50	11		T31	12		T80	7
auto[0]	values[4]	values[2]	201	1			T44	4		T185	11		T145	10
auto[0]	values[4]	values[3]	479	1			T8	20		T21	8		T77	2
auto[0]	values[4]	values[4]	384	1			T226	10		T80	22		T145	30
auto[0]	values[4]	values[5]	177	1			T152	15		T198	14		T227	10
auto[0]	values[4]	values[6]	257	1			T198	11		T200	8		T128	15
auto[0]	values[4]	values[7]	326	1			T80	11		T217	13		T170	13
auto[0]	values[5]	values[0]	246	1			T14	7		T31	11		T199	26
auto[0]	values[5]	values[1]	241	1			T228	8		T33	11		T170	10
auto[0]	values[5]	values[2]	285	1			T152	19		T80	11		T198	12
auto[0]	values[5]	values[3]	239	1			T14	12		T45	13		T127	12
auto[0]	values[5]	values[4]	437	1			T28	31		T229	6		T179	14
auto[0]	values[5]	values[5]	258	1			T49	11		T80	15		T230	7
auto[0]	values[5]	values[6]	255	1			T39	8		T20	10		T85	6
auto[0]	values[5]	values[7]	352	1			T179	15		T217	10		T231	8
auto[0]	values[6]	values[0]	259	1			T20	94		T232	4		T233	6
auto[0]	values[6]	values[1]	256	1			T28	14		T46	13		T174	18
auto[0]	values[6]	values[2]	263	1			T28	9		T73	24		T48	9
auto[0]	values[6]	values[3]	160	1			T214	2		T48	10		T128	9
auto[0]	values[6]	values[4]	242	1			T48	21		T179	12		T183	10
auto[0]	values[6]	values[5]	154	1			T187	15		T170	12		T190	22
auto[0]	values[6]	values[6]	376	1			T124	2		T47	10		T48	14
auto[0]	values[6]	values[7]	134	1			T234	8		T199	10		T235	6
auto[0]	values[7]	values[0]	494	1			T39	14		T28	10		T50	7
auto[0]	values[7]	values[1]	233	1			T28	14		T20	9		T46	11
auto[0]	values[7]	values[2]	415	1			T91	10		T28	31		T179	10
auto[0]	values[7]	values[3]	199	1			T206	6		T152	15		T31	14
auto[0]	values[7]	values[4]	257	1			T3	4		T28	16		T236	4
auto[0]	values[7]	values[5]	360	1			T20	51		T48	12		T182	4
auto[0]	values[7]	values[6]	283	1			T39	9		T125	89		T205	14
auto[0]	values[7]	values[7]	291	1			T21	10		T192	14		T187	41
auto[1]	values[0]	values[0]	419	1			T14	5		T20	17		T47	10
auto[1]	values[0]	values[1]	177	1			T20	6		T47	9		T196	19
auto[1]	values[0]	values[2]	241	1			T237	6		T217	13		T33	7
auto[1]	values[0]	values[3]	237	1			T21	7		T80	63		T187	12
auto[1]	values[0]	values[4]	190	1			T31	12		T196	12		T238	19
auto[1]	values[0]	values[5]	200	1			T48	4		T33	17		T201	6
auto[1]	values[0]	values[6]	312	1			T49	10		T198	13		T200	4
auto[1]	values[0]	values[7]	255	1			T21	12		T50	20		T187	14
auto[1]	values[1]	values[0]	178	1			T28	12		T127	8		T183	4
auto[1]	values[1]	values[1]	137	1			T152	14		T239	6		T80	12
auto[1]	values[1]	values[2]	267	1			T20	7		T21	5		T240	16
auto[1]	values[1]	values[3]	98	1			T185	8		T145	12		T201	11
auto[1]	values[1]	values[4]	191	1			T49	10		T182	8		T179	8
auto[1]	values[1]	values[5]	104	1			T20	9		T241	14		T179	4
auto[1]	values[1]	values[6]	237	1			T21	9		T80	68		T182	12
auto[1]	values[1]	values[7]	223	1			T145	7		T171	6		T180	13
auto[1]	values[2]	values[0]	164	1			T47	6		T49	7		T50	14
auto[1]	values[2]	values[1]	445	1			T28	12		T20	11		T47	72
auto[1]	values[2]	values[2]	292	1			T47	26		T50	15		T152	6
auto[1]	values[2]	values[3]	180	1			T46	7		T182	24		T128	8
auto[1]	values[2]	values[4]	149	1			T50	7		T200	10		T223	12
auto[1]	values[2]	values[5]	269	1			T14	12		T39	12		T46	8
auto[1]	values[2]	values[6]	172	1			T20	19		T217	9		T196	21
auto[1]	values[2]	values[7]	169	1			T224	11		T225	8		T190	9
auto[1]	values[3]	values[0]	210	1			T183	18		T190	22		T201	35
auto[1]	values[3]	values[1]	384	1			T28	13		T20	37		T21	30
auto[1]	values[3]	values[2]	232	1			T21	7		T242	10		T183	16
auto[1]	values[3]	values[3]	243	1			T39	11		T46	5		T49	9
auto[1]	values[3]	values[4]	286	1			T152	6		T187	36		T179	10
auto[1]	values[3]	values[5]	216	1			T28	4		T20	10		T21	14
auto[1]	values[3]	values[6]	132	1			T14	8		T200	9		T128	7
auto[1]	values[3]	values[7]	157	1			T20	8		T192	11		T128	10
auto[1]	values[4]	values[0]	341	1			T28	12		T20	41		T50	5
auto[1]	values[4]	values[1]	449	1			T50	9		T31	10		T80	13
auto[1]	values[4]	values[2]	260	1			T185	10		T145	20		T224	6
auto[1]	values[4]	values[3]	259	1			T21	12		T80	8		T198	3
auto[1]	values[4]	values[4]	282	1			T80	126		T145	8		T196	7
auto[1]	values[4]	values[5]	133	1			T152	5		T198	6		T243	14
auto[1]	values[4]	values[6]	266	1			T198	9		T200	12		T128	5
auto[1]	values[4]	values[7]	272	1			T80	114		T217	9		T170	7
auto[1]	values[5]	values[0]	119	1			T14	13		T31	10		T199	6
auto[1]	values[5]	values[1]	142	1			T11	16		T15	4		T33	9
auto[1]	values[5]	values[2]	292	1			T152	8		T80	96		T198	8
auto[1]	values[5]	values[3]	155	1			T14	8		T45	7		T127	9
auto[1]	values[5]	values[4]	311	1			T28	6		T179	7		T190	14
auto[1]	values[5]	values[5]	236	1			T49	9		T80	6		T230	13
auto[1]	values[5]	values[6]	258	1			T39	12		T20	112		T152	10
auto[1]	values[5]	values[7]	244	1			T179	17		T217	10		T196	7
auto[1]	values[6]	values[0]	189	1			T20	11		T196	28		T204	9
auto[1]	values[6]	values[1]	259	1			T28	6		T46	7		T198	6
auto[1]	values[6]	values[2]	220	1			T28	12		T48	11		T80	11
auto[1]	values[6]	values[3]	118	1			T48	30		T128	11		T33	9
auto[1]	values[6]	values[4]	192	1			T48	5		T179	8		T183	11
auto[1]	values[6]	values[5]	129	1			T2	2		T187	5		T170	8
auto[1]	values[6]	values[6]	469	1			T47	10		T48	7		T31	9
auto[1]	values[6]	values[7]	313	1			T199	10		T235	17		T177	9
auto[1]	values[7]	values[0]	308	1			T39	16		T28	10		T50	13
auto[1]	values[7]	values[1]	250	1			T28	6		T20	11		T46	27
auto[1]	values[7]	values[2]	291	1			T28	35		T179	10		T183	6
auto[1]	values[7]	values[3]	143	1			T152	28		T31	7		T244	15
auto[1]	values[7]	values[4]	220	1			T28	4		T31	13		T179	9
auto[1]	values[7]	values[5]	173	1			T20	6		T48	8		T182	29
auto[1]	values[7]	values[6]	284	1			T39	18		T127	10		T230	7
auto[1]	values[7]	values[7]	212	1			T21	10		T192	6		T187	18