Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	460	1			T14	1		T39	1		T28	3
auto[ReadAddrCrossIntoMailbox]	324	1			T14	2		T39	2		T45	2
auto[ReadAddrCrossOutOfMailbox]	303	1			T14	3		T39	1		T45	2
auto[ReadAddrCrossAllMailbox]	257	1			T14	2		T20	4		T21	2
auto[ReadAddrOutsideMailbox]	3867	1			T11	6		T14	19		T16	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2559

1

T11

3

T14

16

T16

2

auto[1]

2652

1

T11

3

T14

11

T16

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	865	1			T11	2		T14	5		T39	3
read_ops[0x0b]	818	1			T14	3		T16	2		T43	2
read_ops[0x3b]	859	1			T14	2		T39	5		T45	3
read_ops[0x6b]	888	1			T14	6		T16	2		T39	4
read_ops[0xbb]	854	1			T11	2		T14	7		T39	1
read_ops[0xeb]	927	1			T11	2		T14	4		T39	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T152	1		T80	1		T182	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T46	1		T48	1		T80	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T28	1		T179	1		T33	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T14	1		T20	1		T21	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T14	2		T80	1		T187	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T20	1		T127	1		T198	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	30	1			T46	1		T50	1		T80	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T14	1		T20	2		T46	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	312	1			T11	1		T14	1		T39	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	318	1			T11	1		T44	1		T28	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T39	1		T47	1		T198	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T46	2		T50	1		T152	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T152	1		T31	1		T80	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T21	1		T48	1		T196	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T80	1		T187	1		T196	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T46	1		T80	1		T187	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T80	1		T200	1		T190	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T48	1		T31	1		T224	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T14	1		T16	1		T43	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T14	2		T16	1		T43	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T206	1		T228	2		T152	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T21	1		T206	1		T48	3
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T46	1		T50	1		T187	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T39	2		T45	1		T46	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T21	1		T152	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T45	2		T28	3		T21	4
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T47	1		T31	1		T80	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T20	1		T230	1		T217	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	321	1			T28	3		T159	3		T20	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	316	1			T14	2		T39	3		T28	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T28	1		T228	1		T187	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T21	1		T46	1		T228	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T14	1		T45	1		T152	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T50	1		T182	1		T230	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T28	3		T50	1		T80	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T39	1		T127	1		T179	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T179	1		T201	1		T34	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T20	1		T21	1		T46	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	325	1			T14	2		T16	1		T39	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	331	1			T14	3		T16	1		T39	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T14	1		T28	1		T80	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T192	1		T128	1		T217	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T47	1		T152	1		T80	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T46	1		T50	1		T187	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T48	1		T152	1		T80	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T46	1		T192	1		T187	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T152	1		T80	1		T210	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T21	1		T33	1		T224	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	334	1			T11	1		T14	5		T28	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T11	1		T14	1		T39	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T50	1		T33	1		T201	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T28	1		T21	2		T47	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T21	1		T152	1		T192	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T21	1		T46	1		T31	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T80	1		T33	1		T196	4
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T14	1		T21	1		T48	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	31	1			T14	1		T50	1		T196	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T48	1		T152	1		T217	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	318	1			T11	1		T14	2		T39	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	377	1			T11	1		T39	3		T28	10