Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 0 18 100.00
Crosses 128 0 128 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_data 8 0 8 100.00 100 1 1 0
cp_mask 8 0 8 100.00 100 1 1 0
cp_payload_swap_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 0 128 100.00 100 1 1 0


Summary for Variable cp_data

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_data

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 3986 1 T28 36 T20 47 T21 39
values[1] 4344 1 T43 2 T39 20 T28 50
values[2] 4092 1 T3 4 T14 40 T90 4
values[3] 4110 1 T2 2 T39 20 T28 81
values[4] 3738 1 T11 16 T14 20 T16 15
values[5] 4869 1 T44 4 T28 21 T214 2
values[6] 4829 1 T14 40 T32 8 T39 50
values[7] 4514 1 T8 20 T15 4 T39 27



Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4244 1 T3 4 T14 20 T28 94
values[1] 4941 1 T14 20 T16 15 T39 40
values[2] 3916 1 T14 20 T43 2 T90 4
values[3] 4018 1 T2 2 T8 20 T14 20
values[4] 4338 1 T15 4 T39 30 T20 162
values[5] 4091 1 T11 16 T39 27 T28 22
values[6] 4477 1 T39 20 T44 4 T28 30
values[7] 4457 1 T14 20 T28 20 T20 125



Summary for Variable cp_payload_swap_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_payload_swap_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33607 1 T2 2 T3 4 T8 20
auto[1] 875 1 T11 2 T14 3 T39 2



Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_payload_swap_encp_datacp_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] values[0] 704 1 T50 16 T80 125 T187 28
auto[0] values[0] values[1] 432 1 T28 36 T21 38 T46 29
auto[0] values[0] values[2] 524 1 T245 10 T246 2 T217 129
auto[0] values[0] values[3] 351 1 T80 19 T187 72 T179 19
auto[0] values[0] values[4] 473 1 T229 6 T153 27 T128 20
auto[0] values[0] values[5] 390 1 T20 45 T247 10 T187 20
auto[0] values[0] values[6] 614 1 T80 20 T219 4 T182 38
auto[0] values[0] values[7] 378 1 T152 25 T183 20 T224 19
auto[0] values[1] values[0] 541 1 T28 20 T187 20 T241 14
auto[0] values[1] values[1] 809 1 T39 20 T248 14 T182 20
auto[0] values[1] values[2] 445 1 T43 2 T20 49 T49 20
auto[0] values[1] values[3] 449 1 T217 21 T170 19 T190 20
auto[0] values[1] values[4] 578 1 T20 122 T46 20 T239 2
auto[0] values[1] values[5] 526 1 T218 4 T242 10 T217 19
auto[0] values[1] values[6] 448 1 T28 28 T234 8 T208 8
auto[0] values[1] values[7] 461 1 T182 145 T128 40 T190 26
auto[0] values[2] values[0] 455 1 T3 4 T28 24 T20 20
auto[0] values[2] values[1] 448 1 T50 18 T187 40 T249 16
auto[0] values[2] values[2] 485 1 T14 19 T90 4 T46 36
auto[0] values[2] values[3] 528 1 T14 18 T28 33 T49 38
auto[0] values[2] values[4] 381 1 T85 6 T31 20 T170 19
auto[0] values[2] values[5] 630 1 T211 44 T198 20 T179 20
auto[0] values[2] values[6] 617 1 T124 2 T250 12 T50 20
auto[0] values[2] values[7] 431 1 T46 20 T31 26 T251 18
auto[0] values[3] values[0] 500 1 T28 20 T21 20 T195 6
auto[0] values[3] values[1] 549 1 T28 20 T21 54 T47 140
auto[0] values[3] values[2] 393 1 T152 20 T220 2 T182 44
auto[0] values[3] values[3] 394 1 T2 2 T28 38 T191 4
auto[0] values[3] values[4] 822 1 T20 20 T48 95 T152 72
auto[0] values[3] values[5] 631 1 T21 20 T152 20 T80 82
auto[0] values[3] values[6] 323 1 T39 20 T205 14 T31 22
auto[0] values[3] values[7] 383 1 T50 17 T187 20 T216 16
auto[0] values[4] values[0] 269 1 T48 20 T128 23 T252 22
auto[0] values[4] values[1] 629 1 T14 20 T16 15 T236 4
auto[0] values[4] values[2] 373 1 T45 20 T179 30 T200 18
auto[0] values[4] values[3] 445 1 T91 10 T73 24 T50 20
auto[0] values[4] values[4] 317 1 T173 20 T149 58 T253 20
auto[0] values[4] values[5] 366 1 T11 14 T28 21 T159 26
auto[0] values[4] values[6] 668 1 T47 20 T50 20 T80 27
auto[0] values[4] values[7] 588 1 T48 20 T50 20 T192 20
auto[0] values[5] values[0] 570 1 T47 20 T78 16 T80 104
auto[0] values[5] values[1] 564 1 T254 8 T204 36 T173 20
auto[0] values[5] values[2] 457 1 T226 10 T187 29 T182 20
auto[0] values[5] values[3] 514 1 T28 21 T214 2 T21 29
auto[0] values[5] values[4] 583 1 T20 17 T50 14 T128 20
auto[0] values[5] values[5] 496 1 T77 2 T31 24 T80 71
auto[0] values[5] values[6] 797 1 T44 4 T198 19 T179 17
auto[0] values[5] values[7] 762 1 T47 36 T48 136 T182 128
auto[0] values[6] values[0] 664 1 T14 20 T28 28 T21 19
auto[0] values[6] values[1] 706 1 T39 19 T20 20 T48 20
auto[0] values[6] values[2] 438 1 T46 20 T228 8 T255 12
auto[0] values[6] values[3] 599 1 T32 8 T33 20 T256 87
auto[0] values[6] values[4] 576 1 T39 29 T47 79 T152 26
auto[0] values[6] values[5] 631 1 T49 20 T187 39 T145 20
auto[0] values[6] values[6] 348 1 T174 18 T47 77 T257 12
auto[0] values[6] values[7] 753 1 T14 20 T28 20 T20 123
auto[0] values[7] values[0] 443 1 T20 55 T47 18 T232 4
auto[0] values[7] values[1] 682 1 T152 43 T222 8 T145 46
auto[0] values[7] values[2] 685 1 T20 25 T21 20 T182 132
auto[0] values[7] values[3] 631 1 T8 20 T49 81 T198 21
auto[0] values[7] values[4] 480 1 T15 4 T128 20 T33 21
auto[0] values[7] values[5] 348 1 T39 27 T21 19 T31 23
auto[0] values[7] values[6] 549 1 T20 19 T21 20 T125 89
auto[0] values[7] values[7] 583 1 T80 45 T127 42 T179 20
auto[1] values[0] values[0] 19 1 T50 4 T187 1 T145 3
auto[1] values[0] values[1] 16 1 T21 1 T46 2 T33 1
auto[1] values[0] values[2] 12 1 T217 1 T204 2 T235 1
auto[1] values[0] values[3] 12 1 T80 1 T179 1 T33 3
auto[1] values[0] values[4] 20 1 T153 4 T54 1 T235 1
auto[1] values[0] values[5] 8 1 T20 2 T201 2 T193 1
auto[1] values[0] values[6] 24 1 T182 2 T145 2 T177 1
auto[1] values[0] values[7] 9 1 T183 1 T224 1 T201 1
auto[1] values[1] values[0] 9 1 T173 1 T34 1 T54 1
auto[1] values[1] values[1] 11 1 T179 2 T175 2 T203 1
auto[1] values[1] values[2] 8 1 T183 1 T201 1 T34 3
auto[1] values[1] values[3] 7 1 T217 1 T170 1 T149 1
auto[1] values[1] values[4] 19 1 T46 2 T239 4 T179 1
auto[1] values[1] values[5] 9 1 T217 1 T170 3 T196 1
auto[1] values[1] values[6] 9 1 T28 2 T203 2 T258 2
auto[1] values[1] values[7] 15 1 T182 3 T190 2 T199 3
auto[1] values[2] values[0] 14 1 T49 4 T224 1 T235 1
auto[1] values[2] values[1] 14 1 T50 2 T249 2 T223 4
auto[1] values[2] values[2] 20 1 T14 1 T46 2 T198 2
auto[1] values[2] values[3] 27 1 T14 2 T28 4 T49 2
auto[1] values[2] values[4] 14 1 T31 1 T170 1 T259 2
auto[1] values[2] values[5] 7 1 T33 2 T224 1 T201 1
auto[1] values[2] values[6] 16 1 T80 3 T198 1 T230 1
auto[1] values[2] values[7] 5 1 T223 1 T260 1 T261 2
auto[1] values[3] values[0] 9 1 T200 1 T238 2 T203 1
auto[1] values[3] values[1] 19 1 T21 1 T50 2 T262 3
auto[1] values[3] values[2] 16 1 T237 2 T200 2 T223 2
auto[1] values[3] values[3] 12 1 T28 3 T225 2 T263 2
auto[1] values[3] values[4] 20 1 T48 1 T179 3 T196 3
auto[1] values[3] values[5] 10 1 T256 2 T259 1 T264 1
auto[1] values[3] values[6] 7 1 T185 1 T35 1 T238 2
auto[1] values[3] values[7] 22 1 T50 3 T170 1 T177 1
auto[1] values[4] values[0] 4 1 T128 1 T265 1 T266 1
auto[1] values[4] values[1] 15 1 T33 2 T204 4 T201 4
auto[1] values[4] values[2] 11 1 T179 2 T200 2 T267 1
auto[1] values[4] values[3] 6 1 T187 3 T182 1 T178 1
auto[1] values[4] values[4] 5 1 T263 2 T268 2 T130 1
auto[1] values[4] values[5] 9 1 T11 2 T28 1 T260 1
auto[1] values[4] values[6] 13 1 T80 1 T203 1 T269 3
auto[1] values[4] values[7] 20 1 T48 1 T128 3 T190 1
auto[1] values[5] values[0] 11 1 T80 4 T270 1 T271 1
auto[1] values[5] values[1] 17 1 T199 5 T149 1 T259 1
auto[1] values[5] values[2] 19 1 T190 2 T272 3 T266 2
auto[1] values[5] values[3] 7 1 T196 2 T203 1 T273 1
auto[1] values[5] values[4] 18 1 T20 3 T50 6 T33 1
auto[1] values[5] values[5] 13 1 T80 2 T217 1 T34 2
auto[1] values[5] values[6] 25 1 T198 1 T179 4 T224 1
auto[1] values[5] values[7] 16 1 T47 1 T182 1 T33 4
auto[1] values[6] values[0] 19 1 T28 2 T21 1 T80 2
auto[1] values[6] values[1] 14 1 T39 1 T152 1 T185 2
auto[1] values[6] values[2] 15 1 T175 1 T238 4 T265 2
auto[1] values[6] values[3] 15 1 T34 2 T199 2 T149 2
auto[1] values[6] values[4] 16 1 T39 1 T47 3 T152 1
auto[1] values[6] values[5] 11 1 T200 5 T128 2 T274 1
auto[1] values[6] values[6] 6 1 T257 2 T202 1 T275 1
auto[1] values[6] values[7] 18 1 T20 2 T198 3 T170 2
auto[1] values[7] values[0] 13 1 T47 2 T171 3 T262 1
auto[1] values[7] values[1] 16 1 T170 1 T190 2 T272 4
auto[1] values[7] values[2] 15 1 T20 1 T182 2 T200 2
auto[1] values[7] values[3] 21 1 T198 1 T183 1 T34 1
auto[1] values[7] values[4] 16 1 T33 1 T196 2 T171 5
auto[1] values[7] values[5] 6 1 T21 1 T31 2 T127 2
auto[1] values[7] values[6] 13 1 T20 1 T48 1 T217 1
auto[1] values[7] values[7] 13 1 T127 1 T179 1 T276 2

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