Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	751	1			T12	10		T17	14		T18	10
all_values[1]	751	1			T12	10		T17	14		T18	10
all_values[2]	751	1			T12	10		T17	14		T18	10
all_values[3]	751	1			T12	10		T17	14		T18	10
all_values[4]	751	1			T12	10		T17	14		T18	10
all_values[5]	751	1			T12	10		T17	14		T18	10
all_values[6]	751	1			T12	10		T17	14		T18	10
all_values[7]	751	1			T12	10		T17	14		T18	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3232

1

T12

41

T17

56

T18

41

auto[1]

2776

1

T12

39

T17

56

T18

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2462

1

T12

38

T17

46

T18

34

auto[1]

3546

1

T12

42

T17

66

T18

46

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3447

1

T12

52

T17

63

T18

45

auto[1]

2561

1

T12

28

T17

49

T18

35

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	162	1			T12	2		T17	3		T18	1
all_values[0]	auto[0]	auto[0]	auto[1]	69	1			T12	1		T17	2		T20	2
all_values[0]	auto[0]	auto[1]	auto[0]	135	1			T12	3		T17	2		T18	1
all_values[0]	auto[0]	auto[1]	auto[1]	65	1			T12	1		T17	1		T29	2
all_values[0]	auto[1]	auto[0]	auto[1]	171	1			T12	2		T17	2		T18	3
all_values[0]	auto[1]	auto[1]	auto[1]	149	1			T12	1		T17	4		T18	5
all_values[1]	auto[0]	auto[0]	auto[0]	170	1			T12	4		T17	5		T20	5
all_values[1]	auto[0]	auto[0]	auto[1]	68	1			T20	1		T21	1		T29	1
all_values[1]	auto[0]	auto[1]	auto[0]	118	1			T12	2		T17	1		T18	4
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T12	1		T17	2		T18	4
all_values[1]	auto[1]	auto[0]	auto[1]	181	1			T12	2		T17	3		T20	2
all_values[1]	auto[1]	auto[1]	auto[1]	134	1			T12	1		T17	3		T18	2
all_values[2]	auto[0]	auto[0]	auto[0]	162	1			T12	1		T17	4		T18	1
all_values[2]	auto[0]	auto[0]	auto[1]	40	1			T12	1		T17	1		T18	1
all_values[2]	auto[0]	auto[1]	auto[0]	170	1			T12	5		T17	2		T18	2
all_values[2]	auto[0]	auto[1]	auto[1]	60	1			T20	1		T21	1		T29	3
all_values[2]	auto[1]	auto[0]	auto[1]	156	1			T12	1		T17	4		T18	3
all_values[2]	auto[1]	auto[1]	auto[1]	163	1			T12	2		T17	3		T18	3
all_values[3]	auto[0]	auto[0]	auto[0]	154	1			T12	4		T17	2		T18	3
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T17	1		T18	1		T20	3
all_values[3]	auto[0]	auto[1]	auto[0]	111	1			T12	4		T17	4		T18	2
all_values[3]	auto[0]	auto[1]	auto[1]	69	1			T17	1		T20	2		T21	1
all_values[3]	auto[1]	auto[0]	auto[1]	174	1			T12	2		T17	4		T18	4
all_values[3]	auto[1]	auto[1]	auto[1]	155	1			T17	2		T20	5		T21	3
all_values[4]	auto[0]	auto[0]	auto[0]	178	1			T17	3		T18	3		T20	4
all_values[4]	auto[0]	auto[0]	auto[1]	61	1			T12	2		T17	1		T29	5
all_values[4]	auto[0]	auto[1]	auto[0]	102	1			T12	2		T17	5		T18	5
all_values[4]	auto[0]	auto[1]	auto[1]	90	1			T17	1		T20	2		T21	2
all_values[4]	auto[1]	auto[0]	auto[1]	155	1			T12	3		T17	2		T18	2
all_values[4]	auto[1]	auto[1]	auto[1]	165	1			T12	3		T17	2		T20	2
all_values[5]	auto[0]	auto[0]	auto[0]	237	1			T18	2		T20	6		T21	4
all_values[5]	auto[0]	auto[1]	auto[0]	193	1			T12	6		T17	3		T18	4
all_values[5]	auto[1]	auto[0]	auto[1]	169	1			T12	4		T17	5		T18	3
all_values[5]	auto[1]	auto[1]	auto[1]	152	1			T17	6		T18	1		T20	3
all_values[6]	auto[0]	auto[0]	auto[0]	165	1			T12	2		T17	3		T18	4
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T12	1		T17	1		T20	3
all_values[6]	auto[0]	auto[1]	auto[0]	115	1			T12	1		T17	4		T20	2
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T12	2		T17	2		T18	2
all_values[6]	auto[1]	auto[0]	auto[1]	178	1			T12	3		T17	1		T18	2
all_values[6]	auto[1]	auto[1]	auto[1]	144	1			T12	1		T17	3		T18	2
all_values[7]	auto[0]	auto[0]	auto[0]	160	1			T17	2		T18	1		T20	5
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T12	5		T17	3		T18	3
all_values[7]	auto[0]	auto[1]	auto[0]	130	1			T12	2		T17	3		T18	1
all_values[7]	auto[0]	auto[1]	auto[1]	67	1			T17	1		T29	4		T31	1
all_values[7]	auto[1]	auto[0]	auto[1]	185	1			T12	1		T17	4		T18	4
all_values[7]	auto[1]	auto[1]	auto[1]	130	1			T12	2		T17	1		T18	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal