Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1974

1

T1

10

T4

9

T7

23

auto[1]

1912

1

T1

9

T4

4

T7

23

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2150

1

T4

13

T12

17

T13

4

auto[1]

1736

1

T1

19

T7

46

T9

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3067

1

T1

19

T4

10

T7

46

auto[1]

819

1

T4

3

T12

7

T13

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	796	1			T1	5		T4	1		T7	7
valid[1]	798	1			T1	4		T4	1		T7	8
valid[2]	777	1			T1	3		T4	3		T7	11
valid[3]	789	1			T1	3		T4	1		T7	10
valid[4]	726	1			T1	4		T4	7		T7	10

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	150	1			T4	1		T27	1		T28	2
auto[0]	auto[0]	valid[0]	auto[1]	175	1			T1	3		T7	1		T25	1
auto[0]	auto[0]	valid[1]	auto[0]	134	1			T4	1		T12	1		T13	1
auto[0]	auto[0]	valid[1]	auto[1]	173	1			T1	1		T7	5		T9	1
auto[0]	auto[0]	valid[2]	auto[0]	127	1			T4	1		T12	1		T13	1
auto[0]	auto[0]	valid[2]	auto[1]	172	1			T1	2		T7	8		T12	1
auto[0]	auto[0]	valid[3]	auto[0]	158	1			T4	1		T12	3		T17	1
auto[0]	auto[0]	valid[3]	auto[1]	185	1			T1	1		T7	4		T12	1
auto[0]	auto[0]	valid[4]	auto[0]	111	1			T4	3		T17	3		T28	1
auto[0]	auto[0]	valid[4]	auto[1]	181	1			T1	3		T7	5		T25	1
auto[0]	auto[1]	valid[0]	auto[0]	145	1			T12	1		T19	1		T20	1
auto[0]	auto[1]	valid[0]	auto[1]	141	1			T1	2		T7	6		T25	3
auto[0]	auto[1]	valid[1]	auto[0]	139	1			T12	2		T27	1		T28	1
auto[0]	auto[1]	valid[1]	auto[1]	184	1			T1	3		T7	3		T9	2
auto[0]	auto[1]	valid[2]	auto[0]	129	1			T4	1		T19	2		T20	5
auto[0]	auto[1]	valid[2]	auto[1]	188	1			T1	1		T7	3		T9	1
auto[0]	auto[1]	valid[3]	auto[0]	114	1			T12	1		T17	1		T27	2
auto[0]	auto[1]	valid[3]	auto[1]	175	1			T1	2		T7	6		T9	1
auto[0]	auto[1]	valid[4]	auto[0]	124	1			T4	2		T12	1		T27	2
auto[0]	auto[1]	valid[4]	auto[1]	162	1			T1	1		T7	5		T25	4
auto[1]	auto[0]	valid[0]	auto[0]	94	1			T13	1		T17	1		T21	1
auto[1]	auto[0]	valid[1]	auto[0]	79	1			T28	1		T71	1		T155	1
auto[1]	auto[0]	valid[2]	auto[0]	83	1			T4	1		T27	1		T19	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T12	2		T27	1		T28	1
auto[1]	auto[0]	valid[4]	auto[0]	78	1			T4	1		T27	1		T28	1
auto[1]	auto[1]	valid[0]	auto[0]	91	1			T12	1		T13	1		T17	1
auto[1]	auto[1]	valid[1]	auto[0]	89	1			T17	1		T28	2		T21	1
auto[1]	auto[1]	valid[2]	auto[0]	78	1			T17	1		T27	1		T19	1
auto[1]	auto[1]	valid[3]	auto[0]	83	1			T12	2		T28	1		T20	2
auto[1]	auto[1]	valid[4]	auto[0]	70	1			T4	1		T12	2		T27	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal