Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53654

1

T4

324

T12

351

T13

77

auto[1]

18648

1

T1

202

T7

489

T9

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52539

1

T1

202

T4

215

T7

489

auto[1]

19763

1

T4

109

T12

127

T13

27

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	37399	1			T1	97		T4	154		T7	251
others[1]	6027	1			T1	28		T4	33		T7	35
others[2]	5996	1			T1	17		T4	30		T7	41
others[3]	6928	1			T1	19		T4	30		T7	47
interest[1]	3998	1			T1	9		T4	12		T7	29
interest[4]	24418	1			T1	60		T4	107		T7	154
interest[64]	11954	1			T1	32		T4	65		T7	86

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17548	1			T4	102		T12	121		T13	29
auto[0]	auto[0]	others[1]	2829	1			T4	20		T12	22		T13	4
auto[0]	auto[0]	others[2]	2805	1			T4	17		T12	11		T13	4
auto[0]	auto[0]	others[3]	3215	1			T4	24		T12	23		T13	3
auto[0]	auto[0]	interest[1]	1923	1			T4	7		T12	8		T13	1
auto[0]	auto[0]	interest[4]	11379	1			T4	74		T12	73		T13	15
auto[0]	auto[0]	interest[64]	5571	1			T4	45		T12	39		T13	9
auto[0]	auto[1]	others[0]	9723	1			T1	97		T7	251		T9	5
auto[0]	auto[1]	others[1]	1492	1			T1	28		T7	35		T12	1
auto[0]	auto[1]	others[2]	1533	1			T1	17		T7	41		T12	1
auto[0]	auto[1]	others[3]	1815	1			T1	19		T7	47		T12	1
auto[0]	auto[1]	interest[1]	994	1			T1	9		T7	29		T25	20
auto[0]	auto[1]	interest[4]	6402	1			T1	60		T7	154		T9	5
auto[0]	auto[1]	interest[64]	3091	1			T1	32		T7	86		T12	2
auto[1]	auto[0]	others[0]	10128	1			T4	52		T12	62		T13	12
auto[1]	auto[0]	others[1]	1706	1			T4	13		T12	9		T13	3
auto[1]	auto[0]	others[2]	1658	1			T4	13		T12	12		T13	3
auto[1]	auto[0]	others[3]	1898	1			T4	6		T12	17		T13	3
auto[1]	auto[0]	interest[1]	1081	1			T4	5		T12	8		T17	6
auto[1]	auto[0]	interest[4]	6637	1			T4	33		T12	40		T13	9
auto[1]	auto[0]	interest[64]	3292	1			T4	20		T12	19		T13	6

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal